1 /*
2 * nextpnr -- Next Generation Place and Route
3 *
4 * Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
5 * Copyright (C) 2018 David Shah <david@symbioticeda.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include <algorithm>
22 #include <boost/iostreams/device/mapped_file.hpp>
23 #include <boost/range/adaptor/reversed.hpp>
24 #include <cmath>
25 #include <cstring>
26 #include "embed.h"
27 #include "gfx.h"
28 #include "globals.h"
29 #include "log.h"
30 #include "nextpnr.h"
31 #include "placer1.h"
32 #include "placer_heap.h"
33 #include "router1.h"
34 #include "router2.h"
35 #include "timing.h"
36 #include "util.h"
37
38 NEXTPNR_NAMESPACE_BEGIN
39
split_identifier_name(const std::string & name)40 static std::tuple<int, int, std::string> split_identifier_name(const std::string &name)
41 {
42 size_t first_slash = name.find('/');
43 NPNR_ASSERT(first_slash != std::string::npos);
44 size_t second_slash = name.find('/', first_slash + 1);
45 NPNR_ASSERT(second_slash != std::string::npos);
46 return std::make_tuple(std::stoi(name.substr(1, first_slash)),
47 std::stoi(name.substr(first_slash + 2, second_slash - first_slash)),
48 name.substr(second_slash + 1));
49 };
50
51 // -----------------------------------------------------------------------
52
initialize_arch(const BaseCtx * ctx)53 void IdString::initialize_arch(const BaseCtx *ctx)
54 {
55 #define X(t) initialize_add(ctx, #t, ID_##t);
56
57 #include "constids.inc"
58
59 #undef X
60 }
61
62 // -----------------------------------------------------------------------
63
get_chip_info(ArchArgs::ArchArgsTypes chip)64 static const ChipInfoPOD *get_chip_info(ArchArgs::ArchArgsTypes chip)
65 {
66 std::string chipdb;
67 if (chip == ArchArgs::LFE5U_12F || chip == ArchArgs::LFE5U_25F || chip == ArchArgs::LFE5UM_25F ||
68 chip == ArchArgs::LFE5UM5G_25F) {
69 chipdb = "ecp5/chipdb-25k.bin";
70 } else if (chip == ArchArgs::LFE5U_45F || chip == ArchArgs::LFE5UM_45F || chip == ArchArgs::LFE5UM5G_45F) {
71 chipdb = "ecp5/chipdb-45k.bin";
72 } else if (chip == ArchArgs::LFE5U_85F || chip == ArchArgs::LFE5UM_85F || chip == ArchArgs::LFE5UM5G_85F) {
73 chipdb = "ecp5/chipdb-85k.bin";
74 } else {
75 log_error("Unknown chip\n");
76 }
77
78 auto ptr = reinterpret_cast<const RelPtr<ChipInfoPOD> *>(get_chipdb(chipdb));
79 if (ptr == nullptr)
80 return nullptr;
81 return ptr->get();
82 }
83
isAvailable(ArchArgs::ArchArgsTypes chip)84 bool Arch::isAvailable(ArchArgs::ArchArgsTypes chip) { return get_chip_info(chip) != nullptr; }
85
getSupportedPackages(ArchArgs::ArchArgsTypes chip)86 std::vector<std::string> Arch::getSupportedPackages(ArchArgs::ArchArgsTypes chip)
87 {
88 const ChipInfoPOD *chip_info = get_chip_info(chip);
89 std::vector<std::string> packages;
90 for (int i = 0; i < chip_info->num_packages; i++)
91 packages.push_back(chip_info->package_info[i].name.get());
92 return packages;
93 }
94
95 // -----------------------------------------------------------------------
96
Arch(ArchArgs args)97 Arch::Arch(ArchArgs args) : args(args)
98 {
99 chip_info = get_chip_info(args.type);
100 if (chip_info == nullptr)
101 log_error("Unsupported ECP5 chip type.\n");
102 if (chip_info->const_id_count != DB_CONST_ID_COUNT)
103 log_error("Chip database 'bba' and nextpnr code are out of sync; please rebuild (or contact distribution "
104 "maintainer)!\n");
105
106 package_info = nullptr;
107 for (int i = 0; i < chip_info->num_packages; i++) {
108 if (args.package == chip_info->package_info[i].name.get()) {
109 package_info = &(chip_info->package_info[i]);
110 break;
111 }
112 }
113 speed_grade = &(chip_info->speed_grades[args.speed]);
114 if (!package_info)
115 log_error("Unsupported package '%s' for '%s'.\n", args.package.c_str(), getChipName().c_str());
116
117 bel_to_cell.resize(chip_info->height * chip_info->width * max_loc_bels, nullptr);
118 }
119
120 // -----------------------------------------------------------------------
121
getChipName() const122 std::string Arch::getChipName() const
123 {
124 if (args.type == ArchArgs::LFE5U_12F) {
125 return "LFE5U-12F";
126 } else if (args.type == ArchArgs::LFE5U_25F) {
127 return "LFE5U-25F";
128 } else if (args.type == ArchArgs::LFE5U_45F) {
129 return "LFE5U-45F";
130 } else if (args.type == ArchArgs::LFE5U_85F) {
131 return "LFE5U-85F";
132 } else if (args.type == ArchArgs::LFE5UM_25F) {
133 return "LFE5UM-25F";
134 } else if (args.type == ArchArgs::LFE5UM_45F) {
135 return "LFE5UM-45F";
136 } else if (args.type == ArchArgs::LFE5UM_85F) {
137 return "LFE5UM-85F";
138 } else if (args.type == ArchArgs::LFE5UM5G_25F) {
139 return "LFE5UM5G-25F";
140 } else if (args.type == ArchArgs::LFE5UM5G_45F) {
141 return "LFE5UM5G-45F";
142 } else if (args.type == ArchArgs::LFE5UM5G_85F) {
143 return "LFE5UM5G-85F";
144 } else {
145 log_error("Unknown chip\n");
146 }
147 }
148
getFullChipName() const149 std::string Arch::getFullChipName() const
150 {
151 std::string name = getChipName();
152 name += "-";
153 switch (args.speed) {
154 case ArchArgs::SPEED_6:
155 name += "6";
156 break;
157 case ArchArgs::SPEED_7:
158 name += "7";
159 break;
160 case ArchArgs::SPEED_8:
161 case ArchArgs::SPEED_8_5G:
162 name += "8";
163 break;
164 }
165 name += args.package;
166 return name;
167 }
168
169 // -----------------------------------------------------------------------
170
archArgsToId(ArchArgs args) const171 IdString Arch::archArgsToId(ArchArgs args) const
172 {
173 if (args.type == ArchArgs::LFE5U_12F)
174 return id("lfe5u_12f");
175 if (args.type == ArchArgs::LFE5U_25F)
176 return id("lfe5u_25f");
177 if (args.type == ArchArgs::LFE5U_45F)
178 return id("lfe5u_45f");
179 if (args.type == ArchArgs::LFE5U_85F)
180 return id("lfe5u_85f");
181 if (args.type == ArchArgs::LFE5UM_25F)
182 return id("lfe5um_25f");
183 if (args.type == ArchArgs::LFE5UM_45F)
184 return id("lfe5um_45f");
185 if (args.type == ArchArgs::LFE5UM_85F)
186 return id("lfe5um_85f");
187 if (args.type == ArchArgs::LFE5UM5G_25F)
188 return id("lfe5um5g_25f");
189 if (args.type == ArchArgs::LFE5UM5G_45F)
190 return id("lfe5um5g_45f");
191 if (args.type == ArchArgs::LFE5UM5G_85F)
192 return id("lfe5um5g_85f");
193 return IdString();
194 }
195
196 // -----------------------------------------------------------------------
197
getBelByName(IdString name) const198 BelId Arch::getBelByName(IdString name) const
199 {
200 BelId ret;
201 auto it = bel_by_name.find(name);
202 if (it != bel_by_name.end())
203 return it->second;
204
205 Location loc;
206 std::string basename;
207 std::tie(loc.x, loc.y, basename) = split_identifier_name(name.str(this));
208 ret.location = loc;
209 const LocationTypePOD *loci = locInfo(ret);
210 for (int i = 0; i < loci->num_bels; i++) {
211 if (std::strcmp(loci->bel_data[i].name.get(), basename.c_str()) == 0) {
212 ret.index = i;
213 break;
214 }
215 }
216 if (ret.index >= 0)
217 bel_by_name[name] = ret;
218 return ret;
219 }
220
getBelsByTile(int x,int y) const221 BelRange Arch::getBelsByTile(int x, int y) const
222 {
223 BelRange br;
224
225 br.b.cursor_tile = y * chip_info->width + x;
226 br.e.cursor_tile = y * chip_info->width + x;
227 br.b.cursor_index = 0;
228 br.e.cursor_index = chip_info->locations[chip_info->location_type[br.b.cursor_tile]].num_bels - 1;
229 br.b.chip = chip_info;
230 br.e.chip = chip_info;
231 if (br.e.cursor_index == -1)
232 ++br.e.cursor_index;
233 else
234 ++br.e;
235 return br;
236 }
237
getBelPinWire(BelId bel,IdString pin) const238 WireId Arch::getBelPinWire(BelId bel, IdString pin) const
239 {
240 WireId ret;
241
242 NPNR_ASSERT(bel != BelId());
243
244 int num_bel_wires = locInfo(bel)->bel_data[bel.index].num_bel_wires;
245 const BelWirePOD *bel_wires = locInfo(bel)->bel_data[bel.index].bel_wires.get();
246 for (int i = 0; i < num_bel_wires; i++)
247 if (bel_wires[i].port == pin.index) {
248 ret.location = bel.location + bel_wires[i].rel_wire_loc;
249 ret.index = bel_wires[i].wire_index;
250 break;
251 }
252
253 return ret;
254 }
255
getBelPinType(BelId bel,IdString pin) const256 PortType Arch::getBelPinType(BelId bel, IdString pin) const
257 {
258 NPNR_ASSERT(bel != BelId());
259
260 int num_bel_wires = locInfo(bel)->bel_data[bel.index].num_bel_wires;
261 const BelWirePOD *bel_wires = locInfo(bel)->bel_data[bel.index].bel_wires.get();
262
263 for (int i = 0; i < num_bel_wires; i++)
264 if (bel_wires[i].port == pin.index)
265 return PortType(bel_wires[i].type);
266
267 return PORT_INOUT;
268 }
269
270 // -----------------------------------------------------------------------
271
getWireByName(IdString name) const272 WireId Arch::getWireByName(IdString name) const
273 {
274 WireId ret;
275 auto it = wire_by_name.find(name);
276 if (it != wire_by_name.end())
277 return it->second;
278
279 Location loc;
280 std::string basename;
281 std::tie(loc.x, loc.y, basename) = split_identifier_name(name.str(this));
282 ret.location = loc;
283 const LocationTypePOD *loci = locInfo(ret);
284 for (int i = 0; i < loci->num_wires; i++) {
285 if (std::strcmp(loci->wire_data[i].name.get(), basename.c_str()) == 0) {
286 ret.index = i;
287 ret.location = loc;
288 break;
289 }
290 }
291 if (ret.index >= 0)
292 wire_by_name[name] = ret;
293 else
294 ret.location = Location();
295 return ret;
296 }
297
298 // -----------------------------------------------------------------------
299
getPipByName(IdString name) const300 PipId Arch::getPipByName(IdString name) const
301 {
302 auto it = pip_by_name.find(name);
303 if (it != pip_by_name.end())
304 return it->second;
305
306 PipId ret;
307 Location loc;
308 std::string basename;
309 std::tie(loc.x, loc.y, basename) = split_identifier_name(name.str(this));
310 ret.location = loc;
311 const LocationTypePOD *loci = locInfo(ret);
312 for (int i = 0; i < loci->num_pips; i++) {
313 PipId curr;
314 curr.location = loc;
315 curr.index = i;
316 pip_by_name[getPipName(curr)] = curr;
317 }
318 if (pip_by_name.find(name) == pip_by_name.end())
319 NPNR_ASSERT_FALSE_STR("no pip named " + name.str(this));
320 return pip_by_name[name];
321 }
322
getPipName(PipId pip) const323 IdString Arch::getPipName(PipId pip) const
324 {
325 NPNR_ASSERT(pip != PipId());
326
327 int x = pip.location.x;
328 int y = pip.location.y;
329
330 std::string src_name = getWireName(getPipSrcWire(pip)).str(this);
331 std::replace(src_name.begin(), src_name.end(), '/', '.');
332
333 std::string dst_name = getWireName(getPipDstWire(pip)).str(this);
334 std::replace(dst_name.begin(), dst_name.end(), '/', '.');
335
336 return id("X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" + src_name + ".->." + dst_name);
337 }
338
339 // -----------------------------------------------------------------------
340
getPackagePinBel(const std::string & pin) const341 BelId Arch::getPackagePinBel(const std::string &pin) const
342 {
343 for (int i = 0; i < package_info->num_pins; i++) {
344 if (package_info->pin_data[i].name.get() == pin) {
345 BelId bel;
346 bel.location = package_info->pin_data[i].abs_loc;
347 bel.index = package_info->pin_data[i].bel_index;
348 return bel;
349 }
350 }
351 return BelId();
352 }
353
getBelPackagePin(BelId bel) const354 std::string Arch::getBelPackagePin(BelId bel) const
355 {
356 for (int i = 0; i < package_info->num_pins; i++) {
357 if (Location(package_info->pin_data[i].abs_loc) == bel.location &&
358 package_info->pin_data[i].bel_index == bel.index) {
359 return package_info->pin_data[i].name.get();
360 }
361 }
362 return "";
363 }
364
getPioBelBank(BelId bel) const365 int Arch::getPioBelBank(BelId bel) const
366 {
367 for (int i = 0; i < chip_info->num_pios; i++) {
368 if (Location(chip_info->pio_info[i].abs_loc) == bel.location && chip_info->pio_info[i].bel_index == bel.index) {
369 return chip_info->pio_info[i].bank;
370 }
371 }
372 NPNR_ASSERT_FALSE("failed to find PIO");
373 }
374
getPioFunctionName(BelId bel) const375 std::string Arch::getPioFunctionName(BelId bel) const
376 {
377 for (int i = 0; i < chip_info->num_pios; i++) {
378 if (Location(chip_info->pio_info[i].abs_loc) == bel.location && chip_info->pio_info[i].bel_index == bel.index) {
379 const char *func = chip_info->pio_info[i].function_name.get();
380 if (func == nullptr)
381 return "";
382 else
383 return func;
384 }
385 }
386 NPNR_ASSERT_FALSE("failed to find PIO");
387 }
388
getPioByFunctionName(const std::string & name) const389 BelId Arch::getPioByFunctionName(const std::string &name) const
390 {
391 for (int i = 0; i < chip_info->num_pios; i++) {
392 const char *func = chip_info->pio_info[i].function_name.get();
393 if (func != nullptr && func == name) {
394 BelId bel;
395 bel.location = chip_info->pio_info[i].abs_loc;
396 bel.index = chip_info->pio_info[i].bel_index;
397 return bel;
398 }
399 }
400 return BelId();
401 }
402
getBelPins(BelId bel) const403 std::vector<IdString> Arch::getBelPins(BelId bel) const
404 {
405 std::vector<IdString> ret;
406 NPNR_ASSERT(bel != BelId());
407
408 int num_bel_wires = locInfo(bel)->bel_data[bel.index].num_bel_wires;
409 const BelWirePOD *bel_wires = locInfo(bel)->bel_data[bel.index].bel_wires.get();
410
411 for (int i = 0; i < num_bel_wires; i++) {
412 IdString id;
413 id.index = bel_wires[i].port;
414 ret.push_back(id);
415 }
416
417 return ret;
418 }
419
getBelByLocation(Loc loc) const420 BelId Arch::getBelByLocation(Loc loc) const
421 {
422 if (loc.x >= chip_info->width || loc.y >= chip_info->height)
423 return BelId();
424 const LocationTypePOD &locI = chip_info->locations[chip_info->location_type[loc.y * chip_info->width + loc.x]];
425 for (int i = 0; i < locI.num_bels; i++) {
426 if (locI.bel_data[i].z == loc.z) {
427 BelId bi;
428 bi.location.x = loc.x;
429 bi.location.y = loc.y;
430 bi.index = i;
431 return bi;
432 }
433 }
434 return BelId();
435 }
436
437 // -----------------------------------------------------------------------
438
estimateDelay(WireId src,WireId dst) const439 delay_t Arch::estimateDelay(WireId src, WireId dst) const
440 {
441 int num_uh = locInfo(dst)->wire_data[dst.index].num_uphill;
442 if (num_uh < 6) {
443 for (auto uh : getPipsUphill(dst)) {
444 if (getPipSrcWire(uh) == src)
445 return getPipDelay(uh).maxDelay();
446 }
447 }
448
449 auto est_location = [&](WireId w) -> std::pair<int, int> {
450 const auto &wire = locInfo(w)->wire_data[w.index];
451 if (w == gsrclk_wire) {
452 auto phys_wire = getPipSrcWire(*(getPipsUphill(w).begin()));
453 return std::make_pair(int(phys_wire.location.x), int(phys_wire.location.y));
454 } else if (wire.num_bel_pins > 0) {
455 return std::make_pair(w.location.x + wire.bel_pins[0].rel_bel_loc.x,
456 w.location.y + wire.bel_pins[0].rel_bel_loc.y);
457 } else if (wire.num_downhill > 0) {
458 return std::make_pair(w.location.x + wire.pips_downhill[0].rel_loc.x,
459 w.location.y + wire.pips_downhill[0].rel_loc.y);
460 } else if (wire.num_uphill > 0) {
461 return std::make_pair(w.location.x + wire.pips_uphill[0].rel_loc.x,
462 w.location.y + wire.pips_uphill[0].rel_loc.y);
463 } else {
464 return std::make_pair(int(w.location.x), int(w.location.y));
465 }
466 };
467
468 auto src_loc = est_location(src);
469 std::pair<int, int> dst_loc;
470 if (wire_loc_overrides.count(dst)) {
471 dst_loc = wire_loc_overrides.at(dst);
472 } else {
473 dst_loc = est_location(dst);
474 }
475
476 int dx = abs(src_loc.first - dst_loc.first), dy = abs(src_loc.second - dst_loc.second);
477
478 return (120 - 22 * args.speed) *
479 (6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
480 }
481
getRouteBoundingBox(WireId src,WireId dst) const482 ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
483 {
484 ArcBounds bb;
485
486 bb.x0 = src.location.x;
487 bb.y0 = src.location.y;
488 bb.x1 = src.location.x;
489 bb.y1 = src.location.y;
490
491 auto extend = [&](int x, int y) {
492 bb.x0 = std::min(bb.x0, x);
493 bb.x1 = std::max(bb.x1, x);
494 bb.y0 = std::min(bb.y0, y);
495 bb.y1 = std::max(bb.y1, y);
496 };
497
498 auto est_location = [&](WireId w) -> std::pair<int, int> {
499 const auto &wire = locInfo(w)->wire_data[w.index];
500 if (w == gsrclk_wire) {
501 auto phys_wire = getPipSrcWire(*(getPipsUphill(w).begin()));
502 return std::make_pair(int(phys_wire.location.x), int(phys_wire.location.y));
503 } else if (wire.num_bel_pins > 0) {
504 return std::make_pair(w.location.x + wire.bel_pins[0].rel_bel_loc.x,
505 w.location.y + wire.bel_pins[0].rel_bel_loc.y);
506 } else if (wire.num_downhill > 0) {
507 return std::make_pair(w.location.x + wire.pips_downhill[0].rel_loc.x,
508 w.location.y + wire.pips_downhill[0].rel_loc.y);
509 } else if (wire.num_uphill > 0) {
510 return std::make_pair(w.location.x + wire.pips_uphill[0].rel_loc.x,
511 w.location.y + wire.pips_uphill[0].rel_loc.y);
512 } else {
513 return std::make_pair(int(w.location.x), int(w.location.y));
514 }
515 };
516
517 auto src_loc = est_location(src);
518 extend(src_loc.first, src_loc.second);
519 if (wire_loc_overrides.count(src)) {
520 extend(wire_loc_overrides.at(src).first, wire_loc_overrides.at(src).second);
521 }
522 std::pair<int, int> dst_loc;
523 extend(dst.location.x, dst.location.y);
524 if (wire_loc_overrides.count(dst)) {
525 dst_loc = wire_loc_overrides.at(dst);
526 } else {
527 dst_loc = est_location(dst);
528 }
529 extend(dst_loc.first, dst_loc.second);
530 return bb;
531 }
532
predictDelay(const NetInfo * net_info,const PortRef & sink) const533 delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
534 {
535 const auto &driver = net_info->driver;
536 if ((driver.port == id_FCO && sink.port == id_FCI) || sink.port == id_FXA || sink.port == id_FXB)
537 return 0;
538 auto driver_loc = getBelLocation(driver.cell->bel);
539 auto sink_loc = getBelLocation(sink.cell->bel);
540 // Encourage use of direct interconnect
541 if (driver_loc.x == sink_loc.x && driver_loc.y == sink_loc.y) {
542 if ((sink.port == id_A0 || sink.port == id_A1) && (driver.port == id_F1) &&
543 (driver_loc.z == 2 || driver_loc.z == 3))
544 return 0;
545 if ((sink.port == id_B0 || sink.port == id_B1) && (driver.port == id_F1) &&
546 (driver_loc.z == 0 || driver_loc.z == 1))
547 return 0;
548 if ((sink.port == id_C0 || sink.port == id_C1) && (driver.port == id_F0) &&
549 (driver_loc.z == 2 || driver_loc.z == 3))
550 return 0;
551 if ((sink.port == id_D0 || sink.port == id_D1) && (driver.port == id_F0) &&
552 (driver_loc.z == 0 || driver_loc.z == 1))
553 return 0;
554 }
555
556 int dx = abs(driver_loc.x - sink_loc.x), dy = abs(driver_loc.y - sink_loc.y);
557
558 return (120 - 22 * args.speed) *
559 (6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
560 }
561
getBudgetOverride(const NetInfo * net_info,const PortRef & sink,delay_t & budget) const562 bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const
563 {
564 if (net_info->driver.port == id_FCO && sink.port == id_FCI) {
565 budget = 0;
566 return true;
567 } else if (sink.port == id_FXA || sink.port == id_FXB) {
568 budget = 0;
569 return true;
570 } else {
571 return false;
572 }
573 }
574
getRipupDelayPenalty() const575 delay_t Arch::getRipupDelayPenalty() const { return 400; }
576
577 // -----------------------------------------------------------------------
578
place()579 bool Arch::place()
580 {
581 std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
582
583 if (placer == "heap") {
584 PlacerHeapCfg cfg(getCtx());
585 cfg.criticalityExponent = 4;
586 cfg.ioBufTypes.insert(id_TRELLIS_IO);
587 if (!placer_heap(getCtx(), cfg))
588 return false;
589 } else if (placer == "sa") {
590 if (!placer1(getCtx(), Placer1Cfg(getCtx())))
591 return false;
592 } else {
593 log_error("ECP5 architecture does not support placer '%s'\n", placer.c_str());
594 }
595 permute_luts();
596
597 // In out-of-context mode, create a locked macro
598 if (bool_or_default(settings, id("arch.ooc")))
599 for (auto &cell : cells)
600 cell.second->belStrength = STRENGTH_LOCKED;
601
602 getCtx()->settings[getCtx()->id("place")] = 1;
603
604 archInfoToAttributes();
605 return true;
606 }
607
route()608 bool Arch::route()
609 {
610 std::string router = str_or_default(settings, id("router"), defaultRouter);
611
612 setupWireLocations();
613 route_ecp5_globals(getCtx());
614 assignArchInfo();
615 assign_budget(getCtx(), true);
616
617 bool result;
618 if (router == "router1") {
619 result = router1(getCtx(), Router1Cfg(getCtx()));
620 } else if (router == "router2") {
621 router2(getCtx(), Router2Cfg(getCtx()));
622 result = true;
623 } else {
624 log_error("ECP5 architecture does not support router '%s'\n", router.c_str());
625 }
626
627 #if 0
628 std::vector<std::pair<WireId, int>> fanout_vector;
629 std::copy(wire_fanout.begin(), wire_fanout.end(), std::back_inserter(fanout_vector));
630 std::sort(fanout_vector.begin(), fanout_vector.end(), [](const std::pair<WireId, int> &a, const std::pair<WireId, int> &b) {
631 return a.second > b.second;
632 });
633 for (size_t i = 0; i < std::min(size_t(20), fanout_vector.size()); i++)
634 log_info(" fanout %s = %d\n", getWireName(fanout_vector[i].first).c_str(this), fanout_vector[i].second);
635 log_break();
636 PipId slowest_pip;
637 delay_t slowest_pipdelay = 0;
638 for (auto pip : pip_to_net) {
639 if (pip.second) {
640 delay_t dly = getPipDelay(pip.first).maxDelay();
641 if (dly > slowest_pipdelay) {
642 slowest_pip = pip.first;
643 slowest_pipdelay = dly;
644 }
645 }
646 }
647 log_info(" slowest pip %s = %.02f ns\n", getPipName(slowest_pip).c_str(this), getDelayNS(slowest_pipdelay));
648 log_info(" fanout %d\n", wire_fanout[getPipSrcWire(slowest_pip)]);
649 log_info(" base %d adder %d\n", speed_grade->pip_classes[locInfo(slowest_pip)->pip_data[slowest_pip.index].timing_class].max_base_delay,
650 speed_grade->pip_classes[locInfo(slowest_pip)->pip_data[slowest_pip.index].timing_class].max_fanout_adder);
651 #endif
652 getCtx()->settings[getCtx()->id("route")] = 1;
653 archInfoToAttributes();
654 return result;
655 }
656
657 // -----------------------------------------------------------------------
658
getDecalGraphics(DecalId decal) const659 std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
660 {
661 std::vector<GraphicElement> ret;
662
663 if (decal.type == DecalId::TYPE_GROUP) {
664 int type = decal.z;
665 int x = decal.location.x;
666 int y = decal.location.y;
667
668 if (type == GroupId::TYPE_SWITCHBOX) {
669 GraphicElement el;
670 el.type = GraphicElement::TYPE_BOX;
671 el.style = GraphicElement::STYLE_FRAME;
672
673 el.x1 = x + switchbox_x1;
674 el.x2 = x + switchbox_x2;
675 el.y1 = y + switchbox_y1;
676 el.y2 = y + switchbox_y2;
677 ret.push_back(el);
678 }
679 } else if (decal.type == DecalId::TYPE_WIRE) {
680 WireId wire;
681 wire.index = decal.z;
682 wire.location = decal.location;
683 auto wire_type = getWireType(wire);
684 int x = decal.location.x;
685 int y = decal.location.y;
686 GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
687 GfxTileWireId tilewire = GfxTileWireId(locInfo(wire)->wire_data[wire.index].tile_wire);
688 gfxTileWire(ret, x, y, chip_info->width, chip_info->height, wire_type, tilewire, style);
689 } else if (decal.type == DecalId::TYPE_PIP) {
690 PipId pip;
691 pip.index = decal.z;
692 pip.location = decal.location;
693 WireId src_wire = getPipSrcWire(pip);
694 WireId dst_wire = getPipDstWire(pip);
695 int x = decal.location.x;
696 int y = decal.location.y;
697 GfxTileWireId src_id = GfxTileWireId(locInfo(src_wire)->wire_data[src_wire.index].tile_wire);
698 GfxTileWireId dst_id = GfxTileWireId(locInfo(dst_wire)->wire_data[dst_wire.index].tile_wire);
699 GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_HIDDEN;
700 gfxTilePip(ret, x, y, chip_info->width, chip_info->height, src_wire, getWireType(src_wire), src_id, dst_wire,
701 getWireType(dst_wire), dst_id, style);
702 } else if (decal.type == DecalId::TYPE_BEL) {
703 BelId bel;
704 bel.index = decal.z;
705 bel.location = decal.location;
706 auto bel_type = getBelType(bel);
707 int x = decal.location.x;
708 int y = decal.location.y;
709 int z = locInfo(bel)->bel_data[bel.index].z;
710 GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
711 gfxTileBel(ret, x, y, z, chip_info->width, chip_info->height, bel_type, style);
712 }
713
714 return ret;
715 }
716
getBelDecal(BelId bel) const717 DecalXY Arch::getBelDecal(BelId bel) const
718 {
719 DecalXY decalxy;
720 decalxy.decal.type = DecalId::TYPE_BEL;
721 decalxy.decal.location = bel.location;
722 decalxy.decal.z = bel.index;
723 decalxy.decal.active = (bel_to_cell.at(getBelFlatIndex(bel)) != nullptr);
724 return decalxy;
725 }
726
getWireDecal(WireId wire) const727 DecalXY Arch::getWireDecal(WireId wire) const
728 {
729 DecalXY decalxy;
730 decalxy.decal.type = DecalId::TYPE_WIRE;
731 decalxy.decal.location = wire.location;
732 decalxy.decal.z = wire.index;
733 decalxy.decal.active = getBoundWireNet(wire) != nullptr;
734 return decalxy;
735 }
736
getPipDecal(PipId pip) const737 DecalXY Arch::getPipDecal(PipId pip) const
738 {
739 DecalXY decalxy;
740 decalxy.decal.type = DecalId::TYPE_PIP;
741 decalxy.decal.location = pip.location;
742 decalxy.decal.z = pip.index;
743 decalxy.decal.active = getBoundPipNet(pip) != nullptr;
744 return decalxy;
745 };
746
getGroupDecal(GroupId group) const747 DecalXY Arch::getGroupDecal(GroupId group) const
748 {
749 DecalXY decalxy;
750 decalxy.decal.type = DecalId::TYPE_GROUP;
751 decalxy.decal.location = group.location;
752 decalxy.decal.z = group.type;
753 decalxy.decal.active = true;
754 return decalxy;
755 }
756
757 // -----------------------------------------------------------------------
758
getDelayFromTimingDatabase(IdString tctype,IdString from,IdString to,DelayInfo & delay) const759 bool Arch::getDelayFromTimingDatabase(IdString tctype, IdString from, IdString to, DelayInfo &delay) const
760 {
761 auto fnd_dk = celldelay_cache.find({tctype, from, to});
762 if (fnd_dk != celldelay_cache.end()) {
763 delay = fnd_dk->second.second;
764 return fnd_dk->second.first;
765 }
766 for (int i = 0; i < speed_grade->num_cell_timings; i++) {
767 const auto &tc = speed_grade->cell_timings[i];
768 if (tc.cell_type == tctype.index) {
769 for (int j = 0; j < tc.num_prop_delays; j++) {
770 const auto &dly = tc.prop_delays[j];
771 if (dly.from_port == from.index && dly.to_port == to.index) {
772 delay.max_delay = dly.max_delay;
773 delay.min_delay = dly.min_delay;
774 celldelay_cache[{tctype, from, to}] = std::make_pair(true, delay);
775 return true;
776 }
777 }
778 celldelay_cache[{tctype, from, to}] = std::make_pair(false, DelayInfo());
779 return false;
780 }
781 }
782 NPNR_ASSERT_FALSE("failed to find timing cell in db");
783 }
784
getSetupHoldFromTimingDatabase(IdString tctype,IdString clock,IdString port,DelayInfo & setup,DelayInfo & hold) const785 void Arch::getSetupHoldFromTimingDatabase(IdString tctype, IdString clock, IdString port, DelayInfo &setup,
786 DelayInfo &hold) const
787 {
788 for (int i = 0; i < speed_grade->num_cell_timings; i++) {
789 const auto &tc = speed_grade->cell_timings[i];
790 if (tc.cell_type == tctype.index) {
791 for (int j = 0; j < tc.num_setup_holds; j++) {
792 const auto &sh = tc.setup_holds[j];
793 if (sh.clock_port == clock.index && sh.sig_port == port.index) {
794 setup.max_delay = sh.max_setup;
795 setup.min_delay = sh.min_setup;
796 hold.max_delay = sh.max_hold;
797 hold.min_delay = sh.min_hold;
798 return;
799 }
800 }
801 }
802 }
803 NPNR_ASSERT_FALSE("failed to find timing cell in db");
804 }
805
getCellDelay(const CellInfo * cell,IdString fromPort,IdString toPort,DelayInfo & delay) const806 bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
807 {
808 // Data for -8 grade
809 if (cell->type == id_TRELLIS_SLICE) {
810 bool has_carry = cell->sliceInfo.is_carry;
811 if (fromPort == id_A0 || fromPort == id_B0 || fromPort == id_C0 || fromPort == id_D0 || fromPort == id_A1 ||
812 fromPort == id_B1 || fromPort == id_C1 || fromPort == id_D1 || fromPort == id_M0 || fromPort == id_M1 ||
813 fromPort == id_FXA || fromPort == id_FXB || fromPort == id_FCI) {
814 return getDelayFromTimingDatabase(has_carry ? id_SCCU2C : id_SLOGICB, fromPort, toPort, delay);
815 }
816
817 if ((fromPort == id_A0 && toPort == id_WADO3) || (fromPort == id_A1 && toPort == id_WDO1) ||
818 (fromPort == id_B0 && toPort == id_WADO1) || (fromPort == id_B1 && toPort == id_WDO3) ||
819 (fromPort == id_C0 && toPort == id_WADO2) || (fromPort == id_C1 && toPort == id_WDO0) ||
820 (fromPort == id_D0 && toPort == id_WADO0) || (fromPort == id_D1 && toPort == id_WDO2)) {
821 delay.min_delay = 0;
822 delay.max_delay = 0;
823 return true;
824 }
825 return false;
826 } else if (cell->type == id_DCCA) {
827 if (fromPort == id_CLKI && toPort == id_CLKO) {
828 delay.min_delay = 0;
829 delay.max_delay = 0;
830 return true;
831 }
832 return false;
833 } else if (cell->type == id_DP16KD) {
834 return false;
835 } else if (cell->type == id_MULT18X18D) {
836 if (cell->multInfo.is_clocked)
837 return false;
838 std::string fn = fromPort.str(this), tn = toPort.str(this);
839 if (fn.size() > 1 && (fn.front() == 'A' || fn.front() == 'B') && std::isdigit(fn.at(1))) {
840 if (tn.size() > 1 && tn.front() == 'P' && std::isdigit(tn.at(1)))
841 return getDelayFromTimingDatabase(cell->multInfo.timing_id, id(std::string("") + fn.front()), id_P,
842 delay);
843 }
844 return false;
845 } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) {
846 return false;
847 } else {
848 return false;
849 }
850 }
851
getPortTimingClass(const CellInfo * cell,IdString port,int & clockInfoCount) const852 TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
853 {
854 auto disconnected = [cell](IdString p) { return !cell->ports.count(p) || cell->ports.at(p).net == nullptr; };
855 clockInfoCount = 0;
856 if (cell->type == id_TRELLIS_SLICE) {
857 int sd0 = cell->sliceInfo.sd0, sd1 = cell->sliceInfo.sd1;
858 if (port == id_CLK || port == id_WCK)
859 return TMG_CLOCK_INPUT;
860 if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 ||
861 port == id_D0 || port == id_D1 || port == id_FCI || port == id_FXA || port == id_FXB)
862 return TMG_COMB_INPUT;
863 if (port == id_F0 && disconnected(id_A0) && disconnected(id_B0) && disconnected(id_C0) && disconnected(id_D0) &&
864 disconnected(id_FCI))
865 return TMG_IGNORE; // LUT with no inputs is a constant
866 if (port == id_F1 && disconnected(id_A1) && disconnected(id_B1) && disconnected(id_C1) && disconnected(id_D1) &&
867 disconnected(id_FCI))
868 return TMG_IGNORE; // LUT with no inputs is a constant
869
870 if (port == id_F0 || port == id_F1 || port == id_FCO || port == id_OFX0 || port == id_OFX1)
871 return TMG_COMB_OUTPUT;
872 if (port == id_DI0 || port == id_DI1 || port == id_CE || port == id_LSR || (sd0 == 1 && port == id_M0) ||
873 (sd1 == 1 && port == id_M1)) {
874 clockInfoCount = 1;
875 return TMG_REGISTER_INPUT;
876 }
877 if (port == id_M0 || port == id_M1)
878 return TMG_COMB_INPUT;
879 if (port == id_Q0 || port == id_Q1) {
880 clockInfoCount = 1;
881 return TMG_REGISTER_OUTPUT;
882 }
883
884 if (port == id_WDO0 || port == id_WDO1 || port == id_WDO2 || port == id_WDO3 || port == id_WADO0 ||
885 port == id_WADO1 || port == id_WADO2 || port == id_WADO3)
886 return TMG_COMB_OUTPUT;
887
888 if (port == id_WD0 || port == id_WD1 || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 ||
889 port == id_WAD3 || port == id_WRE) {
890 clockInfoCount = 1;
891 return TMG_REGISTER_INPUT;
892 }
893
894 NPNR_ASSERT_FALSE_STR("no timing type for slice port '" + port.str(this) + "'");
895 } else if (cell->type == id_TRELLIS_IO) {
896 if (port == id_T || port == id_I)
897 return TMG_ENDPOINT;
898 if (port == id_O)
899 return TMG_STARTPOINT;
900 return TMG_IGNORE;
901 } else if (cell->type == id_DCCA) {
902 if (port == id_CLKI)
903 return TMG_COMB_INPUT;
904 if (port == id_CLKO)
905 return TMG_COMB_OUTPUT;
906 return TMG_IGNORE;
907 } else if (cell->type == id_DP16KD) {
908 if (port == id_CLKA || port == id_CLKB)
909 return TMG_CLOCK_INPUT;
910 std::string port_name = port.str(this);
911 for (auto c : boost::adaptors::reverse(port_name)) {
912 if (std::isdigit(c))
913 continue;
914 if (c == 'A' || c == 'B')
915 clockInfoCount = 1;
916 else
917 NPNR_ASSERT_FALSE_STR("bad ram port");
918 return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT;
919 }
920 NPNR_ASSERT_FALSE_STR("no timing type for RAM port '" + port.str(this) + "'");
921 } else if (cell->type == id_MULT18X18D) {
922 if (port == id_CLK0 || port == id_CLK1 || port == id_CLK2 || port == id_CLK3)
923 return TMG_CLOCK_INPUT;
924 if (port == id_CE0 || port == id_CE1 || port == id_CE2 || port == id_CE3 || port == id_RST0 ||
925 port == id_RST1 || port == id_RST2 || port == id_RST3 || port == id_SIGNEDA || port == id_SIGNEDB) {
926 if (cell->multInfo.is_clocked) {
927 clockInfoCount = 1;
928 return TMG_REGISTER_INPUT;
929 } else {
930 return TMG_COMB_INPUT;
931 }
932 }
933 std::string pname = port.str(this);
934 if (pname.size() > 1) {
935 if ((pname.front() == 'A' || pname.front() == 'B') && std::isdigit(pname.at(1))) {
936 if (cell->multInfo.is_clocked) {
937 clockInfoCount = 1;
938 return TMG_REGISTER_INPUT;
939 } else {
940 return TMG_COMB_INPUT;
941 }
942 }
943 if ((pname.front() == 'P') && std::isdigit(pname.at(1))) {
944 if (cell->multInfo.is_clocked) {
945 clockInfoCount = 1;
946 return TMG_REGISTER_OUTPUT;
947 } else {
948 return TMG_COMB_OUTPUT;
949 }
950 }
951 }
952 return TMG_IGNORE;
953 } else if (cell->type == id_ALU54B) {
954 return TMG_IGNORE; // FIXME
955 } else if (cell->type == id_EHXPLLL) {
956 return TMG_IGNORE;
957 } else if (cell->type == id_DCUA || cell->type == id_EXTREFB || cell->type == id_PCSCLKDIV) {
958 if (port == id_CH0_FF_TXI_CLK || port == id_CH0_FF_RXI_CLK || port == id_CH1_FF_TXI_CLK ||
959 port == id_CH1_FF_RXI_CLK)
960 return TMG_CLOCK_INPUT;
961 std::string prefix = port.str(this).substr(0, 9);
962 if (prefix == "CH0_FF_TX" || prefix == "CH0_FF_RX" || prefix == "CH1_FF_TX" || prefix == "CH1_FF_RX") {
963 clockInfoCount = 1;
964 return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT;
965 }
966 return TMG_IGNORE;
967 } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) {
968 if (port == id_CLK || port == id_ECLK) {
969 return TMG_CLOCK_INPUT;
970 } else if (port == id_IOLDO || port == id_IOLDOI || port == id_IOLDOD || port == id_IOLTO || port == id_PADDI ||
971 port == id_DQSR90 || port == id_DQSW || port == id_DQSW270) {
972 return TMG_IGNORE;
973 } else {
974 clockInfoCount = 1;
975 return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT;
976 }
977 } else if (cell->type == id_DTR || cell->type == id_USRMCLK || cell->type == id_SEDGA || cell->type == id_GSR ||
978 cell->type == id_JTAGG) {
979 return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
980 } else if (cell->type == id_OSCG) {
981 if (port == id_OSC)
982 return TMG_GEN_CLOCK;
983 else
984 return TMG_IGNORE;
985 } else if (cell->type == id_CLKDIVF) {
986 if (port == id_CLKI)
987 return TMG_CLOCK_INPUT;
988 else if (port == id_RST || port == id_ALIGNWD)
989 return TMG_ENDPOINT;
990 else if (port == id_CDIVX)
991 return TMG_GEN_CLOCK;
992 else
993 NPNR_ASSERT_FALSE("bad clkdiv port");
994 } else if (cell->type == id_DQSBUFM) {
995 if (port == id_READ0 || port == id_READ1) {
996 clockInfoCount = 1;
997 return TMG_REGISTER_INPUT;
998 } else if (port == id_DATAVALID) {
999 clockInfoCount = 1;
1000 return TMG_REGISTER_OUTPUT;
1001 } else if (port == id_SCLK || port == id_ECLK || port == id_DQSI) {
1002 return TMG_CLOCK_INPUT;
1003 } else if (port == id_DQSR90 || port == id_DQSW || port == id_DQSW270) {
1004 return TMG_GEN_CLOCK;
1005 }
1006 return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
1007 } else if (cell->type == id_DDRDLL) {
1008 if (port == id_CLK)
1009 return TMG_CLOCK_INPUT;
1010 return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
1011 } else if (cell->type == id_TRELLIS_ECLKBUF) {
1012 return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
1013 } else if (cell->type == id_ECLKSYNCB) {
1014 if (cell->ports.at(port).name == id_STOP)
1015 return TMG_ENDPOINT;
1016 return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
1017 } else if (cell->type == id_ECLKBRIDGECS) {
1018 if (cell->ports.at(port).name == id_SEL)
1019 return TMG_ENDPOINT;
1020 return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
1021 } else {
1022 log_error("cell type '%s' is unsupported (instantiated as '%s')\n", cell->type.c_str(this),
1023 cell->name.c_str(this));
1024 }
1025 }
1026
getPortClockingInfo(const CellInfo * cell,IdString port,int index) const1027 TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
1028 {
1029 TimingClockingInfo info;
1030 info.setup = getDelayFromNS(0);
1031 info.hold = getDelayFromNS(0);
1032 info.clockToQ = getDelayFromNS(0);
1033 if (cell->type == id_TRELLIS_SLICE) {
1034 int sd0 = cell->sliceInfo.sd0, sd1 = cell->sliceInfo.sd1;
1035 if (port == id_WD0 || port == id_WD1 || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 ||
1036 port == id_WAD3 || port == id_WRE) {
1037 info.edge = RISING_EDGE;
1038 info.clock_port = id_WCK;
1039 getSetupHoldFromTimingDatabase(id_SDPRAME, id_WCK, port, info.setup, info.hold);
1040 } else if (port == id_DI0 || port == id_DI1 || port == id_CE || port == id_LSR || (sd0 == 1 && port == id_M0) ||
1041 (sd1 == 1 && port == id_M1)) {
1042 info.edge = cell->sliceInfo.clkmux == id("INV") ? FALLING_EDGE : RISING_EDGE;
1043 info.clock_port = id_CLK;
1044 getSetupHoldFromTimingDatabase(id_SLOGICB, id_CLK, port, info.setup, info.hold);
1045
1046 } else {
1047 info.edge = cell->sliceInfo.clkmux == id("INV") ? FALLING_EDGE : RISING_EDGE;
1048 info.clock_port = id_CLK;
1049 bool is_path = getDelayFromTimingDatabase(id_SLOGICB, id_CLK, port, info.clockToQ);
1050 NPNR_ASSERT(is_path);
1051 }
1052 } else if (cell->type == id_DP16KD) {
1053 std::string port_name = port.str(this);
1054 IdString half_clock;
1055 for (auto c : boost::adaptors::reverse(port_name)) {
1056 if (std::isdigit(c))
1057 continue;
1058 if (c == 'A') {
1059 half_clock = id_CLKA;
1060 break;
1061 } else if (c == 'B') {
1062 half_clock = id_CLKB;
1063 break;
1064 } else
1065 NPNR_ASSERT_FALSE_STR("bad ram port " + port.str(this));
1066 }
1067 if (cell->ramInfo.is_pdp) {
1068 bool is_output = cell->ports.at(port).type == PORT_OUT;
1069 // In PDP mode, all read signals are in CLKB domain and write signals in CLKA domain
1070 if (is_output || port == id_OCEB || port == id_CEB || port == id_ADB5 || port == id_ADB6 ||
1071 port == id_ADB7 || port == id_ADB8 || port == id_ADB9 || port == id_ADB10 || port == id_ADB11 ||
1072 port == id_ADB12 || port == id_ADB13)
1073 info.clock_port = id_CLKB;
1074 else
1075 info.clock_port = id_CLKA;
1076 } else {
1077 info.clock_port = half_clock;
1078 }
1079 info.edge = (str_or_default(cell->params, info.clock_port == id_CLKB ? id("CLKBMUX") : id("CLKAMUX"), "CLK") ==
1080 "INV")
1081 ? FALLING_EDGE
1082 : RISING_EDGE;
1083 if (cell->ports.at(port).type == PORT_OUT) {
1084 bool is_path = getDelayFromTimingDatabase(cell->ramInfo.regmode_timing_id, half_clock, port, info.clockToQ);
1085 NPNR_ASSERT(is_path);
1086 } else {
1087 getSetupHoldFromTimingDatabase(cell->ramInfo.regmode_timing_id, half_clock, port, info.setup, info.hold);
1088 }
1089 } else if (cell->type == id_DCUA) {
1090 std::string prefix = port.str(this).substr(0, 9);
1091 info.edge = RISING_EDGE;
1092 if (prefix == "CH0_FF_TX")
1093 info.clock_port = id_CH0_FF_TXI_CLK;
1094 else if (prefix == "CH0_FF_RX")
1095 info.clock_port = id_CH0_FF_RXI_CLK;
1096 else if (prefix == "CH1_FF_TX")
1097 info.clock_port = id_CH1_FF_TXI_CLK;
1098 else if (prefix == "CH1_FF_RX")
1099 info.clock_port = id_CH1_FF_RXI_CLK;
1100 if (cell->ports.at(port).type == PORT_OUT) {
1101 info.clockToQ = getDelayFromNS(0.7);
1102 } else {
1103 info.setup = getDelayFromNS(1);
1104 info.hold = getDelayFromNS(0);
1105 }
1106 } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) {
1107 info.clock_port = id_CLK;
1108 if (cell->ports.at(port).type == PORT_OUT) {
1109 info.clockToQ = getDelayFromNS(0.5);
1110 } else {
1111 info.setup = getDelayFromNS(0.1);
1112 info.hold = getDelayFromNS(0);
1113 }
1114 } else if (cell->type == id_DQSBUFM) {
1115 info.clock_port = id_SCLK;
1116 if (port == id_DATAVALID) {
1117 info.clockToQ = getDelayFromNS(0.2);
1118 } else if (port == id_READ0 || port == id_READ1) {
1119 info.setup = getDelayFromNS(0.5);
1120 info.hold = getDelayFromNS(-0.4);
1121 } else {
1122 NPNR_ASSERT_FALSE("unknown DQSBUFM register port");
1123 }
1124 } else if (cell->type == id_MULT18X18D) {
1125 std::string port_name = port.str(this);
1126 // To keep the timing DB small, like signals (e.g. P[35:0] have been
1127 // grouped. To look up the timing, we therefore need to map this port
1128 // to the enclosing port group.
1129 auto has_prefix = [](std::string base, std::string prefix) {
1130 return base.compare(0, prefix.size(), prefix) == 0;
1131 };
1132 IdString port_group;
1133 if (has_prefix(port_name, "A")) {
1134 port_group = id_A;
1135 } else if (has_prefix(port_name, "B")) {
1136 port_group = id_B;
1137 } else if (has_prefix(port_name, "P")) {
1138 port_group = id_P;
1139 } else if (has_prefix(port_name, "CE")) {
1140 port_group = id_CE0;
1141 } else if (has_prefix(port_name, "RST")) {
1142 port_group = id_RST0;
1143 } else if (has_prefix(port_name, "SIGNED")) {
1144 // Both SIGNEDA and SIGNEDB exist in the DB, so can directly use these here
1145 port_group = port;
1146 } else {
1147 NPNR_ASSERT_FALSE("Unknown MULT18X18D register port");
1148 }
1149
1150 // If this port is clocked at all, it must be clocked from CLK0
1151 IdString clock_id = id_CLK0;
1152 info.clock_port = clock_id;
1153 info.edge = RISING_EDGE;
1154 if (cell->ports.at(port).type == PORT_OUT) {
1155 bool is_path = getDelayFromTimingDatabase(cell->multInfo.timing_id, clock_id, port_group, info.clockToQ);
1156 NPNR_ASSERT(is_path);
1157 } else {
1158 getSetupHoldFromTimingDatabase(cell->multInfo.timing_id, clock_id, port_group, info.setup, info.hold);
1159 }
1160 }
1161 return info;
1162 }
1163
getTilesAtLocation(int row,int col)1164 std::vector<std::pair<std::string, std::string>> Arch::getTilesAtLocation(int row, int col)
1165 {
1166 std::vector<std::pair<std::string, std::string>> ret;
1167 auto &tileloc = chip_info->tile_info[row * chip_info->width + col];
1168 for (int i = 0; i < tileloc.num_tiles; i++) {
1169 ret.push_back(std::make_pair(tileloc.tile_names[i].name.get(),
1170 chip_info->tiletype_names[tileloc.tile_names[i].type_idx].get()));
1171 }
1172 return ret;
1173 }
1174
globalInfoAtLoc(Location loc)1175 GlobalInfoPOD Arch::globalInfoAtLoc(Location loc)
1176 {
1177 int locidx = loc.y * chip_info->width + loc.x;
1178 return chip_info->location_glbinfo[locidx];
1179 }
1180
getPIODQSGroup(BelId pio,bool & dqsright,int & dqsrow)1181 bool Arch::getPIODQSGroup(BelId pio, bool &dqsright, int &dqsrow)
1182 {
1183 for (int i = 0; i < chip_info->num_pios; i++) {
1184 if (Location(chip_info->pio_info[i].abs_loc) == pio.location && chip_info->pio_info[i].bel_index == pio.index) {
1185 int dqs = chip_info->pio_info[i].dqsgroup;
1186 if (dqs == -1)
1187 return false;
1188 else {
1189 dqsright = (dqs & 2048) != 0;
1190 dqsrow = dqs & 0x1FF;
1191 return true;
1192 }
1193 }
1194 }
1195 NPNR_ASSERT_FALSE("failed to find PIO");
1196 }
1197
getDQSBUF(bool dqsright,int dqsrow)1198 BelId Arch::getDQSBUF(bool dqsright, int dqsrow)
1199 {
1200 BelId bel;
1201 bel.location.y = dqsrow;
1202 bel.location.x = (dqsright ? (chip_info->width - 1) : 0);
1203 for (int i = 0; i < locInfo(bel)->num_bels; i++) {
1204 auto &bd = locInfo(bel)->bel_data[i];
1205 if (bd.type == id_DQSBUFM.index) {
1206 bel.index = i;
1207 return bel;
1208 }
1209 }
1210 NPNR_ASSERT_FALSE("failed to find DQSBUF");
1211 }
1212
getBankECLK(int bank,int eclk)1213 WireId Arch::getBankECLK(int bank, int eclk)
1214 {
1215 return getWireByLocAndBasename(Location(0, 0), "G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(eclk));
1216 }
1217
1218 #ifdef WITH_HEAP
1219 const std::string Arch::defaultPlacer = "heap";
1220 #else
1221 const std::string Arch::defaultPlacer = "sa";
1222 #endif
1223
1224 const std::vector<std::string> Arch::availablePlacers = {"sa",
1225 #ifdef WITH_HEAP
1226 "heap"
1227 #endif
1228 };
1229
1230 const std::string Arch::defaultRouter = "router1";
1231 const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
1232
1233 // -----------------------------------------------------------------------
1234
getGroupByName(IdString name) const1235 GroupId Arch::getGroupByName(IdString name) const
1236 {
1237 for (auto g : getGroups())
1238 if (getGroupName(g) == name)
1239 return g;
1240 return GroupId();
1241 }
1242
getGroupName(GroupId group) const1243 IdString Arch::getGroupName(GroupId group) const
1244 {
1245 std::string suffix;
1246
1247 switch (group.type) {
1248 case GroupId::TYPE_SWITCHBOX:
1249 suffix = "switchbox";
1250 break;
1251 default:
1252 return IdString();
1253 }
1254
1255 return id("X" + std::to_string(group.location.x) + "/Y" + std::to_string(group.location.y) + "/" + suffix);
1256 }
1257
getGroups() const1258 std::vector<GroupId> Arch::getGroups() const
1259 {
1260 std::vector<GroupId> ret;
1261
1262 for (int y = 1; y < chip_info->height - 1; y++) {
1263 for (int x = 1; x < chip_info->width - 1; x++) {
1264 GroupId group;
1265 group.type = GroupId::TYPE_SWITCHBOX;
1266 group.location.x = x;
1267 group.location.y = y;
1268 ret.push_back(group);
1269 }
1270 }
1271 return ret;
1272 }
1273
getGroupBels(GroupId group) const1274 std::vector<BelId> Arch::getGroupBels(GroupId group) const
1275 {
1276 std::vector<BelId> ret;
1277 return ret;
1278 }
1279
getGroupWires(GroupId group) const1280 std::vector<WireId> Arch::getGroupWires(GroupId group) const
1281 {
1282 std::vector<WireId> ret;
1283 return ret;
1284 }
1285
getGroupPips(GroupId group) const1286 std::vector<PipId> Arch::getGroupPips(GroupId group) const
1287 {
1288 std::vector<PipId> ret;
1289 return ret;
1290 }
1291
getGroupGroups(GroupId group) const1292 std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
1293 {
1294 std::vector<GroupId> ret;
1295 return ret;
1296 }
1297
1298 // -----------------------------------------------------------------------
1299
getWireAttrs(WireId wire) const1300 std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const
1301 {
1302 std::vector<std::pair<IdString, std::string>> ret;
1303 auto &wi = locInfo(wire)->wire_data[wire.index];
1304
1305 ret.push_back(std::make_pair(id("TILE_WIRE_ID"), stringf("%d", wi.tile_wire)));
1306
1307 return ret;
1308 }
1309 NEXTPNR_NAMESPACE_END
1310