1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef _DML2_WRAPPER_H_ 28 #define _DML2_WRAPPER_H_ 29 30 #include "os_types.h" 31 32 #define DML2_MAX_NUM_DPM_LVL 30 33 34 struct dml2_context; 35 struct display_mode_lib_st; 36 struct dc; 37 struct pipe_ctx; 38 struct dc_plane_state; 39 struct dc_sink; 40 struct dc_stream_state; 41 struct resource_context; 42 struct display_stream_compressor; 43 44 // Configuration of the MALL on the SoC 45 struct dml2_soc_mall_info { 46 // Cache line size of 0 means MALL is not enabled/present 47 unsigned int cache_line_size_bytes; 48 unsigned int cache_num_ways; 49 unsigned int max_cab_allocation_bytes; 50 51 unsigned int mblk_width_pixels; 52 unsigned int mblk_size_bytes; 53 unsigned int mblk_height_4bpe_pixels; 54 unsigned int mblk_height_8bpe_pixels; 55 }; 56 57 // Output of DML2 for clock requirements 58 struct dml2_dcn_clocks { 59 unsigned int dispclk_khz; 60 unsigned int dcfclk_khz; 61 unsigned int fclk_khz; 62 unsigned int uclk_mts; 63 unsigned int phyclk_khz; 64 unsigned int socclk_khz; 65 unsigned int ref_dtbclk_khz; 66 bool p_state_supported; 67 unsigned int cab_num_ways_required; 68 unsigned int dcfclk_khz_ds; 69 }; 70 71 struct dml2_dc_callbacks { 72 struct dc *dc; 73 bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx); 74 void (*build_test_pattern_params)(struct resource_context *res_ctx, struct pipe_ctx *otg_master); 75 bool (*can_support_mclk_switch_using_fw_based_vblank_stretch)(struct dc *dc, struct dc_state *context); 76 bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm); 77 bool (*update_pipes_for_stream_with_slice_count)( 78 struct dc_state *new_ctx, 79 const struct dc_state *cur_ctx, 80 const struct resource_pool *pool, 81 const struct dc_stream_state *stream, 82 int new_slice_count); 83 bool (*update_pipes_for_plane_with_slice_count)( 84 struct dc_state *new_ctx, 85 const struct dc_state *cur_ctx, 86 const struct resource_pool *pool, 87 const struct dc_plane_state *plane, 88 int slice_count); 89 int (*get_odm_slice_index)(const struct pipe_ctx *opp_head); 90 int (*get_odm_slice_count)(const struct pipe_ctx *opp_head); 91 int (*get_mpc_slice_index)(const struct pipe_ctx *dpp_pipe); 92 int (*get_mpc_slice_count)(const struct pipe_ctx *dpp_pipe); 93 struct pipe_ctx *(*get_opp_head)(const struct pipe_ctx *pipe_ctx); 94 struct pipe_ctx *(*get_otg_master_for_stream)( 95 struct resource_context *res_ctx, 96 const struct dc_stream_state *stream); 97 int (*get_opp_heads_for_otg_master)(const struct pipe_ctx *otg_master, 98 struct resource_context *res_ctx, 99 struct pipe_ctx *opp_heads[MAX_PIPES]); 100 int (*get_dpp_pipes_for_plane)(const struct dc_plane_state *plane, 101 struct resource_context *res_ctx, 102 struct pipe_ctx *dpp_pipes[MAX_PIPES]); 103 struct dc_stream_status *(*get_stream_status)( 104 struct dc_state *state, 105 const struct dc_stream_state *stream); 106 struct dc_stream_state *(*get_stream_from_id)(const struct dc_state *state, unsigned int id); 107 }; 108 109 struct dml2_dc_svp_callbacks { 110 struct dc *dc; 111 bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx); 112 struct dc_stream_state* (*create_phantom_stream)(const struct dc *dc, 113 struct dc_state *state, 114 struct dc_stream_state *main_stream); 115 struct dc_plane_state* (*create_phantom_plane)(const struct dc *dc, 116 struct dc_state *state, 117 struct dc_plane_state *main_plane); 118 enum dc_status (*add_phantom_stream)(const struct dc *dc, 119 struct dc_state *state, 120 struct dc_stream_state *phantom_stream, 121 struct dc_stream_state *main_stream); 122 bool (*add_phantom_plane)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context); 123 bool (*remove_phantom_plane)(const struct dc *dc, 124 struct dc_stream_state *stream, 125 struct dc_plane_state *plane_state, 126 struct dc_state *context); 127 enum dc_status (*remove_phantom_stream)(const struct dc *dc, 128 struct dc_state *state, 129 struct dc_stream_state *stream); 130 void (*release_phantom_plane)(const struct dc *dc, 131 struct dc_state *state, 132 struct dc_plane_state *plane); 133 void (*release_phantom_stream)(const struct dc *dc, 134 struct dc_state *state, 135 struct dc_stream_state *stream); 136 void (*release_dsc)(struct resource_context *res_ctx, const struct resource_pool *pool, struct display_stream_compressor **dsc); 137 enum mall_stream_type (*get_pipe_subvp_type)(const struct dc_state *state, const struct pipe_ctx *pipe_ctx); 138 enum mall_stream_type (*get_stream_subvp_type)(const struct dc_state *state, const struct dc_stream_state *stream); 139 struct dc_stream_state *(*get_paired_subvp_stream)(const struct dc_state *state, const struct dc_stream_state *stream); 140 bool (*remove_phantom_streams_and_planes)( 141 const struct dc *dc, 142 struct dc_state *state); 143 void (*release_phantom_streams_and_planes)( 144 const struct dc *dc, 145 struct dc_state *state); 146 unsigned int (*calculate_mall_ways_from_bytes)( 147 const struct dc *dc, 148 unsigned int total_size_in_mall_bytes); 149 }; 150 151 struct dml2_clks_table_entry { 152 unsigned int dcfclk_mhz; 153 unsigned int fclk_mhz; 154 unsigned int memclk_mhz; 155 unsigned int socclk_mhz; 156 unsigned int dtbclk_mhz; 157 unsigned int dispclk_mhz; 158 unsigned int dppclk_mhz; 159 }; 160 161 struct dml2_clks_num_entries { 162 unsigned int num_dcfclk_levels; 163 unsigned int num_fclk_levels; 164 unsigned int num_memclk_levels; 165 unsigned int num_socclk_levels; 166 unsigned int num_dtbclk_levels; 167 unsigned int num_dispclk_levels; 168 unsigned int num_dppclk_levels; 169 }; 170 171 struct dml2_clks_limit_table { 172 struct dml2_clks_table_entry clk_entries[DML2_MAX_NUM_DPM_LVL]; 173 struct dml2_clks_num_entries num_entries_per_clk; 174 unsigned int num_states; 175 }; 176 177 // Various overrides, per ASIC or per SKU specific, or for debugging purpose when/if available 178 struct dml2_soc_bbox_overrides { 179 double xtalclk_mhz; 180 double dchub_refclk_mhz; 181 double dprefclk_mhz; 182 double disp_pll_vco_speed_mhz; 183 double urgent_latency_us; 184 double sr_exit_latency_us; 185 double sr_enter_plus_exit_latency_us; 186 double sr_exit_z8_time_us; 187 double sr_enter_plus_exit_z8_time_us; 188 double dram_clock_change_latency_us; 189 double fclk_change_latency_us; 190 unsigned int dram_num_chan; 191 unsigned int dram_chanel_width_bytes; 192 struct dml2_clks_limit_table clks_table; 193 }; 194 195 struct dml2_configuration_options { 196 int dcn_pipe_count; 197 bool use_native_pstate_optimization; 198 bool enable_windowed_mpo_odm; 199 bool use_native_soc_bb_construction; 200 bool skip_hw_state_mapping; 201 bool optimize_odm_4to1; 202 bool minimize_dispclk_using_odm; 203 bool override_det_buffer_size_kbytes; 204 struct dml2_dc_callbacks callbacks; 205 struct { 206 bool force_disable_subvp; 207 bool force_enable_subvp; 208 unsigned int subvp_fw_processing_delay_us; 209 unsigned int subvp_pstate_allow_width_us; 210 unsigned int subvp_prefetch_end_to_mall_start_us; 211 unsigned int subvp_swath_height_margin_lines; 212 struct dml2_dc_svp_callbacks callbacks; 213 } svp_pstate; 214 struct dml2_soc_mall_info mall_cfg; 215 struct dml2_soc_bbox_overrides bbox_overrides; 216 unsigned int max_segments_per_hubp; 217 unsigned int det_segment_size; 218 bool map_dc_pipes_with_callbacks; 219 220 bool use_clock_dc_limits; 221 }; 222 223 /* 224 * dml2_create - Creates dml2_context. 225 * @in_dc: dc. 226 * @config: dml2 configuration options. 227 * @dml2: Created dml2 context. 228 * 229 * Create and destroy of DML2 is done as part of dc_state creation 230 * and dc_state_free. DML2 IP, SOC and STATES are initialized at 231 * creation time. 232 * 233 * Return: True if dml2 is successfully created, false otherwise. 234 */ 235 bool dml2_create(const struct dc *in_dc, 236 const struct dml2_configuration_options *config, 237 struct dml2_context **dml2); 238 239 void dml2_destroy(struct dml2_context *dml2); 240 void dml2_copy(struct dml2_context *dst_dml2, 241 struct dml2_context *src_dml2); 242 bool dml2_create_copy(struct dml2_context **dst_dml2, 243 struct dml2_context *src_dml2); 244 void dml2_reinit(const struct dc *in_dc, 245 const struct dml2_configuration_options *config, 246 struct dml2_context **dml2); 247 248 /* 249 * dml2_validate - Determines if a display configuration is supported or not. 250 * @in_dc: dc. 251 * @context: dc_state to be validated. 252 * @fast_validate: Fast validate will not populate context.res_ctx. 253 * 254 * DML1.0 compatible interface for validation. 255 * 256 * Based on fast_validate option internally would call: 257 * 258 * -dml2_validate_and_build_resource - for non fast_validate option 259 * Calculates if dc_state can be supported on the SOC, and attempts to 260 * optimize the power management feature supports versus minimum clocks. 261 * If supported, also builds out_new_hw_state to represent the hw programming 262 * for the new dc state. 263 * 264 * -dml2_validate_only - for fast_validate option 265 * Calculates if dc_state can be supported on the SOC (i.e. at maximum 266 * clocks) with all mandatory power features enabled. 267 268 * Context: Two threads may not invoke this function concurrently unless they reference 269 * separate dc_states for validation. 270 * Return: True if mode is supported, false otherwise. 271 */ 272 bool dml2_validate(const struct dc *in_dc, 273 struct dc_state *context, 274 struct dml2_context *dml2, 275 bool fast_validate); 276 277 /* 278 * dml2_extract_dram_and_fclk_change_support - Extracts the FCLK and UCLK change support info. 279 * @dml2: input dml2 context pointer. 280 * @fclk_change_support: output pointer holding the fclk change support info (vactive, vblank, unsupported). 281 * @dram_clk_change_support: output pointer holding the uclk change support info (vactive, vblank, unsupported). 282 */ 283 void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2, 284 unsigned int *fclk_change_support, unsigned int *dram_clk_change_support); 285 286 #endif //_DML2_WRAPPER_H_ 287