1 /*-
2 * Copyright (c) 2016 Stormshield
3 * Copyright (c) 2016 Semihalf
4 * All rights reserved.
5 *
6 * Developed by Semihalf.
7 *
8 * Portions of this software were developed by Semihalf
9 * under sponsorship from the FreeBSD Foundation.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. Neither the name of MARVELL nor the names of contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36 /*
37 * Marvell integrated PCI/PCI-Express Bus Controller Driver.
38 */
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/lock.h>
44 #include <sys/malloc.h>
45 #include <sys/module.h>
46 #include <sys/bus.h>
47 #include <sys/rman.h>
48
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
51
52 static int mv_pcib_ctrl_probe(device_t);
53 static int mv_pcib_ctrl_attach(device_t);
54 static device_t mv_pcib_ctrl_add_child(device_t, u_int, const char *, int);
55 static const struct ofw_bus_devinfo * mv_pcib_ctrl_get_devinfo(device_t, device_t);
56 static struct resource * mv_pcib_ctrl_alloc_resource(device_t, device_t, int,
57 int *, rman_res_t, rman_res_t, rman_res_t, u_int);
58 void mv_pcib_ctrl_init(device_t, phandle_t);
59 static int mv_pcib_ofw_bus_attach(device_t);
60
61 struct mv_pcib_ctrl_range {
62 uint64_t bus;
63 uint64_t host;
64 uint64_t size;
65 };
66
67 typedef int (*get_rl_t)(device_t dev, phandle_t node, pcell_t acells,
68 pcell_t scells, struct resource_list *rl);
69
70 struct mv_pcib_ctrl_softc {
71 pcell_t addr_cells;
72 pcell_t size_cells;
73 int nranges;
74 struct mv_pcib_ctrl_range *ranges;
75 };
76
77 struct mv_pcib_ctrl_devinfo {
78 struct ofw_bus_devinfo di_dinfo;
79 struct resource_list di_rl;
80 };
81
82 static int mv_pcib_ctrl_fill_ranges(phandle_t, struct mv_pcib_ctrl_softc *);
83
84 /*
85 * Bus interface definitions
86 */
87 static device_method_t mv_pcib_ctrl_methods[] = {
88 /* Device interface */
89 DEVMETHOD(device_probe, mv_pcib_ctrl_probe),
90 DEVMETHOD(device_attach, mv_pcib_ctrl_attach),
91
92 /* Bus interface */
93 DEVMETHOD(bus_add_child, mv_pcib_ctrl_add_child),
94 DEVMETHOD(bus_alloc_resource, mv_pcib_ctrl_alloc_resource),
95 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
96 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
97 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
98 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
99
100 /* ofw_bus interface */
101 DEVMETHOD(ofw_bus_get_devinfo, mv_pcib_ctrl_get_devinfo),
102 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
103 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
104 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
105 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
106 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
107
108 DEVMETHOD_END
109 };
110
111 static struct ofw_compat_data mv_pcib_ctrl_compat[] = {
112 {"mrvl,pcie-ctrl", (uintptr_t)&ofw_bus_reg_to_rl},
113 {"marvell,armada-370-pcie",
114 (uintptr_t)&ofw_bus_assigned_addresses_to_rl},
115 {NULL, (uintptr_t)NULL},
116 };
117
118 static driver_t mv_pcib_ctrl_driver = {
119 "pcib_ctrl",
120 mv_pcib_ctrl_methods,
121 sizeof(struct mv_pcib_ctrl_softc),
122 };
123
124 DRIVER_MODULE(pcib_ctrl, simplebus, mv_pcib_ctrl_driver, 0, 0);
125
126 MALLOC_DEFINE(M_PCIB_CTRL, "PCIe Bus Controller",
127 "Marvell Integrated PCIe Bus Controller");
128
129 static int
mv_pcib_ctrl_probe(device_t dev)130 mv_pcib_ctrl_probe(device_t dev)
131 {
132
133 if (!ofw_bus_status_okay(dev))
134 return (ENXIO);
135
136 if (!ofw_bus_search_compatible(dev, mv_pcib_ctrl_compat)->ocd_data)
137 return (ENXIO);
138
139 device_set_desc(dev, "Marvell Integrated PCIe Bus Controller");
140 return (BUS_PROBE_DEFAULT);
141 }
142
143 static int
mv_pcib_ctrl_attach(device_t dev)144 mv_pcib_ctrl_attach(device_t dev)
145 {
146 int err;
147
148 err = mv_pcib_ofw_bus_attach(dev);
149 if (err != 0)
150 return (err);
151
152 return (bus_generic_attach(dev));
153 }
154
155 static int
mv_pcib_ofw_bus_attach(device_t dev)156 mv_pcib_ofw_bus_attach(device_t dev)
157 {
158 struct mv_pcib_ctrl_devinfo *di;
159 struct mv_pcib_ctrl_softc *sc;
160 device_t child;
161 phandle_t parent, node;
162 get_rl_t get_rl;
163
164 parent = ofw_bus_get_node(dev);
165 sc = device_get_softc(dev);
166 if (parent > 0) {
167 sc->addr_cells = 1;
168 if (OF_getencprop(parent, "#address-cells", &(sc->addr_cells),
169 sizeof(sc->addr_cells)) <= 0)
170 return(ENXIO);
171
172 sc->size_cells = 1;
173 if (OF_getencprop(parent, "#size-cells", &(sc->size_cells),
174 sizeof(sc->size_cells)) <= 0)
175 return(ENXIO);
176
177 for (node = OF_child(parent); node > 0; node = OF_peer(node)) {
178 di = malloc(sizeof(*di), M_PCIB_CTRL, M_WAITOK | M_ZERO);
179 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node)) {
180 if (bootverbose) {
181 device_printf(dev,
182 "Could not set up devinfo for PCI\n");
183 }
184 free(di, M_PCIB_CTRL);
185 continue;
186 }
187
188 child = device_add_child(dev, NULL, -1);
189 if (child == NULL) {
190 if (bootverbose) {
191 device_printf(dev,
192 "Could not add child: %s\n",
193 di->di_dinfo.obd_name);
194 }
195 ofw_bus_gen_destroy_devinfo(&di->di_dinfo);
196 free(di, M_PCIB_CTRL);
197 continue;
198 }
199
200 resource_list_init(&di->di_rl);
201 get_rl = (get_rl_t) ofw_bus_search_compatible(dev,
202 mv_pcib_ctrl_compat)->ocd_data;
203 if (get_rl != NULL)
204 get_rl(child, node, sc->addr_cells,
205 sc->size_cells, &di->di_rl);
206
207 device_set_ivars(child, di);
208 }
209 }
210
211 if (mv_pcib_ctrl_fill_ranges(parent, sc) < 0) {
212 device_printf(dev, "could not get ranges\n");
213 return (ENXIO);
214 }
215
216 return (0);
217 }
218
219 static device_t
mv_pcib_ctrl_add_child(device_t dev,u_int order,const char * name,int unit)220 mv_pcib_ctrl_add_child(device_t dev, u_int order, const char *name, int unit)
221 {
222 device_t cdev;
223 struct mv_pcib_ctrl_devinfo *di;
224
225 cdev = device_add_child_ordered(dev, order, name, unit);
226 if (cdev == NULL)
227 return (NULL);
228
229 di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO);
230 di->di_dinfo.obd_node = -1;
231 resource_list_init(&di->di_rl);
232 device_set_ivars(cdev, di);
233
234 return (cdev);
235 }
236
237 static struct resource *
mv_pcib_ctrl_alloc_resource(device_t bus,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)238 mv_pcib_ctrl_alloc_resource(device_t bus, device_t child, int type, int *rid,
239 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
240 {
241 struct mv_pcib_ctrl_devinfo *di;
242 struct resource_list_entry *rle;
243 struct mv_pcib_ctrl_softc *sc;
244 int i;
245
246 if (RMAN_IS_DEFAULT_RANGE(start, end)) {
247 if ((di = device_get_ivars(child)) == NULL)
248 return (NULL);
249 if (type != SYS_RES_MEMORY)
250 return (NULL);
251
252 /* Find defaults for this rid */
253 rle = resource_list_find(&di->di_rl, type, *rid);
254
255 if (rle == NULL)
256 return (NULL);
257
258 start = rle->start;
259 end = rle->end;
260 count = rle->count;
261 }
262
263 sc = device_get_softc(bus);
264 if (type == SYS_RES_MEMORY) {
265 /* Remap through ranges property */
266 for (i = 0; i < sc->nranges; i++) {
267 if (start >= sc->ranges[i].bus && end <
268 sc->ranges[i].bus + sc->ranges[i].size) {
269 start -= sc->ranges[i].bus;
270 start += sc->ranges[i].host;
271 end -= sc->ranges[i].bus;
272 end += sc->ranges[i].host;
273 break;
274 }
275 }
276
277 if (i == sc->nranges && sc->nranges != 0) {
278 device_printf(bus, "Could not map resource "
279 "%#llx-%#llx\n", start, end);
280 return (NULL);
281 }
282 }
283
284 return (bus_generic_alloc_resource(bus, child, type, rid, start, end,
285 count, flags));
286 }
287
288 static int
mv_pcib_ctrl_fill_ranges(phandle_t node,struct mv_pcib_ctrl_softc * sc)289 mv_pcib_ctrl_fill_ranges(phandle_t node, struct mv_pcib_ctrl_softc *sc)
290 {
291 int host_address_cells;
292 cell_t *base_ranges;
293 ssize_t nbase_ranges;
294 int err;
295 int i, j, k;
296
297 err = OF_searchencprop(OF_parent(node), "#address-cells",
298 &host_address_cells, sizeof(host_address_cells));
299 if (err <= 0)
300 return (-1);
301
302 nbase_ranges = OF_getproplen(node, "ranges");
303 if (nbase_ranges < 0)
304 return (-1);
305 sc->nranges = nbase_ranges / sizeof(cell_t) /
306 (sc->addr_cells + host_address_cells + sc->size_cells);
307 if (sc->nranges == 0)
308 return (0);
309
310 sc->ranges = malloc(sc->nranges * sizeof(sc->ranges[0]),
311 M_DEVBUF, M_WAITOK);
312 base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK);
313 OF_getencprop(node, "ranges", base_ranges, nbase_ranges);
314
315 for (i = 0, j = 0; i < sc->nranges; i++) {
316 sc->ranges[i].bus = 0;
317 for (k = 0; k < sc->addr_cells; k++) {
318 sc->ranges[i].bus <<= 32;
319 sc->ranges[i].bus |= base_ranges[j++];
320 }
321 sc->ranges[i].host = 0;
322 for (k = 0; k < host_address_cells; k++) {
323 sc->ranges[i].host <<= 32;
324 sc->ranges[i].host |= base_ranges[j++];
325 }
326 sc->ranges[i].size = 0;
327 for (k = 0; k < sc->size_cells; k++) {
328 sc->ranges[i].size <<= 32;
329 sc->ranges[i].size |= base_ranges[j++];
330 }
331 }
332
333 free(base_ranges, M_DEVBUF);
334 return (sc->nranges);
335 }
336
337 static const struct ofw_bus_devinfo *
mv_pcib_ctrl_get_devinfo(device_t bus __unused,device_t child)338 mv_pcib_ctrl_get_devinfo(device_t bus __unused, device_t child)
339 {
340 struct mv_pcib_ctrl_devinfo *di;
341
342 di = device_get_ivars(child);
343 return (&di->di_dinfo);
344 }
345