1 /*
2 * UAE - The Un*x Amiga Emulator
3 *
4 * Cirrus Logic based graphics board emulation
5 *
6 * Copyright 2013 Toni Wilen
7 *
8 */
9
10 #define VRAMLOG 0
11 #define MEMLOGR 0
12 #define MEMLOGW 0
13 #define MEMLOGINDIRECT 0
14 #define MEMDEBUG 0
15 #define MEMDEBUGMASK 0x7fffff
16 #define MEMDEBUGTEST 0x1ff000
17 #define PICASSOIV_DEBUG_IO 0
18
19 #if MEMLOGR
20 static bool memlogr = false;
21 static bool memlogw = false;
22 #endif
23
24 #define BYTESWAP_WORD -1
25 #define BYTESWAP_LONG 1
26
27 #include "sysconfig.h"
28 #include "sysdeps.h"
29
30 #include "options.h"
31 #include "uae.h"
32 #include "memory.h"
33 #include "debug.h"
34 #include "custom.h"
35 #include "newcpu.h"
36 #include "picasso96.h"
37 #include "statusline.h"
38 #include "rommgr.h"
39 #include "zfile.h"
40 #include "gfxboard.h"
41 #include "rommgr.h"
42
43 #include "qemuvga/qemuuaeglue.h"
44 #include "qemuvga/vga.h"
45
46 #define MONITOR_SWITCH_DELAY 25
47
48 #define GFXBOARD_AUTOCONFIG_SIZE 131072
49
50 #define BOARD_REGISTERS_SIZE 0x00010000
51
52 #define BOARD_MANUFACTURER_PICASSO 2167
53 #define BOARD_MODEL_MEMORY_PICASSOII 11
54 #define BOARD_MODEL_REGISTERS_PICASSOII 12
55
56 #define BOARD_MODEL_MEMORY_PICASSOIV 24
57 #define BOARD_MODEL_REGISTERS_PICASSOIV 23
58 #define PICASSOIV_REG 0x00600000
59 #define PICASSOIV_IO 0x00200000
60 #define PICASSOIV_VRAM1 0x01000000
61 #define PICASSOIV_VRAM2 0x00800000
62 #define PICASSOIV_ROM_OFFSET 0x0200
63 #define PICASSOIV_FLASH_OFFSET 0x8000
64 #define PICASSOIV_FLASH_BANK 0x8000
65 #define PICASSOIV_MAX_FLASH (GFXBOARD_AUTOCONFIG_SIZE - 32768)
66
67 #define PICASSOIV_BANK_UNMAPFLASH 2
68 #define PICASSOIV_BANK_MAPRAM 4
69 #define PICASSOIV_BANK_FLASHBANK 128
70
71 #define PICASSOIV_INT_VBLANK 128
72
73 #define BOARD_MANUFACTURER_PICCOLO 2195
74 #define BOARD_MODEL_MEMORY_PICCOLO 5
75 #define BOARD_MODEL_REGISTERS_PICCOLO 6
76 #define BOARD_MODEL_MEMORY_PICCOLO64 10
77 #define BOARD_MODEL_REGISTERS_PICCOLO64 11
78
79 #define BOARD_MANUFACTURER_SPECTRUM 2193
80 #define BOARD_MODEL_MEMORY_SPECTRUM 1
81 #define BOARD_MODEL_REGISTERS_SPECTRUM 2
82
83 struct gfxboard
84 {
85 const TCHAR *name;
86 const TCHAR *manufacturername;
87 const TCHAR *configname;
88 int manufacturer;
89 int model_memory;
90 int model_registers;
91 int serial;
92 int vrammin;
93 int vrammax;
94 int banksize;
95 int chiptype;
96 int configtype;
97 int irq;
98 bool swap;
99 uae_u32 romtype;
100 };
101
102 #define ISP4() (currprefs.rtgmem_type == GFXBOARD_PICASSO4_Z2 || currprefs.rtgmem_type == GFXBOARD_PICASSO4_Z3)
103
104 // Picasso II: 8* 4x256 (1M) or 16* 4x256 (2M)
105 // Piccolo: 8* 4x256 + 2* 16x256 (2M)
106
107 static const struct gfxboard boards[] =
108 {
109 {
110 _T("Picasso II"), _T("Village Tronic"), _T("PicassoII"),
111 BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOII, BOARD_MODEL_REGISTERS_PICASSOII,
112 0x00020000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, 2, 0, false
113 },
114 {
115 _T("Picasso II+"), _T("Village Tronic"), _T("PicassoII+"),
116 BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOII, BOARD_MODEL_REGISTERS_PICASSOII,
117 0x00100000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5428, 2, 2, false
118 },
119 {
120 _T("Piccolo Zorro II"), _T("Ingenieurb�ro Helfrich"), _T("Piccolo_Z2"),
121 BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO, BOARD_MODEL_REGISTERS_PICCOLO,
122 0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, 2, 6, true
123 },
124 {
125 _T("Piccolo Zorro III"), _T("Ingenieurb�ro Helfrich"), _T("Piccolo_Z3"),
126 BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO, BOARD_MODEL_REGISTERS_PICCOLO,
127 0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, 3, 6, true
128 },
129 {
130 _T("Piccolo SD64 Zorro II"), _T("Ingenieurb�ro Helfrich"), _T("PiccoloSD64_Z2"),
131 BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO64, BOARD_MODEL_REGISTERS_PICCOLO64,
132 0x00000000, 0x00200000, 0x00400000, 0x00400000, CIRRUS_ID_CLGD5434, 2, 6, true
133 },
134 {
135 _T("Piccolo SD64 Zorro III"), _T("Ingenieurb�ro Helfrich"), _T("PiccoloSD64_Z3"),
136 BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO64, BOARD_MODEL_REGISTERS_PICCOLO64,
137 0x00000000, 0x00200000, 0x00400000, 0x04000000, CIRRUS_ID_CLGD5434, 3, 6, true
138 },
139 {
140 _T("Spectrum 28/24 Zorro II"), _T("Great Valley Products"), _T("Spectrum28/24_Z2"),
141 BOARD_MANUFACTURER_SPECTRUM, BOARD_MODEL_MEMORY_SPECTRUM, BOARD_MODEL_REGISTERS_SPECTRUM,
142 0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5428, 2, 6, true
143 },
144 {
145 _T("Spectrum 28/24 Zorro III"), _T("Great Valley Products"), _T("Spectrum28/24_Z3"),
146 BOARD_MANUFACTURER_SPECTRUM, BOARD_MODEL_MEMORY_SPECTRUM, BOARD_MODEL_REGISTERS_SPECTRUM,
147 0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5428, 3, 6, true
148 },
149 {
150 _T("Picasso IV Zorro II"), _T("Village Tronic"), _T("PicassoIV_Z2"),
151 BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOIV, BOARD_MODEL_REGISTERS_PICASSOIV,
152 0x00000000, 0x00400000, 0x00400000, 0x00400000, CIRRUS_ID_CLGD5446, 2, 2, false,
153 ROMTYPE_PICASSOIV
154 },
155 {
156 // REG:00600000 IO:00200000 VRAM:01000000
157 _T("Picasso IV Zorro III"), _T("Village Tronic"), _T("PicassoIV_Z3"),
158 BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOIV, 0,
159 0x00000000, 0x00400000, 0x00400000, 0x04000000, CIRRUS_ID_CLGD5446, 3, 2, false,
160 ROMTYPE_PICASSOIV
161 },
162 {
163 _T("A2410"), _T("Commodore"), _T("A2410"),
164 1030, 0, 0,
165 0x00000000, 0x00200000, 0x00200000, 0x00000000, 0, 0, 2, false
166 },
167 {
168 _T("x86 bridgeboard VGA"), _T("x86"), _T("VGA"),
169 0, 0, 0,
170 0x00000000, 0x00100000, 0x00100000, 0x00000000, CIRRUS_ID_CLGD5426, 0, 0, false,
171 ROMTYPE_x86_VGA
172 },
173 {
174 NULL
175 }
176 };
177
178 struct rtggfxboard
179 {
180 TCHAR memorybankname[40];
181 TCHAR wbsmemorybankname[40];
182 TCHAR lbsmemorybankname[40];
183 TCHAR regbankname[40];
184
185 int configured_mem, configured_regs;
186 const struct gfxboard *board;
187 uae_u8 expamem_lo;
188 uae_u8 *automemory;
189 uae_u32 banksize_mask;
190
191 uae_u8 picassoiv_bank, picassoiv_flifi;
192 uae_u8 p4autoconfig[256];
193 struct zfile *p4rom;
194 bool p4z2;
195 uae_u32 p4_mmiobase;
196 uae_u32 p4_special_mask;
197 uae_u32 p4_vram_bank[2];
198
199 CirrusVGAState vga;
200 uae_u8 *vram, *vramrealstart;
201 int vram_start_offset;
202 uae_u32 gfxboardmem_start;
203 bool monswitch_current, monswitch_new;
204 bool monswitch_reset;
205 int monswitch_delay;
206 int fullrefresh;
207 bool modechanged;
208 uae_u8 *gfxboard_surface, *fakesurface_surface;
209 bool gfxboard_vblank;
210 bool gfxboard_intena;
211 bool vram_enabled, vram_offset_enabled;
212 hwaddr vram_offset[2];
213 uae_u8 cirrus_pci[0x44];
214 uae_u8 p4_pci[0x44];
215 int vga_width, vga_height;
216 bool vga_refresh_active;
217 bool vga_changed;
218
219 uae_u32 vgaioregionptr, vgavramregionptr, vgabank0regionptr, vgabank1regionptr;
220
221 const MemoryRegionOps *vgaio, *vgaram, *vgalowram, *vgammio;
222 MemoryRegion vgaioregion, vgavramregion;
223 };
224
225 static struct rtggfxboard rtggfxboards[1];
226
227 DECLARE_MEMORY_FUNCTIONS(gfxboard);
228 DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, mem);
229 DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, mem_nojit);
230 DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, bsmem);
231 DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, wbsmem);
232 DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, lbsmem);
233 DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, nbsmem);
234 DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, regs);
235 DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboards, regs);
236
237 static addrbank gfxboard_bank_memory = {
238 gfxboard_lget_mem, gfxboard_wget_mem, gfxboard_bget_mem,
239 gfxboard_lput_mem, gfxboard_wput_mem, gfxboard_bput_mem,
240 gfxboard_xlate, gfxboard_check, NULL, NULL, NULL,
241 gfxboard_lget_mem, gfxboard_wget_mem,
242 ABFLAG_RAM | ABFLAG_THREADSAFE, 0, 0
243 };
244
245 static addrbank gfxboard_bank_memory_nojit = {
246 gfxboard_lget_mem_nojit, gfxboard_wget_mem_nojit, gfxboard_bget_mem_nojit,
247 gfxboard_lput_mem_nojit, gfxboard_wput_mem_nojit, gfxboard_bput_mem_nojit,
248 gfxboard_xlate, gfxboard_check, NULL, NULL, NULL,
249 gfxboard_lget_mem_nojit, gfxboard_wget_mem_nojit,
250 ABFLAG_RAM | ABFLAG_THREADSAFE, S_READ, S_WRITE
251 };
252
253 static addrbank gfxboard_bank_wbsmemory = {
254 gfxboard_lget_wbsmem, gfxboard_wget_wbsmem, gfxboard_bget_wbsmem,
255 gfxboard_lput_wbsmem, gfxboard_wput_wbsmem, gfxboard_bput_wbsmem,
256 gfxboard_xlate, gfxboard_check, NULL, NULL, NULL,
257 gfxboard_lget_wbsmem, gfxboard_wget_wbsmem,
258 ABFLAG_RAM | ABFLAG_THREADSAFE, S_READ, S_WRITE
259 };
260
261 static addrbank gfxboard_bank_lbsmemory = {
262 gfxboard_lget_lbsmem, gfxboard_wget_lbsmem, gfxboard_bget_lbsmem,
263 gfxboard_lput_lbsmem, gfxboard_wput_lbsmem, gfxboard_bput_lbsmem,
264 gfxboard_xlate, gfxboard_check, NULL, NULL, NULL,
265 gfxboard_lget_lbsmem, gfxboard_wget_lbsmem,
266 ABFLAG_RAM | ABFLAG_THREADSAFE, S_READ, S_WRITE
267 };
268
269 static addrbank gfxboard_bank_nbsmemory = {
270 gfxboard_lget_nbsmem, gfxboard_wget_nbsmem, gfxboard_bget_bsmem,
271 gfxboard_lput_nbsmem, gfxboard_wput_nbsmem, gfxboard_bput_bsmem,
272 gfxboard_xlate, gfxboard_check, NULL, NULL, _T("Picasso IV banked VRAM"),
273 gfxboard_lget_nbsmem, gfxboard_wget_nbsmem,
274 ABFLAG_RAM | ABFLAG_THREADSAFE, S_READ, S_WRITE
275 };
276
277 static addrbank gfxboard_bank_registers = {
278 gfxboard_lget_regs, gfxboard_wget_regs, gfxboard_bget_regs,
279 gfxboard_lput_regs, gfxboard_wput_regs, gfxboard_bput_regs,
280 default_xlate, default_check, NULL, NULL, NULL,
281 dummy_lgeti, dummy_wgeti,
282 ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
283 };
284
285 static addrbank gfxboard_bank_special = {
286 gfxboards_lget_regs, gfxboards_wget_regs, gfxboards_bget_regs,
287 gfxboards_lput_regs, gfxboards_wput_regs, gfxboards_bput_regs,
288 default_xlate, default_check, NULL, NULL, _T("Picasso IV MISC"),
289 dummy_lgeti, dummy_wgeti,
290 ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
291 };
292
init_board(struct rtggfxboard * gb)293 static void init_board (struct rtggfxboard *gb)
294 {
295 int vramsize = gb->board->vrammax;
296
297 gb->vga_width = 0;
298 mapped_free(&gfxmem_bank);
299 gb->vram_start_offset = 0;
300 if (ISP4() && !gb->p4z2) // JIT direct compatibility hack
301 gb->vram_start_offset = 0x01000000;
302 vramsize += gb->vram_start_offset;
303 xfree (gb->fakesurface_surface);
304 gb->fakesurface_surface = xmalloc (uae_u8, 4 * 10000);
305 gb->vram_offset[0] = gb->vram_offset[1] = 0;
306 gb->vram_enabled = true;
307 gb->vram_offset_enabled = false;
308 if (gb->board->manufacturer) {
309 gfxmem_bank.label = gb->board->configtype == 3 ? _T("z3_gfx") : _T("z2_gfx");
310 } else {
311 gfxmem_bank.label = _T("ram_a8");
312 }
313 gfxmem_bank.allocated = vramsize;
314 mapped_malloc (&gfxmem_bank);
315 gb->vram = gfxmem_bank.baseaddr;
316 gb->vramrealstart = gb->vram;
317 gb->vram += gb->vram_start_offset;
318 gfxmem_bank.baseaddr = gb->vram;
319 gfxmem_bank.allocated = currprefs.rtgmem_size;
320 gb->vga.vga.vram_size_mb = currprefs.rtgmem_size >> 20;
321 gb->vgaioregion.opaque = &gb->vgaioregionptr;
322 gb->vgavramregion.opaque = &gb->vgavramregionptr;
323 gb->vga.vga.vram.opaque = &gb->vgavramregionptr;
324 vga_common_init(&gb->vga.vga);
325 cirrus_init_common(&gb->vga, gb->board->chiptype, 0, NULL, NULL, gb->board->manufacturer == 0);
326 picasso_allocatewritewatch (currprefs.rtgmem_size);
327 }
328
vga_update_size(struct rtggfxboard * gb)329 static void vga_update_size(struct rtggfxboard *gb)
330 {
331 // this forces qemu_console_resize() call
332 gb->vga.vga.graphic_mode = -1;
333 gb->vga.vga.hw_ops->gfx_update(&gb->vga);
334 }
335
gfxboard_setmode(struct rtggfxboard * gb)336 static bool gfxboard_setmode(struct rtggfxboard *gb)
337 {
338 int bpp = gb->vga.vga.get_bpp(&gb->vga.vga);
339 if (bpp == 0)
340 bpp = 8;
341 vga_update_size(gb);
342 if (gb->vga_width <= 16 || gb->vga_height <= 16)
343 return false;
344 picasso96_state.Width = gb->vga_width;
345 picasso96_state.Height = gb->vga_height;
346 picasso96_state.BytesPerPixel = bpp / 8;
347 picasso96_state.RGBFormat = RGBFB_CLUT;
348 write_log(_T("GFXBOARD %dx%dx%d\n"), gb->vga_width, gb->vga_height, bpp);
349 gfx_set_picasso_modeinfo(gb->vga_width, gb->vga_height, bpp, RGBFB_NONE);
350 gb->fullrefresh = 2;
351 gb->vga_changed = false;
352 return true;
353 }
354
gfxboard_toggle(int mode)355 bool gfxboard_toggle (int mode)
356 {
357 struct rtggfxboard *gb = &rtggfxboards[0];
358
359 if (currprefs.rtgmem_type == GFXBOARD_A2410) {
360 return tms_toggle(mode);
361 }
362
363 if (gb->vram == NULL)
364 return false;
365 if (gb->monswitch_current) {
366 gb->vga_width = 0;
367 gb->monswitch_new = false;
368 gb->monswitch_delay = 1;
369 picasso_requested_on = 0;
370 return true;
371 } else {
372 vga_update_size(gb);
373 if (gb->vga_width > 16 && gb->vga_height > 16) {
374 if (!gfxboard_setmode(gb))
375 return false;
376 gb->monswitch_new = true;
377 gb->monswitch_delay = 1;
378 picasso_requested_on = 1;
379 return true;
380 }
381 }
382 return false;
383 }
384
gfxboard_checkchanged(struct rtggfxboard * gb)385 static bool gfxboard_checkchanged (struct rtggfxboard *gb)
386 {
387 int bpp = gb->vga.vga.get_bpp (&gb->vga.vga);
388 if (bpp == 0)
389 bpp = 8;
390 if (gb->vga_width <= 16 || gb->vga_height <= 16)
391 return false;
392 if (picasso96_state.Width != gb->vga_width ||
393 picasso96_state.Height != gb->vga_height ||
394 picasso96_state.BytesPerPixel != bpp / 8)
395 return true;
396 return false;
397 }
398
399 static DisplaySurface gfxsurface, fakesurface;
qemu_console_surface(QemuConsole * con)400 DisplaySurface *qemu_console_surface(QemuConsole *con)
401 {
402 struct rtggfxboard *gb = &rtggfxboards[0];
403 if (picasso_on)
404 return &gfxsurface;
405 gb->modechanged = true;
406 return &fakesurface;
407 }
408
qemu_console_resize(QemuConsole * con,int width,int height)409 void qemu_console_resize(QemuConsole *con, int width, int height)
410 {
411 struct rtggfxboard *gb = &rtggfxboards[0];
412 if (width != gb->vga_width || gb->vga_height != height)
413 gb->vga_changed = true;
414 gb->vga_width = width;
415 gb->vga_height = height;
416 }
417
linear_memory_region_set_dirty(MemoryRegion * mr,hwaddr addr,hwaddr size)418 void linear_memory_region_set_dirty(MemoryRegion *mr, hwaddr addr, hwaddr size)
419 {
420 }
421
vga_memory_region_set_dirty(MemoryRegion * mr,hwaddr addr,hwaddr size)422 void vga_memory_region_set_dirty(MemoryRegion *mr, hwaddr addr, hwaddr size)
423 {
424 struct rtggfxboard *gb = &rtggfxboards[0];
425 if (gb->vga.vga.graphic_mode != 1)
426 return;
427 if (!gb->fullrefresh)
428 gb->fullrefresh = 1;
429 }
430
431 #if 0
432 static uae_u8 pal64 (uae_u8 v)
433 {
434 v = (v << 2) | ((v >> 2) & 3);
435 return v;
436 }
437 #endif
438
qemu_create_displaysurface_from(int width,int height,int bpp,int linesize,uint8_t * data,bool byteswap)439 DisplaySurface* qemu_create_displaysurface_from(int width, int height, int bpp,
440 int linesize, uint8_t *data,
441 bool byteswap)
442 {
443 struct rtggfxboard *gb = &rtggfxboards[0];
444 gb->modechanged = true;
445 return &fakesurface;
446 }
447
surface_bits_per_pixel(DisplaySurface * s)448 int surface_bits_per_pixel(DisplaySurface *s)
449 {
450 if (s == &fakesurface)
451 return 32;
452 return picasso_vidinfo.pixbytes * 8;
453 }
surface_bytes_per_pixel(DisplaySurface * s)454 int surface_bytes_per_pixel(DisplaySurface *s)
455 {
456 if (s == &fakesurface)
457 return 4;
458 return picasso_vidinfo.pixbytes;
459 }
460
surface_stride(DisplaySurface * s)461 int surface_stride(DisplaySurface *s)
462 {
463 struct rtggfxboard *gb = &rtggfxboards[0];
464 if (s == &fakesurface || !gb->vga_refresh_active)
465 return 0;
466 if (gb->gfxboard_surface == NULL)
467 gb->gfxboard_surface = gfx_lock_picasso (false, false);
468 return picasso_vidinfo.rowbytes;
469 }
surface_data(DisplaySurface * s)470 uint8_t *surface_data(DisplaySurface *s)
471 {
472 struct rtggfxboard *gb = &rtggfxboards[0];
473 if (gb->vga_changed)
474 return NULL;
475 if (s == &fakesurface || !gb->vga_refresh_active)
476 return gb->fakesurface_surface;
477 if (gb->gfxboard_surface == NULL)
478 gb->gfxboard_surface = gfx_lock_picasso (false, false);
479 return gb->gfxboard_surface;
480 }
481
gfxboard_refresh(void)482 void gfxboard_refresh (void)
483 {
484 struct rtggfxboard *gb = &rtggfxboards[0];
485 gb->fullrefresh = 2;
486 }
487
gfxboard_hsync_handler(void)488 void gfxboard_hsync_handler(void)
489 {
490 struct rtggfxboard *gb = &rtggfxboards[0];
491 if (currprefs.rtgmem_type == GFXBOARD_A2410) {
492 tms_hsync_handler();
493 }
494 }
495
gfxboard_vsync_handler(void)496 bool gfxboard_vsync_handler (void)
497 {
498 struct rtggfxboard *gb = &rtggfxboards[0];
499 bool flushed = false;
500
501 if (currprefs.rtgmem_type == GFXBOARD_A2410) {
502 return tms_vsync_handler();
503 }
504
505 if (!gb->configured_mem || !gb->configured_regs)
506 return false;
507
508 if (gb->monswitch_current && (gb->modechanged || gfxboard_checkchanged(gb))) {
509 gb->modechanged = false;
510 if (!gfxboard_setmode (gb)) {
511 picasso_requested_on = 0;
512 return false;
513 }
514 init_hz_p96 ();
515 picasso_requested_on = 1;
516 return false;
517 }
518
519 if (gb->monswitch_new != gb->monswitch_current) {
520 if (gb->monswitch_delay > 0)
521 gb->monswitch_delay--;
522 if (gb->monswitch_delay == 0) {
523 if (!gb->monswitch_new)
524 picasso_requested_on = 0;
525 gb->monswitch_current = gb->monswitch_new;
526 vga_update_size(gb);
527 write_log (_T("GFXBOARD ACTIVE=%d\n"), gb->monswitch_current);
528 }
529 } else {
530 gb->monswitch_delay = 0;
531 }
532
533 if (!gb->monswitch_delay && gb->monswitch_current && picasso_on && picasso_requested_on && !gb->vga_changed) {
534 picasso_getwritewatch (gb->vram_start_offset);
535 if (gb->fullrefresh)
536 gb->vga.vga.graphic_mode = -1;
537 gb->vga_refresh_active = true;
538 gb->vga.vga.hw_ops->gfx_update(&gb->vga);
539 gb->vga_refresh_active = false;
540 }
541
542 if (picasso_on && !gb->vga_changed) {
543 if (currprefs.leds_on_screen & STATUSLINE_RTG) {
544 if (gb->gfxboard_surface == NULL) {
545 gb->gfxboard_surface = gfx_lock_picasso (false, false);
546 }
547 if (gb->gfxboard_surface) {
548 if (!(currprefs.leds_on_screen & STATUSLINE_TARGET))
549 picasso_statusline (gb->gfxboard_surface);
550 }
551 }
552 if (gb->fullrefresh > 0)
553 gb->fullrefresh--;
554 }
555
556 if (gb->gfxboard_surface) {
557 flushed = true;
558 gfx_unlock_picasso (true);
559 }
560 gb->gfxboard_surface = NULL;
561
562 // Vertical Sync End Register, 0x20 = Disable Vertical Interrupt, 0x10 = Clear Vertical Interrupt.
563 if (gb->board->irq) {
564 if ((!(gb->vga.vga.cr[0x11] & 0x20) && (gb->vga.vga.cr[0x11] & 0x10) && !(gb->vga.vga.gr[0x17] & 4))) {
565 if (gb->gfxboard_intena) {
566 gb->gfxboard_vblank = true;
567 if (gb->board->irq == 2)
568 INTREQ (0x8000 | 0x0008);
569 else
570 INTREQ (0x8000 | 0x2000);
571 }
572 }
573 }
574 return flushed;
575 }
576
gfxboard_get_vsync(void)577 double gfxboard_get_vsync (void)
578 {
579 return vblank_hz; // FIXME
580 }
581
dpy_gfx_update(QemuConsole * con,int x,int y,int w,int h)582 void dpy_gfx_update(QemuConsole *con, int x, int y, int w, int h)
583 {
584 picasso_invalidate (x, y, w, h);
585 }
586
memory_region_init_alias(MemoryRegion * mr,const char * name,MemoryRegion * orig,hwaddr offset,uint64_t size)587 void memory_region_init_alias(MemoryRegion *mr,
588 const char *name,
589 MemoryRegion *orig,
590 hwaddr offset,
591 uint64_t size)
592 {
593 struct rtggfxboard *gb = &rtggfxboards[0];
594 if (!stricmp(name, "vga.bank0")) {
595 mr->opaque = &gb->vgabank0regionptr;
596 } else if (!stricmp(name, "vga.bank1")) {
597 mr->opaque = &gb->vgabank1regionptr;
598 }
599 }
600
jit_reset(void)601 static void jit_reset (void)
602 {
603 #ifdef JIT
604 if (currprefs.cachesize && (!currprefs.comptrustbyte || !currprefs.comptrustword || !currprefs.comptrustlong)) {
605 flush_icache (0, 3);
606 }
607 #endif
608 }
609
remap_vram(struct rtggfxboard * gb,hwaddr offset0,hwaddr offset1,bool enabled)610 static void remap_vram (struct rtggfxboard *gb, hwaddr offset0, hwaddr offset1, bool enabled)
611 {
612 jit_reset ();
613 gb->vram_offset[0] = offset0;
614 gb->vram_offset[1] = offset1;
615 #if VRAMLOG
616 if (vram_enabled != enabled)
617 write_log (_T("VRAM state=%d\n"), enabled);
618 bool was_vram_offset_enabled = vram_offset_enabled;
619 #endif
620 gb->vram_enabled = enabled && (gb->vga.vga.sr[0x07] & 0x01);
621 #if 0
622 vram_enabled = false;
623 #endif
624 // offset==0 and offset1==0x8000: linear vram mapping
625 gb->vram_offset_enabled = offset0 != 0 || offset1 != 0x8000;
626 #if VRAMLOG
627 if (gb->vram_offset_enabled || gb->was_vram_offset_enabled)
628 write_log (_T("VRAM offset %08x and %08x\n"), offset0, offset1);
629 #endif
630 }
631
memory_region_set_alias_offset(MemoryRegion * mr,hwaddr offset)632 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
633 {
634 struct rtggfxboard *gb = &rtggfxboards[0];
635 if (mr->opaque == &gb->vgabank0regionptr) {
636 if (offset != gb->vram_offset[0]) {
637 //write_log (_T("vgavramregion0 %08x\n"), offset);
638 remap_vram (gb, offset, gb->vram_offset[1], gb->vram_enabled);
639 }
640 } else if (mr->opaque == &gb->vgabank1regionptr) {
641 if (offset != gb->vram_offset[1]) {
642 //write_log (_T("vgavramregion1 %08x\n"), offset);
643 remap_vram (gb, gb->vram_offset[0], offset, gb->vram_enabled);
644 }
645 } else if (mr->opaque == &gb->vgaioregionptr) {
646 write_log (_T("vgaioregion %d\n"), offset);
647 } else {
648 write_log (_T("unknown region %d\n"), offset);
649 }
650
651 }
memory_region_set_enabled(MemoryRegion * mr,bool enabled)652 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
653 {
654 struct rtggfxboard *gb = &rtggfxboards[0];
655 if (mr->opaque == &gb->vgabank0regionptr || mr->opaque == &gb->vgabank1regionptr) {
656 if (enabled != gb->vram_enabled) {
657 //write_log (_T("enable vgavramregion %d\n"), enabled);
658 remap_vram (gb, gb->vram_offset[0], gb->vram_offset[1], enabled);
659 }
660 } else if (mr->opaque == &gb->vgaioregionptr) {
661 write_log (_T("enable vgaioregion %d\n"), enabled);
662 } else {
663 write_log (_T("enable unknown region %d\n"), enabled);
664 }
665 }
memory_region_reset_dirty(MemoryRegion * mr,hwaddr addr,hwaddr size,unsigned client)666 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
667 hwaddr size, unsigned client)
668 {
669 //write_log (_T("memory_region_reset_dirty %08x %08x\n"), addr, size);
670 }
memory_region_get_dirty(MemoryRegion * mr,hwaddr addr,hwaddr size,unsigned client)671 bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
672 hwaddr size, unsigned client)
673 {
674 struct rtggfxboard *gb = &rtggfxboards[0];
675 if (mr->opaque != &gb->vgavramregionptr)
676 return false;
677 //write_log (_T("memory_region_get_dirty %08x %08x\n"), addr, size);
678 if (gb->fullrefresh)
679 return true;
680 return picasso_is_vram_dirty (addr + gfxmem_bank.start, size);
681 }
682
683 static QEMUResetHandler *reset_func;
684 static void *reset_parm;
qemu_register_reset(QEMUResetHandler * func,void * opaque)685 void qemu_register_reset(QEMUResetHandler *func, void *opaque)
686 {
687 reset_func = func;
688 reset_parm = opaque;
689 reset_func (reset_parm);
690 }
691
p4_pci_check(struct rtggfxboard * gb)692 static void p4_pci_check (struct rtggfxboard *gb)
693 {
694 uaecptr b0, b1;
695
696 b0 = gb->p4_pci[0x10 + 2] << 16;
697 b1 = gb->p4_pci[0x14 + 2] << 16;
698
699 gb->p4_vram_bank[0] = b0;
700 gb->p4_vram_bank[1] = b1;
701 #if PICASSOIV_DEBUG_IO
702 write_log (_T("%08X %08X\n"), p4_vram_bank[0], p4_vram_bank[1]);
703 #endif
704 }
705
reset_pci(struct rtggfxboard * gb)706 static void reset_pci (struct rtggfxboard *gb)
707 {
708 gb->cirrus_pci[0] = 0x00;
709 gb->cirrus_pci[1] = 0xb8;
710 gb->cirrus_pci[2] = 0x10;
711 gb->cirrus_pci[3] = 0x13;
712
713 gb->cirrus_pci[4] = 2;
714 gb->cirrus_pci[5] = 0;
715 gb->cirrus_pci[6] = 0;
716 gb->cirrus_pci[7] &= ~(1 | 2 | 32);
717
718 gb->cirrus_pci[8] = 3;
719 gb->cirrus_pci[9] = 0;
720 gb->cirrus_pci[10] = 0;
721 gb->cirrus_pci[11] = 68;
722
723 gb->cirrus_pci[0x10] &= ~1; // B revision
724 gb->cirrus_pci[0x13] &= ~1; // memory
725 }
726
set_monswitch(struct rtggfxboard * gb,bool newval)727 static void set_monswitch(struct rtggfxboard *gb, bool newval)
728 {
729 if (gb->monswitch_new == newval)
730 return;
731 gb->monswitch_new = newval;
732 gb->monswitch_delay = MONITOR_SWITCH_DELAY;
733 }
734
picassoiv_checkswitch(struct rtggfxboard * gb)735 static void picassoiv_checkswitch (struct rtggfxboard *gb)
736 {
737 if (ISP4()) {
738 bool rtg_active = (gb->picassoiv_flifi & 1) == 0 || (gb->vga.vga.cr[0x51] & 8) == 0;
739 // do not switch to P4 RTG until monitor switch is set to native at least
740 // once after reset.
741 if (gb->monswitch_reset && rtg_active)
742 return;
743 gb->monswitch_reset = false;
744 set_monswitch(gb, rtg_active);
745 }
746 }
747
bput_regtest(struct rtggfxboard * gb,uaecptr addr,uae_u8 v)748 static void bput_regtest (struct rtggfxboard *gb, uaecptr addr, uae_u8 v)
749 {
750 addr += 0x3b0;
751 if (addr == 0x3d5) { // CRxx
752 if (gb->vga.vga.cr_index == 0x11) {
753 if (!(gb->vga.vga.cr[0x11] & 0x10)) {
754 gb->gfxboard_vblank = false;
755 }
756 }
757 }
758 if (!(gb->vga.vga.sr[0x07] & 0x01) && gb->vram_enabled) {
759 remap_vram (gb, gb->vram_offset[0], gb->vram_offset[1], false);
760 }
761 picassoiv_checkswitch (gb);
762 }
763
bget_regtest(struct rtggfxboard * gb,uaecptr addr,uae_u8 v)764 static uae_u8 bget_regtest (struct rtggfxboard *gb, uaecptr addr, uae_u8 v)
765 {
766 addr += 0x3b0;
767 // Input Status 0
768 if (addr == 0x3c2) {
769 if (gb->gfxboard_vblank) {
770 // Disable Vertical Interrupt == 0?
771 // Clear Vertical Interrupt == 1
772 // GR17 bit 2 = INTR disable
773 if (!(gb->vga.vga.cr[0x11] & 0x20) && (gb->vga.vga.cr[0x11] & 0x10) && !(gb->vga.vga.gr[0x17] & 4)) {
774 v |= 0x80; // VGA Interrupt Pending
775 }
776 }
777 v |= 0x10; // DAC sensing
778 }
779 if (addr == 0x3c5) {
780 if (gb->vga.vga.sr_index == 8) {
781 // TODO: DDC
782 }
783 }
784 return v;
785 }
786
vga_io_put(int portnum,uae_u8 v)787 void vga_io_put(int portnum, uae_u8 v)
788 {
789 struct rtggfxboard *gb = &rtggfxboards[0];
790 if (!gb->vgaio)
791 return;
792 portnum -= 0x3b0;
793 bput_regtest(gb, portnum, v);
794 gb->vgaio->write(&gb->vga, portnum, v, 1);
795 }
vga_io_get(int portnum)796 uae_u8 vga_io_get(int portnum)
797 {
798 struct rtggfxboard *gb = &rtggfxboards[0];
799 uae_u8 v = 0xff;
800 if (!gb->vgaio)
801 return v;
802 portnum -= 0x3b0;
803 v = gb->vgaio->read(&gb->vga, portnum, 1);
804 v = bget_regtest(gb, portnum, v);
805 return v;
806 }
vga_ram_put(int offset,uae_u8 v)807 void vga_ram_put(int offset, uae_u8 v)
808 {
809 struct rtggfxboard *gb = &rtggfxboards[0];
810 if (!gb->vgalowram)
811 return;
812 offset -= 0xa0000;
813 gb->vgalowram->write(&gb->vga, offset, v, 1);
814 }
vga_ram_get(int offset)815 uae_u8 vga_ram_get(int offset)
816 {
817 struct rtggfxboard *gb = &rtggfxboards[0];
818 if (!gb->vgalowram)
819 return 0xff;
820 offset -= 0xa0000;
821 return gb->vgalowram->read(&gb->vga, offset, 1);
822 }
823
memory_region_get_ram_ptr(MemoryRegion * mr)824 void *memory_region_get_ram_ptr(MemoryRegion *mr)
825 {
826 struct rtggfxboard *gb = &rtggfxboards[0];
827 if (mr->opaque == &gb->vgavramregionptr)
828 return gb->vram;
829 return NULL;
830 }
831
memory_region_init_ram(MemoryRegion * mr,const char * name,uint64_t size)832 void memory_region_init_ram(MemoryRegion *mr,
833 const char *name,
834 uint64_t size)
835 {
836 struct rtggfxboard *gb = &rtggfxboards[0];
837 if (!stricmp (name, "vga.vram")) {
838 gb->vgavramregion.opaque = mr->opaque;
839 }
840 }
841
memory_region_init_io(MemoryRegion * mr,const MemoryRegionOps * ops,void * opaque,const char * name,uint64_t size)842 void memory_region_init_io(MemoryRegion *mr,
843 const MemoryRegionOps *ops,
844 void *opaque,
845 const char *name,
846 uint64_t size)
847 {
848 struct rtggfxboard *gb = &rtggfxboards[0];
849 if (!stricmp (name, "cirrus-io")) {
850 gb->vgaio = ops;
851 mr->opaque = gb->vgaioregion.opaque;
852 } else if (!stricmp (name, "cirrus-linear-io")) {
853 gb->vgaram = ops;
854 } else if (!stricmp (name, "cirrus-low-memory")) {
855 gb->vgalowram = ops;
856 } else if (!stricmp (name, "cirrus-mmio")) {
857 gb->vgammio = ops;
858 }
859 }
860
is_surface_bgr(DisplaySurface * surface)861 int is_surface_bgr(DisplaySurface *surface)
862 {
863 struct rtggfxboard *gb = &rtggfxboards[0];
864 return gb->board->swap;
865 }
866
fixaddr_bs(struct rtggfxboard * gb,uaecptr addr,int mask,int * bs)867 static uaecptr fixaddr_bs (struct rtggfxboard *gb, uaecptr addr, int mask, int *bs)
868 {
869 bool swapped = false;
870 addr &= gfxmem_bank.mask;
871 if (gb->p4z2) {
872 if (addr < 0x200000) {
873 addr |= gb->p4_vram_bank[0];
874 if (addr >= 0x400000 && addr < 0x600000) {
875 *bs = BYTESWAP_WORD;
876 swapped = true;
877 } else if (addr >= 0x800000 && addr < 0xa00000) {
878 *bs = BYTESWAP_LONG;
879 swapped = true;
880 }
881 } else {
882 addr |= gb->p4_vram_bank[1];
883 if (addr >= 0x600000 && addr < 0x800000) {
884 *bs = BYTESWAP_WORD;
885 swapped = true;
886 } else if (addr >= 0xa00000 && addr < 0xc00000) {
887 *bs = BYTESWAP_LONG;
888 swapped = true;
889 }
890 }
891 }
892 #ifdef JIT
893 if (mask && (gb->vram_offset_enabled || !gb->vram_enabled || swapped || gb->p4z2))
894 special_mem |= mask;
895 #endif
896 if (gb->vram_offset_enabled) {
897 if (addr & 0x8000) {
898 addr += gb->vram_offset[1] & ~0x8000;
899 } else {
900 addr += gb->vram_offset[0];
901 }
902 }
903 addr &= gfxmem_bank.mask;
904 return addr;
905 }
906
fixaddr(struct rtggfxboard * gb,uaecptr addr,int mask)907 STATIC_INLINE uaecptr fixaddr (struct rtggfxboard *gb, uaecptr addr, int mask)
908 {
909 #ifdef JIT
910 if (mask && (gb->vram_offset_enabled || !gb->vram_enabled))
911 special_mem |= mask;
912 #endif
913 if (gb->vram_offset_enabled) {
914 if (addr & 0x8000) {
915 addr += gb->vram_offset[1] & ~0x8000;
916 } else {
917 addr += gb->vram_offset[0];
918 }
919 }
920 addr &= gfxmem_bank.mask;
921 return addr;
922 }
923
fixaddr(struct rtggfxboard * gb,uaecptr addr)924 STATIC_INLINE uaecptr fixaddr (struct rtggfxboard *gb, uaecptr addr)
925 {
926 if (gb->vram_offset_enabled) {
927 if (addr & 0x8000) {
928 addr += gb->vram_offset[1] & ~0x8000;
929 } else {
930 addr += gb->vram_offset[0];
931 }
932 }
933 addr &= gfxmem_bank.mask;
934 return addr;
935 }
936
getvgabank(struct rtggfxboard * gb,uaecptr * paddr)937 STATIC_INLINE const MemoryRegionOps *getvgabank (struct rtggfxboard *gb, uaecptr *paddr)
938 {
939 uaecptr addr = *paddr;
940 addr &= gfxmem_bank.mask;
941 *paddr = addr;
942 return gb->vgaram;
943 }
944
gfxboard_lget_vram(struct rtggfxboard * gb,uaecptr addr,int bs)945 static uae_u32 gfxboard_lget_vram (struct rtggfxboard *gb, uaecptr addr, int bs)
946 {
947 uae_u32 v;
948 if (!gb->vram_enabled) {
949 const MemoryRegionOps *bank = getvgabank (gb, &addr);
950 addr &= gfxmem_bank.mask;
951 if (bs < 0) { // WORD
952 v = bank->read (&gb->vga, addr + 1, 1) << 24;
953 v |= bank->read (&gb->vga, addr + 0, 1) << 16;
954 v |= bank->read (&gb->vga, addr + 3, 1) << 8;
955 v |= bank->read (&gb->vga, addr + 2, 1) << 0;
956 } else if (bs > 0) { // LONG
957 v = bank->read (&gb->vga, addr + 3, 1) << 24;
958 v |= bank->read (&gb->vga, addr + 2, 1) << 16;
959 v |= bank->read (&gb->vga, addr + 1, 1) << 8;
960 v |= bank->read (&gb->vga, addr + 0, 1) << 0;
961 } else {
962 v = bank->read (&gb->vga, addr + 0, 1) << 24;
963 v |= bank->read (&gb->vga, addr + 1, 1) << 16;
964 v |= bank->read (&gb->vga, addr + 2, 1) << 8;
965 v |= bank->read (&gb->vga, addr + 3, 1) << 0;
966 }
967 } else {
968 uae_u8 *m = gb->vram + addr;
969 if (bs < 0) {
970 v = (*((uae_u16*)(m + 0))) << 16;
971 v |= (*((uae_u16*)(m + 2))) << 0;
972 } else if (bs > 0) {
973 v = *((uae_u32*)m);
974 } else {
975 v = do_get_mem_long ((uae_u32*)m);
976 }
977 }
978 #if MEMLOGR
979 #if MEMLOGINDIRECT
980 if (!vram_enabled || vram_offset_enabled)
981 #endif
982 if (memlogr)
983 write_log (_T("R %08X L %08X BS=%d EN=%d\n"), addr, v, bs, vram_enabled);
984 #endif
985 return v;
986 }
gfxboard_wget_vram(struct rtggfxboard * gb,uaecptr addr,int bs)987 static uae_u16 gfxboard_wget_vram (struct rtggfxboard *gb, uaecptr addr, int bs)
988 {
989 uae_u32 v;
990 if (!gb->vram_enabled) {
991 const MemoryRegionOps *bank = getvgabank (gb, &addr);
992 if (bs) {
993 v = bank->read (&gb->vga, addr + 0, 1) << 0;
994 v |= bank->read (&gb->vga, addr + 1, 1) << 8;
995 } else {
996 v = bank->read (&gb->vga, addr + 0, 1) << 8;
997 v |= bank->read (&gb->vga, addr + 1, 1) << 0;
998 }
999 } else {
1000 uae_u8 *m = gb->vram + addr;
1001 if (bs)
1002 v = *((uae_u16*)m);
1003 else
1004 v = do_get_mem_word ((uae_u16*)m);
1005 }
1006 #if MEMLOGR
1007 #if MEMLOGINDIRECT
1008 if (!vram_enabled || vram_offset_enabled)
1009 #endif
1010 if (memlogr)
1011 write_log (_T("R %08X W %08X BS=%d EN=%d\n"), addr, v, bs, vram_enabled);
1012 #endif
1013 return v;
1014 }
gfxboard_bget_vram(struct rtggfxboard * gb,uaecptr addr,int bs)1015 static uae_u8 gfxboard_bget_vram (struct rtggfxboard *gb, uaecptr addr, int bs)
1016 {
1017 uae_u32 v;
1018 if (!gb->vram_enabled) {
1019 const MemoryRegionOps *bank = getvgabank (gb, &addr);
1020 if (bs)
1021 v = bank->read (&gb->vga, addr ^ 1, 1);
1022 else
1023 v = bank->read (&gb->vga, addr + 0, 1);
1024 } else {
1025 if (bs)
1026 v = gb->vram[addr ^ 1];
1027 else
1028 v = gb->vram[addr];
1029 }
1030 #if MEMLOGR
1031 #if MEMLOGINDIRECT
1032 if (!vram_enabled || vram_offset_enabled)
1033 #endif
1034 if (memlogr)
1035 write_log (_T("R %08X B %08X BS=0 EN=%d\n"), addr, v, vram_enabled);
1036 #endif
1037 return v;
1038 }
1039
gfxboard_lput_vram(struct rtggfxboard * gb,uaecptr addr,uae_u32 l,int bs)1040 static void gfxboard_lput_vram (struct rtggfxboard *gb, uaecptr addr, uae_u32 l, int bs)
1041 {
1042 #if MEMDEBUG
1043 if ((addr & MEMDEBUGMASK) >= MEMDEBUGTEST && l)
1044 write_log (_T("%08X L %08X\n"), addr, l);
1045 #endif
1046 #if MEMLOGW
1047 #if MEMLOGINDIRECT
1048 if (!vram_enabled || vram_offset_enabled)
1049 #endif
1050 if (memlogw)
1051 write_log (_T("W %08X L %08X\n"), addr, l);
1052 #endif
1053 if (!gb->vram_enabled) {
1054 const MemoryRegionOps *bank = getvgabank (gb, &addr);
1055 if (bs < 0) { // WORD
1056 bank->write (&gb->vga, addr + 1, l >> 24, 1);
1057 bank->write (&gb->vga, addr + 0, (l >> 16) & 0xff, 1);
1058 bank->write (&gb->vga, addr + 3, (l >> 8) & 0xff, 1);
1059 bank->write (&gb->vga, addr + 2, (l >> 0) & 0xff, 1);
1060 } else if (bs > 0) { // LONG
1061 bank->write (&gb->vga, addr + 3, l >> 24, 1);
1062 bank->write (&gb->vga, addr + 2, (l >> 16) & 0xff, 1);
1063 bank->write (&gb->vga, addr + 1, (l >> 8) & 0xff, 1);
1064 bank->write (&gb->vga, addr + 0, (l >> 0) & 0xff, 1);
1065 } else {
1066 bank->write (&gb->vga, addr + 0, l >> 24, 1);
1067 bank->write (&gb->vga, addr + 1, (l >> 16) & 0xff, 1);
1068 bank->write (&gb->vga, addr + 2, (l >> 8) & 0xff, 1);
1069 bank->write (&gb->vga, addr + 3, (l >> 0) & 0xff, 1);
1070 }
1071 } else {
1072 uae_u8 *m = gb->vram + addr;
1073 if (bs < 0) {
1074 *((uae_u16*)(m + 0)) = l >> 16;
1075 *((uae_u16*)(m + 2)) = l >> 0;
1076 } else if (bs > 0) {
1077 *((uae_u32*)m) = l;
1078 } else {
1079 do_put_mem_long ((uae_u32*) m, l);
1080 }
1081 }
1082 }
gfxboard_wput_vram(struct rtggfxboard * gb,uaecptr addr,uae_u16 w,int bs)1083 static void gfxboard_wput_vram (struct rtggfxboard *gb, uaecptr addr, uae_u16 w, int bs)
1084 {
1085 #if MEMDEBUG
1086 if ((addr & MEMDEBUGMASK) >= MEMDEBUGTEST && w)
1087 write_log (_T("%08X W %04X\n"), addr, w & 0xffff);
1088 #endif
1089 #if MEMLOGW
1090 #if MEMLOGINDIRECT
1091 if (!vram_enabled || vram_offset_enabled)
1092 #endif
1093 if (memlogw)
1094 write_log (_T("W %08X W %04X\n"), addr, w & 0xffff);
1095 #endif
1096 if (!gb->vram_enabled) {
1097 const MemoryRegionOps *bank = getvgabank (gb, &addr);
1098 if (bs) {
1099 bank->write (&gb->vga, addr + 0, (w >> 0) & 0xff, 1);
1100 bank->write (&gb->vga, addr + 1, w >> 8, 1);
1101 } else {
1102 bank->write (&gb->vga, addr + 0, w >> 8, 1);
1103 bank->write (&gb->vga, addr + 1, (w >> 0) & 0xff, 1);
1104 }
1105 } else {
1106 uae_u8 *m = gb->vram + addr;
1107 if (bs)
1108 *((uae_u16*)m) = w;
1109 else
1110 do_put_mem_word ((uae_u16*)m, w);
1111 }
1112 }
gfxboard_bput_vram(struct rtggfxboard * gb,uaecptr addr,uae_u8 b,int bs)1113 static void gfxboard_bput_vram (struct rtggfxboard *gb, uaecptr addr, uae_u8 b, int bs)
1114 {
1115 #if MEMDEBUG
1116 if ((addr & MEMDEBUGMASK) >= MEMDEBUGTEST && b)
1117 write_log (_T("%08X B %02X\n"), addr, b & 0xff);
1118 #endif
1119 #if MEMLOGW
1120 #if MEMLOGINDIRECT
1121 if (!vram_enabled || vram_offset_enabled)
1122 #endif
1123 if (memlogw)
1124 write_log (_T("W %08X B %02X\n"), addr, b & 0xff);
1125 #endif
1126 if (!gb->vram_enabled) {
1127 const MemoryRegionOps *bank = getvgabank (gb, &addr);
1128 #ifdef JIT
1129 special_mem |= S_WRITE;
1130 #endif
1131 if (bs)
1132 bank->write (&gb->vga, addr ^ 1, b, 1);
1133 else
1134 bank->write (&gb->vga, addr, b, 1);
1135 } else {
1136 if (bs)
1137 gb->vram[addr ^ 1] = b;
1138 else
1139 gb->vram[addr] = b;
1140 }
1141 }
1142
getgfxboard(uaecptr addr)1143 STATIC_INLINE rtggfxboard *getgfxboard(uaecptr addr)
1144 {
1145 return &rtggfxboards[0];
1146 }
1147
1148 // LONG byteswapped VRAM
gfxboard_lget_lbsmem(uaecptr addr)1149 static uae_u32 REGPARAM2 gfxboard_lget_lbsmem (uaecptr addr)
1150 {
1151 struct rtggfxboard *gb = getgfxboard(addr);
1152 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1153 addr = fixaddr(gb, addr, 0);
1154 if (addr == -1)
1155 return 0;
1156 return gfxboard_lget_vram (gb, addr, BYTESWAP_LONG);
1157 }
gfxboard_wget_lbsmem(uaecptr addr)1158 static uae_u32 REGPARAM2 gfxboard_wget_lbsmem (uaecptr addr)
1159 {
1160 struct rtggfxboard *gb = getgfxboard(addr);
1161 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1162 addr = fixaddr(gb, addr, 0);
1163 if (addr == -1)
1164 return 0;
1165 return gfxboard_wget_vram (gb, addr, BYTESWAP_LONG);
1166 }
gfxboard_bget_lbsmem(uaecptr addr)1167 static uae_u32 REGPARAM2 gfxboard_bget_lbsmem (uaecptr addr)
1168 {
1169 struct rtggfxboard *gb = getgfxboard(addr);
1170 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1171 addr = fixaddr(gb, addr, 0);
1172 if (addr == -1)
1173 return 0;
1174 return gfxboard_bget_vram (gb, addr, BYTESWAP_LONG);
1175 }
1176
gfxboard_lput_lbsmem(uaecptr addr,uae_u32 l)1177 static void REGPARAM2 gfxboard_lput_lbsmem (uaecptr addr, uae_u32 l)
1178 {
1179 struct rtggfxboard *gb = getgfxboard(addr);
1180 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1181 addr = fixaddr(gb, addr, 0);
1182 if (addr == -1)
1183 return;
1184 gfxboard_lput_vram (gb, addr, l, BYTESWAP_LONG);
1185 }
gfxboard_wput_lbsmem(uaecptr addr,uae_u32 w)1186 static void REGPARAM2 gfxboard_wput_lbsmem (uaecptr addr, uae_u32 w)
1187 {
1188 struct rtggfxboard *gb = getgfxboard(addr);
1189 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1190 addr = fixaddr(gb, addr, 0);
1191 if (addr == -1)
1192 return;
1193 gfxboard_wput_vram (gb, addr, w, BYTESWAP_LONG);
1194 }
gfxboard_bput_lbsmem(uaecptr addr,uae_u32 w)1195 static void REGPARAM2 gfxboard_bput_lbsmem (uaecptr addr, uae_u32 w)
1196 {
1197 struct rtggfxboard *gb = getgfxboard(addr);
1198 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1199 addr = fixaddr(gb, addr, 0);
1200 if (addr == -1)
1201 return;
1202 gfxboard_bput_vram (gb, addr, w, BYTESWAP_LONG);
1203 }
1204
1205 // WORD byteswapped VRAM
gfxboard_lget_wbsmem(uaecptr addr)1206 static uae_u32 REGPARAM2 gfxboard_lget_wbsmem (uaecptr addr)
1207 {
1208 struct rtggfxboard *gb = getgfxboard(addr);
1209 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1210 addr = fixaddr(gb, addr, 0);
1211 if (addr == -1)
1212 return 0;
1213 return gfxboard_lget_vram (gb, addr, BYTESWAP_WORD);
1214 }
gfxboard_wget_wbsmem(uaecptr addr)1215 static uae_u32 REGPARAM2 gfxboard_wget_wbsmem (uaecptr addr)
1216 {
1217 struct rtggfxboard *gb = getgfxboard(addr);
1218 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1219 addr = fixaddr(gb, addr, 0);
1220 if (addr == -1)
1221 return 0;
1222 return gfxboard_wget_vram (gb, addr, BYTESWAP_WORD);
1223 }
gfxboard_bget_wbsmem(uaecptr addr)1224 static uae_u32 REGPARAM2 gfxboard_bget_wbsmem (uaecptr addr)
1225 {
1226 struct rtggfxboard *gb = getgfxboard(addr);
1227 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1228 addr = fixaddr(gb, addr, 0);
1229 if (addr == -1)
1230 return 0;
1231 return gfxboard_bget_vram (gb, addr, BYTESWAP_WORD);
1232 }
1233
gfxboard_lput_wbsmem(uaecptr addr,uae_u32 l)1234 static void REGPARAM2 gfxboard_lput_wbsmem (uaecptr addr, uae_u32 l)
1235 {
1236 struct rtggfxboard *gb = getgfxboard(addr);
1237 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1238 addr = fixaddr(gb, addr, 0);
1239 if (addr == -1)
1240 return;
1241 gfxboard_lput_vram (gb, addr, l, BYTESWAP_WORD);
1242 }
gfxboard_wput_wbsmem(uaecptr addr,uae_u32 w)1243 static void REGPARAM2 gfxboard_wput_wbsmem (uaecptr addr, uae_u32 w)
1244 {
1245 struct rtggfxboard *gb = getgfxboard(addr);
1246 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1247 addr = fixaddr(gb, addr, 0);
1248 if (addr == -1)
1249 return;
1250 gfxboard_wput_vram (gb, addr, w, BYTESWAP_WORD);
1251 }
gfxboard_bput_wbsmem(uaecptr addr,uae_u32 w)1252 static void REGPARAM2 gfxboard_bput_wbsmem (uaecptr addr, uae_u32 w)
1253 {
1254 struct rtggfxboard *gb = getgfxboard(addr);
1255 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1256 addr = fixaddr(gb, addr, 0);
1257 if (addr == -1)
1258 return;
1259 gfxboard_bput_vram (gb, addr, w, BYTESWAP_WORD);
1260 }
1261
1262 // normal or byteswapped (banked) vram
gfxboard_lget_nbsmem(uaecptr addr)1263 static uae_u32 REGPARAM2 gfxboard_lget_nbsmem (uaecptr addr)
1264 {
1265 struct rtggfxboard *gb = getgfxboard(addr);
1266 int bs = 0;
1267 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1268 addr = fixaddr_bs (gb, addr, 0, &bs);
1269 if (addr == -1)
1270 return 0;
1271 // activate_debugger();
1272 return gfxboard_lget_vram (gb, addr, bs);
1273 }
gfxboard_wget_nbsmem(uaecptr addr)1274 static uae_u32 REGPARAM2 gfxboard_wget_nbsmem (uaecptr addr)
1275 {
1276 struct rtggfxboard *gb = getgfxboard(addr);
1277 int bs = 0;
1278 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1279 addr = fixaddr_bs (gb, addr, 0, &bs);
1280 if (addr == -1)
1281 return 0;
1282 return gfxboard_wget_vram (gb, addr, bs);
1283 }
1284
gfxboard_lput_nbsmem(uaecptr addr,uae_u32 l)1285 static void REGPARAM2 gfxboard_lput_nbsmem (uaecptr addr, uae_u32 l)
1286 {
1287 struct rtggfxboard *gb = getgfxboard(addr);
1288 int bs = 0;
1289 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1290 addr = fixaddr_bs (gb, addr, 0, &bs);
1291 if (addr == -1)
1292 return;
1293 gfxboard_lput_vram (gb, addr, l, bs);
1294 }
gfxboard_wput_nbsmem(uaecptr addr,uae_u32 w)1295 static void REGPARAM2 gfxboard_wput_nbsmem (uaecptr addr, uae_u32 w)
1296 {
1297 struct rtggfxboard *gb = getgfxboard(addr);
1298 int bs = 0;
1299 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1300 addr = fixaddr_bs (gb, addr, 0, &bs);
1301 if (addr == -1)
1302 return;
1303 gfxboard_wput_vram (gb, addr, w, bs);
1304 }
1305
gfxboard_bget_bsmem(uaecptr addr)1306 static uae_u32 REGPARAM2 gfxboard_bget_bsmem (uaecptr addr)
1307 {
1308 struct rtggfxboard *gb = getgfxboard(addr);
1309 int bs = 0;
1310 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1311 addr = fixaddr(gb, addr, 0);
1312 if (addr == -1)
1313 return 0;
1314 return gfxboard_bget_vram (gb, addr, bs);
1315 }
gfxboard_bput_bsmem(uaecptr addr,uae_u32 b)1316 static void REGPARAM2 gfxboard_bput_bsmem (uaecptr addr, uae_u32 b)
1317 {
1318 struct rtggfxboard *gb = getgfxboard(addr);
1319 int bs = 0;
1320 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1321 addr = fixaddr_bs (gb, addr, 0, &bs);
1322 if (addr == -1)
1323 return;
1324 gfxboard_bput_vram (gb, addr, b, bs);
1325 }
1326
1327 // normal vram
gfxboard_lget_mem(uaecptr addr)1328 static uae_u32 REGPARAM2 gfxboard_lget_mem (uaecptr addr)
1329 {
1330 struct rtggfxboard *gb = getgfxboard(addr);
1331 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1332 addr = fixaddr(gb, addr, S_READ);
1333 if (addr == -1)
1334 return 0;
1335 return gfxboard_lget_vram (gb, addr, 0);
1336 }
gfxboard_wget_mem(uaecptr addr)1337 static uae_u32 REGPARAM2 gfxboard_wget_mem (uaecptr addr)
1338 {
1339 struct rtggfxboard *gb = getgfxboard(addr);
1340 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1341 addr = fixaddr(gb, addr, S_READ);
1342 if (addr == -1)
1343 return 0;
1344 return gfxboard_wget_vram (gb, addr, 0);
1345 }
gfxboard_bget_mem(uaecptr addr)1346 static uae_u32 REGPARAM2 gfxboard_bget_mem (uaecptr addr)
1347 {
1348 struct rtggfxboard *gb = getgfxboard(addr);
1349 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1350 addr = fixaddr(gb, addr, S_READ);
1351 if (addr == -1)
1352 return 0;
1353 return gfxboard_bget_vram (gb, addr, 0);
1354 }
gfxboard_lput_mem(uaecptr addr,uae_u32 l)1355 static void REGPARAM2 gfxboard_lput_mem (uaecptr addr, uae_u32 l)
1356 {
1357 struct rtggfxboard *gb = getgfxboard(addr);
1358 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1359 addr = fixaddr(gb, addr, S_WRITE);
1360 if (addr == -1)
1361 return;
1362 gfxboard_lput_vram (gb, addr, l, 0);
1363 }
gfxboard_wput_mem(uaecptr addr,uae_u32 w)1364 static void REGPARAM2 gfxboard_wput_mem (uaecptr addr, uae_u32 w)
1365 {
1366 struct rtggfxboard *gb = getgfxboard(addr);
1367 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1368 addr = fixaddr(gb, addr, S_WRITE);
1369 if (addr == -1)
1370 return;
1371 gfxboard_wput_vram (gb, addr, w, 0);
1372 }
gfxboard_bput_mem(uaecptr addr,uae_u32 b)1373 static void REGPARAM2 gfxboard_bput_mem (uaecptr addr, uae_u32 b)
1374 {
1375 struct rtggfxboard *gb = getgfxboard(addr);
1376 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1377 addr = fixaddr(gb, addr, S_WRITE);
1378 if (addr == -1)
1379 return;
1380 gfxboard_bput_vram (gb, addr, b, 0);
1381 }
1382
1383 // normal vram, no jit direct
gfxboard_lget_mem_nojit(uaecptr addr)1384 static uae_u32 REGPARAM2 gfxboard_lget_mem_nojit (uaecptr addr)
1385 {
1386 struct rtggfxboard *gb = getgfxboard(addr);
1387 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1388 addr = fixaddr (gb, addr);
1389 if (addr == -1)
1390 return 0;
1391 return gfxboard_lget_vram (gb, addr, 0);
1392 }
gfxboard_wget_mem_nojit(uaecptr addr)1393 static uae_u32 REGPARAM2 gfxboard_wget_mem_nojit (uaecptr addr)
1394 {
1395 struct rtggfxboard *gb = getgfxboard(addr);
1396 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1397 addr = fixaddr (gb, addr);
1398 if (addr == -1)
1399 return 0;
1400 return gfxboard_wget_vram (gb, addr, 0);
1401 }
gfxboard_bget_mem_nojit(uaecptr addr)1402 static uae_u32 REGPARAM2 gfxboard_bget_mem_nojit (uaecptr addr)
1403 {
1404 struct rtggfxboard *gb = getgfxboard(addr);
1405 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1406 addr = fixaddr (gb, addr);
1407 if (addr == -1)
1408 return 0;
1409 return gfxboard_bget_vram (gb, addr, 0);
1410 }
gfxboard_lput_mem_nojit(uaecptr addr,uae_u32 l)1411 static void REGPARAM2 gfxboard_lput_mem_nojit (uaecptr addr, uae_u32 l)
1412 {
1413 struct rtggfxboard *gb = getgfxboard(addr);
1414 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1415 addr = fixaddr (gb, addr);
1416 if (addr == -1)
1417 return;
1418 gfxboard_lput_vram (gb, addr, l, 0);
1419 }
gfxboard_wput_mem_nojit(uaecptr addr,uae_u32 w)1420 static void REGPARAM2 gfxboard_wput_mem_nojit (uaecptr addr, uae_u32 w)
1421 {
1422 struct rtggfxboard *gb = getgfxboard(addr);
1423 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1424 addr = fixaddr (gb, addr);
1425 if (addr == -1)
1426 return;
1427 gfxboard_wput_vram (gb, addr, w, 0);
1428 }
gfxboard_bput_mem_nojit(uaecptr addr,uae_u32 b)1429 static void REGPARAM2 gfxboard_bput_mem_nojit (uaecptr addr, uae_u32 b)
1430 {
1431 struct rtggfxboard *gb = getgfxboard(addr);
1432 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1433 addr = fixaddr (gb, addr);
1434 if (addr == -1)
1435 return;
1436 gfxboard_bput_vram (gb, addr, b, 0);
1437 }
1438
gfxboard_check(uaecptr addr,uae_u32 size)1439 static int REGPARAM2 gfxboard_check (uaecptr addr, uae_u32 size)
1440 {
1441 struct rtggfxboard *gb = getgfxboard(addr);
1442 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1443 addr &= gfxmem_bank.mask;
1444 return (addr + size) <= currprefs.rtgmem_size;
1445 }
gfxboard_xlate(uaecptr addr)1446 static uae_u8 *REGPARAM2 gfxboard_xlate (uaecptr addr)
1447 {
1448 struct rtggfxboard *gb = getgfxboard(addr);
1449 addr -= gb->gfxboardmem_start & gfxmem_bank.mask;
1450 addr &= gfxmem_bank.mask;
1451 return gb->vram + addr;
1452 }
1453
gfxboard_bget_mem_autoconfig(uaecptr addr)1454 static uae_u32 REGPARAM2 gfxboard_bget_mem_autoconfig (uaecptr addr)
1455 {
1456 struct rtggfxboard *gb = getgfxboard(addr);
1457 uae_u32 v = 0;
1458 addr &= 65535;
1459 if (addr < GFXBOARD_AUTOCONFIG_SIZE)
1460 v = gb->automemory[addr];
1461 return v;
1462 }
1463
gfxboard_wput_mem_autoconfig(uaecptr addr,uae_u32 b)1464 static void REGPARAM2 gfxboard_wput_mem_autoconfig (uaecptr addr, uae_u32 b)
1465 {
1466 struct rtggfxboard *gb = getgfxboard(addr);
1467 if (gb->board->configtype == 2)
1468 return;
1469 b &= 0xffff;
1470 addr &= 65535;
1471 if (addr == 0x44) {
1472 uae_u32 start;
1473 if (!expamem_z3hack(&currprefs)) {
1474 start = (b & 0xff00) | gb->expamem_lo;
1475 gfxmem_bank.start = start << 16;
1476 }
1477 gfxboard_bank_memory.bget = gfxboard_bget_mem;
1478 gfxboard_bank_memory.bput = gfxboard_bput_mem;
1479 gfxboard_bank_memory.wput = gfxboard_wput_mem;
1480 init_board (gb);
1481 if (ISP4()) {
1482 if (validate_banks_z3(&gfxboard_bank_memory, gfxmem_bank.start >> 16, expamem_z3_size >> 16)) {
1483 // main vram
1484 map_banks_z3(&gfxboard_bank_memory, (gfxmem_bank.start + PICASSOIV_VRAM1) >> 16, 0x400000 >> 16);
1485 map_banks_z3(&gfxboard_bank_wbsmemory, (gfxmem_bank.start + PICASSOIV_VRAM1 + 0x400000) >> 16, 0x400000 >> 16);
1486 // secondary
1487 map_banks_z3(&gfxboard_bank_memory_nojit, (gfxmem_bank.start + PICASSOIV_VRAM2) >> 16, 0x400000 >> 16);
1488 map_banks_z3(&gfxboard_bank_wbsmemory, (gfxmem_bank.start + PICASSOIV_VRAM2 + 0x400000) >> 16, 0x400000 >> 16);
1489 // regs
1490 map_banks_z3(&gfxboard_bank_registers, (gfxmem_bank.start + PICASSOIV_REG) >> 16, 0x200000 >> 16);
1491 map_banks_z3(&gfxboard_bank_special, gfxmem_bank.start >> 16, PICASSOIV_REG >> 16);
1492 }
1493 gb->picassoiv_bank = 0;
1494 gb->picassoiv_flifi = 1;
1495 gb->configured_regs = gfxmem_bank.start >> 16;
1496 } else {
1497 map_banks_z3(&gfxboard_bank_memory, gfxmem_bank.start >> 16, gb->board->banksize >> 16);
1498 }
1499 gb->configured_mem = gfxmem_bank.start >> 16;
1500 gb->gfxboardmem_start = gfxmem_bank.start;
1501 expamem_next (&gfxboard_bank_memory, NULL);
1502 return;
1503 }
1504 if (addr == 0x4c) {
1505 gb->configured_mem = 0xff;
1506 expamem_shutup(&gfxboard_bank_memory);
1507 return;
1508 }
1509 }
1510
gfxboard_bput_mem_autoconfig(uaecptr addr,uae_u32 b)1511 static void REGPARAM2 gfxboard_bput_mem_autoconfig (uaecptr addr, uae_u32 b)
1512 {
1513 struct rtggfxboard *gb = getgfxboard(addr);
1514 b &= 0xff;
1515 addr &= 65535;
1516 if (addr == 0x48) {
1517 if (gb->board->configtype == 2) {
1518 addrbank *ab;
1519 if (ISP4()) {
1520 ab = &gfxboard_bank_nbsmemory;
1521 if (gb->configured_mem == 0)
1522 init_board (gb);
1523 map_banks_z2 (ab, b, 0x00200000 >> 16);
1524 if (gb->configured_mem == 0) {
1525 gb->configured_mem = b;
1526 gb->gfxboardmem_start = b << 16;
1527 } else {
1528 gfxboard_bank_memory.bget = gfxboard_bget_mem;
1529 gfxboard_bank_memory.bput = gfxboard_bput_mem;
1530 }
1531 } else {
1532 ab = &gfxboard_bank_memory;
1533 gfxboard_bank_memory.bget = gfxboard_bget_mem;
1534 gfxboard_bank_memory.bput = gfxboard_bput_mem;
1535 init_board (gb);
1536 map_banks_z2 (ab, b, gb->board->banksize >> 16);
1537 gb->configured_mem = b;
1538 gb->gfxboardmem_start = b << 16;
1539 }
1540 expamem_next (ab, NULL);
1541 } else {
1542 gb->expamem_lo = b & 0xff;
1543 }
1544 return;
1545 }
1546 if (addr == 0x4c) {
1547 gb->configured_mem = 0xff;
1548 expamem_shutup(&gfxboard_bank_memory);
1549 return;
1550 }
1551 }
1552
mungeaddr(struct rtggfxboard * gb,uaecptr addr,bool write)1553 static uaecptr mungeaddr (struct rtggfxboard *gb, uaecptr addr, bool write)
1554 {
1555 addr &= 65535;
1556 if (addr >= 0x2000) {
1557 if (addr == 0x46e8) {
1558 // wakeup register
1559 return 0;
1560 }
1561 write_log (_T("GFXBOARD: %c unknown IO address %x\n"), write ? 'W' : 'R', addr);
1562 return 0;
1563 }
1564 if (addr >= 0x1000) {
1565 if (gb->board->manufacturer == BOARD_MANUFACTURER_PICASSO) {
1566 if (addr == 0x1001) {
1567 gb->gfxboard_intena = true;
1568 return 0;
1569 }
1570 if (addr == 0x1000) {
1571 gb->gfxboard_intena = false;
1572 return 0;
1573 }
1574 }
1575 if ((addr & 0xfff) < 0x3b0) {
1576 write_log (_T("GFXBOARD: %c unknown IO address %x\n"), write ? 'W' : 'R', addr);
1577 return 0;
1578 }
1579 addr++;
1580 }
1581 addr &= 0x0fff;
1582 if (addr == 0x102) {
1583 // POS102
1584 return 0;
1585 }
1586 if (addr < 0x3b0) {
1587 write_log (_T("GFXBOARD: %c unknown IO address %x\n"), write ? 'W' : 'R', addr);
1588 return 0;
1589 }
1590 addr -= 0x3b0;
1591 return addr;
1592 }
1593
gfxboard_lget_regs(uaecptr addr)1594 static uae_u32 REGPARAM2 gfxboard_lget_regs (uaecptr addr)
1595 {
1596 struct rtggfxboard *gb = getgfxboard(addr);
1597 uae_u32 v = 0xffffffff;
1598 addr = mungeaddr (gb, addr, false);
1599 if (addr)
1600 v = gb->vgaio->read (&gb->vga, addr, 4);
1601 return v;
1602 }
gfxboard_wget_regs(uaecptr addr)1603 static uae_u32 REGPARAM2 gfxboard_wget_regs (uaecptr addr)
1604 {
1605 struct rtggfxboard *gb = getgfxboard(addr);
1606 uae_u16 v = 0xffff;
1607 addr = mungeaddr (gb, addr, false);
1608 if (addr) {
1609 uae_u8 v1, v2;
1610 v1 = gb->vgaio->read (&gb->vga, addr + 0, 1);
1611 v1 = bget_regtest (gb, addr + 0, v1);
1612 v2 = gb->vgaio->read (&gb->vga, addr + 1, 1);
1613 v2 = bget_regtest (gb, addr + 1, v2);
1614 v = (v1 << 8) | v2;
1615 }
1616 return v;
1617 }
gfxboard_bget_regs(uaecptr addr)1618 static uae_u32 REGPARAM2 gfxboard_bget_regs (uaecptr addr)
1619 {
1620 struct rtggfxboard *gb = getgfxboard(addr);
1621 uae_u8 v = 0xff;
1622 addr &= 65535;
1623 if (addr >= 0x8000) {
1624 write_log (_T("GFX SPECIAL BGET IO %08X\n"), addr);
1625 return 0;
1626 }
1627 addr = mungeaddr (gb, addr, false);
1628 if (addr) {
1629 v = gb->vgaio->read (&gb->vga, addr, 1);
1630 v = bget_regtest (gb, addr, v);
1631 }
1632 return v;
1633 }
1634
gfxboard_lput_regs(uaecptr addr,uae_u32 l)1635 static void REGPARAM2 gfxboard_lput_regs (uaecptr addr, uae_u32 l)
1636 {
1637 struct rtggfxboard *gb = getgfxboard(addr);
1638 //write_log (_T("GFX LONG PUT IO %04X = %04X\n"), addr & 65535, l);
1639 addr = mungeaddr (gb, addr, true);
1640 if (addr) {
1641 gb->vgaio->write (&gb->vga, addr + 0, l >> 24, 1);
1642 bput_regtest (gb, addr + 0, (l >> 24));
1643 gb->vgaio->write (&gb->vga, addr + 1, (l >> 16) & 0xff, 1);
1644 bput_regtest (gb, addr + 0, (l >> 16));
1645 gb->vgaio->write (&gb->vga, addr + 2, (l >> 8) & 0xff, 1);
1646 bput_regtest (gb, addr + 0, (l >> 8));
1647 gb->vgaio->write (&gb->vga, addr + 3, (l >> 0) & 0xff, 1);
1648 bput_regtest (gb, addr + 0, (l >> 0));
1649 }
1650 }
gfxboard_wput_regs(uaecptr addr,uae_u32 w)1651 static void REGPARAM2 gfxboard_wput_regs (uaecptr addr, uae_u32 w)
1652 {
1653 struct rtggfxboard *gb = getgfxboard(addr);
1654 //write_log (_T("GFX WORD PUT IO %04X = %04X\n"), addr & 65535, w & 0xffff);
1655 addr = mungeaddr (gb, addr, true);
1656 if (addr) {
1657 gb->vgaio->write (&gb->vga, addr + 0, (w >> 8) & 0xff, 1);
1658 bput_regtest (gb, addr + 0, (w >> 8));
1659 gb->vgaio->write (&gb->vga, addr + 1, (w >> 0) & 0xff, 1);
1660 bput_regtest (gb, addr + 1, (w >> 0));
1661 }
1662 }
gfxboard_bput_regs(uaecptr addr,uae_u32 b)1663 static void REGPARAM2 gfxboard_bput_regs (uaecptr addr, uae_u32 b)
1664 {
1665 struct rtggfxboard *gb = getgfxboard(addr);
1666 //write_log (_T("GFX BYTE PUT IO %04X = %02X\n"), addr & 65535, b & 0xff);
1667 addr &= 65535;
1668 if (addr >= 0x8000) {
1669 write_log (_T("GFX SPECIAL BPUT IO %08X = %02X\n"), addr, b & 0xff);
1670 switch (gb->board->manufacturer)
1671 {
1672 case BOARD_MANUFACTURER_PICASSO:
1673 {
1674 if ((addr & 1) == 0) {
1675 int idx = addr >> 12;
1676 if (idx == 0x0b || idx == 0x09) {
1677 set_monswitch(gb, false);
1678 } else if (idx == 0x0a || idx == 0x08) {
1679 set_monswitch(gb, true);
1680 }
1681 }
1682 }
1683 break;
1684 case BOARD_MANUFACTURER_PICCOLO:
1685 case BOARD_MANUFACTURER_SPECTRUM:
1686 set_monswitch(gb, (b & 0x20) != 0);
1687 gb->gfxboard_intena = (b & 0x40) != 0;
1688 break;
1689 }
1690 return;
1691 }
1692 addr = mungeaddr (gb, addr, true);
1693 if (addr) {
1694 gb->vgaio->write (&gb->vga, addr, b & 0xff, 1);
1695 bput_regtest (gb, addr, b);
1696 }
1697 }
1698
gfxboard_bget_regs_autoconfig(uaecptr addr)1699 static uae_u32 REGPARAM2 gfxboard_bget_regs_autoconfig (uaecptr addr)
1700 {
1701 struct rtggfxboard *gb = getgfxboard(addr);
1702 uae_u32 v = 0;
1703 addr &= 65535;
1704 if (addr < GFXBOARD_AUTOCONFIG_SIZE)
1705 v = gb->automemory[addr];
1706 return v;
1707 }
1708
gfxboard_bput_regs_autoconfig(uaecptr addr,uae_u32 b)1709 static void REGPARAM2 gfxboard_bput_regs_autoconfig (uaecptr addr, uae_u32 b)
1710 {
1711 struct rtggfxboard *gb = getgfxboard(addr);
1712 addrbank *ab;
1713 b &= 0xff;
1714 addr &= 65535;
1715 if (addr == 0x48) {
1716 gfxboard_bank_registers.bget = gfxboard_bget_regs;
1717 gfxboard_bank_registers.bput = gfxboard_bput_regs;
1718 if (gb->p4z2) {
1719 ab = &gfxboard_bank_special;
1720 map_banks_z2(ab, b, gfxboard_bank_special.allocated >> 16);
1721 } else {
1722 ab = &gfxboard_bank_registers;
1723 map_banks_z2(ab, b, gfxboard_bank_registers.allocated >> 16);
1724 }
1725 gb->configured_regs = b;
1726 expamem_next (ab, NULL);
1727 return;
1728 }
1729 if (addr == 0x4c) {
1730 gb->configured_regs = 0xff;
1731 expamem_next (NULL, NULL);
1732 return;
1733 }
1734 }
1735
gfxboard_free(void)1736 void gfxboard_free(void)
1737 {
1738 struct rtggfxboard *gb = &rtggfxboards[0];
1739 if (currprefs.rtgmem_type == GFXBOARD_A2410) {
1740 tms_free();
1741 return;
1742 }
1743 if (gb->vram) {
1744 gfxmem_bank.baseaddr = gb->vramrealstart;
1745 mapped_free (&gfxmem_bank);
1746 }
1747 gb->vram = NULL;
1748 gb->vramrealstart = NULL;
1749 xfree (gb->fakesurface_surface);
1750 gb->fakesurface_surface = NULL;
1751 gb->configured_mem = 0;
1752 gb->configured_regs = 0;
1753 gb->monswitch_new = false;
1754 gb->monswitch_current = false;
1755 gb->monswitch_delay = -1;
1756 gb->monswitch_reset = true;
1757 gb->modechanged = false;
1758 gb->gfxboard_vblank = false;
1759 gb->gfxboard_intena = false;
1760 gb->picassoiv_bank = 0;
1761 }
1762
gfxboard_reset(void)1763 void gfxboard_reset (void)
1764 {
1765 struct rtggfxboard *gb = &rtggfxboards[0];
1766 if (currprefs.rtgmem_type == GFXBOARD_A2410) {
1767 tms_reset();
1768 return;
1769 }
1770 if (currprefs.rtgmem_type >= GFXBOARD_HARDWARE) {
1771 gb->board = &boards[currprefs.rtgmem_type - GFXBOARD_HARDWARE];
1772 gfxmem_bank.mask = currprefs.rtgmem_size - 1;
1773 }
1774 gfxboard_free();
1775 if (gb->board) {
1776 if (gb->board->configtype == 3)
1777 gfxboard_bank_memory.wput = gfxboard_wput_mem_autoconfig;
1778 if (reset_func)
1779 reset_func (reset_parm);
1780 }
1781 }
1782
gfxboards_lget_regs(uaecptr addr)1783 static uae_u32 REGPARAM2 gfxboards_lget_regs (uaecptr addr)
1784 {
1785 struct rtggfxboard *gb = getgfxboard(addr);
1786 uae_u32 v = 0;
1787 addr &= gb->p4_special_mask;
1788 // pci config
1789 if (addr >= 0x400000 || (gb->p4z2 && !(gb->picassoiv_bank & PICASSOIV_BANK_MAPRAM) && (gb->picassoiv_bank & PICASSOIV_BANK_UNMAPFLASH) && ((addr >= 0x800 && addr < 0xc00) || (addr >= 0x1000 && addr < 0x2000)))) {
1790 uae_u32 addr2 = addr & 0xffff;
1791 if (addr2 >= 0x0800 && addr2 < 0x840) {
1792 addr2 -= 0x800;
1793 v = gb->p4_pci[addr2 + 0] << 24;
1794 v |= gb->p4_pci[addr2 + 1] << 16;
1795 v |= gb->p4_pci[addr2 + 2] << 8;
1796 v |= gb->p4_pci[addr2 + 3] << 0;
1797 #if PICASSOIV_DEBUG_IO
1798 write_log (_T("PicassoIV PCI LGET %08x %08x\n"), addr, v);
1799 #endif
1800 } else if (addr2 >= 0x1000 && addr2 < 0x1040) {
1801 addr2 -= 0x1000;
1802 v = gb->cirrus_pci[addr2 + 0] << 24;
1803 v |= gb->cirrus_pci[addr2 + 1] << 16;
1804 v |= gb->cirrus_pci[addr2 + 2] << 8;
1805 v |= gb->cirrus_pci[addr2 + 3] << 0;
1806 #if PICASSOIV_DEBUG_IO
1807 write_log (_T("PicassoIV CL PCI LGET %08x %08x\n"), addr, v);
1808 #endif
1809 }
1810 return v;
1811 }
1812 if (gb->picassoiv_bank & PICASSOIV_BANK_MAPRAM) {
1813 // memory mapped io
1814 if (addr >= gb->p4_mmiobase && addr < gb->p4_mmiobase + 0x8000) {
1815 uae_u32 addr2 = addr - gb->p4_mmiobase;
1816 v = gb->vgammio->read(&gb->vga, addr2 + 0, 1) << 24;
1817 v |= gb->vgammio->read(&gb->vga, addr2 + 1, 1) << 16;
1818 v |= gb->vgammio->read(&gb->vga, addr2 + 2, 1) << 8;
1819 v |= gb->vgammio->read(&gb->vga, addr2 + 3, 1) << 0;
1820 #if PICASSOIV_DEBUG_IO
1821 write_log (_T("PicassoIV MMIO LGET %08x %08x\n"), addr, v);
1822 #endif
1823 return v;
1824 }
1825 }
1826 #if PICASSOIV_DEBUG_IO
1827 write_log (_T("PicassoIV LGET %08x %08x\n"), addr, v);
1828 #endif
1829 return v;
1830 }
gfxboards_wget_regs(uaecptr addr)1831 static uae_u32 REGPARAM2 gfxboards_wget_regs (uaecptr addr)
1832 {
1833 struct rtggfxboard *gb = getgfxboard(addr);
1834 uae_u16 v = 0;
1835 addr &= gb->p4_special_mask;
1836 // pci config
1837 if (addr >= 0x400000 || (gb->p4z2 && !(gb->picassoiv_bank & PICASSOIV_BANK_MAPRAM) && (gb->picassoiv_bank & PICASSOIV_BANK_UNMAPFLASH) && ((addr >= 0x800 && addr < 0xc00) || (addr >= 0x1000 && addr < 0x2000)))) {
1838 uae_u32 addr2 = addr & 0xffff;
1839 if (addr2 >= 0x0800 && addr2 < 0x840) {
1840 addr2 -= 0x800;
1841 v = gb->p4_pci[addr2 + 0] << 8;
1842 v |= gb->p4_pci[addr2 + 1] << 0;
1843 #if PICASSOIV_DEBUG_IO
1844 write_log (_T("PicassoIV PCI WGET %08x %04x\n"), addr, v);
1845 #endif
1846 } else if (addr2 >= 0x1000 && addr2 < 0x1040) {
1847 addr2 -= 0x1000;
1848 v = gb->cirrus_pci[addr2 + 0] << 8;
1849 v |= gb->cirrus_pci[addr2 + 1] << 0;
1850 #if PICASSOIV_DEBUG_IO
1851 write_log (_T("PicassoIV CL PCI WGET %08x %04x\n"), addr, v);
1852 #endif
1853 }
1854 return v;
1855 }
1856 if (gb->picassoiv_bank & PICASSOIV_BANK_MAPRAM) {
1857 // memory mapped io
1858 if (addr >= gb->p4_mmiobase && addr < gb->p4_mmiobase + 0x8000) {
1859 uae_u32 addr2 = addr - gb->p4_mmiobase;
1860 v = gb->vgammio->read(&gb->vga, addr2 + 0, 1) << 8;
1861 v |= gb->vgammio->read(&gb->vga, addr2 + 1, 1) << 0;
1862 #if PICASSOIV_DEBUG_IO
1863 write_log (_T("PicassoIV MMIO WGET %08x %04x\n"), addr, v & 0xffff);
1864 #endif
1865 return v;
1866 }
1867 }
1868 #if PICASSOIV_DEBUG_IO
1869 write_log (_T("PicassoIV WGET %04x %04x\n"), addr, v);
1870 #endif
1871 return v;
1872 }
gfxboards_bget_regs(uaecptr addr)1873 static uae_u32 REGPARAM2 gfxboards_bget_regs (uaecptr addr)
1874 {
1875 struct rtggfxboard *gb = getgfxboard(addr);
1876 uae_u8 v = 0xff;
1877 addr &= gb->p4_special_mask;
1878
1879 // pci config
1880 if (addr >= 0x400000 || (gb->p4z2 && !(gb->picassoiv_bank & PICASSOIV_BANK_MAPRAM) && (gb->picassoiv_bank & PICASSOIV_BANK_UNMAPFLASH) && ((addr >= 0x800 && addr < 0xc00) || (addr >= 0x1000 && addr < 0x2000)))) {
1881 uae_u32 addr2 = addr & 0xffff;
1882 v = 0;
1883 if (addr2 >= 0x0800 && addr2 < 0x840) {
1884 addr2 -= 0x800;
1885 v = gb->p4_pci[addr2];
1886 #if PICASSOIV_DEBUG_IO
1887 write_log (_T("PicassoIV PCI BGET %08x %02x\n"), addr, v);
1888 #endif
1889 } else if (addr2 >= 0x800 && addr2 <= 0x1000) {
1890 if (addr2 == 0x802)
1891 v = 2; // ???
1892 if (addr2 == 0x808)
1893 v = 4; // bridge revision
1894 #if PICASSOIV_DEBUG_IO
1895 write_log (_T("PicassoIV PCI BGET %08x %02x\n"), addr, v);
1896 #endif
1897 } else if (addr2 >= 0x1000 && addr2 <= 0x1040) {
1898 addr2 -= 0x1000;
1899 v = gb->cirrus_pci[addr2];
1900 #if PICASSOIV_DEBUG_IO
1901 write_log (_T("PicassoIV CL PCI BGET %08x %02x\n"), addr, v);
1902 #endif
1903 }
1904 return v;
1905 }
1906
1907 if (gb->picassoiv_bank & PICASSOIV_BANK_MAPRAM) {
1908 // memory mapped io
1909 if (addr >= gb->p4_mmiobase && addr < gb->p4_mmiobase + 0x8000) {
1910 uae_u32 addr2 = addr - gb->p4_mmiobase;
1911 v = gb->vgammio->read(&gb->vga, addr2, 1);
1912 #if PICASSOIV_DEBUG_IO
1913 write_log (_T("PicassoIV MMIO BGET %08x %02x\n"), addr, v & 0xff);
1914 #endif
1915 return v;
1916 }
1917 }
1918 if (addr == 0) {
1919 v = gb->picassoiv_bank;
1920 return v;
1921 }
1922 if (gb->picassoiv_bank & PICASSOIV_BANK_UNMAPFLASH) {
1923 v = 0;
1924 if (addr == 0x404) {
1925 v = 0x70; // FLIFI revision
1926 // FLIFI type in use
1927 if (currprefs.chipset_mask & CSMASK_AGA)
1928 v |= 4 | 8;
1929 else
1930 v |= 8;
1931 } else if (addr == 0x408) {
1932 v = gb->gfxboard_vblank ? 0x80 : 0;
1933 } else if (gb->p4z2 && addr >= 0x10000) {
1934 addr -= 0x10000;
1935 uaecptr addr2 = mungeaddr (gb, addr, true);
1936 if (addr2) {
1937 v = gb->vgaio->read (&gb->vga, addr2, 1);
1938 v = bget_regtest (gb, addr2, v);
1939 }
1940 //write_log (_T("PicassoIV IO %08x %02x\n"), addr, v);
1941 return v;
1942 }
1943 #if PICASSOIV_DEBUG_IO
1944 if (addr != 0x408)
1945 write_log (_T("PicassoIV BGET %08x %02x\n"), addr, v);
1946 #endif
1947 } else {
1948 if (addr < PICASSOIV_FLASH_OFFSET) {
1949 v = gb->automemory[addr];
1950 return v;
1951 }
1952 addr -= PICASSOIV_FLASH_OFFSET;
1953 addr /= 2;
1954 v = gb->automemory[addr + PICASSOIV_FLASH_OFFSET + ((gb->picassoiv_bank & PICASSOIV_BANK_FLASHBANK) ? 0x8000 : 0)];
1955 }
1956 return v;
1957 }
gfxboards_lput_regs(uaecptr addr,uae_u32 l)1958 static void REGPARAM2 gfxboards_lput_regs (uaecptr addr, uae_u32 l)
1959 {
1960 struct rtggfxboard *gb = getgfxboard(addr);
1961 addr &= gb->p4_special_mask;
1962 if (addr >= 0x400000 || (gb->p4z2 && !(gb->picassoiv_bank & PICASSOIV_BANK_MAPRAM) && (gb->picassoiv_bank & PICASSOIV_BANK_UNMAPFLASH) && ((addr >= 0x800 && addr < 0xc00) || (addr >= 0x1000 && addr < 0x2000)))) {
1963 uae_u32 addr2 = addr & 0xffff;
1964 if (addr2 >= 0x0800 && addr2 < 0x840) {
1965 addr2 -= 0x800;
1966 #if PICASSOIV_DEBUG_IO
1967 write_log (_T("PicassoIV PCI LPUT %08x %08x\n"), addr, l);
1968 #endif
1969 gb->p4_pci[addr2 + 0] = l >> 24;
1970 gb->p4_pci[addr2 + 1] = l >> 16;
1971 gb->p4_pci[addr2 + 2] = l >> 8;
1972 gb->p4_pci[addr2 + 3] = l >> 0;
1973 p4_pci_check (gb);
1974 } else if (addr2 >= 0x1000 && addr2 < 0x1040) {
1975 addr2 -= 0x1000;
1976 #if PICASSOIV_DEBUG_IO
1977 write_log (_T("PicassoIV CL PCI LPUT %08x %08x\n"), addr, l);
1978 #endif
1979 gb->cirrus_pci[addr2 + 0] = l >> 24;
1980 gb->cirrus_pci[addr2 + 1] = l >> 16;
1981 gb->cirrus_pci[addr2 + 2] = l >> 8;
1982 gb->cirrus_pci[addr2 + 3] = l >> 0;
1983 reset_pci (gb);
1984 }
1985 return;
1986 }
1987 if (gb->picassoiv_bank & PICASSOIV_BANK_MAPRAM) {
1988 // memory mapped io
1989 if (addr >= gb->p4_mmiobase && addr < gb->p4_mmiobase + 0x8000) {
1990 #if PICASSOIV_DEBUG_IO
1991 write_log (_T("PicassoIV MMIO LPUT %08x %08x\n"), addr, l);
1992 #endif
1993 uae_u32 addr2 = addr - gb->p4_mmiobase;
1994 gb->vgammio->write(&gb->vga, addr2 + 0, l >> 24, 1);
1995 gb->vgammio->write(&gb->vga, addr2 + 1, l >> 16, 1);
1996 gb->vgammio->write(&gb->vga, addr2 + 2, l >> 8, 1);
1997 gb->vgammio->write(&gb->vga, addr2 + 3, l >> 0, 1);
1998 return;
1999 }
2000 }
2001 #if PICASSOIV_DEBUG_IO
2002 write_log (_T("PicassoIV LPUT %08x %08x\n"), addr, l);
2003 #endif
2004 }
gfxboards_wput_regs(uaecptr addr,uae_u32 v)2005 static void REGPARAM2 gfxboards_wput_regs (uaecptr addr, uae_u32 v)
2006 {
2007 struct rtggfxboard *gb = getgfxboard(addr);
2008 uae_u16 w = (uae_u16)v;
2009 addr &= gb->p4_special_mask;
2010 if (addr >= 0x400000 || (gb->p4z2 && !(gb->picassoiv_bank & PICASSOIV_BANK_MAPRAM) && (gb->picassoiv_bank & PICASSOIV_BANK_UNMAPFLASH) && ((addr >= 0x800 && addr < 0xc00) || (addr >= 0x1000 && addr < 0x2000)))) {
2011 uae_u32 addr2 = addr & 0xffff;
2012 if (addr2 >= 0x0800 && addr2 < 0x840) {
2013 addr2 -= 0x800;
2014 #if PICASSOIV_DEBUG_IO
2015 write_log (_T("PicassoIV PCI WPUT %08x %04x\n"), addr, w & 0xffff);
2016 #endif
2017 gb->p4_pci[addr2 + 0] = w >> 8;
2018 gb->p4_pci[addr2 + 1] = w >> 0;
2019 p4_pci_check (gb);
2020 } else if (addr2 >= 0x1000 && addr2 < 0x1040) {
2021 addr2 -= 0x1000;
2022 #if PICASSOIV_DEBUG_IO
2023 write_log (_T("PicassoIV CL PCI WPUT %08x %04x\n"), addr, w & 0xffff);
2024 #endif
2025 gb->cirrus_pci[addr2 + 0] = w >> 8;
2026 gb->cirrus_pci[addr2 + 1] = w >> 0;
2027 reset_pci (gb);
2028 }
2029 return;
2030 }
2031 if (gb->picassoiv_bank & PICASSOIV_BANK_MAPRAM) {
2032 // memory mapped io
2033 if (addr >= gb->p4_mmiobase && addr < gb->p4_mmiobase + 0x8000) {
2034 #if PICASSOIV_DEBUG_IO
2035 write_log (_T("PicassoIV MMIO LPUT %08x %08x\n"), addr, w & 0xffff);
2036 #endif
2037 uae_u32 addr2 = addr - gb->p4_mmiobase;
2038 gb->vgammio->write(&gb->vga, addr2 + 0, w >> 8, 1);
2039 gb->vgammio->write(&gb->vga, addr2 + 1, (w >> 0) & 0xff, 1);
2040 return;
2041 }
2042 }
2043 if (gb->p4z2 && addr >= 0x10000) {
2044 addr -= 0x10000;
2045 addr = mungeaddr (gb, addr, true);
2046 if (addr) {
2047 gb->vgaio->write (&gb->vga, addr + 0, w >> 8, 1);
2048 bput_regtest (gb, addr + 0, w >> 8);
2049 gb->vgaio->write (&gb->vga, addr + 1, (w >> 0) & 0xff, 1);
2050 bput_regtest (gb, addr + 1, w >> 0);
2051 }
2052 return;
2053 }
2054 #if PICASSOIV_DEBUG_IO
2055 write_log (_T("PicassoIV WPUT %08x %04x\n"), addr, w & 0xffff);
2056 #endif
2057 }
2058
gfxboards_bput_regs(uaecptr addr,uae_u32 v)2059 static void REGPARAM2 gfxboards_bput_regs (uaecptr addr, uae_u32 v)
2060 {
2061 struct rtggfxboard *gb = getgfxboard(addr);
2062 uae_u8 b = (uae_u8)v;
2063 addr &= gb->p4_special_mask;
2064 if (addr >= 0x400000 || (gb->p4z2 && !(gb->picassoiv_bank & PICASSOIV_BANK_MAPRAM) && (gb->picassoiv_bank & PICASSOIV_BANK_UNMAPFLASH) && ((addr >= 0x800 && addr < 0xc00) || (addr >= 0x1000 && addr < 0x2000)))) {
2065 uae_u32 addr2 = addr & 0xffff;
2066 if (addr2 >= 0x0800 && addr2 < 0x840) {
2067 addr2 -= 0x800;
2068 gb->p4_pci[addr2] = b;
2069 p4_pci_check (gb);
2070 #if PICASSOIV_DEBUG_IO
2071 write_log (_T("PicassoIV PCI BPUT %08x %02x\n"), addr, b & 0xff);
2072 #endif
2073 } else if (addr2 >= 0x1000 && addr2 < 0x1040) {
2074 addr2 -= 0x1000;
2075 gb->cirrus_pci[addr2] = b;
2076 reset_pci (gb);
2077 #if PICASSOIV_DEBUG_IO
2078 write_log (_T("PicassoIV CL PCI BPUT %08x %02x\n"), addr, b & 0xff);
2079 #endif
2080 }
2081 return;
2082 }
2083 if (gb->picassoiv_bank & PICASSOIV_BANK_UNMAPFLASH) {
2084 if (addr == 0x404) {
2085 gb->picassoiv_flifi = b;
2086 picassoiv_checkswitch (gb);
2087 }
2088 }
2089 if (gb->picassoiv_bank & PICASSOIV_BANK_MAPRAM) {
2090 // memory mapped io
2091 if (addr >= gb->p4_mmiobase && addr < gb->p4_mmiobase + 0x8000) {
2092 #if PICASSOIV_DEBUG_IO
2093 write_log (_T("PicassoIV MMIO BPUT %08x %08x\n"), addr, b & 0xff);
2094 #endif
2095 uae_u32 addr2 = addr - gb->p4_mmiobase;
2096 gb->vgammio->write(&gb->vga, addr2, b, 1);
2097 return;
2098 }
2099 }
2100 if (gb->p4z2 && addr >= 0x10000) {
2101 addr -= 0x10000;
2102 addr = mungeaddr (gb, addr, true);
2103 if (addr) {
2104 gb->vgaio->write (&gb->vga, addr, b & 0xff, 1);
2105 bput_regtest (gb, addr, b);
2106 }
2107 return;
2108 }
2109 #if PICASSOIV_DEBUG_IO
2110 write_log (_T("PicassoIV BPUT %08x %02X\n"), addr, b & 0xff);
2111 #endif
2112 if (addr == 0) {
2113 gb->picassoiv_bank = b;
2114 }
2115 }
2116
gfxboard_get_name(int type)2117 const TCHAR *gfxboard_get_name(int type)
2118 {
2119 if (type == GFXBOARD_UAE_Z2)
2120 return _T("UAE Zorro II");
2121 if (type == GFXBOARD_UAE_Z3)
2122 return _T("UAE Zorro III (*)");
2123 return boards[type - GFXBOARD_HARDWARE].name;
2124 }
2125
gfxboard_get_manufacturername(int type)2126 const TCHAR *gfxboard_get_manufacturername(int type)
2127 {
2128 if (type == GFXBOARD_UAE_Z2)
2129 return NULL;
2130 if (type == GFXBOARD_UAE_Z3)
2131 return NULL;
2132 return boards[type - GFXBOARD_HARDWARE].manufacturername;
2133 }
2134
gfxboard_get_configname(int type)2135 const TCHAR *gfxboard_get_configname(int type)
2136 {
2137 if (type == GFXBOARD_UAE_Z2)
2138 return _T("ZorroII");
2139 if (type == GFXBOARD_UAE_Z3)
2140 return _T("ZorroIII");
2141 return boards[type - GFXBOARD_HARDWARE].configname;
2142 }
2143
gfxboard_get_configtype(int type)2144 int gfxboard_get_configtype(int type)
2145 {
2146 if (type == GFXBOARD_UAE_Z2)
2147 return 2;
2148 if (type == GFXBOARD_UAE_Z3)
2149 return 3;
2150 struct rtggfxboard *gb = &rtggfxboards[0];
2151 gb->board = &boards[type - GFXBOARD_HARDWARE];
2152 return gb->board->configtype;
2153 }
2154
gfxboard_need_byteswap(int type)2155 bool gfxboard_need_byteswap (int type)
2156 {
2157 if (type < GFXBOARD_HARDWARE)
2158 return false;
2159 struct rtggfxboard *gb = &rtggfxboards[0];
2160 gb->board = &boards[type - GFXBOARD_HARDWARE];
2161 return gb->board->swap;
2162 }
2163
gfxboard_get_autoconfig_size(int type)2164 int gfxboard_get_autoconfig_size(int type)
2165 {
2166 if (type == GFXBOARD_PICASSO4_Z3)
2167 return 32 * 1024 * 1024;
2168 return -1;
2169 }
2170
gfxboard_get_vram_min(int type)2171 int gfxboard_get_vram_min (int type)
2172 {
2173 if (type < GFXBOARD_HARDWARE)
2174 return -1;
2175 struct rtggfxboard *gb = &rtggfxboards[0];
2176 gb->board = &boards[type - GFXBOARD_HARDWARE];
2177 return gb->board->vrammin;
2178 }
2179
gfxboard_get_vram_max(int type)2180 int gfxboard_get_vram_max (int type)
2181 {
2182 if (type < GFXBOARD_HARDWARE)
2183 return -1;
2184 struct rtggfxboard *gb = &rtggfxboards[0];
2185 gb->board = &boards[type - GFXBOARD_HARDWARE];
2186 return gb->board->vrammax;
2187 }
2188
gfxboard_is_registers(int type)2189 bool gfxboard_is_registers (int type)
2190 {
2191 if (type < 2)
2192 return false;
2193 struct rtggfxboard *gb = &rtggfxboards[0];
2194 gb->board = &boards[type - 2];
2195 return gb->board->model_registers != 0;
2196 }
2197
gfxboard_num_boards(int type)2198 int gfxboard_num_boards (int type)
2199 {
2200 if (type < 2)
2201 return 1;
2202 struct rtggfxboard *gb = &rtggfxboards[0];
2203 gb->board = &boards[type - 2];
2204 if (type == GFXBOARD_PICASSO4_Z2)
2205 return 3;
2206 if (gb->board->model_registers == 0)
2207 return 1;
2208 return 2;
2209 }
2210
gfxboard_get_romtype(int type)2211 uae_u32 gfxboard_get_romtype(int type)
2212 {
2213 if (type < 2)
2214 return 0;
2215 struct rtggfxboard *gb = &rtggfxboards[0];
2216 gb->board = &boards[type - 2];
2217 return gb->board->romtype;
2218 }
2219
gfxboard_init(struct rtggfxboard * gb)2220 static void gfxboard_init (struct rtggfxboard *gb)
2221 {
2222 if (!gb->automemory)
2223 gb->automemory = xmalloc (uae_u8, GFXBOARD_AUTOCONFIG_SIZE);
2224 memset (gb->automemory, 0xff, GFXBOARD_AUTOCONFIG_SIZE);
2225 gb->p4z2 = false;
2226 zfile_fclose (gb->p4rom);
2227 gb->p4rom = NULL;
2228 gb->banksize_mask = gb->board->banksize - 1;
2229 memset (gb->cirrus_pci, 0, sizeof gb->cirrus_pci);
2230 reset_pci (gb);
2231 }
2232
copyp4autoconfig(struct rtggfxboard * gb,int startoffset)2233 static void copyp4autoconfig (struct rtggfxboard *gb, int startoffset)
2234 {
2235 int size = 0;
2236 int offset = 0;
2237 memset (gb->automemory, 0xff, 64);
2238 while (size < 32) {
2239 uae_u8 b = gb->p4autoconfig[size + startoffset];
2240 gb->automemory[offset] = b;
2241 offset += 2;
2242 size++;
2243 }
2244 }
2245
loadp4rom(struct rtggfxboard * gb)2246 static void loadp4rom (struct rtggfxboard *gb)
2247 {
2248 int size, offset;
2249 uae_u8 b;
2250 // rom loader code
2251 zfile_fseek (gb->p4rom, 256, SEEK_SET);
2252 offset = PICASSOIV_ROM_OFFSET;
2253 size = 0;
2254 while (size < 4096 - 256) {
2255 if (!zfile_fread (&b, 1, 1, gb->p4rom))
2256 break;
2257 gb->automemory[offset] = b;
2258 offset += 2;
2259 size++;
2260 }
2261 // main flash code
2262 zfile_fseek (gb->p4rom, 16384, SEEK_SET);
2263 zfile_fread (&gb->automemory[PICASSOIV_FLASH_OFFSET], 1, PICASSOIV_MAX_FLASH, gb->p4rom);
2264 zfile_fclose (gb->p4rom);
2265 gb->p4rom = NULL;
2266 write_log (_T("PICASSOIV: flash rom loaded\n"));
2267 }
2268
ew(struct rtggfxboard * gb,int addr,uae_u32 value)2269 static void ew (struct rtggfxboard *gb, int addr, uae_u32 value)
2270 {
2271 addr &= 0xffff;
2272 if (addr == 00 || addr == 02 || addr == 0x40 || addr == 0x42) {
2273 gb->automemory[addr] = (value & 0xf0);
2274 gb->automemory[addr + 2] = (value & 0x0f) << 4;
2275 } else {
2276 gb->automemory[addr] = ~(value & 0xf0);
2277 gb->automemory[addr + 2] = ~((value & 0x0f) << 4);
2278 }
2279 }
2280
gfxboard_init_memory(int devnum)2281 addrbank *gfxboard_init_memory (int devnum)
2282 {
2283 struct rtggfxboard *gb = &rtggfxboards[0];
2284 int bank;
2285 uae_u8 z2_flags, z3_flags, type;
2286
2287 gfxboard_init (gb);
2288
2289 memset (gb->automemory, 0xff, GFXBOARD_AUTOCONFIG_SIZE);
2290
2291 z2_flags = 0x05; // 1M
2292 z3_flags = 0x06; // 1M
2293 bank = gb->board->banksize;
2294 bank /= 0x00100000;
2295 while (bank > 1) {
2296 z2_flags++;
2297 z3_flags++;
2298 bank >>= 1;
2299 }
2300 if (gb->board->configtype == 3) {
2301 type = 0x00 | 0x08 | 0x80; // 16M Z3
2302 ew (gb, 0x08, z3_flags | 0x10 | 0x20);
2303 } else {
2304 type = z2_flags | 0x08 | 0xc0;
2305 }
2306 ew (gb, 0x04, gb->board->model_memory);
2307 ew (gb, 0x10, gb->board->manufacturer >> 8);
2308 ew (gb, 0x14, gb->board->manufacturer);
2309
2310 uae_u32 ser = gb->board->serial;
2311 ew (gb, 0x18, ser >> 24); /* ser.no. Byte 0 */
2312 ew (gb, 0x1c, ser >> 16); /* ser.no. Byte 1 */
2313 ew (gb, 0x20, ser >> 8); /* ser.no. Byte 2 */
2314 ew (gb, 0x24, ser >> 0); /* ser.no. Byte 3 */
2315
2316 ew (gb, 0x00, type);
2317
2318 if (ISP4()) {
2319 int roms[] = { 91, -1 };
2320 struct romlist *rl = getromlistbyids(roms, NULL);
2321 TCHAR path[MAX_DPATH];
2322 fetch_rompath (path, sizeof path / sizeof (TCHAR));
2323
2324 gb->p4rom = read_device_rom(&currprefs, ROMTYPE_PICASSOIV, 0, roms);
2325
2326 if (!gb->p4rom && currprefs.picassoivromfile[0] && zfile_exists(currprefs.picassoivromfile))
2327 gb->p4rom = read_rom_name(currprefs.picassoivromfile);
2328
2329 if (!gb->p4rom && rl)
2330 gb->p4rom = read_rom(rl->rd);
2331
2332 if (!gb->p4rom) {
2333 _tcscat (path, _T("picasso_iv_flash.rom"));
2334 gb->p4rom = read_rom_name (path);
2335 if (!gb->p4rom)
2336 gb->p4rom = read_rom_name (_T("picasso_iv_flash.rom"));
2337 }
2338 if (gb->p4rom) {
2339 zfile_fread (gb->p4autoconfig, sizeof gb->p4autoconfig, 1, gb->p4rom);
2340 copyp4autoconfig (gb, gb->board->configtype == 3 ? 192 : 0);
2341 if (gb->board->configtype == 3) {
2342 loadp4rom (gb);
2343 gb->p4_mmiobase = 0x200000;
2344 gb->p4_special_mask = 0x7fffff;
2345 } else {
2346 gb->p4z2 = true;
2347 gb->p4_mmiobase = 0x8000;
2348 gb->p4_special_mask = 0x1ffff;
2349 }
2350 gb->gfxboard_intena = true;
2351 } else {
2352 error_log (_T("Picasso IV: '%s' flash rom image not found!\nAvailable from http://www.sophisticated-development.de/\nPIV_FlashImageXX -> picasso_iv_flash.rom"), path);
2353 gui_message (_T("Picasso IV: '%s' flash rom image not found!\nAvailable from http://www.sophisticated-development.de/\nPIV_FlashImageXX -> picasso_iv_flash.rom"), path);
2354 }
2355 }
2356
2357 _stprintf (gb->memorybankname, _T("%s VRAM"), gb->board->name);
2358 _stprintf (gb->wbsmemorybankname, _T("%s VRAM WORDSWAP"), gb->board->name);
2359 _stprintf (gb->lbsmemorybankname, _T("%s VRAM LONGSWAP"), gb->board->name);
2360 _stprintf (gb->regbankname, _T("%s REG"), gb->board->name);
2361
2362 gfxboard_bank_memory.name = gb->memorybankname;
2363 gfxboard_bank_memory_nojit.name = gb->memorybankname;
2364 gfxboard_bank_wbsmemory.name = gb->wbsmemorybankname;
2365 gfxboard_bank_lbsmemory.name = gb->lbsmemorybankname;
2366 gfxboard_bank_registers.name = gb->regbankname;
2367
2368 gfxboard_bank_memory.bget = gfxboard_bget_mem_autoconfig;
2369 gfxboard_bank_memory.bput = gfxboard_bput_mem_autoconfig;
2370
2371 if (currprefs.rtgmem_type == GFXBOARD_VGA) {
2372 init_board(gb);
2373 gb->configured_mem = 1;
2374 gb->configured_regs = 1;
2375 return &expamem_null;
2376 }
2377
2378 return &gfxboard_bank_memory;
2379 }
2380
gfxboard_init_memory_p4_z2(int devnum)2381 addrbank *gfxboard_init_memory_p4_z2 (int devnum)
2382 {
2383 struct rtggfxboard *gb = &rtggfxboards[0];
2384 if (gb->board->configtype == 3)
2385 return &expamem_null;
2386
2387 copyp4autoconfig (gb, 64);
2388 return &gfxboard_bank_memory;
2389 }
2390
gfxboard_init_registers(int devnum)2391 addrbank *gfxboard_init_registers (int devnum)
2392 {
2393 struct rtggfxboard *gb = &rtggfxboards[0];
2394 if (!gb->board->model_registers)
2395 return &expamem_null;
2396
2397 memset (gb->automemory, 0xff, GFXBOARD_AUTOCONFIG_SIZE);
2398 ew (gb, 0x00, 0xc0 | 0x01); // 64k Z2
2399 ew (gb, 0x04, gb->board->model_registers);
2400 ew (gb, 0x10, gb->board->manufacturer >> 8);
2401 ew (gb, 0x14, gb->board->manufacturer);
2402
2403 uae_u32 ser = gb->board->serial;
2404 ew (gb, 0x18, ser >> 24); /* ser.no. Byte 0 */
2405 ew (gb, 0x1c, ser >> 16); /* ser.no. Byte 1 */
2406 ew (gb, 0x20, ser >> 8); /* ser.no. Byte 2 */
2407 ew (gb, 0x24, ser >> 0); /* ser.no. Byte 3 */
2408
2409 gfxboard_bank_registers.allocated = BOARD_REGISTERS_SIZE;
2410
2411 if (ISP4()) {
2412 uae_u8 v;
2413 copyp4autoconfig (gb, 128);
2414 loadp4rom (gb);
2415 v = (((gb->automemory[0] & 0xf0) | (gb->automemory[2] >> 4)) & 3) - 1;
2416 gfxboard_bank_special.allocated = 0x10000 << v;
2417 }
2418
2419 gfxboard_bank_registers.bget = gfxboard_bget_regs_autoconfig;
2420 gfxboard_bank_registers.bput = gfxboard_bput_regs_autoconfig;
2421
2422 return &gfxboard_bank_registers;
2423 }
2424