1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * The order of pokes in the initiation sequence is based on Linux
31 * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom
32 * woller (twoller@crystal.cirrus.com). Shingo Watanabe (nabe@nabechan.org)
33 * contributed towards power management.
34 */
35
36 #ifdef HAVE_KERNEL_OPTION_HEADERS
37 #include "opt_snd.h"
38 #endif
39
40 #include <dev/sound/pcm/sound.h>
41 #include <dev/sound/pcm/ac97.h>
42
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pcivar.h>
45
46 #include <dev/sound/pci/cs4281.h>
47
48 #define CS4281_DEFAULT_BUFSZ 16384
49
50 /* Max fifo size for full duplex is 64 */
51 #define CS4281_FIFO_SIZE 15
52
53 /* DMA Engine Indices */
54 #define CS4281_DMA_PLAY 0
55 #define CS4281_DMA_REC 1
56
57 /* Misc */
58
59 #define inline __inline
60
61 #ifndef DEB
62 #define DEB(x) /* x */
63 #endif /* DEB */
64
65 /* ------------------------------------------------------------------------- */
66 /* Structures */
67
68 struct sc_info;
69
70 /* channel registers */
71 struct sc_chinfo {
72 struct sc_info *parent;
73
74 struct snd_dbuf *buffer;
75 struct pcm_channel *channel;
76
77 u_int32_t spd, fmt, bps, blksz;
78
79 int dma_setup, dma_active, dma_chan;
80 };
81
82 /* device private data */
83 struct sc_info {
84 device_t dev;
85 u_int32_t type;
86
87 bus_space_tag_t st;
88 bus_space_handle_t sh;
89 bus_dma_tag_t parent_dmat;
90
91 struct resource *reg, *irq, *mem;
92 int regtype, regid, irqid, memid;
93 void *ih;
94
95 int power;
96 unsigned long bufsz;
97 struct sc_chinfo pch;
98 struct sc_chinfo rch;
99 };
100
101 /* -------------------------------------------------------------------- */
102 /* prototypes */
103
104 /* ADC/DAC control */
105 static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go);
106 static void adcdac_prog(struct sc_chinfo *ch);
107
108 /* power management and interrupt control */
109 static void cs4281_intr(void *);
110 static int cs4281_power(struct sc_info *, int);
111 static int cs4281_init(struct sc_info *);
112
113 /* talk to the card */
114 static u_int32_t cs4281_rd(struct sc_info *, int);
115 static void cs4281_wr(struct sc_info *, int, u_int32_t);
116
117 /* misc */
118 static u_int8_t cs4281_rate_to_rv(u_int32_t);
119 static u_int32_t cs4281_format_to_dmr(u_int32_t);
120 static u_int32_t cs4281_format_to_bps(u_int32_t);
121
122 /* -------------------------------------------------------------------- */
123 /* formats (do not add formats without editing cs_fmt_tab) */
124
125 static u_int32_t cs4281_fmts[] = {
126 SND_FORMAT(AFMT_U8, 1, 0),
127 SND_FORMAT(AFMT_U8, 2, 0),
128 SND_FORMAT(AFMT_S8, 1, 0),
129 SND_FORMAT(AFMT_S8, 2, 0),
130 SND_FORMAT(AFMT_S16_LE, 1, 0),
131 SND_FORMAT(AFMT_S16_LE, 2, 0),
132 SND_FORMAT(AFMT_U16_LE, 1, 0),
133 SND_FORMAT(AFMT_U16_LE, 2, 0),
134 SND_FORMAT(AFMT_S16_BE, 1, 0),
135 SND_FORMAT(AFMT_S16_BE, 2, 0),
136 SND_FORMAT(AFMT_U16_BE, 1, 0),
137 SND_FORMAT(AFMT_U16_BE, 2, 0),
138 0
139 };
140
141 static struct pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0};
142
143 /* -------------------------------------------------------------------- */
144 /* Hardware */
145
146 static inline u_int32_t
cs4281_rd(struct sc_info * sc,int regno)147 cs4281_rd(struct sc_info *sc, int regno)
148 {
149 return bus_space_read_4(sc->st, sc->sh, regno);
150 }
151
152 static inline void
cs4281_wr(struct sc_info * sc,int regno,u_int32_t data)153 cs4281_wr(struct sc_info *sc, int regno, u_int32_t data)
154 {
155 bus_space_write_4(sc->st, sc->sh, regno, data);
156 DELAY(100);
157 }
158
159 static inline void
cs4281_clr4(struct sc_info * sc,int regno,u_int32_t mask)160 cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask)
161 {
162 u_int32_t r;
163 r = cs4281_rd(sc, regno);
164 cs4281_wr(sc, regno, r & ~mask);
165 }
166
167 static inline void
cs4281_set4(struct sc_info * sc,int regno,u_int32_t mask)168 cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask)
169 {
170 u_int32_t v;
171 v = cs4281_rd(sc, regno);
172 cs4281_wr(sc, regno, v | mask);
173 }
174
175 static int
cs4281_waitset(struct sc_info * sc,int regno,u_int32_t mask,int tries)176 cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries)
177 {
178 u_int32_t v;
179
180 while (tries > 0) {
181 DELAY(100);
182 v = cs4281_rd(sc, regno);
183 if ((v & mask) == mask) break;
184 tries --;
185 }
186 return tries;
187 }
188
189 static int
cs4281_waitclr(struct sc_info * sc,int regno,u_int32_t mask,int tries)190 cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries)
191 {
192 u_int32_t v;
193
194 while (tries > 0) {
195 DELAY(100);
196 v = ~ cs4281_rd(sc, regno);
197 if (v & mask) break;
198 tries --;
199 }
200 return tries;
201 }
202
203 /* ------------------------------------------------------------------------- */
204 /* Register value mapping functions */
205
206 static u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000};
207 #define CS4281_NUM_RATES sizeof(cs4281_rates)/sizeof(cs4281_rates[0])
208
209 static u_int8_t
cs4281_rate_to_rv(u_int32_t rate)210 cs4281_rate_to_rv(u_int32_t rate)
211 {
212 u_int32_t v;
213
214 for (v = 0; v < CS4281_NUM_RATES; v++) {
215 if (rate == cs4281_rates[v]) return v;
216 }
217
218 v = 1536000 / rate;
219 if (v > 255 || v < 32) v = 5; /* default to 8k */
220 return v;
221 }
222
223 static u_int32_t
cs4281_rv_to_rate(u_int8_t rv)224 cs4281_rv_to_rate(u_int8_t rv)
225 {
226 u_int32_t r;
227
228 if (rv < CS4281_NUM_RATES) return cs4281_rates[rv];
229 r = 1536000 / rv;
230 return r;
231 }
232
233 static inline u_int32_t
cs4281_format_to_dmr(u_int32_t format)234 cs4281_format_to_dmr(u_int32_t format)
235 {
236 u_int32_t dmr = 0;
237 if (AFMT_8BIT & format) dmr |= CS4281PCI_DMR_SIZE8;
238 if (AFMT_CHANNEL(format) < 2) dmr |= CS4281PCI_DMR_MONO;
239 if (AFMT_BIGENDIAN & format) dmr |= CS4281PCI_DMR_BEND;
240 if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN;
241 return dmr;
242 }
243
244 static inline u_int32_t
cs4281_format_to_bps(u_int32_t format)245 cs4281_format_to_bps(u_int32_t format)
246 {
247 return ((AFMT_8BIT & format) ? 1 : 2) *
248 ((AFMT_CHANNEL(format) > 1) ? 2 : 1);
249 }
250
251 /* -------------------------------------------------------------------- */
252 /* ac97 codec */
253
254 static int
cs4281_rdcd(kobj_t obj,void * devinfo,int regno)255 cs4281_rdcd(kobj_t obj, void *devinfo, int regno)
256 {
257 struct sc_info *sc = (struct sc_info *)devinfo;
258
259 regno &= 0xff;
260
261 /* Remove old state */
262 cs4281_rd(sc, CS4281PCI_ACSDA);
263
264 /* Fill in AC97 register value request form */
265 cs4281_wr(sc, CS4281PCI_ACCAD, regno);
266 cs4281_wr(sc, CS4281PCI_ACCDA, 0);
267 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
268 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV |
269 CS4281PCI_ACCTL_CRW);
270
271 /* Wait for read to complete */
272 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
273 device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n");
274 return -1;
275 }
276
277 /* Wait for valid status */
278 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_VSTS, 250) == 0) {
279 device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n");
280 return -1;
281 }
282
283 return cs4281_rd(sc, CS4281PCI_ACSDA);
284 }
285
286 static int
cs4281_wrcd(kobj_t obj,void * devinfo,int regno,u_int32_t data)287 cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
288 {
289 struct sc_info *sc = (struct sc_info *)devinfo;
290
291 regno &= 0xff;
292
293 cs4281_wr(sc, CS4281PCI_ACCAD, regno);
294 cs4281_wr(sc, CS4281PCI_ACCDA, data);
295 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
296 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV);
297
298 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
299 device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n");
300 }
301
302 return 0;
303 }
304
305 static kobj_method_t cs4281_ac97_methods[] = {
306 KOBJMETHOD(ac97_read, cs4281_rdcd),
307 KOBJMETHOD(ac97_write, cs4281_wrcd),
308 KOBJMETHOD_END
309 };
310 AC97_DECLARE(cs4281_ac97);
311
312 /* ------------------------------------------------------------------------- */
313 /* shared rec/play channel interface */
314
315 static void *
cs4281chan_init(kobj_t obj,void * devinfo,struct snd_dbuf * b,struct pcm_channel * c,int dir)316 cs4281chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
317 {
318 struct sc_info *sc = devinfo;
319 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
320
321 ch->buffer = b;
322 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
323 return NULL;
324 }
325 ch->parent = sc;
326 ch->channel = c;
327
328 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
329 ch->spd = DSP_DEFAULT_SPEED;
330 ch->bps = 1;
331 ch->blksz = sndbuf_getsize(ch->buffer);
332
333 ch->dma_chan = (dir == PCMDIR_PLAY) ? CS4281_DMA_PLAY : CS4281_DMA_REC;
334 ch->dma_setup = 0;
335
336 adcdac_go(ch, 0);
337 adcdac_prog(ch);
338
339 return ch;
340 }
341
342 static u_int32_t
cs4281chan_setblocksize(kobj_t obj,void * data,u_int32_t blocksize)343 cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
344 {
345 struct sc_chinfo *ch = data;
346 struct sc_info *sc = ch->parent;
347 u_int32_t go;
348
349 go = adcdac_go(ch, 0);
350
351 /* 2 interrupts are possible and used in buffer (half-empty,empty),
352 * hence factor of 2. */
353 ch->blksz = MIN(blocksize, sc->bufsz / 2);
354 sndbuf_resize(ch->buffer, 2, ch->blksz);
355 ch->dma_setup = 0;
356 adcdac_prog(ch);
357 adcdac_go(ch, go);
358
359 DEB(printf("cs4281chan_setblocksize: blksz %d Setting %d\n", blocksize, ch->blksz));
360
361 return ch->blksz;
362 }
363
364 static u_int32_t
cs4281chan_setspeed(kobj_t obj,void * data,u_int32_t speed)365 cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed)
366 {
367 struct sc_chinfo *ch = data;
368 struct sc_info *sc = ch->parent;
369 u_int32_t go, v, r;
370
371 go = adcdac_go(ch, 0); /* pause */
372 r = (ch->dma_chan == CS4281_DMA_PLAY) ? CS4281PCI_DACSR : CS4281PCI_ADCSR;
373 v = cs4281_rate_to_rv(speed);
374 cs4281_wr(sc, r, v);
375 adcdac_go(ch, go); /* unpause */
376
377 ch->spd = cs4281_rv_to_rate(v);
378 return ch->spd;
379 }
380
381 static int
cs4281chan_setformat(kobj_t obj,void * data,u_int32_t format)382 cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format)
383 {
384 struct sc_chinfo *ch = data;
385 struct sc_info *sc = ch->parent;
386 u_int32_t v, go;
387
388 go = adcdac_go(ch, 0); /* pause */
389
390 if (ch->dma_chan == CS4281_DMA_PLAY)
391 v = CS4281PCI_DMR_TR_PLAY;
392 else
393 v = CS4281PCI_DMR_TR_REC;
394 v |= CS4281PCI_DMR_DMA | CS4281PCI_DMR_AUTO;
395 v |= cs4281_format_to_dmr(format);
396 cs4281_wr(sc, CS4281PCI_DMR(ch->dma_chan), v);
397
398 adcdac_go(ch, go); /* unpause */
399
400 ch->fmt = format;
401 ch->bps = cs4281_format_to_bps(format);
402 ch->dma_setup = 0;
403
404 return 0;
405 }
406
407 static u_int32_t
cs4281chan_getptr(kobj_t obj,void * data)408 cs4281chan_getptr(kobj_t obj, void *data)
409 {
410 struct sc_chinfo *ch = data;
411 struct sc_info *sc = ch->parent;
412 u_int32_t dba, dca, ptr;
413 int sz;
414
415 sz = sndbuf_getsize(ch->buffer);
416 dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan));
417 dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan));
418 ptr = (dca - dba + sz) % sz;
419
420 return ptr;
421 }
422
423 static int
cs4281chan_trigger(kobj_t obj,void * data,int go)424 cs4281chan_trigger(kobj_t obj, void *data, int go)
425 {
426 struct sc_chinfo *ch = data;
427
428 switch(go) {
429 case PCMTRIG_START:
430 adcdac_prog(ch);
431 adcdac_go(ch, 1);
432 break;
433 case PCMTRIG_STOP:
434 case PCMTRIG_ABORT:
435 adcdac_go(ch, 0);
436 break;
437 default:
438 break;
439 }
440
441 /* return 0 if ok */
442 return 0;
443 }
444
445 static struct pcmchan_caps *
cs4281chan_getcaps(kobj_t obj,void * data)446 cs4281chan_getcaps(kobj_t obj, void *data)
447 {
448 return &cs4281_caps;
449 }
450
451 static kobj_method_t cs4281chan_methods[] = {
452 KOBJMETHOD(channel_init, cs4281chan_init),
453 KOBJMETHOD(channel_setformat, cs4281chan_setformat),
454 KOBJMETHOD(channel_setspeed, cs4281chan_setspeed),
455 KOBJMETHOD(channel_setblocksize, cs4281chan_setblocksize),
456 KOBJMETHOD(channel_trigger, cs4281chan_trigger),
457 KOBJMETHOD(channel_getptr, cs4281chan_getptr),
458 KOBJMETHOD(channel_getcaps, cs4281chan_getcaps),
459 KOBJMETHOD_END
460 };
461 CHANNEL_DECLARE(cs4281chan);
462
463 /* -------------------------------------------------------------------- */
464 /* ADC/DAC control */
465
466 /* adcdac_go enables/disable DMA channel, returns non-zero if DMA was
467 * active before call */
468
469 static u_int32_t
adcdac_go(struct sc_chinfo * ch,u_int32_t go)470 adcdac_go(struct sc_chinfo *ch, u_int32_t go)
471 {
472 struct sc_info *sc = ch->parent;
473 u_int32_t going;
474
475 going = !(cs4281_rd(sc, CS4281PCI_DCR(ch->dma_chan)) & CS4281PCI_DCR_MSK);
476
477 if (go)
478 cs4281_clr4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
479 else
480 cs4281_set4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
481
482 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
483
484 return going;
485 }
486
487 static void
adcdac_prog(struct sc_chinfo * ch)488 adcdac_prog(struct sc_chinfo *ch)
489 {
490 struct sc_info *sc = ch->parent;
491 u_int32_t go;
492
493 if (!ch->dma_setup) {
494 go = adcdac_go(ch, 0);
495 cs4281_wr(sc, CS4281PCI_DBA(ch->dma_chan),
496 sndbuf_getbufaddr(ch->buffer));
497 cs4281_wr(sc, CS4281PCI_DBC(ch->dma_chan),
498 sndbuf_getsize(ch->buffer) / ch->bps - 1);
499 ch->dma_setup = 1;
500 adcdac_go(ch, go);
501 }
502 }
503
504 /* -------------------------------------------------------------------- */
505 /* The interrupt handler */
506
507 static void
cs4281_intr(void * p)508 cs4281_intr(void *p)
509 {
510 struct sc_info *sc = (struct sc_info *)p;
511 u_int32_t hisr;
512
513 hisr = cs4281_rd(sc, CS4281PCI_HISR);
514
515 if (hisr == 0) return;
516
517 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_PLAY)) {
518 chn_intr(sc->pch.channel);
519 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */
520 }
521
522 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_REC)) {
523 chn_intr(sc->rch.channel);
524 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */
525 }
526
527 /* Signal End-of-Interrupt */
528 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
529 }
530
531 /* -------------------------------------------------------------------- */
532 /* power management related */
533
534 static int
cs4281_power(struct sc_info * sc,int state)535 cs4281_power(struct sc_info *sc, int state)
536 {
537
538 switch (state) {
539 case 0:
540 /* Permit r/w access to all BA0 registers */
541 cs4281_wr(sc, CS4281PCI_CWPR, CS4281PCI_CWPR_MAGIC);
542 /* Power on */
543 cs4281_clr4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
544 break;
545 case 3:
546 /* Power off card and codec */
547 cs4281_set4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
548 cs4281_clr4(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
549 break;
550 }
551
552 DEB(printf("cs4281_power %d -> %d\n", sc->power, state));
553 sc->power = state;
554
555 return 0;
556 }
557
558 static int
cs4281_init(struct sc_info * sc)559 cs4281_init(struct sc_info *sc)
560 {
561 u_int32_t i, v;
562
563 /* (0) Blast clock register and serial port */
564 cs4281_wr(sc, CS4281PCI_CLKCR1, 0);
565 cs4281_wr(sc, CS4281PCI_SERMC, 0);
566
567 /* (1) Make ESYN 0 to turn sync pulse on AC97 link */
568 cs4281_wr(sc, CS4281PCI_ACCTL, 0);
569 DELAY(50);
570
571 /* (2) Effect Reset */
572 cs4281_wr(sc, CS4281PCI_SPMC, 0);
573 DELAY(100);
574 cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
575 /* Wait 50ms for ABITCLK to become stable */
576 DELAY(50000);
577
578 /* (3) Enable Sound System Clocks */
579 cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP);
580 DELAY(50000); /* Wait for PLL to stabilize */
581 cs4281_wr(sc, CS4281PCI_CLKCR1,
582 CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE);
583
584 /* (4) Power Up - this combination is essential. */
585 cs4281_set4(sc, CS4281PCI_SSPM,
586 CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN |
587 CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN);
588
589 /* (5) Wait for clock stabilization */
590 if (cs4281_waitset(sc,
591 CS4281PCI_CLKCR1,
592 CS4281PCI_CLKCR1_DLLRDY,
593 250) == 0) {
594 device_printf(sc->dev, "Clock stabilization failed\n");
595 return -1;
596 }
597
598 /* (6) Enable ASYNC generation. */
599 cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN);
600
601 /* Wait to allow AC97 to start generating clock bit */
602 DELAY(50000);
603
604 /* Set AC97 timing */
605 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
606
607 /* (7) Wait for AC97 ready signal */
608 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) {
609 device_printf(sc->dev, "codec did not avail\n");
610 return -1;
611 }
612
613 /* (8) Assert valid frame signal to begin sending commands to
614 * AC97 codec */
615 cs4281_wr(sc,
616 CS4281PCI_ACCTL,
617 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN);
618
619 /* (9) Wait for codec calibration */
620 for(i = 0 ; i < 1000; i++) {
621 DELAY(10000);
622 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
623 if ((v & 0x0f) == 0x0f) {
624 break;
625 }
626 }
627 if (i == 1000) {
628 device_printf(sc->dev, "codec failed to calibrate\n");
629 return -1;
630 }
631
632 /* (10) Set AC97 timing */
633 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
634
635 /* (11) Wait for valid data to arrive */
636 if (cs4281_waitset(sc,
637 CS4281PCI_ACISV,
638 CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4),
639 10000) == 0) {
640 device_printf(sc->dev, "cs4281 never got valid data\n");
641 return -1;
642 }
643
644 /* (12) Start digital data transfer of audio data to codec */
645 cs4281_wr(sc,
646 CS4281PCI_ACOSV,
647 CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4));
648
649 /* Set Master and headphone to max */
650 cs4281_wrcd(0, sc, AC97_MIX_AUXOUT, 0);
651 cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0);
652
653 /* Power on the DAC */
654 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff;
655 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
656
657 /* Wait until DAC state ready */
658 for(i = 0; i < 320; i++) {
659 DELAY(100);
660 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
661 if (v & 0x02) break;
662 }
663
664 /* Power on the ADC */
665 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff;
666 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
667
668 /* Wait until ADC state ready */
669 for(i = 0; i < 320; i++) {
670 DELAY(100);
671 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
672 if (v & 0x01) break;
673 }
674
675 /* FIFO configuration (driver is DMA orientated, implicit FIFO) */
676 /* Play FIFO */
677
678 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_PLAY_SLOT) |
679 CS4281PCI_FCR_LS(CS4281PCI_LPCM_PLAY_SLOT) |
680 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
681 CS4281PCI_FCR_OF(0);
682 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v);
683
684 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v | CS4281PCI_FCR_FEN);
685
686 /* Record FIFO */
687 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_REC_SLOT) |
688 CS4281PCI_FCR_LS(CS4281PCI_LPCM_REC_SLOT) |
689 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
690 CS4281PCI_FCR_OF(CS4281_FIFO_SIZE + 1);
691 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_PSH);
692 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_FEN);
693
694 /* Match AC97 slots to FIFOs */
695 v = CS4281PCI_SRCSA_PLSS(CS4281PCI_LPCM_PLAY_SLOT) |
696 CS4281PCI_SRCSA_PRSS(CS4281PCI_RPCM_PLAY_SLOT) |
697 CS4281PCI_SRCSA_CLSS(CS4281PCI_LPCM_REC_SLOT) |
698 CS4281PCI_SRCSA_CRSS(CS4281PCI_RPCM_REC_SLOT);
699 cs4281_wr(sc, CS4281PCI_SRCSA, v);
700
701 /* Set Auto-Initialize and set directions */
702 cs4281_wr(sc,
703 CS4281PCI_DMR(CS4281_DMA_PLAY),
704 CS4281PCI_DMR_DMA |
705 CS4281PCI_DMR_AUTO |
706 CS4281PCI_DMR_TR_PLAY);
707 cs4281_wr(sc,
708 CS4281PCI_DMR(CS4281_DMA_REC),
709 CS4281PCI_DMR_DMA |
710 CS4281PCI_DMR_AUTO |
711 CS4281PCI_DMR_TR_REC);
712
713 /* Enable half and empty buffer interrupts keeping DMA paused */
714 cs4281_wr(sc,
715 CS4281PCI_DCR(CS4281_DMA_PLAY),
716 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
717 cs4281_wr(sc,
718 CS4281PCI_DCR(CS4281_DMA_REC),
719 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
720
721 /* Enable Interrupts */
722 cs4281_clr4(sc,
723 CS4281PCI_HIMR,
724 CS4281PCI_HIMR_DMAI |
725 CS4281PCI_HIMR_DMA(CS4281_DMA_PLAY) |
726 CS4281PCI_HIMR_DMA(CS4281_DMA_REC));
727
728 /* Set playback volume */
729 cs4281_wr(sc, CS4281PCI_PPLVC, 7);
730 cs4281_wr(sc, CS4281PCI_PPRVC, 7);
731
732 return 0;
733 }
734
735 /* -------------------------------------------------------------------- */
736 /* Probe and attach the card */
737
738 static int
cs4281_pci_probe(device_t dev)739 cs4281_pci_probe(device_t dev)
740 {
741 char *s = NULL;
742
743 switch (pci_get_devid(dev)) {
744 case CS4281_PCI_ID:
745 s = "Crystal Semiconductor CS4281";
746 break;
747 }
748
749 if (s)
750 device_set_desc(dev, s);
751 return s ? BUS_PROBE_DEFAULT : ENXIO;
752 }
753
754 static int
cs4281_pci_attach(device_t dev)755 cs4281_pci_attach(device_t dev)
756 {
757 struct sc_info *sc;
758 struct ac97_info *codec = NULL;
759 char status[SND_STATUSLEN];
760
761 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
762 sc->dev = dev;
763 sc->type = pci_get_devid(dev);
764
765 pci_enable_busmaster(dev);
766
767 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
768 /* Reset the power state. */
769 device_printf(dev, "chip is in D%d power mode "
770 "-- setting to D0\n", pci_get_powerstate(dev));
771
772 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
773 }
774
775 sc->regid = PCIR_BAR(0);
776 sc->regtype = SYS_RES_MEMORY;
777 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, RF_ACTIVE);
778 if (!sc->reg) {
779 sc->regtype = SYS_RES_IOPORT;
780 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
781 RF_ACTIVE);
782 if (!sc->reg) {
783 device_printf(dev, "unable to allocate register space\n");
784 goto bad;
785 }
786 }
787 sc->st = rman_get_bustag(sc->reg);
788 sc->sh = rman_get_bushandle(sc->reg);
789
790 sc->memid = PCIR_BAR(1);
791 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->memid,
792 RF_ACTIVE);
793 if (sc->mem == NULL) {
794 device_printf(dev, "unable to allocate fifo space\n");
795 goto bad;
796 }
797
798 sc->irqid = 0;
799 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
800 RF_ACTIVE | RF_SHAREABLE);
801 if (!sc->irq) {
802 device_printf(dev, "unable to allocate interrupt\n");
803 goto bad;
804 }
805
806 if (snd_setup_intr(dev, sc->irq, 0, cs4281_intr, sc, &sc->ih)) {
807 device_printf(dev, "unable to setup interrupt\n");
808 goto bad;
809 }
810
811 sc->bufsz = pcm_getbuffersize(dev, 4096, CS4281_DEFAULT_BUFSZ, 65536);
812
813 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
814 /*boundary*/0,
815 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
816 /*highaddr*/BUS_SPACE_MAXADDR,
817 /*filter*/NULL, /*filterarg*/NULL,
818 /*maxsize*/sc->bufsz, /*nsegments*/1,
819 /*maxsegz*/0x3ffff,
820 /*flags*/0, /*lockfunc*/NULL, /*lockarg*/NULL,
821 &sc->parent_dmat) != 0) {
822 device_printf(dev, "unable to create dma tag\n");
823 goto bad;
824 }
825
826 /* power up */
827 cs4281_power(sc, 0);
828
829 /* init chip */
830 if (cs4281_init(sc) == -1) {
831 device_printf(dev, "unable to initialize the card\n");
832 goto bad;
833 }
834
835 /* create/init mixer */
836 codec = AC97_CREATE(dev, sc, cs4281_ac97);
837 if (codec == NULL)
838 goto bad;
839
840 mixer_init(dev, ac97_getmixerclass(), codec);
841
842 if (pcm_register(dev, sc, 1, 1))
843 goto bad;
844
845 pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc);
846 pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc);
847
848 snprintf(status, SND_STATUSLEN, "%s 0x%jx irq %jd on %s",
849 (sc->regtype == SYS_RES_IOPORT)? "port" : "mem",
850 rman_get_start(sc->reg), rman_get_start(sc->irq),
851 device_get_nameunit(device_get_parent(dev)));
852 pcm_setstatus(dev, status);
853
854 return 0;
855
856 bad:
857 if (codec)
858 ac97_destroy(codec);
859 if (sc->reg)
860 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
861 if (sc->mem)
862 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
863 if (sc->ih)
864 bus_teardown_intr(dev, sc->irq, sc->ih);
865 if (sc->irq)
866 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
867 if (sc->parent_dmat)
868 bus_dma_tag_destroy(sc->parent_dmat);
869 free(sc, M_DEVBUF);
870
871 return ENXIO;
872 }
873
874 static int
cs4281_pci_detach(device_t dev)875 cs4281_pci_detach(device_t dev)
876 {
877 int r;
878 struct sc_info *sc;
879
880 r = pcm_unregister(dev);
881 if (r)
882 return r;
883
884 sc = pcm_getdevinfo(dev);
885
886 /* power off */
887 cs4281_power(sc, 3);
888
889 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
890 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
891 bus_teardown_intr(dev, sc->irq, sc->ih);
892 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
893 bus_dma_tag_destroy(sc->parent_dmat);
894 free(sc, M_DEVBUF);
895
896 return 0;
897 }
898
899 static int
cs4281_pci_suspend(device_t dev)900 cs4281_pci_suspend(device_t dev)
901 {
902 struct sc_info *sc;
903
904 sc = pcm_getdevinfo(dev);
905
906 sc->rch.dma_active = adcdac_go(&sc->rch, 0);
907 sc->pch.dma_active = adcdac_go(&sc->pch, 0);
908
909 cs4281_power(sc, 3);
910
911 return 0;
912 }
913
914 static int
cs4281_pci_resume(device_t dev)915 cs4281_pci_resume(device_t dev)
916 {
917 struct sc_info *sc;
918
919 sc = pcm_getdevinfo(dev);
920
921 /* power up */
922 cs4281_power(sc, 0);
923
924 /* initialize chip */
925 if (cs4281_init(sc) == -1) {
926 device_printf(dev, "unable to reinitialize the card\n");
927 return ENXIO;
928 }
929
930 /* restore mixer state */
931 if (mixer_reinit(dev) == -1) {
932 device_printf(dev, "unable to reinitialize the mixer\n");
933 return ENXIO;
934 }
935
936 /* restore chip state */
937 cs4281chan_setspeed(NULL, &sc->rch, sc->rch.spd);
938 cs4281chan_setblocksize(NULL, &sc->rch, sc->rch.blksz);
939 cs4281chan_setformat(NULL, &sc->rch, sc->rch.fmt);
940 adcdac_go(&sc->rch, sc->rch.dma_active);
941
942 cs4281chan_setspeed(NULL, &sc->pch, sc->pch.spd);
943 cs4281chan_setblocksize(NULL, &sc->pch, sc->pch.blksz);
944 cs4281chan_setformat(NULL, &sc->pch, sc->pch.fmt);
945 adcdac_go(&sc->pch, sc->pch.dma_active);
946
947 return 0;
948 }
949
950 static device_method_t cs4281_methods[] = {
951 /* Device interface */
952 DEVMETHOD(device_probe, cs4281_pci_probe),
953 DEVMETHOD(device_attach, cs4281_pci_attach),
954 DEVMETHOD(device_detach, cs4281_pci_detach),
955 DEVMETHOD(device_suspend, cs4281_pci_suspend),
956 DEVMETHOD(device_resume, cs4281_pci_resume),
957 { 0, 0 }
958 };
959
960 static driver_t cs4281_driver = {
961 "pcm",
962 cs4281_methods,
963 PCM_SOFTC_SIZE,
964 };
965
966 DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, 0, 0);
967 MODULE_DEPEND(snd_cs4281, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
968 MODULE_VERSION(snd_cs4281, 1);
969