1 /*
2 * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <core/core.h>
25 #include <gpu/gpu.h>
26 #include <gpu/eng_desc.h>
27 #include <g_allclasses.h>
28
29
30
31 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_TU102(POBJGPU pGpu,NvU32 * pNumClassDescriptors)32 gpuGetClassDescriptorList_TU102(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
33 {
34 static const CLASSDESCRIPTOR halTU102ClassDescriptorList[] = {
35 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
36 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
37 { FERMI_TWOD_A, ENG_GR(0) },
38 { FERMI_VASPACE_A, ENG_DMA },
39 { G84_PERFBUFFER, ENG_BUS },
40 { GF100_DISP_SW, ENG_SW },
41 { GF100_HDACODEC, ENG_HDACODEC },
42 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
43 { GF100_SUBDEVICE_MASTER, ENG_GPU },
44 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
45 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
46 { GP100_UVM_SW, ENG_SW },
47 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
48 { KEPLER_DEVICE_VGPU, ENG_GPU },
49 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
50 { MMU_FAULT_BUFFER, ENG_GR(0) },
51 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
52 { NV01_MEMORY_VIRTUAL, ENG_DMA },
53 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
54 { NV04_SOFTWARE_TEST, ENG_SW },
55 { NV50_DEFERRED_API_CLASS, ENG_SW },
56 { NV50_MEMORY_VIRTUAL, ENG_DMA },
57 { NV50_P2P, ENG_BUS },
58 { NV50_THIRD_PARTY_P2P, ENG_BUS },
59 { NVA081_VGPU_CONFIG, ENG_GPU },
60 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
61 { NVC371_DISP_SF_USER, ENG_KERNEL_DISPLAY },
62 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
63 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(0) },
64 { NVC4B7_VIDEO_ENCODER, ENG_MSENC(0) },
65 { NVC570_DISPLAY, ENG_KERNEL_DISPLAY },
66 { NVC573_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
67 { NVC57A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
68 { NVC57B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
69 { NVC57D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
70 { NVC57E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
71 { RM_USER_SHARED_DATA, ENG_GPU },
72 { TURING_A, ENG_GR(0) },
73 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
74 { TURING_COMPUTE_A, ENG_GR(0) },
75 { TURING_DMA_COPY_A, ENG_CE(0) },
76 { TURING_DMA_COPY_A, ENG_CE(1) },
77 { TURING_DMA_COPY_A, ENG_CE(2) },
78 { TURING_DMA_COPY_A, ENG_CE(3) },
79 { TURING_DMA_COPY_A, ENG_CE(4) },
80 { TURING_USERMODE_A, ENG_GPU },
81 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
82 { VOLTA_USERMODE_A, ENG_GPU },
83 };
84
85 #define HALTU102_NUM_CLASS_DESCS (sizeof(halTU102ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
86
87 #define HALTU102_NUM_CLASSES 52
88
89 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU102_NUM_CLASSES);
90
91 *pNumClassDescriptors = HALTU102_NUM_CLASS_DESCS;
92 return halTU102ClassDescriptorList;
93 }
94
95
96
97 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_TU104(POBJGPU pGpu,NvU32 * pNumClassDescriptors)98 gpuGetClassDescriptorList_TU104(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
99 {
100 static const CLASSDESCRIPTOR halTU104ClassDescriptorList[] = {
101 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
102 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
103 { FERMI_TWOD_A, ENG_GR(0) },
104 { FERMI_VASPACE_A, ENG_DMA },
105 { G84_PERFBUFFER, ENG_BUS },
106 { GF100_DISP_SW, ENG_SW },
107 { GF100_HDACODEC, ENG_HDACODEC },
108 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
109 { GF100_SUBDEVICE_MASTER, ENG_GPU },
110 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
111 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
112 { GP100_UVM_SW, ENG_SW },
113 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
114 { KEPLER_DEVICE_VGPU, ENG_GPU },
115 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
116 { MMU_FAULT_BUFFER, ENG_GR(0) },
117 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
118 { NV01_MEMORY_VIRTUAL, ENG_DMA },
119 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
120 { NV04_SOFTWARE_TEST, ENG_SW },
121 { NV50_DEFERRED_API_CLASS, ENG_SW },
122 { NV50_MEMORY_VIRTUAL, ENG_DMA },
123 { NV50_P2P, ENG_BUS },
124 { NV50_THIRD_PARTY_P2P, ENG_BUS },
125 { NVA081_VGPU_CONFIG, ENG_GPU },
126 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
127 { NVC371_DISP_SF_USER, ENG_KERNEL_DISPLAY },
128 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
129 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(0) },
130 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(1) },
131 { NVC4B7_VIDEO_ENCODER, ENG_MSENC(0) },
132 { NVC570_DISPLAY, ENG_KERNEL_DISPLAY },
133 { NVC573_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
134 { NVC57A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
135 { NVC57B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
136 { NVC57D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
137 { NVC57E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
138 { RM_USER_SHARED_DATA, ENG_GPU },
139 { TURING_A, ENG_GR(0) },
140 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
141 { TURING_COMPUTE_A, ENG_GR(0) },
142 { TURING_DMA_COPY_A, ENG_CE(0) },
143 { TURING_DMA_COPY_A, ENG_CE(1) },
144 { TURING_DMA_COPY_A, ENG_CE(2) },
145 { TURING_DMA_COPY_A, ENG_CE(3) },
146 { TURING_DMA_COPY_A, ENG_CE(4) },
147 { TURING_USERMODE_A, ENG_GPU },
148 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
149 { VOLTA_USERMODE_A, ENG_GPU },
150 };
151
152 #define HALTU104_NUM_CLASS_DESCS (sizeof(halTU104ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
153
154 #define HALTU104_NUM_CLASSES 52
155
156 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU104_NUM_CLASSES);
157
158 *pNumClassDescriptors = HALTU104_NUM_CLASS_DESCS;
159 return halTU104ClassDescriptorList;
160 }
161
162
163
164 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_TU106(POBJGPU pGpu,NvU32 * pNumClassDescriptors)165 gpuGetClassDescriptorList_TU106(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
166 {
167 static const CLASSDESCRIPTOR halTU106ClassDescriptorList[] = {
168 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
169 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
170 { FERMI_TWOD_A, ENG_GR(0) },
171 { FERMI_VASPACE_A, ENG_DMA },
172 { G84_PERFBUFFER, ENG_BUS },
173 { GF100_DISP_SW, ENG_SW },
174 { GF100_HDACODEC, ENG_HDACODEC },
175 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
176 { GF100_SUBDEVICE_MASTER, ENG_GPU },
177 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
178 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
179 { GP100_UVM_SW, ENG_SW },
180 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
181 { KEPLER_DEVICE_VGPU, ENG_GPU },
182 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
183 { MMU_FAULT_BUFFER, ENG_GR(0) },
184 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
185 { NV01_MEMORY_VIRTUAL, ENG_DMA },
186 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
187 { NV04_SOFTWARE_TEST, ENG_SW },
188 { NV50_DEFERRED_API_CLASS, ENG_SW },
189 { NV50_MEMORY_VIRTUAL, ENG_DMA },
190 { NV50_P2P, ENG_BUS },
191 { NV50_THIRD_PARTY_P2P, ENG_BUS },
192 { NVA081_VGPU_CONFIG, ENG_GPU },
193 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
194 { NVC371_DISP_SF_USER, ENG_KERNEL_DISPLAY },
195 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
196 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(0) },
197 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(1) },
198 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(2) },
199 { NVC4B7_VIDEO_ENCODER, ENG_MSENC(0) },
200 { NVC570_DISPLAY, ENG_KERNEL_DISPLAY },
201 { NVC573_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
202 { NVC57A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
203 { NVC57B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
204 { NVC57D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
205 { NVC57E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
206 { RM_USER_SHARED_DATA, ENG_GPU },
207 { TURING_A, ENG_GR(0) },
208 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
209 { TURING_COMPUTE_A, ENG_GR(0) },
210 { TURING_DMA_COPY_A, ENG_CE(0) },
211 { TURING_DMA_COPY_A, ENG_CE(1) },
212 { TURING_DMA_COPY_A, ENG_CE(2) },
213 { TURING_DMA_COPY_A, ENG_CE(3) },
214 { TURING_DMA_COPY_A, ENG_CE(4) },
215 { TURING_USERMODE_A, ENG_GPU },
216 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
217 { VOLTA_USERMODE_A, ENG_GPU },
218 };
219
220 #define HALTU106_NUM_CLASS_DESCS (sizeof(halTU106ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
221
222 #define HALTU106_NUM_CLASSES 52
223
224 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU106_NUM_CLASSES);
225
226 *pNumClassDescriptors = HALTU106_NUM_CLASS_DESCS;
227 return halTU106ClassDescriptorList;
228 }
229
230
231
232 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_TU116(POBJGPU pGpu,NvU32 * pNumClassDescriptors)233 gpuGetClassDescriptorList_TU116(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
234 {
235 static const CLASSDESCRIPTOR halTU116ClassDescriptorList[] = {
236 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
237 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
238 { FERMI_TWOD_A, ENG_GR(0) },
239 { FERMI_VASPACE_A, ENG_DMA },
240 { G84_PERFBUFFER, ENG_BUS },
241 { GF100_DISP_SW, ENG_SW },
242 { GF100_HDACODEC, ENG_HDACODEC },
243 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
244 { GF100_SUBDEVICE_MASTER, ENG_GPU },
245 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
246 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
247 { GP100_UVM_SW, ENG_SW },
248 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
249 { KEPLER_DEVICE_VGPU, ENG_GPU },
250 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
251 { MMU_FAULT_BUFFER, ENG_GR(0) },
252 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
253 { NV01_MEMORY_VIRTUAL, ENG_DMA },
254 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
255 { NV04_SOFTWARE_TEST, ENG_SW },
256 { NV50_DEFERRED_API_CLASS, ENG_SW },
257 { NV50_MEMORY_VIRTUAL, ENG_DMA },
258 { NV50_P2P, ENG_BUS },
259 { NV50_THIRD_PARTY_P2P, ENG_BUS },
260 { NVA081_VGPU_CONFIG, ENG_GPU },
261 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
262 { NVC371_DISP_SF_USER, ENG_KERNEL_DISPLAY },
263 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
264 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(0) },
265 { NVC4B7_VIDEO_ENCODER, ENG_MSENC(0) },
266 { NVC570_DISPLAY, ENG_KERNEL_DISPLAY },
267 { NVC573_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
268 { NVC57A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
269 { NVC57B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
270 { NVC57D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
271 { NVC57E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
272 { RM_USER_SHARED_DATA, ENG_GPU },
273 { TURING_A, ENG_GR(0) },
274 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
275 { TURING_COMPUTE_A, ENG_GR(0) },
276 { TURING_DMA_COPY_A, ENG_CE(0) },
277 { TURING_DMA_COPY_A, ENG_CE(1) },
278 { TURING_DMA_COPY_A, ENG_CE(2) },
279 { TURING_DMA_COPY_A, ENG_CE(3) },
280 { TURING_DMA_COPY_A, ENG_CE(4) },
281 { TURING_USERMODE_A, ENG_GPU },
282 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
283 { VOLTA_USERMODE_A, ENG_GPU },
284 };
285
286 #define HALTU116_NUM_CLASS_DESCS (sizeof(halTU116ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
287
288 #define HALTU116_NUM_CLASSES 52
289
290 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU116_NUM_CLASSES);
291
292 *pNumClassDescriptors = HALTU116_NUM_CLASS_DESCS;
293 return halTU116ClassDescriptorList;
294 }
295
296
297
298 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_TU117(POBJGPU pGpu,NvU32 * pNumClassDescriptors)299 gpuGetClassDescriptorList_TU117(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
300 {
301 static const CLASSDESCRIPTOR halTU117ClassDescriptorList[] = {
302 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
303 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
304 { FERMI_TWOD_A, ENG_GR(0) },
305 { FERMI_VASPACE_A, ENG_DMA },
306 { G84_PERFBUFFER, ENG_BUS },
307 { GF100_DISP_SW, ENG_SW },
308 { GF100_HDACODEC, ENG_HDACODEC },
309 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
310 { GF100_SUBDEVICE_MASTER, ENG_GPU },
311 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
312 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
313 { GP100_UVM_SW, ENG_SW },
314 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
315 { KEPLER_DEVICE_VGPU, ENG_GPU },
316 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
317 { MMU_FAULT_BUFFER, ENG_GR(0) },
318 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
319 { NV01_MEMORY_VIRTUAL, ENG_DMA },
320 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
321 { NV04_SOFTWARE_TEST, ENG_SW },
322 { NV50_DEFERRED_API_CLASS, ENG_SW },
323 { NV50_MEMORY_VIRTUAL, ENG_DMA },
324 { NV50_P2P, ENG_BUS },
325 { NV50_THIRD_PARTY_P2P, ENG_BUS },
326 { NVA081_VGPU_CONFIG, ENG_GPU },
327 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
328 { NVB4B7_VIDEO_ENCODER, ENG_MSENC(0) },
329 { NVC371_DISP_SF_USER, ENG_KERNEL_DISPLAY },
330 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
331 { NVC4B0_VIDEO_DECODER, ENG_NVDEC(0) },
332 { NVC570_DISPLAY, ENG_KERNEL_DISPLAY },
333 { NVC573_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
334 { NVC57A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
335 { NVC57B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
336 { NVC57D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
337 { NVC57E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
338 { RM_USER_SHARED_DATA, ENG_GPU },
339 { TURING_A, ENG_GR(0) },
340 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
341 { TURING_COMPUTE_A, ENG_GR(0) },
342 { TURING_DMA_COPY_A, ENG_CE(0) },
343 { TURING_DMA_COPY_A, ENG_CE(1) },
344 { TURING_DMA_COPY_A, ENG_CE(2) },
345 { TURING_DMA_COPY_A, ENG_CE(3) },
346 { TURING_DMA_COPY_A, ENG_CE(4) },
347 { TURING_USERMODE_A, ENG_GPU },
348 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
349 { VOLTA_USERMODE_A, ENG_GPU },
350 };
351
352 #define HALTU117_NUM_CLASS_DESCS (sizeof(halTU117ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
353
354 #define HALTU117_NUM_CLASSES 52
355
356 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU117_NUM_CLASSES);
357
358 *pNumClassDescriptors = HALTU117_NUM_CLASS_DESCS;
359 return halTU117ClassDescriptorList;
360 }
361
362
363
364 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_GA100(POBJGPU pGpu,NvU32 * pNumClassDescriptors)365 gpuGetClassDescriptorList_GA100(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
366 {
367 static const CLASSDESCRIPTOR halGA100ClassDescriptorList[] = {
368 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
369 { AMPERE_A, ENG_GR(0) },
370 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
371 { AMPERE_COMPUTE_A, ENG_GR(0) },
372 { AMPERE_COMPUTE_A, ENG_GR(1) },
373 { AMPERE_COMPUTE_A, ENG_GR(2) },
374 { AMPERE_COMPUTE_A, ENG_GR(3) },
375 { AMPERE_COMPUTE_A, ENG_GR(4) },
376 { AMPERE_COMPUTE_A, ENG_GR(5) },
377 { AMPERE_COMPUTE_A, ENG_GR(6) },
378 { AMPERE_COMPUTE_A, ENG_GR(7) },
379 { AMPERE_DMA_COPY_A, ENG_CE(0) },
380 { AMPERE_DMA_COPY_A, ENG_CE(1) },
381 { AMPERE_DMA_COPY_A, ENG_CE(2) },
382 { AMPERE_DMA_COPY_A, ENG_CE(3) },
383 { AMPERE_DMA_COPY_A, ENG_CE(4) },
384 { AMPERE_DMA_COPY_A, ENG_CE(5) },
385 { AMPERE_DMA_COPY_A, ENG_CE(6) },
386 { AMPERE_DMA_COPY_A, ENG_CE(7) },
387 { AMPERE_DMA_COPY_A, ENG_CE(8) },
388 { AMPERE_DMA_COPY_A, ENG_CE(9) },
389 { AMPERE_USERMODE_A, ENG_GPU },
390 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
391 { FERMI_TWOD_A, ENG_GR(0) },
392 { FERMI_VASPACE_A, ENG_DMA },
393 { G84_PERFBUFFER, ENG_BUS },
394 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
395 { GF100_SUBDEVICE_MASTER, ENG_GPU },
396 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
397 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
398 { GP100_UVM_SW, ENG_SW },
399 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
400 { KEPLER_DEVICE_VGPU, ENG_GPU },
401 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
402 { MMU_FAULT_BUFFER, ENG_GR(0) },
403 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
404 { NV01_MEMORY_VIRTUAL, ENG_DMA },
405 { NV04_SOFTWARE_TEST, ENG_SW },
406 { NV50_DEFERRED_API_CLASS, ENG_SW },
407 { NV50_MEMORY_VIRTUAL, ENG_DMA },
408 { NV50_P2P, ENG_BUS },
409 { NV50_THIRD_PARTY_P2P, ENG_BUS },
410 { NVA081_VGPU_CONFIG, ENG_GPU },
411 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
412 { NVC4D1_VIDEO_NVJPG, ENG_NVJPG },
413 { NVC6B0_VIDEO_DECODER, ENG_NVDEC(0) },
414 { NVC6B0_VIDEO_DECODER, ENG_NVDEC(1) },
415 { NVC6B0_VIDEO_DECODER, ENG_NVDEC(2) },
416 { NVC6B0_VIDEO_DECODER, ENG_NVDEC(3) },
417 { NVC6B0_VIDEO_DECODER, ENG_NVDEC(4) },
418 { NVC6FA_VIDEO_OFA, ENG_OFA(0) },
419 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE },
420 { RM_USER_SHARED_DATA, ENG_GPU },
421 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
422 { TURING_USERMODE_A, ENG_GPU },
423 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
424 { VOLTA_USERMODE_A, ENG_GPU },
425 };
426
427 #define HALGA100_NUM_CLASS_DESCS (sizeof(halGA100ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
428
429 #define HALGA100_NUM_CLASSES 46
430
431 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA100_NUM_CLASSES);
432
433 *pNumClassDescriptors = HALGA100_NUM_CLASS_DESCS;
434 return halGA100ClassDescriptorList;
435 }
436
437
438
439 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_GA102(POBJGPU pGpu,NvU32 * pNumClassDescriptors)440 gpuGetClassDescriptorList_GA102(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
441 {
442 static const CLASSDESCRIPTOR halGA102ClassDescriptorList[] = {
443 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
444 { AMPERE_B, ENG_GR(0) },
445 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
446 { AMPERE_COMPUTE_B, ENG_GR(0) },
447 { AMPERE_DMA_COPY_B, ENG_CE(0) },
448 { AMPERE_DMA_COPY_B, ENG_CE(1) },
449 { AMPERE_DMA_COPY_B, ENG_CE(2) },
450 { AMPERE_DMA_COPY_B, ENG_CE(3) },
451 { AMPERE_DMA_COPY_B, ENG_CE(4) },
452 { AMPERE_USERMODE_A, ENG_GPU },
453 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
454 { FERMI_TWOD_A, ENG_GR(0) },
455 { FERMI_VASPACE_A, ENG_DMA },
456 { G84_PERFBUFFER, ENG_BUS },
457 { GF100_DISP_SW, ENG_SW },
458 { GF100_HDACODEC, ENG_HDACODEC },
459 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
460 { GF100_SUBDEVICE_MASTER, ENG_GPU },
461 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
462 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
463 { GP100_UVM_SW, ENG_SW },
464 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
465 { KEPLER_DEVICE_VGPU, ENG_GPU },
466 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
467 { MMU_FAULT_BUFFER, ENG_GR(0) },
468 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
469 { NV01_MEMORY_VIRTUAL, ENG_DMA },
470 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
471 { NV04_SOFTWARE_TEST, ENG_SW },
472 { NV50_DEFERRED_API_CLASS, ENG_SW },
473 { NV50_MEMORY_VIRTUAL, ENG_DMA },
474 { NV50_P2P, ENG_BUS },
475 { NV50_THIRD_PARTY_P2P, ENG_BUS },
476 { NVA081_VGPU_CONFIG, ENG_GPU },
477 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
478 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
479 { NVC670_DISPLAY, ENG_KERNEL_DISPLAY },
480 { NVC671_DISP_SF_USER, ENG_KERNEL_DISPLAY },
481 { NVC673_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
482 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
483 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
484 { NVC67D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
485 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
486 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
487 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) },
488 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) },
489 { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) },
490 { NVC7FA_VIDEO_OFA, ENG_OFA(0) },
491 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE },
492 { RM_USER_SHARED_DATA, ENG_GPU },
493 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
494 { TURING_USERMODE_A, ENG_GPU },
495 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
496 { VOLTA_USERMODE_A, ENG_GPU },
497 };
498
499 #define HALGA102_NUM_CLASS_DESCS (sizeof(halGA102ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
500
501 #define HALGA102_NUM_CLASSES 58
502
503 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA102_NUM_CLASSES);
504
505 *pNumClassDescriptors = HALGA102_NUM_CLASS_DESCS;
506 return halGA102ClassDescriptorList;
507 }
508
509
510
511 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_GA103(POBJGPU pGpu,NvU32 * pNumClassDescriptors)512 gpuGetClassDescriptorList_GA103(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
513 {
514 static const CLASSDESCRIPTOR halGA103ClassDescriptorList[] = {
515 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
516 { AMPERE_B, ENG_GR(0) },
517 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
518 { AMPERE_COMPUTE_B, ENG_GR(0) },
519 { AMPERE_DMA_COPY_B, ENG_CE(0) },
520 { AMPERE_DMA_COPY_B, ENG_CE(1) },
521 { AMPERE_DMA_COPY_B, ENG_CE(2) },
522 { AMPERE_DMA_COPY_B, ENG_CE(3) },
523 { AMPERE_DMA_COPY_B, ENG_CE(4) },
524 { AMPERE_USERMODE_A, ENG_GPU },
525 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
526 { FERMI_TWOD_A, ENG_GR(0) },
527 { FERMI_VASPACE_A, ENG_DMA },
528 { G84_PERFBUFFER, ENG_BUS },
529 { GF100_DISP_SW, ENG_SW },
530 { GF100_HDACODEC, ENG_HDACODEC },
531 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
532 { GF100_SUBDEVICE_MASTER, ENG_GPU },
533 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
534 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
535 { GP100_UVM_SW, ENG_SW },
536 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
537 { KEPLER_DEVICE_VGPU, ENG_GPU },
538 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
539 { MMU_FAULT_BUFFER, ENG_GR(0) },
540 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
541 { NV01_MEMORY_VIRTUAL, ENG_DMA },
542 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
543 { NV04_SOFTWARE_TEST, ENG_SW },
544 { NV50_DEFERRED_API_CLASS, ENG_SW },
545 { NV50_MEMORY_VIRTUAL, ENG_DMA },
546 { NV50_P2P, ENG_BUS },
547 { NV50_THIRD_PARTY_P2P, ENG_BUS },
548 { NVA081_VGPU_CONFIG, ENG_GPU },
549 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
550 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
551 { NVC670_DISPLAY, ENG_KERNEL_DISPLAY },
552 { NVC671_DISP_SF_USER, ENG_KERNEL_DISPLAY },
553 { NVC673_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
554 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
555 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
556 { NVC67D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
557 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
558 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
559 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) },
560 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) },
561 { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) },
562 { NVC7FA_VIDEO_OFA, ENG_OFA(0) },
563 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE },
564 { RM_USER_SHARED_DATA, ENG_GPU },
565 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
566 { TURING_USERMODE_A, ENG_GPU },
567 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
568 { VOLTA_USERMODE_A, ENG_GPU },
569 };
570
571 #define HALGA103_NUM_CLASS_DESCS (sizeof(halGA103ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
572
573 #define HALGA103_NUM_CLASSES 58
574
575 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA103_NUM_CLASSES);
576
577 *pNumClassDescriptors = HALGA103_NUM_CLASS_DESCS;
578 return halGA103ClassDescriptorList;
579 }
580
581
582
583 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_GA104(POBJGPU pGpu,NvU32 * pNumClassDescriptors)584 gpuGetClassDescriptorList_GA104(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
585 {
586 static const CLASSDESCRIPTOR halGA104ClassDescriptorList[] = {
587 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
588 { AMPERE_B, ENG_GR(0) },
589 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
590 { AMPERE_COMPUTE_B, ENG_GR(0) },
591 { AMPERE_DMA_COPY_B, ENG_CE(0) },
592 { AMPERE_DMA_COPY_B, ENG_CE(1) },
593 { AMPERE_DMA_COPY_B, ENG_CE(2) },
594 { AMPERE_DMA_COPY_B, ENG_CE(3) },
595 { AMPERE_DMA_COPY_B, ENG_CE(4) },
596 { AMPERE_USERMODE_A, ENG_GPU },
597 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
598 { FERMI_TWOD_A, ENG_GR(0) },
599 { FERMI_VASPACE_A, ENG_DMA },
600 { G84_PERFBUFFER, ENG_BUS },
601 { GF100_DISP_SW, ENG_SW },
602 { GF100_HDACODEC, ENG_HDACODEC },
603 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
604 { GF100_SUBDEVICE_MASTER, ENG_GPU },
605 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
606 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
607 { GP100_UVM_SW, ENG_SW },
608 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
609 { KEPLER_DEVICE_VGPU, ENG_GPU },
610 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
611 { MMU_FAULT_BUFFER, ENG_GR(0) },
612 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
613 { NV01_MEMORY_VIRTUAL, ENG_DMA },
614 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
615 { NV04_SOFTWARE_TEST, ENG_SW },
616 { NV50_DEFERRED_API_CLASS, ENG_SW },
617 { NV50_MEMORY_VIRTUAL, ENG_DMA },
618 { NV50_P2P, ENG_BUS },
619 { NV50_THIRD_PARTY_P2P, ENG_BUS },
620 { NVA081_VGPU_CONFIG, ENG_GPU },
621 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
622 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
623 { NVC670_DISPLAY, ENG_KERNEL_DISPLAY },
624 { NVC671_DISP_SF_USER, ENG_KERNEL_DISPLAY },
625 { NVC673_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
626 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
627 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
628 { NVC67D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
629 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
630 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
631 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) },
632 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) },
633 { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) },
634 { NVC7FA_VIDEO_OFA, ENG_OFA(0) },
635 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE },
636 { RM_USER_SHARED_DATA, ENG_GPU },
637 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
638 { TURING_USERMODE_A, ENG_GPU },
639 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
640 { VOLTA_USERMODE_A, ENG_GPU },
641 };
642
643 #define HALGA104_NUM_CLASS_DESCS (sizeof(halGA104ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
644
645 #define HALGA104_NUM_CLASSES 58
646
647 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA104_NUM_CLASSES);
648
649 *pNumClassDescriptors = HALGA104_NUM_CLASS_DESCS;
650 return halGA104ClassDescriptorList;
651 }
652
653
654
655 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_GA106(POBJGPU pGpu,NvU32 * pNumClassDescriptors)656 gpuGetClassDescriptorList_GA106(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
657 {
658 static const CLASSDESCRIPTOR halGA106ClassDescriptorList[] = {
659 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
660 { AMPERE_B, ENG_GR(0) },
661 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
662 { AMPERE_COMPUTE_B, ENG_GR(0) },
663 { AMPERE_DMA_COPY_B, ENG_CE(0) },
664 { AMPERE_DMA_COPY_B, ENG_CE(1) },
665 { AMPERE_DMA_COPY_B, ENG_CE(2) },
666 { AMPERE_DMA_COPY_B, ENG_CE(3) },
667 { AMPERE_DMA_COPY_B, ENG_CE(4) },
668 { AMPERE_USERMODE_A, ENG_GPU },
669 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
670 { FERMI_TWOD_A, ENG_GR(0) },
671 { FERMI_VASPACE_A, ENG_DMA },
672 { G84_PERFBUFFER, ENG_BUS },
673 { GF100_DISP_SW, ENG_SW },
674 { GF100_HDACODEC, ENG_HDACODEC },
675 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
676 { GF100_SUBDEVICE_MASTER, ENG_GPU },
677 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
678 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
679 { GP100_UVM_SW, ENG_SW },
680 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
681 { KEPLER_DEVICE_VGPU, ENG_GPU },
682 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
683 { MMU_FAULT_BUFFER, ENG_GR(0) },
684 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
685 { NV01_MEMORY_VIRTUAL, ENG_DMA },
686 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
687 { NV04_SOFTWARE_TEST, ENG_SW },
688 { NV50_DEFERRED_API_CLASS, ENG_SW },
689 { NV50_MEMORY_VIRTUAL, ENG_DMA },
690 { NV50_P2P, ENG_BUS },
691 { NV50_THIRD_PARTY_P2P, ENG_BUS },
692 { NVA081_VGPU_CONFIG, ENG_GPU },
693 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
694 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
695 { NVC670_DISPLAY, ENG_KERNEL_DISPLAY },
696 { NVC671_DISP_SF_USER, ENG_KERNEL_DISPLAY },
697 { NVC673_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
698 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
699 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
700 { NVC67D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
701 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
702 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
703 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) },
704 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) },
705 { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) },
706 { NVC7FA_VIDEO_OFA, ENG_OFA(0) },
707 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE },
708 { RM_USER_SHARED_DATA, ENG_GPU },
709 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
710 { TURING_USERMODE_A, ENG_GPU },
711 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
712 { VOLTA_USERMODE_A, ENG_GPU },
713 };
714
715 #define HALGA106_NUM_CLASS_DESCS (sizeof(halGA106ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
716
717 #define HALGA106_NUM_CLASSES 58
718
719 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA106_NUM_CLASSES);
720
721 *pNumClassDescriptors = HALGA106_NUM_CLASS_DESCS;
722 return halGA106ClassDescriptorList;
723 }
724
725
726
727 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_GA107(POBJGPU pGpu,NvU32 * pNumClassDescriptors)728 gpuGetClassDescriptorList_GA107(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
729 {
730 static const CLASSDESCRIPTOR halGA107ClassDescriptorList[] = {
731 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
732 { AMPERE_B, ENG_GR(0) },
733 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
734 { AMPERE_COMPUTE_B, ENG_GR(0) },
735 { AMPERE_DMA_COPY_B, ENG_CE(0) },
736 { AMPERE_DMA_COPY_B, ENG_CE(1) },
737 { AMPERE_DMA_COPY_B, ENG_CE(2) },
738 { AMPERE_DMA_COPY_B, ENG_CE(3) },
739 { AMPERE_DMA_COPY_B, ENG_CE(4) },
740 { AMPERE_USERMODE_A, ENG_GPU },
741 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
742 { FERMI_TWOD_A, ENG_GR(0) },
743 { FERMI_VASPACE_A, ENG_DMA },
744 { G84_PERFBUFFER, ENG_BUS },
745 { GF100_DISP_SW, ENG_SW },
746 { GF100_HDACODEC, ENG_HDACODEC },
747 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
748 { GF100_SUBDEVICE_MASTER, ENG_GPU },
749 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
750 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
751 { GP100_UVM_SW, ENG_SW },
752 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
753 { KEPLER_DEVICE_VGPU, ENG_GPU },
754 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
755 { MMU_FAULT_BUFFER, ENG_GR(0) },
756 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
757 { NV01_MEMORY_VIRTUAL, ENG_DMA },
758 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
759 { NV04_SOFTWARE_TEST, ENG_SW },
760 { NV50_DEFERRED_API_CLASS, ENG_SW },
761 { NV50_MEMORY_VIRTUAL, ENG_DMA },
762 { NV50_P2P, ENG_BUS },
763 { NV50_THIRD_PARTY_P2P, ENG_BUS },
764 { NVA081_VGPU_CONFIG, ENG_GPU },
765 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
766 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
767 { NVC670_DISPLAY, ENG_KERNEL_DISPLAY },
768 { NVC671_DISP_SF_USER, ENG_KERNEL_DISPLAY },
769 { NVC673_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
770 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
771 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
772 { NVC67D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
773 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
774 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
775 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) },
776 { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) },
777 { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) },
778 { NVC7FA_VIDEO_OFA, ENG_OFA(0) },
779 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE },
780 { RM_USER_SHARED_DATA, ENG_GPU },
781 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
782 { TURING_USERMODE_A, ENG_GPU },
783 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
784 { VOLTA_USERMODE_A, ENG_GPU },
785 };
786
787 #define HALGA107_NUM_CLASS_DESCS (sizeof(halGA107ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
788
789 #define HALGA107_NUM_CLASSES 58
790
791 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA107_NUM_CLASSES);
792
793 *pNumClassDescriptors = HALGA107_NUM_CLASS_DESCS;
794 return halGA107ClassDescriptorList;
795 }
796
797
798
799 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_AD102(POBJGPU pGpu,NvU32 * pNumClassDescriptors)800 gpuGetClassDescriptorList_AD102(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
801 {
802 static const CLASSDESCRIPTOR halAD102ClassDescriptorList[] = {
803 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
804 { ADA_A, ENG_GR(0) },
805 { ADA_COMPUTE_A, ENG_GR(0) },
806 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
807 { AMPERE_DMA_COPY_B, ENG_CE(0) },
808 { AMPERE_DMA_COPY_B, ENG_CE(1) },
809 { AMPERE_DMA_COPY_B, ENG_CE(2) },
810 { AMPERE_DMA_COPY_B, ENG_CE(3) },
811 { AMPERE_DMA_COPY_B, ENG_CE(4) },
812 { AMPERE_USERMODE_A, ENG_GPU },
813 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
814 { FERMI_TWOD_A, ENG_GR(0) },
815 { FERMI_VASPACE_A, ENG_DMA },
816 { G84_PERFBUFFER, ENG_BUS },
817 { GF100_DISP_SW, ENG_SW },
818 { GF100_HDACODEC, ENG_HDACODEC },
819 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
820 { GF100_SUBDEVICE_MASTER, ENG_GPU },
821 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
822 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
823 { GP100_UVM_SW, ENG_SW },
824 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
825 { KEPLER_DEVICE_VGPU, ENG_GPU },
826 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
827 { MMU_FAULT_BUFFER, ENG_GR(0) },
828 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
829 { NV01_MEMORY_VIRTUAL, ENG_DMA },
830 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
831 { NV04_SOFTWARE_TEST, ENG_SW },
832 { NV50_DEFERRED_API_CLASS, ENG_SW },
833 { NV50_MEMORY_VIRTUAL, ENG_DMA },
834 { NV50_P2P, ENG_BUS },
835 { NV50_THIRD_PARTY_P2P, ENG_BUS },
836 { NVA081_VGPU_CONFIG, ENG_GPU },
837 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
838 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
839 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
840 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
841 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
842 { NVC770_DISPLAY, ENG_KERNEL_DISPLAY },
843 { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY },
844 { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
845 { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
846 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
847 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) },
848 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) },
849 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) },
850 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) },
851 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) },
852 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) },
853 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) },
854 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) },
855 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) },
856 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) },
857 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) },
858 { NVC9FA_VIDEO_OFA, ENG_OFA(0) },
859 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE },
860 { RM_USER_SHARED_DATA, ENG_GPU },
861 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
862 { TURING_USERMODE_A, ENG_GPU },
863 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
864 { VOLTA_USERMODE_A, ENG_GPU },
865 };
866
867 #define HALAD102_NUM_CLASS_DESCS (sizeof(halAD102ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
868
869 #define HALAD102_NUM_CLASSES 60
870
871 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD102_NUM_CLASSES);
872
873 *pNumClassDescriptors = HALAD102_NUM_CLASS_DESCS;
874 return halAD102ClassDescriptorList;
875 }
876
877
878
879 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_AD103(POBJGPU pGpu,NvU32 * pNumClassDescriptors)880 gpuGetClassDescriptorList_AD103(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
881 {
882 static const CLASSDESCRIPTOR halAD103ClassDescriptorList[] = {
883 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
884 { ADA_A, ENG_GR(0) },
885 { ADA_COMPUTE_A, ENG_GR(0) },
886 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
887 { AMPERE_DMA_COPY_B, ENG_CE(0) },
888 { AMPERE_DMA_COPY_B, ENG_CE(1) },
889 { AMPERE_DMA_COPY_B, ENG_CE(2) },
890 { AMPERE_DMA_COPY_B, ENG_CE(3) },
891 { AMPERE_DMA_COPY_B, ENG_CE(4) },
892 { AMPERE_USERMODE_A, ENG_GPU },
893 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
894 { FERMI_TWOD_A, ENG_GR(0) },
895 { FERMI_VASPACE_A, ENG_DMA },
896 { G84_PERFBUFFER, ENG_BUS },
897 { GF100_DISP_SW, ENG_SW },
898 { GF100_HDACODEC, ENG_HDACODEC },
899 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
900 { GF100_SUBDEVICE_MASTER, ENG_GPU },
901 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
902 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
903 { GP100_UVM_SW, ENG_SW },
904 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
905 { KEPLER_DEVICE_VGPU, ENG_GPU },
906 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
907 { MMU_FAULT_BUFFER, ENG_GR(0) },
908 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
909 { NV01_MEMORY_VIRTUAL, ENG_DMA },
910 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
911 { NV04_SOFTWARE_TEST, ENG_SW },
912 { NV50_DEFERRED_API_CLASS, ENG_SW },
913 { NV50_MEMORY_VIRTUAL, ENG_DMA },
914 { NV50_P2P, ENG_BUS },
915 { NV50_THIRD_PARTY_P2P, ENG_BUS },
916 { NVA081_VGPU_CONFIG, ENG_GPU },
917 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
918 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
919 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
920 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
921 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
922 { NVC770_DISPLAY, ENG_KERNEL_DISPLAY },
923 { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY },
924 { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
925 { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
926 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
927 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) },
928 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) },
929 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) },
930 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) },
931 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) },
932 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) },
933 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) },
934 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) },
935 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) },
936 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) },
937 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) },
938 { NVC9FA_VIDEO_OFA, ENG_OFA(0) },
939 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE },
940 { RM_USER_SHARED_DATA, ENG_GPU },
941 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
942 { TURING_USERMODE_A, ENG_GPU },
943 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
944 { VOLTA_USERMODE_A, ENG_GPU },
945 };
946
947 #define HALAD103_NUM_CLASS_DESCS (sizeof(halAD103ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
948
949 #define HALAD103_NUM_CLASSES 60
950
951 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD103_NUM_CLASSES);
952
953 *pNumClassDescriptors = HALAD103_NUM_CLASS_DESCS;
954 return halAD103ClassDescriptorList;
955 }
956
957
958
959 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_AD104(POBJGPU pGpu,NvU32 * pNumClassDescriptors)960 gpuGetClassDescriptorList_AD104(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
961 {
962 static const CLASSDESCRIPTOR halAD104ClassDescriptorList[] = {
963 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
964 { ADA_A, ENG_GR(0) },
965 { ADA_COMPUTE_A, ENG_GR(0) },
966 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
967 { AMPERE_DMA_COPY_B, ENG_CE(0) },
968 { AMPERE_DMA_COPY_B, ENG_CE(1) },
969 { AMPERE_DMA_COPY_B, ENG_CE(2) },
970 { AMPERE_DMA_COPY_B, ENG_CE(3) },
971 { AMPERE_DMA_COPY_B, ENG_CE(4) },
972 { AMPERE_USERMODE_A, ENG_GPU },
973 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
974 { FERMI_TWOD_A, ENG_GR(0) },
975 { FERMI_VASPACE_A, ENG_DMA },
976 { G84_PERFBUFFER, ENG_BUS },
977 { GF100_DISP_SW, ENG_SW },
978 { GF100_HDACODEC, ENG_HDACODEC },
979 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
980 { GF100_SUBDEVICE_MASTER, ENG_GPU },
981 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
982 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
983 { GP100_UVM_SW, ENG_SW },
984 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
985 { KEPLER_DEVICE_VGPU, ENG_GPU },
986 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
987 { MMU_FAULT_BUFFER, ENG_GR(0) },
988 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
989 { NV01_MEMORY_VIRTUAL, ENG_DMA },
990 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
991 { NV04_SOFTWARE_TEST, ENG_SW },
992 { NV50_DEFERRED_API_CLASS, ENG_SW },
993 { NV50_MEMORY_VIRTUAL, ENG_DMA },
994 { NV50_P2P, ENG_BUS },
995 { NV50_THIRD_PARTY_P2P, ENG_BUS },
996 { NVA081_VGPU_CONFIG, ENG_GPU },
997 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
998 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
999 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
1000 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
1001 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
1002 { NVC770_DISPLAY, ENG_KERNEL_DISPLAY },
1003 { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY },
1004 { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
1005 { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
1006 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
1007 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) },
1008 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) },
1009 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) },
1010 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) },
1011 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) },
1012 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) },
1013 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) },
1014 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) },
1015 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) },
1016 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) },
1017 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) },
1018 { NVC9FA_VIDEO_OFA, ENG_OFA(0) },
1019 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE },
1020 { RM_USER_SHARED_DATA, ENG_GPU },
1021 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
1022 { TURING_USERMODE_A, ENG_GPU },
1023 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
1024 { VOLTA_USERMODE_A, ENG_GPU },
1025 };
1026
1027 #define HALAD104_NUM_CLASS_DESCS (sizeof(halAD104ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
1028
1029 #define HALAD104_NUM_CLASSES 60
1030
1031 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD104_NUM_CLASSES);
1032
1033 *pNumClassDescriptors = HALAD104_NUM_CLASS_DESCS;
1034 return halAD104ClassDescriptorList;
1035 }
1036
1037
1038
1039 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_AD106(POBJGPU pGpu,NvU32 * pNumClassDescriptors)1040 gpuGetClassDescriptorList_AD106(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
1041 {
1042 static const CLASSDESCRIPTOR halAD106ClassDescriptorList[] = {
1043 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
1044 { ADA_A, ENG_GR(0) },
1045 { ADA_COMPUTE_A, ENG_GR(0) },
1046 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
1047 { AMPERE_DMA_COPY_B, ENG_CE(0) },
1048 { AMPERE_DMA_COPY_B, ENG_CE(1) },
1049 { AMPERE_DMA_COPY_B, ENG_CE(2) },
1050 { AMPERE_DMA_COPY_B, ENG_CE(3) },
1051 { AMPERE_DMA_COPY_B, ENG_CE(4) },
1052 { AMPERE_USERMODE_A, ENG_GPU },
1053 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
1054 { FERMI_TWOD_A, ENG_GR(0) },
1055 { FERMI_VASPACE_A, ENG_DMA },
1056 { G84_PERFBUFFER, ENG_BUS },
1057 { GF100_DISP_SW, ENG_SW },
1058 { GF100_HDACODEC, ENG_HDACODEC },
1059 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
1060 { GF100_SUBDEVICE_MASTER, ENG_GPU },
1061 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
1062 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
1063 { GP100_UVM_SW, ENG_SW },
1064 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
1065 { KEPLER_DEVICE_VGPU, ENG_GPU },
1066 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
1067 { MMU_FAULT_BUFFER, ENG_GR(0) },
1068 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
1069 { NV01_MEMORY_VIRTUAL, ENG_DMA },
1070 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
1071 { NV04_SOFTWARE_TEST, ENG_SW },
1072 { NV50_DEFERRED_API_CLASS, ENG_SW },
1073 { NV50_MEMORY_VIRTUAL, ENG_DMA },
1074 { NV50_P2P, ENG_BUS },
1075 { NV50_THIRD_PARTY_P2P, ENG_BUS },
1076 { NVA081_VGPU_CONFIG, ENG_GPU },
1077 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
1078 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
1079 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
1080 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
1081 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
1082 { NVC770_DISPLAY, ENG_KERNEL_DISPLAY },
1083 { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY },
1084 { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
1085 { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
1086 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
1087 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) },
1088 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) },
1089 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) },
1090 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) },
1091 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) },
1092 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) },
1093 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) },
1094 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) },
1095 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) },
1096 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) },
1097 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) },
1098 { NVC9FA_VIDEO_OFA, ENG_OFA(0) },
1099 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE },
1100 { RM_USER_SHARED_DATA, ENG_GPU },
1101 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
1102 { TURING_USERMODE_A, ENG_GPU },
1103 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
1104 { VOLTA_USERMODE_A, ENG_GPU },
1105 };
1106
1107 #define HALAD106_NUM_CLASS_DESCS (sizeof(halAD106ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
1108
1109 #define HALAD106_NUM_CLASSES 60
1110
1111 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD106_NUM_CLASSES);
1112
1113 *pNumClassDescriptors = HALAD106_NUM_CLASS_DESCS;
1114 return halAD106ClassDescriptorList;
1115 }
1116
1117
1118
1119 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_AD107(POBJGPU pGpu,NvU32 * pNumClassDescriptors)1120 gpuGetClassDescriptorList_AD107(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
1121 {
1122 static const CLASSDESCRIPTOR halAD107ClassDescriptorList[] = {
1123 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
1124 { ADA_A, ENG_GR(0) },
1125 { ADA_COMPUTE_A, ENG_GR(0) },
1126 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
1127 { AMPERE_DMA_COPY_B, ENG_CE(0) },
1128 { AMPERE_DMA_COPY_B, ENG_CE(1) },
1129 { AMPERE_DMA_COPY_B, ENG_CE(2) },
1130 { AMPERE_DMA_COPY_B, ENG_CE(3) },
1131 { AMPERE_DMA_COPY_B, ENG_CE(4) },
1132 { AMPERE_USERMODE_A, ENG_GPU },
1133 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
1134 { FERMI_TWOD_A, ENG_GR(0) },
1135 { FERMI_VASPACE_A, ENG_DMA },
1136 { G84_PERFBUFFER, ENG_BUS },
1137 { GF100_DISP_SW, ENG_SW },
1138 { GF100_HDACODEC, ENG_HDACODEC },
1139 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
1140 { GF100_SUBDEVICE_MASTER, ENG_GPU },
1141 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
1142 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
1143 { GP100_UVM_SW, ENG_SW },
1144 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
1145 { KEPLER_DEVICE_VGPU, ENG_GPU },
1146 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
1147 { MMU_FAULT_BUFFER, ENG_GR(0) },
1148 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
1149 { NV01_MEMORY_VIRTUAL, ENG_DMA },
1150 { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY },
1151 { NV04_SOFTWARE_TEST, ENG_SW },
1152 { NV50_DEFERRED_API_CLASS, ENG_SW },
1153 { NV50_MEMORY_VIRTUAL, ENG_DMA },
1154 { NV50_P2P, ENG_BUS },
1155 { NV50_THIRD_PARTY_P2P, ENG_BUS },
1156 { NVA081_VGPU_CONFIG, ENG_GPU },
1157 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
1158 { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY },
1159 { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY },
1160 { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
1161 { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
1162 { NVC770_DISPLAY, ENG_KERNEL_DISPLAY },
1163 { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY },
1164 { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY },
1165 { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
1166 { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY },
1167 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) },
1168 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) },
1169 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) },
1170 { NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) },
1171 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) },
1172 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) },
1173 { NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) },
1174 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) },
1175 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) },
1176 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) },
1177 { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) },
1178 { NVC9FA_VIDEO_OFA, ENG_OFA(0) },
1179 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE },
1180 { RM_USER_SHARED_DATA, ENG_GPU },
1181 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
1182 { TURING_USERMODE_A, ENG_GPU },
1183 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
1184 { VOLTA_USERMODE_A, ENG_GPU },
1185 };
1186
1187 #define HALAD107_NUM_CLASS_DESCS (sizeof(halAD107ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
1188
1189 #define HALAD107_NUM_CLASSES 60
1190
1191 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD107_NUM_CLASSES);
1192
1193 *pNumClassDescriptors = HALAD107_NUM_CLASS_DESCS;
1194 return halAD107ClassDescriptorList;
1195 }
1196
1197
1198
1199 const CLASSDESCRIPTOR *
gpuGetClassDescriptorList_GH100(POBJGPU pGpu,NvU32 * pNumClassDescriptors)1200 gpuGetClassDescriptorList_GH100(POBJGPU pGpu, NvU32 *pNumClassDescriptors)
1201 {
1202 static const CLASSDESCRIPTOR halGH100ClassDescriptorList[] = {
1203 { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) },
1204 { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
1205 { AMPERE_USERMODE_A, ENG_GPU },
1206 { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO },
1207 { FERMI_TWOD_A, ENG_GR(0) },
1208 { FERMI_VASPACE_A, ENG_DMA },
1209 { G84_PERFBUFFER, ENG_BUS },
1210 { GF100_SUBDEVICE_INFOROM, ENG_GPU },
1211 { GF100_SUBDEVICE_MASTER, ENG_GPU },
1212 { GF100_TIMED_SEMAPHORE_SW, ENG_SW },
1213 { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM },
1214 { GP100_UVM_SW, ENG_SW },
1215 { HOPPER_A, ENG_GR(0) },
1216 { HOPPER_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
1217 { HOPPER_COMPUTE_A, ENG_GR(0) },
1218 { HOPPER_COMPUTE_A, ENG_GR(1) },
1219 { HOPPER_COMPUTE_A, ENG_GR(2) },
1220 { HOPPER_COMPUTE_A, ENG_GR(3) },
1221 { HOPPER_COMPUTE_A, ENG_GR(4) },
1222 { HOPPER_COMPUTE_A, ENG_GR(5) },
1223 { HOPPER_COMPUTE_A, ENG_GR(6) },
1224 { HOPPER_COMPUTE_A, ENG_GR(7) },
1225 { HOPPER_DMA_COPY_A, ENG_CE(0) },
1226 { HOPPER_DMA_COPY_A, ENG_CE(1) },
1227 { HOPPER_DMA_COPY_A, ENG_CE(2) },
1228 { HOPPER_DMA_COPY_A, ENG_CE(3) },
1229 { HOPPER_DMA_COPY_A, ENG_CE(4) },
1230 { HOPPER_DMA_COPY_A, ENG_CE(5) },
1231 { HOPPER_DMA_COPY_A, ENG_CE(6) },
1232 { HOPPER_DMA_COPY_A, ENG_CE(7) },
1233 { HOPPER_DMA_COPY_A, ENG_CE(8) },
1234 { HOPPER_DMA_COPY_A, ENG_CE(9) },
1235 { HOPPER_SEC2_WORK_LAUNCH_A, ENG_SEC2 },
1236 { HOPPER_USERMODE_A, ENG_GPU },
1237 { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO },
1238 { KEPLER_DEVICE_VGPU, ENG_GPU },
1239 { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) },
1240 { MMU_FAULT_BUFFER, ENG_GR(0) },
1241 { NV0060_SYNC_GPU_BOOST, ENG_GPU },
1242 { NV01_MEMORY_VIRTUAL, ENG_DMA },
1243 { NV04_SOFTWARE_TEST, ENG_SW },
1244 { NV50_DEFERRED_API_CLASS, ENG_SW },
1245 { NV50_MEMORY_VIRTUAL, ENG_DMA },
1246 { NV50_P2P, ENG_BUS },
1247 { NV50_THIRD_PARTY_P2P, ENG_BUS },
1248 { NVA081_VGPU_CONFIG, ENG_GPU },
1249 { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU },
1250 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(0) },
1251 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(1) },
1252 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(2) },
1253 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(3) },
1254 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(4) },
1255 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(5) },
1256 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(6) },
1257 { NVB8B0_VIDEO_DECODER, ENG_NVDEC(7) },
1258 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(0) },
1259 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(1) },
1260 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(2) },
1261 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(3) },
1262 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(4) },
1263 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(5) },
1264 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(6) },
1265 { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(7) },
1266 { NVB8FA_VIDEO_OFA, ENG_OFA(0) },
1267 { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE },
1268 { RM_USER_SHARED_DATA, ENG_GPU },
1269 { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
1270 { TURING_USERMODE_A, ENG_GPU },
1271 { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO },
1272 { VOLTA_USERMODE_A, ENG_GPU },
1273 };
1274
1275 #define HALGH100_NUM_CLASS_DESCS (sizeof(halGH100ClassDescriptorList) / sizeof(CLASSDESCRIPTOR))
1276
1277 #define HALGH100_NUM_CLASSES 49
1278
1279 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGH100_NUM_CLASSES);
1280
1281 *pNumClassDescriptors = HALGH100_NUM_CLASS_DESCS;
1282 return halGH100ClassDescriptorList;
1283 }
1284
1285
1286