1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/agp_backend.h>
64 #include <linux/atomic.h>
65 #include <linux/wait.h>
66 #include <linux/list.h>
67 #include <linux/kref.h>
68 #include <linux/interval_tree.h>
69 #include <linux/hashtable.h>
70 #include <linux/dma-fence.h>
71
72 #ifdef CONFIG_MMU_NOTIFIER
73 #include <linux/mmu_notifier.h>
74 #endif
75
76 #include <drm/ttm/ttm_bo.h>
77 #include <drm/ttm/ttm_placement.h>
78 #include <drm/ttm/ttm_execbuf_util.h>
79
80 #include <drm/drm_gem.h>
81 #include <drm/drm_audio_component.h>
82 #include <drm/drm_suballoc.h>
83 #include <drm/drm_legacy.h>
84
85 #include <dev/wscons/wsconsio.h>
86 #include <dev/wscons/wsdisplayvar.h>
87 #include <dev/rasops/rasops.h>
88
89 #include <dev/pci/pcivar.h>
90
91 #ifdef __sparc64__
92 #include <machine/fbvar.h>
93 #endif
94
95 #include "radeon_family.h"
96 #include "radeon_mode.h"
97 #include "radeon_reg.h"
98
99 /*
100 * Modules parameters.
101 */
102 extern int radeon_no_wb;
103 extern int radeon_modeset;
104 extern int radeon_dynclks;
105 extern int radeon_r4xx_atom;
106 extern int radeon_agpmode;
107 extern int radeon_vram_limit;
108 extern int radeon_gart_size;
109 extern int radeon_benchmarking;
110 extern int radeon_testing;
111 extern int radeon_connector_table;
112 extern int radeon_tv;
113 extern int radeon_audio;
114 extern int radeon_disp_priority;
115 extern int radeon_hw_i2c;
116 extern int radeon_pcie_gen2;
117 extern int radeon_msi;
118 extern int radeon_lockup_timeout;
119 extern int radeon_fastfb;
120 extern int radeon_dpm;
121 extern int radeon_aspm;
122 extern int radeon_runtime_pm;
123 extern int radeon_hard_reset;
124 extern int radeon_vm_size;
125 extern int radeon_vm_block_size;
126 extern int radeon_deep_color;
127 extern int radeon_use_pflipirq;
128 extern int radeon_bapm;
129 extern int radeon_backlight;
130 extern int radeon_auxch;
131 extern int radeon_uvd;
132 extern int radeon_vce;
133 extern int radeon_si_support;
134 extern int radeon_cik_support;
135
136 /*
137 * Copy from radeon_drv.h so we don't have to include both and have conflicting
138 * symbol;
139 */
140 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
141 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
142 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
143 /* RADEON_IB_POOL_SIZE must be a power of 2 */
144 #define RADEON_IB_POOL_SIZE 16
145 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
146 #define RADEONFB_CONN_LIMIT 4
147 #define RADEON_BIOS_NUM_SCRATCH 8
148
149 /* internal ring indices */
150 /* r1xx+ has gfx CP ring */
151 #define RADEON_RING_TYPE_GFX_INDEX 0
152
153 /* cayman has 2 compute CP rings */
154 #define CAYMAN_RING_TYPE_CP1_INDEX 1
155 #define CAYMAN_RING_TYPE_CP2_INDEX 2
156
157 /* R600+ has an async dma ring */
158 #define R600_RING_TYPE_DMA_INDEX 3
159 /* cayman add a second async dma ring */
160 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
161
162 /* R600+ */
163 #define R600_RING_TYPE_UVD_INDEX 5
164
165 /* TN+ */
166 #define TN_RING_TYPE_VCE1_INDEX 6
167 #define TN_RING_TYPE_VCE2_INDEX 7
168
169 /* max number of rings */
170 #define RADEON_NUM_RINGS 8
171
172 /* number of hw syncs before falling back on blocking */
173 #define RADEON_NUM_SYNCS 4
174
175 /* hardcode those limit for now */
176 #define RADEON_VA_IB_OFFSET (1 << 20)
177 #define RADEON_VA_RESERVED_SIZE (8 << 20)
178 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
179
180 /* hard reset data */
181 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
182
183 /* reset flags */
184 #define RADEON_RESET_GFX (1 << 0)
185 #define RADEON_RESET_COMPUTE (1 << 1)
186 #define RADEON_RESET_DMA (1 << 2)
187 #define RADEON_RESET_CP (1 << 3)
188 #define RADEON_RESET_GRBM (1 << 4)
189 #define RADEON_RESET_DMA1 (1 << 5)
190 #define RADEON_RESET_RLC (1 << 6)
191 #define RADEON_RESET_SEM (1 << 7)
192 #define RADEON_RESET_IH (1 << 8)
193 #define RADEON_RESET_VMC (1 << 9)
194 #define RADEON_RESET_MC (1 << 10)
195 #define RADEON_RESET_DISPLAY (1 << 11)
196
197 /* CG block flags */
198 #define RADEON_CG_BLOCK_GFX (1 << 0)
199 #define RADEON_CG_BLOCK_MC (1 << 1)
200 #define RADEON_CG_BLOCK_SDMA (1 << 2)
201 #define RADEON_CG_BLOCK_UVD (1 << 3)
202 #define RADEON_CG_BLOCK_VCE (1 << 4)
203 #define RADEON_CG_BLOCK_HDP (1 << 5)
204 #define RADEON_CG_BLOCK_BIF (1 << 6)
205
206 /* CG flags */
207 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
208 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
209 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
210 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
211 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
212 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
213 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
214 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
215 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
216 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
217 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
218 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
219 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
220 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
221 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
222 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
223 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
224
225 /* PG flags */
226 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
227 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
228 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
229 #define RADEON_PG_SUPPORT_UVD (1 << 3)
230 #define RADEON_PG_SUPPORT_VCE (1 << 4)
231 #define RADEON_PG_SUPPORT_CP (1 << 5)
232 #define RADEON_PG_SUPPORT_GDS (1 << 6)
233 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
234 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
235 #define RADEON_PG_SUPPORT_ACP (1 << 9)
236 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
237
238 /* max cursor sizes (in pixels) */
239 #define CURSOR_WIDTH 64
240 #define CURSOR_HEIGHT 64
241
242 #define CIK_CURSOR_WIDTH 128
243 #define CIK_CURSOR_HEIGHT 128
244
245 /*
246 * Errata workarounds.
247 */
248 enum radeon_pll_errata {
249 CHIP_ERRATA_R300_CG = 0x00000001,
250 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
251 CHIP_ERRATA_PLL_DELAY = 0x00000004
252 };
253
254
255 struct radeon_device;
256
257
258 /*
259 * BIOS.
260 */
261 bool radeon_get_bios(struct radeon_device *rdev);
262
263 /*
264 * Dummy page
265 */
266 struct radeon_dummy_page {
267 uint64_t entry;
268 struct drm_dmamem *dmah;
269 dma_addr_t addr;
270 };
271 int radeon_dummy_page_init(struct radeon_device *rdev);
272 void radeon_dummy_page_fini(struct radeon_device *rdev);
273
274
275 /*
276 * Clocks
277 */
278 struct radeon_clock {
279 struct radeon_pll p1pll;
280 struct radeon_pll p2pll;
281 struct radeon_pll dcpll;
282 struct radeon_pll spll;
283 struct radeon_pll mpll;
284 /* 10 Khz units */
285 uint32_t default_mclk;
286 uint32_t default_sclk;
287 uint32_t default_dispclk;
288 uint32_t current_dispclk;
289 uint32_t dp_extclk;
290 uint32_t max_pixel_clock;
291 uint32_t vco_freq;
292 };
293
294 /*
295 * Power management
296 */
297 int radeon_pm_init(struct radeon_device *rdev);
298 int radeon_pm_late_init(struct radeon_device *rdev);
299 void radeon_pm_fini(struct radeon_device *rdev);
300 void radeon_pm_compute_clocks(struct radeon_device *rdev);
301 void radeon_pm_suspend(struct radeon_device *rdev);
302 void radeon_pm_resume(struct radeon_device *rdev);
303 void radeon_combios_get_power_modes(struct radeon_device *rdev);
304 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
305 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
306 u8 clock_type,
307 u32 clock,
308 bool strobe_mode,
309 struct atom_clock_dividers *dividers);
310 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
311 u32 clock,
312 bool strobe_mode,
313 struct atom_mpll_param *mpll_param);
314 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
315 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
316 u16 voltage_level, u8 voltage_type,
317 u32 *gpio_value, u32 *gpio_mask);
318 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
319 u32 eng_clock, u32 mem_clock);
320 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
321 u8 voltage_type, u16 *voltage_step);
322 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
323 u16 voltage_id, u16 *voltage);
324 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
325 u16 *voltage,
326 u16 leakage_idx);
327 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
328 u16 *leakage_id);
329 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
330 u16 *vddc, u16 *vddci,
331 u16 virtual_voltage_id,
332 u16 vbios_voltage_id);
333 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
334 u16 virtual_voltage_id,
335 u16 *voltage);
336 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
337 u8 voltage_type,
338 u16 nominal_voltage,
339 u16 *true_voltage);
340 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
341 u8 voltage_type, u16 *min_voltage);
342 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
343 u8 voltage_type, u16 *max_voltage);
344 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
345 u8 voltage_type, u8 voltage_mode,
346 struct atom_voltage_table *voltage_table);
347 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
348 u8 voltage_type, u8 voltage_mode);
349 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
350 u8 voltage_type,
351 u8 *svd_gpio_id, u8 *svc_gpio_id);
352 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
353 u32 mem_clock);
354 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
355 u32 mem_clock);
356 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
357 u8 module_index,
358 struct atom_mc_reg_table *reg_table);
359 int radeon_atom_get_memory_info(struct radeon_device *rdev,
360 u8 module_index, struct atom_memory_info *mem_info);
361 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
362 bool gddr5, u8 module_index,
363 struct atom_memory_clock_range_table *mclk_range_table);
364 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
365 u16 voltage_id, u16 *voltage);
366 void rs690_pm_info(struct radeon_device *rdev);
367 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
368 unsigned *bankh, unsigned *mtaspect,
369 unsigned *tile_split);
370
371 /*
372 * Fences.
373 */
374 struct radeon_fence_driver {
375 struct radeon_device *rdev;
376 uint32_t scratch_reg;
377 uint64_t gpu_addr;
378 volatile uint32_t *cpu_addr;
379 /* sync_seq is protected by ring emission lock */
380 uint64_t sync_seq[RADEON_NUM_RINGS];
381 atomic64_t last_seq;
382 bool initialized, delayed_irq;
383 struct delayed_work lockup_work;
384 };
385
386 struct radeon_fence {
387 struct dma_fence base;
388
389 struct radeon_device *rdev;
390 uint64_t seq;
391 /* RB, DMA, etc. */
392 unsigned ring;
393 bool is_vm_update;
394
395 wait_queue_entry_t fence_wake;
396 };
397
398 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
399 void radeon_fence_driver_init(struct radeon_device *rdev);
400 void radeon_fence_driver_fini(struct radeon_device *rdev);
401 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
402 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
403 void radeon_fence_process(struct radeon_device *rdev, int ring);
404 bool radeon_fence_signaled(struct radeon_fence *fence);
405 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
406 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
407 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
408 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
409 int radeon_fence_wait_any(struct radeon_device *rdev,
410 struct radeon_fence **fences,
411 bool intr);
412 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
413 void radeon_fence_unref(struct radeon_fence **fence);
414 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
415 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
416 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
radeon_fence_later(struct radeon_fence * a,struct radeon_fence * b)417 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
418 struct radeon_fence *b)
419 {
420 if (!a) {
421 return b;
422 }
423
424 if (!b) {
425 return a;
426 }
427
428 BUG_ON(a->ring != b->ring);
429
430 if (a->seq > b->seq) {
431 return a;
432 } else {
433 return b;
434 }
435 }
436
radeon_fence_is_earlier(struct radeon_fence * a,struct radeon_fence * b)437 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
438 struct radeon_fence *b)
439 {
440 if (!a) {
441 return false;
442 }
443
444 if (!b) {
445 return true;
446 }
447
448 BUG_ON(a->ring != b->ring);
449
450 return a->seq < b->seq;
451 }
452
453 /*
454 * Tiling registers
455 */
456 struct radeon_surface_reg {
457 struct radeon_bo *bo;
458 };
459
460 #define RADEON_GEM_MAX_SURFACES 8
461
462 /*
463 * TTM.
464 */
465 struct radeon_mman {
466 struct ttm_device bdev;
467 bool initialized;
468 };
469
470 struct radeon_bo_list {
471 struct radeon_bo *robj;
472 struct ttm_validate_buffer tv;
473 uint64_t gpu_offset;
474 unsigned preferred_domains;
475 unsigned allowed_domains;
476 uint32_t tiling_flags;
477 };
478
479 /* bo virtual address in a specific vm */
480 struct radeon_bo_va {
481 /* protected by bo being reserved */
482 struct list_head bo_list;
483 uint32_t flags;
484 struct radeon_fence *last_pt_update;
485 unsigned ref_count;
486
487 /* protected by vm mutex */
488 struct interval_tree_node it;
489 struct list_head vm_status;
490
491 /* constant after initialization */
492 struct radeon_vm *vm;
493 struct radeon_bo *bo;
494 };
495
496 struct radeon_bo {
497 /* Protected by gem.mutex */
498 struct list_head list;
499 /* Protected by tbo.reserved */
500 u32 initial_domain;
501 struct ttm_place placements[4];
502 struct ttm_placement placement;
503 struct ttm_buffer_object tbo;
504 struct ttm_bo_kmap_obj kmap;
505 u32 flags;
506 void *kptr;
507 u32 tiling_flags;
508 u32 pitch;
509 int surface_reg;
510 unsigned prime_shared_count;
511 /* list of all virtual address to which this bo
512 * is associated to
513 */
514 struct list_head va;
515 /* Constant after initialization */
516 struct radeon_device *rdev;
517
518 pid_t pid;
519
520 #ifdef CONFIG_MMU_NOTIFIER
521 struct mmu_interval_notifier notifier;
522 #endif
523 };
524 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base)
525
526 struct radeon_sa_manager {
527 struct drm_suballoc_manager base;
528 struct radeon_bo *bo;
529 uint64_t gpu_addr;
530 void *cpu_ptr;
531 u32 domain;
532 };
533
534 /*
535 * GEM objects.
536 */
537 struct radeon_gem {
538 struct rwlock mutex;
539 struct list_head objects;
540 };
541
542 extern const struct drm_gem_object_funcs radeon_gem_object_funcs;
543
544 int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled);
545
546 int radeon_gem_init(struct radeon_device *rdev);
547 void radeon_gem_fini(struct radeon_device *rdev);
548 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
549 int alignment, int initial_domain,
550 u32 flags, bool kernel,
551 struct drm_gem_object **obj);
552
553 int radeon_mode_dumb_create(struct drm_file *file_priv,
554 struct drm_device *dev,
555 struct drm_mode_create_dumb *args);
556 int radeon_mode_dumb_mmap(struct drm_file *filp,
557 struct drm_device *dev,
558 uint32_t handle, uint64_t *offset_p);
559
560 /*
561 * Semaphores.
562 */
563 struct radeon_semaphore {
564 struct drm_suballoc *sa_bo;
565 signed waiters;
566 uint64_t gpu_addr;
567 };
568
569 int radeon_semaphore_create(struct radeon_device *rdev,
570 struct radeon_semaphore **semaphore);
571 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
572 struct radeon_semaphore *semaphore);
573 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
574 struct radeon_semaphore *semaphore);
575 void radeon_semaphore_free(struct radeon_device *rdev,
576 struct radeon_semaphore **semaphore,
577 struct radeon_fence *fence);
578
579 /*
580 * Synchronization
581 */
582 struct radeon_sync {
583 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
584 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
585 struct radeon_fence *last_vm_update;
586 };
587
588 void radeon_sync_create(struct radeon_sync *sync);
589 void radeon_sync_fence(struct radeon_sync *sync,
590 struct radeon_fence *fence);
591 int radeon_sync_resv(struct radeon_device *rdev,
592 struct radeon_sync *sync,
593 struct dma_resv *resv,
594 bool shared);
595 int radeon_sync_rings(struct radeon_device *rdev,
596 struct radeon_sync *sync,
597 int waiting_ring);
598 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
599 struct radeon_fence *fence);
600
601 /*
602 * GART structures, functions & helpers
603 */
604 struct radeon_mc;
605
606 #define RADEON_GPU_PAGE_SIZE 4096
607 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
608 #define RADEON_GPU_PAGE_SHIFT 12
609 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
610
611 #define RADEON_GART_PAGE_DUMMY 0
612 #define RADEON_GART_PAGE_VALID (1 << 0)
613 #define RADEON_GART_PAGE_READ (1 << 1)
614 #define RADEON_GART_PAGE_WRITE (1 << 2)
615 #define RADEON_GART_PAGE_SNOOP (1 << 3)
616
617 struct radeon_gart {
618 dma_addr_t table_addr;
619 struct drm_dmamem *dmah;
620 struct radeon_bo *robj;
621 void *ptr;
622 unsigned num_gpu_pages;
623 unsigned num_cpu_pages;
624 unsigned table_size;
625 struct vm_page **pages;
626 uint64_t *pages_entry;
627 bool ready;
628 };
629
630 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
631 void radeon_gart_table_ram_free(struct radeon_device *rdev);
632 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
633 void radeon_gart_table_vram_free(struct radeon_device *rdev);
634 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
635 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
636 int radeon_gart_init(struct radeon_device *rdev);
637 void radeon_gart_fini(struct radeon_device *rdev);
638 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
639 int pages);
640 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
641 int pages, struct vm_page **pagelist,
642 dma_addr_t *dma_addr, uint32_t flags);
643
644
645 /*
646 * GPU MC structures, functions & helpers
647 */
648 struct radeon_mc {
649 resource_size_t aper_size;
650 resource_size_t aper_base;
651 resource_size_t agp_base;
652 /* for some chips with <= 32MB we need to lie
653 * about vram size near mc fb location */
654 u64 mc_vram_size;
655 u64 visible_vram_size;
656 u64 gtt_size;
657 u64 gtt_start;
658 u64 gtt_end;
659 u64 vram_start;
660 u64 vram_end;
661 unsigned vram_width;
662 u64 real_vram_size;
663 int vram_mtrr;
664 bool vram_is_ddr;
665 bool igp_sideport_enabled;
666 u64 gtt_base_align;
667 u64 mc_mask;
668 };
669
670 bool radeon_combios_sideport_present(struct radeon_device *rdev);
671 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
672
673 /*
674 * GPU scratch registers structures, functions & helpers
675 */
676 struct radeon_scratch {
677 unsigned num_reg;
678 uint32_t reg_base;
679 bool free[32];
680 uint32_t reg[32];
681 };
682
683 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
684 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
685
686 /*
687 * GPU doorbell structures, functions & helpers
688 */
689 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
690
691 struct radeon_doorbell {
692 /* doorbell mmio */
693 resource_size_t base;
694 resource_size_t size;
695 u32 __iomem *ptr;
696 bus_space_handle_t bsh;
697 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
698 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
699 };
700
701 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
702 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
703
704 /*
705 * IRQS.
706 */
707
708 struct radeon_flip_work {
709 struct work_struct flip_work;
710 struct work_struct unpin_work;
711 struct radeon_device *rdev;
712 int crtc_id;
713 u32 target_vblank;
714 uint64_t base;
715 struct drm_pending_vblank_event *event;
716 struct radeon_bo *old_rbo;
717 struct dma_fence *fence;
718 bool async;
719 };
720
721 struct r500_irq_stat_regs {
722 u32 disp_int;
723 u32 hdmi0_status;
724 };
725
726 struct r600_irq_stat_regs {
727 u32 disp_int;
728 u32 disp_int_cont;
729 u32 disp_int_cont2;
730 u32 d1grph_int;
731 u32 d2grph_int;
732 u32 hdmi0_status;
733 u32 hdmi1_status;
734 };
735
736 struct evergreen_irq_stat_regs {
737 u32 disp_int[6];
738 u32 grph_int[6];
739 u32 afmt_status[6];
740 };
741
742 struct cik_irq_stat_regs {
743 u32 disp_int;
744 u32 disp_int_cont;
745 u32 disp_int_cont2;
746 u32 disp_int_cont3;
747 u32 disp_int_cont4;
748 u32 disp_int_cont5;
749 u32 disp_int_cont6;
750 u32 d1grph_int;
751 u32 d2grph_int;
752 u32 d3grph_int;
753 u32 d4grph_int;
754 u32 d5grph_int;
755 u32 d6grph_int;
756 };
757
758 union radeon_irq_stat_regs {
759 struct r500_irq_stat_regs r500;
760 struct r600_irq_stat_regs r600;
761 struct evergreen_irq_stat_regs evergreen;
762 struct cik_irq_stat_regs cik;
763 };
764
765 struct radeon_irq {
766 bool installed;
767 spinlock_t lock;
768 atomic_t ring_int[RADEON_NUM_RINGS];
769 bool crtc_vblank_int[RADEON_MAX_CRTCS];
770 atomic_t pflip[RADEON_MAX_CRTCS];
771 wait_queue_head_t vblank_queue;
772 bool hpd[RADEON_MAX_HPD_PINS];
773 bool afmt[RADEON_MAX_AFMT_BLOCKS];
774 union radeon_irq_stat_regs stat_regs;
775 bool dpm_thermal;
776 };
777
778 int radeon_irq_kms_init(struct radeon_device *rdev);
779 void radeon_irq_kms_fini(struct radeon_device *rdev);
780 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
781 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
782 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
783 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
784 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
785 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
786 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
787 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
788 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
789
790 /*
791 * CP & rings.
792 */
793
794 struct radeon_ib {
795 struct drm_suballoc *sa_bo;
796 uint32_t length_dw;
797 uint64_t gpu_addr;
798 uint32_t *ptr;
799 int ring;
800 struct radeon_fence *fence;
801 struct radeon_vm *vm;
802 bool is_const_ib;
803 struct radeon_sync sync;
804 };
805
806 struct radeon_ring {
807 struct radeon_device *rdev;
808 struct radeon_bo *ring_obj;
809 volatile uint32_t *ring;
810 unsigned rptr_offs;
811 unsigned rptr_save_reg;
812 u64 next_rptr_gpu_addr;
813 volatile u32 *next_rptr_cpu_addr;
814 unsigned wptr;
815 unsigned wptr_old;
816 unsigned ring_size;
817 unsigned ring_free_dw;
818 int count_dw;
819 atomic_t last_rptr;
820 atomic64_t last_activity;
821 uint64_t gpu_addr;
822 uint32_t align_mask;
823 uint32_t ptr_mask;
824 bool ready;
825 u32 nop;
826 u32 idx;
827 u64 last_semaphore_signal_addr;
828 u64 last_semaphore_wait_addr;
829 /* for CIK queues */
830 u32 me;
831 u32 pipe;
832 u32 queue;
833 struct radeon_bo *mqd_obj;
834 u32 doorbell_index;
835 unsigned wptr_offs;
836 };
837
838 struct radeon_mec {
839 struct radeon_bo *hpd_eop_obj;
840 u64 hpd_eop_gpu_addr;
841 u32 num_pipe;
842 u32 num_mec;
843 u32 num_queue;
844 };
845
846 /*
847 * VM
848 */
849
850 /* maximum number of VMIDs */
851 #define RADEON_NUM_VM 16
852
853 /* number of entries in page table */
854 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
855
856 /* PTBs (Page Table Blocks) need to be aligned to 32K */
857 #define RADEON_VM_PTB_ALIGN_SIZE 32768
858 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
859 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
860
861 #define R600_PTE_VALID (1 << 0)
862 #define R600_PTE_SYSTEM (1 << 1)
863 #define R600_PTE_SNOOPED (1 << 2)
864 #define R600_PTE_READABLE (1 << 5)
865 #define R600_PTE_WRITEABLE (1 << 6)
866
867 /* PTE (Page Table Entry) fragment field for different page sizes */
868 #define R600_PTE_FRAG_4KB (0 << 7)
869 #define R600_PTE_FRAG_64KB (4 << 7)
870 #define R600_PTE_FRAG_256KB (6 << 7)
871
872 /* flags needed to be set so we can copy directly from the GART table */
873 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
874 R600_PTE_SYSTEM | R600_PTE_VALID )
875
876 struct radeon_vm_pt {
877 struct radeon_bo *bo;
878 uint64_t addr;
879 };
880
881 struct radeon_vm_id {
882 unsigned id;
883 uint64_t pd_gpu_addr;
884 /* last flushed PD/PT update */
885 struct radeon_fence *flushed_updates;
886 /* last use of vmid */
887 struct radeon_fence *last_id_use;
888 };
889
890 struct radeon_vm {
891 struct rwlock mutex;
892
893 struct rb_root_cached va;
894
895 /* protecting invalidated and freed */
896 spinlock_t status_lock;
897
898 /* BOs moved, but not yet updated in the PT */
899 struct list_head invalidated;
900
901 /* BOs freed, but not yet updated in the PT */
902 struct list_head freed;
903
904 /* BOs cleared in the PT */
905 struct list_head cleared;
906
907 /* contains the page directory */
908 struct radeon_bo *page_directory;
909 unsigned max_pde_used;
910
911 /* array of page tables, one for each page directory entry */
912 struct radeon_vm_pt *page_tables;
913
914 struct radeon_bo_va *ib_bo_va;
915
916 /* for id and flush management per ring */
917 struct radeon_vm_id ids[RADEON_NUM_RINGS];
918 };
919
920 struct radeon_vm_manager {
921 struct radeon_fence *active[RADEON_NUM_VM];
922 uint32_t max_pfn;
923 /* number of VMIDs */
924 unsigned nvm;
925 /* vram base address for page table entry */
926 u64 vram_base_offset;
927 /* is vm enabled? */
928 bool enabled;
929 /* for hw to save the PD addr on suspend/resume */
930 uint32_t saved_table_addr[RADEON_NUM_VM];
931 };
932
933 /*
934 * file private structure
935 */
936 struct radeon_fpriv {
937 struct radeon_vm vm;
938 };
939
940 /*
941 * R6xx+ IH ring
942 */
943 struct r600_ih {
944 struct radeon_bo *ring_obj;
945 volatile uint32_t *ring;
946 unsigned rptr;
947 unsigned ring_size;
948 uint64_t gpu_addr;
949 uint32_t ptr_mask;
950 atomic_t lock;
951 bool enabled;
952 };
953
954 /*
955 * RLC stuff
956 */
957 #include "clearstate_defs.h"
958
959 struct radeon_rlc {
960 /* for power gating */
961 struct radeon_bo *save_restore_obj;
962 uint64_t save_restore_gpu_addr;
963 volatile uint32_t *sr_ptr;
964 const u32 *reg_list;
965 u32 reg_list_size;
966 /* for clear state */
967 struct radeon_bo *clear_state_obj;
968 uint64_t clear_state_gpu_addr;
969 volatile uint32_t *cs_ptr;
970 const struct cs_section_def *cs_data;
971 u32 clear_state_size;
972 /* for cp tables */
973 struct radeon_bo *cp_table_obj;
974 uint64_t cp_table_gpu_addr;
975 volatile uint32_t *cp_table_ptr;
976 u32 cp_table_size;
977 };
978
979 int radeon_ib_get(struct radeon_device *rdev, int ring,
980 struct radeon_ib *ib, struct radeon_vm *vm,
981 unsigned size);
982 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
983 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
984 struct radeon_ib *const_ib, bool hdp_flush);
985 int radeon_ib_pool_init(struct radeon_device *rdev);
986 void radeon_ib_pool_fini(struct radeon_device *rdev);
987 int radeon_ib_ring_tests(struct radeon_device *rdev);
988 /* Ring access between begin & end cannot sleep */
989 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
990 struct radeon_ring *ring);
991 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
992 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
993 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
994 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
995 bool hdp_flush);
996 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
997 bool hdp_flush);
998 void radeon_ring_undo(struct radeon_ring *ring);
999 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1000 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1001 void radeon_ring_lockup_update(struct radeon_device *rdev,
1002 struct radeon_ring *ring);
1003 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1004 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1005 uint32_t **data);
1006 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1007 unsigned size, uint32_t *data);
1008 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1009 unsigned rptr_offs, u32 nop);
1010 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1011
1012
1013 /* r600 async dma */
1014 void r600_dma_stop(struct radeon_device *rdev);
1015 int r600_dma_resume(struct radeon_device *rdev);
1016 void r600_dma_fini(struct radeon_device *rdev);
1017
1018 void cayman_dma_stop(struct radeon_device *rdev);
1019 int cayman_dma_resume(struct radeon_device *rdev);
1020 void cayman_dma_fini(struct radeon_device *rdev);
1021
1022 /*
1023 * CS.
1024 */
1025 struct radeon_cs_chunk {
1026 uint32_t length_dw;
1027 uint32_t *kdata;
1028 void __user *user_ptr;
1029 };
1030
1031 struct radeon_cs_parser {
1032 struct device *dev;
1033 struct radeon_device *rdev;
1034 struct drm_file *filp;
1035 /* chunks */
1036 unsigned nchunks;
1037 struct radeon_cs_chunk *chunks;
1038 uint64_t *chunks_array;
1039 /* IB */
1040 unsigned idx;
1041 /* relocations */
1042 unsigned nrelocs;
1043 struct radeon_bo_list *relocs;
1044 struct radeon_bo_list *vm_bos;
1045 struct list_head validated;
1046 unsigned dma_reloc_idx;
1047 /* indices of various chunks */
1048 struct radeon_cs_chunk *chunk_ib;
1049 struct radeon_cs_chunk *chunk_relocs;
1050 struct radeon_cs_chunk *chunk_flags;
1051 struct radeon_cs_chunk *chunk_const_ib;
1052 struct radeon_ib ib;
1053 struct radeon_ib const_ib;
1054 void *track;
1055 unsigned family;
1056 int parser_error;
1057 u32 cs_flags;
1058 u32 ring;
1059 s32 priority;
1060 struct ww_acquire_ctx ticket;
1061 };
1062
radeon_get_ib_value(struct radeon_cs_parser * p,int idx)1063 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1064 {
1065 struct radeon_cs_chunk *ibc = p->chunk_ib;
1066
1067 if (ibc->kdata)
1068 return ibc->kdata[idx];
1069 return p->ib.ptr[idx];
1070 }
1071
1072
1073 struct radeon_cs_packet {
1074 unsigned idx;
1075 unsigned type;
1076 unsigned reg;
1077 unsigned opcode;
1078 int count;
1079 unsigned one_reg_wr;
1080 };
1081
1082 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1083 struct radeon_cs_packet *pkt,
1084 unsigned idx, unsigned reg);
1085
1086 /*
1087 * AGP
1088 */
1089
1090 struct radeon_agp_mode {
1091 unsigned long mode; /**< AGP mode */
1092 };
1093
1094 struct radeon_agp_info {
1095 int agp_version_major;
1096 int agp_version_minor;
1097 unsigned long mode;
1098 unsigned long aperture_base; /* physical address */
1099 unsigned long aperture_size; /* bytes */
1100 unsigned long memory_allowed; /* bytes */
1101 unsigned long memory_used;
1102
1103 /* PCI information */
1104 unsigned short id_vendor;
1105 unsigned short id_device;
1106 };
1107
1108 struct radeon_agp_head {
1109 #ifdef notyet
1110 struct agp_kern_info agp_info;
1111 #endif
1112 struct list_head memory;
1113 unsigned long mode;
1114 struct agp_bridge_data *bridge;
1115 int enabled;
1116 int acquired;
1117 unsigned long base;
1118 int agp_mtrr;
1119 int cant_use_aperture;
1120 unsigned long page_mask;
1121 };
1122
1123 #if IS_ENABLED(CONFIG_AGP)
1124 struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev);
1125 #else
radeon_agp_head_init(struct drm_device * dev)1126 static inline struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev)
1127 {
1128 return NULL;
1129 }
1130 #endif
1131 int radeon_agp_init(struct radeon_device *rdev);
1132 void radeon_agp_resume(struct radeon_device *rdev);
1133 void radeon_agp_suspend(struct radeon_device *rdev);
1134 void radeon_agp_fini(struct radeon_device *rdev);
1135
1136
1137 /*
1138 * Writeback
1139 */
1140 struct radeon_wb {
1141 struct radeon_bo *wb_obj;
1142 volatile uint32_t *wb;
1143 uint64_t gpu_addr;
1144 bool enabled;
1145 bool use_event;
1146 };
1147
1148 #define RADEON_WB_SCRATCH_OFFSET 0
1149 #define RADEON_WB_RING0_NEXT_RPTR 256
1150 #define RADEON_WB_CP_RPTR_OFFSET 1024
1151 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1152 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1153 #define R600_WB_DMA_RPTR_OFFSET 1792
1154 #define R600_WB_IH_WPTR_OFFSET 2048
1155 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1156 #define R600_WB_EVENT_OFFSET 3072
1157 #define CIK_WB_CP1_WPTR_OFFSET 3328
1158 #define CIK_WB_CP2_WPTR_OFFSET 3584
1159 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1160 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1161
1162 /**
1163 * struct radeon_pm - power management datas
1164 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1165 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1166 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1167 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1168 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1169 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1170 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1171 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1172 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1173 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1174 * @needed_bandwidth: current bandwidth needs
1175 *
1176 * It keeps track of various data needed to take powermanagement decision.
1177 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1178 * Equation between gpu/memory clock and available bandwidth is hw dependent
1179 * (type of memory, bus size, efficiency, ...)
1180 */
1181
1182 enum radeon_pm_method {
1183 PM_METHOD_PROFILE,
1184 PM_METHOD_DYNPM,
1185 PM_METHOD_DPM,
1186 };
1187
1188 enum radeon_dynpm_state {
1189 DYNPM_STATE_DISABLED,
1190 DYNPM_STATE_MINIMUM,
1191 DYNPM_STATE_PAUSED,
1192 DYNPM_STATE_ACTIVE,
1193 DYNPM_STATE_SUSPENDED,
1194 };
1195 enum radeon_dynpm_action {
1196 DYNPM_ACTION_NONE,
1197 DYNPM_ACTION_MINIMUM,
1198 DYNPM_ACTION_DOWNCLOCK,
1199 DYNPM_ACTION_UPCLOCK,
1200 DYNPM_ACTION_DEFAULT
1201 };
1202
1203 enum radeon_voltage_type {
1204 VOLTAGE_NONE = 0,
1205 VOLTAGE_GPIO,
1206 VOLTAGE_VDDC,
1207 VOLTAGE_SW
1208 };
1209
1210 enum radeon_pm_state_type {
1211 /* not used for dpm */
1212 POWER_STATE_TYPE_DEFAULT,
1213 POWER_STATE_TYPE_POWERSAVE,
1214 /* user selectable states */
1215 POWER_STATE_TYPE_BATTERY,
1216 POWER_STATE_TYPE_BALANCED,
1217 POWER_STATE_TYPE_PERFORMANCE,
1218 /* internal states */
1219 POWER_STATE_TYPE_INTERNAL_UVD,
1220 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1221 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1222 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1223 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1224 POWER_STATE_TYPE_INTERNAL_BOOT,
1225 POWER_STATE_TYPE_INTERNAL_THERMAL,
1226 POWER_STATE_TYPE_INTERNAL_ACPI,
1227 POWER_STATE_TYPE_INTERNAL_ULV,
1228 POWER_STATE_TYPE_INTERNAL_3DPERF,
1229 };
1230
1231 enum radeon_pm_profile_type {
1232 PM_PROFILE_DEFAULT,
1233 PM_PROFILE_AUTO,
1234 PM_PROFILE_LOW,
1235 PM_PROFILE_MID,
1236 PM_PROFILE_HIGH,
1237 };
1238
1239 #define PM_PROFILE_DEFAULT_IDX 0
1240 #define PM_PROFILE_LOW_SH_IDX 1
1241 #define PM_PROFILE_MID_SH_IDX 2
1242 #define PM_PROFILE_HIGH_SH_IDX 3
1243 #define PM_PROFILE_LOW_MH_IDX 4
1244 #define PM_PROFILE_MID_MH_IDX 5
1245 #define PM_PROFILE_HIGH_MH_IDX 6
1246 #define PM_PROFILE_MAX 7
1247
1248 struct radeon_pm_profile {
1249 int dpms_off_ps_idx;
1250 int dpms_on_ps_idx;
1251 int dpms_off_cm_idx;
1252 int dpms_on_cm_idx;
1253 };
1254
1255 enum radeon_int_thermal_type {
1256 THERMAL_TYPE_NONE,
1257 THERMAL_TYPE_EXTERNAL,
1258 THERMAL_TYPE_EXTERNAL_GPIO,
1259 THERMAL_TYPE_RV6XX,
1260 THERMAL_TYPE_RV770,
1261 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1262 THERMAL_TYPE_EVERGREEN,
1263 THERMAL_TYPE_SUMO,
1264 THERMAL_TYPE_NI,
1265 THERMAL_TYPE_SI,
1266 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1267 THERMAL_TYPE_CI,
1268 THERMAL_TYPE_KV,
1269 };
1270
1271 struct radeon_voltage {
1272 enum radeon_voltage_type type;
1273 /* gpio voltage */
1274 struct radeon_gpio_rec gpio;
1275 u32 delay; /* delay in usec from voltage drop to sclk change */
1276 bool active_high; /* voltage drop is active when bit is high */
1277 /* VDDC voltage */
1278 u8 vddc_id; /* index into vddc voltage table */
1279 u8 vddci_id; /* index into vddci voltage table */
1280 bool vddci_enabled;
1281 /* r6xx+ sw */
1282 u16 voltage;
1283 /* evergreen+ vddci */
1284 u16 vddci;
1285 };
1286
1287 /* clock mode flags */
1288 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1289
1290 struct radeon_pm_clock_info {
1291 /* memory clock */
1292 u32 mclk;
1293 /* engine clock */
1294 u32 sclk;
1295 /* voltage info */
1296 struct radeon_voltage voltage;
1297 /* standardized clock flags */
1298 u32 flags;
1299 };
1300
1301 /* state flags */
1302 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1303
1304 struct radeon_power_state {
1305 enum radeon_pm_state_type type;
1306 struct radeon_pm_clock_info *clock_info;
1307 /* number of valid clock modes in this power state */
1308 int num_clock_modes;
1309 struct radeon_pm_clock_info *default_clock_mode;
1310 /* standardized state flags */
1311 u32 flags;
1312 u32 misc; /* vbios specific flags */
1313 u32 misc2; /* vbios specific flags */
1314 int pcie_lanes; /* pcie lanes */
1315 };
1316
1317 /*
1318 * Some modes are overclocked by very low value, accept them
1319 */
1320 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1321
1322 enum radeon_dpm_auto_throttle_src {
1323 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1324 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1325 };
1326
1327 enum radeon_dpm_event_src {
1328 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1329 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1330 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1331 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1332 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1333 };
1334
1335 #define RADEON_MAX_VCE_LEVELS 6
1336
1337 enum radeon_vce_level {
1338 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1339 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1340 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1341 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1342 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1343 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1344 };
1345
1346 struct radeon_ps {
1347 u32 caps; /* vbios flags */
1348 u32 class; /* vbios flags */
1349 u32 class2; /* vbios flags */
1350 /* UVD clocks */
1351 u32 vclk;
1352 u32 dclk;
1353 /* VCE clocks */
1354 u32 evclk;
1355 u32 ecclk;
1356 bool vce_active;
1357 enum radeon_vce_level vce_level;
1358 /* asic priv */
1359 void *ps_priv;
1360 };
1361
1362 struct radeon_dpm_thermal {
1363 /* thermal interrupt work */
1364 struct work_struct work;
1365 /* low temperature threshold */
1366 int min_temp;
1367 /* high temperature threshold */
1368 int max_temp;
1369 /* was interrupt low to high or high to low */
1370 bool high_to_low;
1371 };
1372
1373 enum radeon_clk_action
1374 {
1375 RADEON_SCLK_UP = 1,
1376 RADEON_SCLK_DOWN
1377 };
1378
1379 struct radeon_blacklist_clocks
1380 {
1381 u32 sclk;
1382 u32 mclk;
1383 enum radeon_clk_action action;
1384 };
1385
1386 struct radeon_clock_and_voltage_limits {
1387 u32 sclk;
1388 u32 mclk;
1389 u16 vddc;
1390 u16 vddci;
1391 };
1392
1393 struct radeon_clock_array {
1394 u32 count;
1395 u32 *values;
1396 };
1397
1398 struct radeon_clock_voltage_dependency_entry {
1399 u32 clk;
1400 u16 v;
1401 };
1402
1403 struct radeon_clock_voltage_dependency_table {
1404 u32 count;
1405 struct radeon_clock_voltage_dependency_entry *entries;
1406 };
1407
1408 union radeon_cac_leakage_entry {
1409 struct {
1410 u16 vddc;
1411 u32 leakage;
1412 };
1413 struct {
1414 u16 vddc1;
1415 u16 vddc2;
1416 u16 vddc3;
1417 };
1418 };
1419
1420 struct radeon_cac_leakage_table {
1421 u32 count;
1422 union radeon_cac_leakage_entry *entries;
1423 };
1424
1425 struct radeon_phase_shedding_limits_entry {
1426 u16 voltage;
1427 u32 sclk;
1428 u32 mclk;
1429 };
1430
1431 struct radeon_phase_shedding_limits_table {
1432 u32 count;
1433 struct radeon_phase_shedding_limits_entry *entries;
1434 };
1435
1436 struct radeon_uvd_clock_voltage_dependency_entry {
1437 u32 vclk;
1438 u32 dclk;
1439 u16 v;
1440 };
1441
1442 struct radeon_uvd_clock_voltage_dependency_table {
1443 u8 count;
1444 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1445 };
1446
1447 struct radeon_vce_clock_voltage_dependency_entry {
1448 u32 ecclk;
1449 u32 evclk;
1450 u16 v;
1451 };
1452
1453 struct radeon_vce_clock_voltage_dependency_table {
1454 u8 count;
1455 struct radeon_vce_clock_voltage_dependency_entry *entries;
1456 };
1457
1458 struct radeon_ppm_table {
1459 u8 ppm_design;
1460 u16 cpu_core_number;
1461 u32 platform_tdp;
1462 u32 small_ac_platform_tdp;
1463 u32 platform_tdc;
1464 u32 small_ac_platform_tdc;
1465 u32 apu_tdp;
1466 u32 dgpu_tdp;
1467 u32 dgpu_ulv_power;
1468 u32 tj_max;
1469 };
1470
1471 struct radeon_cac_tdp_table {
1472 u16 tdp;
1473 u16 configurable_tdp;
1474 u16 tdc;
1475 u16 battery_power_limit;
1476 u16 small_power_limit;
1477 u16 low_cac_leakage;
1478 u16 high_cac_leakage;
1479 u16 maximum_power_delivery_limit;
1480 };
1481
1482 struct radeon_dpm_dynamic_state {
1483 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1484 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1485 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1486 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1487 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1488 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1489 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1490 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1491 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1492 struct radeon_clock_array valid_sclk_values;
1493 struct radeon_clock_array valid_mclk_values;
1494 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1495 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1496 u32 mclk_sclk_ratio;
1497 u32 sclk_mclk_delta;
1498 u16 vddc_vddci_delta;
1499 u16 min_vddc_for_pcie_gen2;
1500 struct radeon_cac_leakage_table cac_leakage_table;
1501 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1502 struct radeon_ppm_table *ppm_table;
1503 struct radeon_cac_tdp_table *cac_tdp_table;
1504 };
1505
1506 struct radeon_dpm_fan {
1507 u16 t_min;
1508 u16 t_med;
1509 u16 t_high;
1510 u16 pwm_min;
1511 u16 pwm_med;
1512 u16 pwm_high;
1513 u8 t_hyst;
1514 u32 cycle_delay;
1515 u16 t_max;
1516 u8 control_mode;
1517 u16 default_max_fan_pwm;
1518 u16 default_fan_output_sensitivity;
1519 u16 fan_output_sensitivity;
1520 bool ucode_fan_control;
1521 };
1522
1523 enum radeon_pcie_gen {
1524 RADEON_PCIE_GEN1 = 0,
1525 RADEON_PCIE_GEN2 = 1,
1526 RADEON_PCIE_GEN3 = 2,
1527 RADEON_PCIE_GEN_INVALID = 0xffff
1528 };
1529
1530 enum radeon_dpm_forced_level {
1531 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1532 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1533 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1534 };
1535
1536 struct radeon_vce_state {
1537 /* vce clocks */
1538 u32 evclk;
1539 u32 ecclk;
1540 /* gpu clocks */
1541 u32 sclk;
1542 u32 mclk;
1543 u8 clk_idx;
1544 u8 pstate;
1545 };
1546
1547 struct radeon_dpm {
1548 struct radeon_ps *ps;
1549 /* number of valid power states */
1550 int num_ps;
1551 /* current power state that is active */
1552 struct radeon_ps *current_ps;
1553 /* requested power state */
1554 struct radeon_ps *requested_ps;
1555 /* boot up power state */
1556 struct radeon_ps *boot_ps;
1557 /* default uvd power state */
1558 struct radeon_ps *uvd_ps;
1559 /* vce requirements */
1560 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1561 enum radeon_vce_level vce_level;
1562 enum radeon_pm_state_type state;
1563 enum radeon_pm_state_type user_state;
1564 u32 platform_caps;
1565 u32 voltage_response_time;
1566 u32 backbias_response_time;
1567 void *priv;
1568 u32 new_active_crtcs;
1569 int new_active_crtc_count;
1570 int high_pixelclock_count;
1571 u32 current_active_crtcs;
1572 int current_active_crtc_count;
1573 bool single_display;
1574 struct radeon_dpm_dynamic_state dyn_state;
1575 struct radeon_dpm_fan fan;
1576 u32 tdp_limit;
1577 u32 near_tdp_limit;
1578 u32 near_tdp_limit_adjusted;
1579 u32 sq_ramping_threshold;
1580 u32 cac_leakage;
1581 u16 tdp_od_limit;
1582 u32 tdp_adjustment;
1583 u16 load_line_slope;
1584 bool power_control;
1585 bool ac_power;
1586 /* special states active */
1587 bool thermal_active;
1588 bool uvd_active;
1589 bool vce_active;
1590 /* thermal handling */
1591 struct radeon_dpm_thermal thermal;
1592 /* forced levels */
1593 enum radeon_dpm_forced_level forced_level;
1594 /* track UVD streams */
1595 unsigned sd;
1596 unsigned hd;
1597 };
1598
1599 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1600 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1601
1602 struct radeon_pm {
1603 struct rwlock mutex;
1604 /* write locked while reprogramming mclk */
1605 struct rwlock mclk_lock;
1606 u32 active_crtcs;
1607 int active_crtc_count;
1608 int req_vblank;
1609 bool vblank_sync;
1610 fixed20_12 max_bandwidth;
1611 fixed20_12 igp_sideport_mclk;
1612 fixed20_12 igp_system_mclk;
1613 fixed20_12 igp_ht_link_clk;
1614 fixed20_12 igp_ht_link_width;
1615 fixed20_12 k8_bandwidth;
1616 fixed20_12 sideport_bandwidth;
1617 fixed20_12 ht_bandwidth;
1618 fixed20_12 core_bandwidth;
1619 fixed20_12 sclk;
1620 fixed20_12 mclk;
1621 fixed20_12 needed_bandwidth;
1622 struct radeon_power_state *power_state;
1623 /* number of valid power states */
1624 int num_power_states;
1625 int current_power_state_index;
1626 int current_clock_mode_index;
1627 int requested_power_state_index;
1628 int requested_clock_mode_index;
1629 int default_power_state_index;
1630 u32 current_sclk;
1631 u32 current_mclk;
1632 u16 current_vddc;
1633 u16 current_vddci;
1634 u32 default_sclk;
1635 u32 default_mclk;
1636 u16 default_vddc;
1637 u16 default_vddci;
1638 struct radeon_i2c_chan *i2c_bus;
1639 /* selected pm method */
1640 enum radeon_pm_method pm_method;
1641 /* dynpm power management */
1642 struct delayed_work dynpm_idle_work;
1643 enum radeon_dynpm_state dynpm_state;
1644 enum radeon_dynpm_action dynpm_planned_action;
1645 unsigned long dynpm_action_timeout;
1646 bool dynpm_can_upclock;
1647 bool dynpm_can_downclock;
1648 /* profile-based power management */
1649 enum radeon_pm_profile_type profile;
1650 int profile_index;
1651 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1652 /* internal thermal controller on rv6xx+ */
1653 enum radeon_int_thermal_type int_thermal_type;
1654 struct device *int_hwmon_dev;
1655 /* fan control parameters */
1656 bool no_fan;
1657 u8 fan_pulses_per_revolution;
1658 u8 fan_min_rpm;
1659 u8 fan_max_rpm;
1660 /* dpm */
1661 bool dpm_enabled;
1662 bool sysfs_initialized;
1663 struct radeon_dpm dpm;
1664 };
1665
1666 #define RADEON_PCIE_SPEED_25 1
1667 #define RADEON_PCIE_SPEED_50 2
1668 #define RADEON_PCIE_SPEED_80 4
1669
1670 int radeon_pm_get_type_index(struct radeon_device *rdev,
1671 enum radeon_pm_state_type ps_type,
1672 int instance);
1673 /*
1674 * UVD
1675 */
1676 #define RADEON_DEFAULT_UVD_HANDLES 10
1677 #define RADEON_MAX_UVD_HANDLES 30
1678 #define RADEON_UVD_STACK_SIZE (200*1024)
1679 #define RADEON_UVD_HEAP_SIZE (256*1024)
1680 #define RADEON_UVD_SESSION_SIZE (50*1024)
1681
1682 struct radeon_uvd {
1683 bool fw_header_present;
1684 struct radeon_bo *vcpu_bo;
1685 void *cpu_addr;
1686 uint64_t gpu_addr;
1687 unsigned max_handles;
1688 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1689 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1690 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1691 struct delayed_work idle_work;
1692 };
1693
1694 int radeon_uvd_init(struct radeon_device *rdev);
1695 void radeon_uvd_fini(struct radeon_device *rdev);
1696 int radeon_uvd_suspend(struct radeon_device *rdev);
1697 int radeon_uvd_resume(struct radeon_device *rdev);
1698 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1699 uint32_t handle, struct radeon_fence **fence);
1700 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1701 uint32_t handle, struct radeon_fence **fence);
1702 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1703 uint32_t allowed_domains);
1704 void radeon_uvd_free_handles(struct radeon_device *rdev,
1705 struct drm_file *filp);
1706 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1707 void radeon_uvd_note_usage(struct radeon_device *rdev);
1708 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1709 unsigned vclk, unsigned dclk,
1710 unsigned vco_min, unsigned vco_max,
1711 unsigned fb_factor, unsigned fb_mask,
1712 unsigned pd_min, unsigned pd_max,
1713 unsigned pd_even,
1714 unsigned *optimal_fb_div,
1715 unsigned *optimal_vclk_div,
1716 unsigned *optimal_dclk_div);
1717 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1718 unsigned cg_upll_func_cntl);
1719
1720 /*
1721 * VCE
1722 */
1723 #define RADEON_MAX_VCE_HANDLES 16
1724
1725 struct radeon_vce {
1726 struct radeon_bo *vcpu_bo;
1727 uint64_t gpu_addr;
1728 unsigned fw_version;
1729 unsigned fb_version;
1730 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1731 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1732 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1733 struct delayed_work idle_work;
1734 uint32_t keyselect;
1735 };
1736
1737 int radeon_vce_init(struct radeon_device *rdev);
1738 void radeon_vce_fini(struct radeon_device *rdev);
1739 int radeon_vce_suspend(struct radeon_device *rdev);
1740 int radeon_vce_resume(struct radeon_device *rdev);
1741 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1742 uint32_t handle, struct radeon_fence **fence);
1743 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1744 uint32_t handle, struct radeon_fence **fence);
1745 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1746 void radeon_vce_note_usage(struct radeon_device *rdev);
1747 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1748 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1749 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1750 struct radeon_ring *ring,
1751 struct radeon_semaphore *semaphore,
1752 bool emit_wait);
1753 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1754 void radeon_vce_fence_emit(struct radeon_device *rdev,
1755 struct radeon_fence *fence);
1756 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1757 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1758
1759 struct r600_audio_pin {
1760 int channels;
1761 int rate;
1762 int bits_per_sample;
1763 u8 status_bits;
1764 u8 category_code;
1765 u32 offset;
1766 bool connected;
1767 u32 id;
1768 };
1769
1770 struct r600_audio {
1771 bool enabled;
1772 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1773 int num_pins;
1774 struct radeon_audio_funcs *hdmi_funcs;
1775 struct radeon_audio_funcs *dp_funcs;
1776 struct radeon_audio_basic_funcs *funcs;
1777 struct drm_audio_component *component;
1778 bool component_registered;
1779 struct rwlock component_mutex;
1780 };
1781
1782 /*
1783 * Benchmarking
1784 */
1785 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1786
1787
1788 /*
1789 * Testing
1790 */
1791 void radeon_test_moves(struct radeon_device *rdev);
1792 void radeon_test_ring_sync(struct radeon_device *rdev,
1793 struct radeon_ring *cpA,
1794 struct radeon_ring *cpB);
1795 void radeon_test_syncing(struct radeon_device *rdev);
1796
1797 /*
1798 * MMU Notifier
1799 */
1800 #if defined(CONFIG_MMU_NOTIFIER)
1801 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1802 void radeon_mn_unregister(struct radeon_bo *bo);
1803 #else
radeon_mn_register(struct radeon_bo * bo,unsigned long addr)1804 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1805 {
1806 return -ENODEV;
1807 }
radeon_mn_unregister(struct radeon_bo * bo)1808 static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1809 #endif
1810
1811 /*
1812 * Debugfs
1813 */
1814 void radeon_debugfs_fence_init(struct radeon_device *rdev);
1815 void radeon_gem_debugfs_init(struct radeon_device *rdev);
1816
1817 /*
1818 * ASIC ring specific functions.
1819 */
1820 struct radeon_asic_ring {
1821 /* ring read/write ptr handling */
1822 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1823 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1824 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1825
1826 /* validating and patching of IBs */
1827 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1828 int (*cs_parse)(struct radeon_cs_parser *p);
1829
1830 /* command emmit functions */
1831 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1832 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1833 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1834 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1835 struct radeon_semaphore *semaphore, bool emit_wait);
1836 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1837 unsigned vm_id, uint64_t pd_addr);
1838
1839 /* testing functions */
1840 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1841 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1842 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1843
1844 /* deprecated */
1845 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1846 };
1847
1848 /*
1849 * ASIC specific functions.
1850 */
1851 struct radeon_asic {
1852 int (*init)(struct radeon_device *rdev);
1853 void (*fini)(struct radeon_device *rdev);
1854 int (*resume)(struct radeon_device *rdev);
1855 int (*suspend)(struct radeon_device *rdev);
1856 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1857 int (*asic_reset)(struct radeon_device *rdev, bool hard);
1858 /* Flush the HDP cache via MMIO */
1859 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1860 /* check if 3D engine is idle */
1861 bool (*gui_idle)(struct radeon_device *rdev);
1862 /* wait for mc_idle */
1863 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1864 /* get the reference clock */
1865 u32 (*get_xclk)(struct radeon_device *rdev);
1866 /* get the gpu clock counter */
1867 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1868 /* get register for info ioctl */
1869 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1870 /* gart */
1871 struct {
1872 void (*tlb_flush)(struct radeon_device *rdev);
1873 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1874 void (*set_page)(struct radeon_device *rdev, unsigned i,
1875 uint64_t entry);
1876 } gart;
1877 struct {
1878 int (*init)(struct radeon_device *rdev);
1879 void (*fini)(struct radeon_device *rdev);
1880 void (*copy_pages)(struct radeon_device *rdev,
1881 struct radeon_ib *ib,
1882 uint64_t pe, uint64_t src,
1883 unsigned count);
1884 void (*write_pages)(struct radeon_device *rdev,
1885 struct radeon_ib *ib,
1886 uint64_t pe,
1887 uint64_t addr, unsigned count,
1888 uint32_t incr, uint32_t flags);
1889 void (*set_pages)(struct radeon_device *rdev,
1890 struct radeon_ib *ib,
1891 uint64_t pe,
1892 uint64_t addr, unsigned count,
1893 uint32_t incr, uint32_t flags);
1894 void (*pad_ib)(struct radeon_ib *ib);
1895 } vm;
1896 /* ring specific callbacks */
1897 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1898 /* irqs */
1899 struct {
1900 int (*set)(struct radeon_device *rdev);
1901 int (*process)(struct radeon_device *rdev);
1902 } irq;
1903 /* displays */
1904 struct {
1905 /* display watermarks */
1906 void (*bandwidth_update)(struct radeon_device *rdev);
1907 /* get frame count */
1908 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1909 /* wait for vblank */
1910 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1911 /* set backlight level */
1912 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1913 /* get backlight level */
1914 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1915 /* audio callbacks */
1916 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1917 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1918 } display;
1919 /* copy functions for bo handling */
1920 struct {
1921 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1922 uint64_t src_offset,
1923 uint64_t dst_offset,
1924 unsigned num_gpu_pages,
1925 struct dma_resv *resv);
1926 u32 blit_ring_index;
1927 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1928 uint64_t src_offset,
1929 uint64_t dst_offset,
1930 unsigned num_gpu_pages,
1931 struct dma_resv *resv);
1932 u32 dma_ring_index;
1933 /* method used for bo copy */
1934 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1935 uint64_t src_offset,
1936 uint64_t dst_offset,
1937 unsigned num_gpu_pages,
1938 struct dma_resv *resv);
1939 /* ring used for bo copies */
1940 u32 copy_ring_index;
1941 } copy;
1942 /* surfaces */
1943 struct {
1944 int (*set_reg)(struct radeon_device *rdev, int reg,
1945 uint32_t tiling_flags, uint32_t pitch,
1946 uint32_t offset, uint32_t obj_size);
1947 void (*clear_reg)(struct radeon_device *rdev, int reg);
1948 } surface;
1949 /* hotplug detect */
1950 struct {
1951 void (*init)(struct radeon_device *rdev);
1952 void (*fini)(struct radeon_device *rdev);
1953 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1954 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1955 } hpd;
1956 /* static power management */
1957 struct {
1958 void (*misc)(struct radeon_device *rdev);
1959 void (*prepare)(struct radeon_device *rdev);
1960 void (*finish)(struct radeon_device *rdev);
1961 void (*init_profile)(struct radeon_device *rdev);
1962 void (*get_dynpm_state)(struct radeon_device *rdev);
1963 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1964 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1965 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1966 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1967 int (*get_pcie_lanes)(struct radeon_device *rdev);
1968 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1969 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1970 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1971 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1972 int (*get_temperature)(struct radeon_device *rdev);
1973 } pm;
1974 /* dynamic power management */
1975 struct {
1976 int (*init)(struct radeon_device *rdev);
1977 void (*setup_asic)(struct radeon_device *rdev);
1978 int (*enable)(struct radeon_device *rdev);
1979 int (*late_enable)(struct radeon_device *rdev);
1980 void (*disable)(struct radeon_device *rdev);
1981 int (*pre_set_power_state)(struct radeon_device *rdev);
1982 int (*set_power_state)(struct radeon_device *rdev);
1983 void (*post_set_power_state)(struct radeon_device *rdev);
1984 void (*display_configuration_changed)(struct radeon_device *rdev);
1985 void (*fini)(struct radeon_device *rdev);
1986 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1987 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1988 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1989 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1990 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1991 bool (*vblank_too_short)(struct radeon_device *rdev);
1992 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1993 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1994 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1995 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1996 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1997 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
1998 u32 (*get_current_sclk)(struct radeon_device *rdev);
1999 u32 (*get_current_mclk)(struct radeon_device *rdev);
2000 u16 (*get_current_vddc)(struct radeon_device *rdev);
2001 } dpm;
2002 /* pageflipping */
2003 struct {
2004 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
2005 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
2006 } pflip;
2007 };
2008
2009 /*
2010 * Asic structures
2011 */
2012 struct r100_asic {
2013 const unsigned *reg_safe_bm;
2014 unsigned reg_safe_bm_size;
2015 u32 hdp_cntl;
2016 };
2017
2018 struct r300_asic {
2019 const unsigned *reg_safe_bm;
2020 unsigned reg_safe_bm_size;
2021 u32 resync_scratch;
2022 u32 hdp_cntl;
2023 };
2024
2025 struct r600_asic {
2026 unsigned max_pipes;
2027 unsigned max_tile_pipes;
2028 unsigned max_simds;
2029 unsigned max_backends;
2030 unsigned max_gprs;
2031 unsigned max_threads;
2032 unsigned max_stack_entries;
2033 unsigned max_hw_contexts;
2034 unsigned max_gs_threads;
2035 unsigned sx_max_export_size;
2036 unsigned sx_max_export_pos_size;
2037 unsigned sx_max_export_smx_size;
2038 unsigned sq_num_cf_insts;
2039 unsigned tiling_nbanks;
2040 unsigned tiling_npipes;
2041 unsigned tiling_group_size;
2042 unsigned tile_config;
2043 unsigned backend_map;
2044 unsigned active_simds;
2045 };
2046
2047 struct rv770_asic {
2048 unsigned max_pipes;
2049 unsigned max_tile_pipes;
2050 unsigned max_simds;
2051 unsigned max_backends;
2052 unsigned max_gprs;
2053 unsigned max_threads;
2054 unsigned max_stack_entries;
2055 unsigned max_hw_contexts;
2056 unsigned max_gs_threads;
2057 unsigned sx_max_export_size;
2058 unsigned sx_max_export_pos_size;
2059 unsigned sx_max_export_smx_size;
2060 unsigned sq_num_cf_insts;
2061 unsigned sx_num_of_sets;
2062 unsigned sc_prim_fifo_size;
2063 unsigned sc_hiz_tile_fifo_size;
2064 unsigned sc_earlyz_tile_fifo_fize;
2065 unsigned tiling_nbanks;
2066 unsigned tiling_npipes;
2067 unsigned tiling_group_size;
2068 unsigned tile_config;
2069 unsigned backend_map;
2070 unsigned active_simds;
2071 };
2072
2073 struct evergreen_asic {
2074 unsigned num_ses;
2075 unsigned max_pipes;
2076 unsigned max_tile_pipes;
2077 unsigned max_simds;
2078 unsigned max_backends;
2079 unsigned max_gprs;
2080 unsigned max_threads;
2081 unsigned max_stack_entries;
2082 unsigned max_hw_contexts;
2083 unsigned max_gs_threads;
2084 unsigned sx_max_export_size;
2085 unsigned sx_max_export_pos_size;
2086 unsigned sx_max_export_smx_size;
2087 unsigned sq_num_cf_insts;
2088 unsigned sx_num_of_sets;
2089 unsigned sc_prim_fifo_size;
2090 unsigned sc_hiz_tile_fifo_size;
2091 unsigned sc_earlyz_tile_fifo_size;
2092 unsigned tiling_nbanks;
2093 unsigned tiling_npipes;
2094 unsigned tiling_group_size;
2095 unsigned tile_config;
2096 unsigned backend_map;
2097 unsigned active_simds;
2098 };
2099
2100 struct cayman_asic {
2101 unsigned max_shader_engines;
2102 unsigned max_pipes_per_simd;
2103 unsigned max_tile_pipes;
2104 unsigned max_simds_per_se;
2105 unsigned max_backends_per_se;
2106 unsigned max_texture_channel_caches;
2107 unsigned max_gprs;
2108 unsigned max_threads;
2109 unsigned max_gs_threads;
2110 unsigned max_stack_entries;
2111 unsigned sx_num_of_sets;
2112 unsigned sx_max_export_size;
2113 unsigned sx_max_export_pos_size;
2114 unsigned sx_max_export_smx_size;
2115 unsigned max_hw_contexts;
2116 unsigned sq_num_cf_insts;
2117 unsigned sc_prim_fifo_size;
2118 unsigned sc_hiz_tile_fifo_size;
2119 unsigned sc_earlyz_tile_fifo_size;
2120
2121 unsigned num_shader_engines;
2122 unsigned num_shader_pipes_per_simd;
2123 unsigned num_tile_pipes;
2124 unsigned num_simds_per_se;
2125 unsigned num_backends_per_se;
2126 unsigned backend_disable_mask_per_asic;
2127 unsigned backend_map;
2128 unsigned num_texture_channel_caches;
2129 unsigned mem_max_burst_length_bytes;
2130 unsigned mem_row_size_in_kb;
2131 unsigned shader_engine_tile_size;
2132 unsigned num_gpus;
2133 unsigned multi_gpu_tile_size;
2134
2135 unsigned tile_config;
2136 unsigned active_simds;
2137 };
2138
2139 struct si_asic {
2140 unsigned max_shader_engines;
2141 unsigned max_tile_pipes;
2142 unsigned max_cu_per_sh;
2143 unsigned max_sh_per_se;
2144 unsigned max_backends_per_se;
2145 unsigned max_texture_channel_caches;
2146 unsigned max_gprs;
2147 unsigned max_gs_threads;
2148 unsigned max_hw_contexts;
2149 unsigned sc_prim_fifo_size_frontend;
2150 unsigned sc_prim_fifo_size_backend;
2151 unsigned sc_hiz_tile_fifo_size;
2152 unsigned sc_earlyz_tile_fifo_size;
2153
2154 unsigned num_tile_pipes;
2155 unsigned backend_enable_mask;
2156 unsigned backend_disable_mask_per_asic;
2157 unsigned backend_map;
2158 unsigned num_texture_channel_caches;
2159 unsigned mem_max_burst_length_bytes;
2160 unsigned mem_row_size_in_kb;
2161 unsigned shader_engine_tile_size;
2162 unsigned num_gpus;
2163 unsigned multi_gpu_tile_size;
2164
2165 unsigned tile_config;
2166 uint32_t tile_mode_array[32];
2167 uint32_t active_cus;
2168 };
2169
2170 struct cik_asic {
2171 unsigned max_shader_engines;
2172 unsigned max_tile_pipes;
2173 unsigned max_cu_per_sh;
2174 unsigned max_sh_per_se;
2175 unsigned max_backends_per_se;
2176 unsigned max_texture_channel_caches;
2177 unsigned max_gprs;
2178 unsigned max_gs_threads;
2179 unsigned max_hw_contexts;
2180 unsigned sc_prim_fifo_size_frontend;
2181 unsigned sc_prim_fifo_size_backend;
2182 unsigned sc_hiz_tile_fifo_size;
2183 unsigned sc_earlyz_tile_fifo_size;
2184
2185 unsigned num_tile_pipes;
2186 unsigned backend_enable_mask;
2187 unsigned backend_disable_mask_per_asic;
2188 unsigned backend_map;
2189 unsigned num_texture_channel_caches;
2190 unsigned mem_max_burst_length_bytes;
2191 unsigned mem_row_size_in_kb;
2192 unsigned shader_engine_tile_size;
2193 unsigned num_gpus;
2194 unsigned multi_gpu_tile_size;
2195
2196 unsigned tile_config;
2197 uint32_t tile_mode_array[32];
2198 uint32_t macrotile_mode_array[16];
2199 uint32_t active_cus;
2200 };
2201
2202 union radeon_asic_config {
2203 struct r300_asic r300;
2204 struct r100_asic r100;
2205 struct r600_asic r600;
2206 struct rv770_asic rv770;
2207 struct evergreen_asic evergreen;
2208 struct cayman_asic cayman;
2209 struct si_asic si;
2210 struct cik_asic cik;
2211 };
2212
2213 /*
2214 * asic initizalization from radeon_asic.c
2215 */
2216 void radeon_agp_disable(struct radeon_device *rdev);
2217 int radeon_asic_init(struct radeon_device *rdev);
2218
2219
2220 /*
2221 * IOCTL.
2222 */
2223 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2224 struct drm_file *filp);
2225 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2226 struct drm_file *filp);
2227 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2228 struct drm_file *filp);
2229 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2230 struct drm_file *file_priv);
2231 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2232 struct drm_file *file_priv);
2233 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2234 struct drm_file *filp);
2235 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2236 struct drm_file *filp);
2237 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2238 struct drm_file *filp);
2239 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2240 struct drm_file *filp);
2241 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2242 struct drm_file *filp);
2243 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2244 struct drm_file *filp);
2245 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2246 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2247 struct drm_file *filp);
2248 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2249 struct drm_file *filp);
2250 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2251
2252 /* VRAM scratch page for HDP bug, default vram page */
2253 struct r600_vram_scratch {
2254 struct radeon_bo *robj;
2255 volatile uint32_t *ptr;
2256 u64 gpu_addr;
2257 };
2258
2259 /*
2260 * ACPI
2261 */
2262 struct radeon_atif_notification_cfg {
2263 bool enabled;
2264 int command_code;
2265 };
2266
2267 struct radeon_atif_notifications {
2268 bool display_switch;
2269 bool expansion_mode_change;
2270 bool thermal_state;
2271 bool forced_power_state;
2272 bool system_power_state;
2273 bool display_conf_change;
2274 bool px_gfx_switch;
2275 bool brightness_change;
2276 bool dgpu_display_event;
2277 };
2278
2279 struct radeon_atif_functions {
2280 bool system_params;
2281 bool sbios_requests;
2282 bool select_active_disp;
2283 bool lid_state;
2284 bool get_tv_standard;
2285 bool set_tv_standard;
2286 bool get_panel_expansion_mode;
2287 bool set_panel_expansion_mode;
2288 bool temperature_change;
2289 bool graphics_device_types;
2290 };
2291
2292 struct radeon_atif {
2293 struct radeon_atif_notifications notifications;
2294 struct radeon_atif_functions functions;
2295 struct radeon_atif_notification_cfg notification_cfg;
2296 struct radeon_encoder *encoder_for_bl;
2297 };
2298
2299 struct radeon_atcs_functions {
2300 bool get_ext_state;
2301 bool pcie_perf_req;
2302 bool pcie_dev_rdy;
2303 bool pcie_bus_width;
2304 };
2305
2306 struct radeon_atcs {
2307 struct radeon_atcs_functions functions;
2308 };
2309
2310 /*
2311 * Core structure, functions and helpers.
2312 */
2313 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2314 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2315
2316 struct radeon_device {
2317 struct device self;
2318 struct device *dev;
2319 struct drm_device *ddev;
2320 struct pci_dev *pdev;
2321 #ifdef __alpha__
2322 struct pci_controller *hose;
2323 #endif
2324 struct radeon_agp_head *agp;
2325 struct rwlock exclusive_lock;
2326
2327 pci_chipset_tag_t pc;
2328 pcitag_t pa_tag;
2329 pci_intr_handle_t intrh;
2330 bus_space_tag_t iot;
2331 bus_space_tag_t memt;
2332 bus_dma_tag_t dmat;
2333 void *irqh;
2334
2335 void (*switchcb)(void *, int, int);
2336 void *switchcbarg;
2337 void *switchcookie;
2338 struct task switchtask;
2339 struct rasops_info ro;
2340 int console;
2341 int primary;
2342
2343 struct task burner_task;
2344 int burner_fblank;
2345
2346 #ifdef __sparc64__
2347 struct sunfb sf;
2348 bus_size_t fb_offset;
2349 bus_space_handle_t memh;
2350 #endif
2351
2352 unsigned long fb_aper_offset;
2353 unsigned long fb_aper_size;
2354
2355 /* ASIC */
2356 union radeon_asic_config config;
2357 enum radeon_family family;
2358 unsigned long flags;
2359 int usec_timeout;
2360 enum radeon_pll_errata pll_errata;
2361 int num_gb_pipes;
2362 int num_z_pipes;
2363 int disp_priority;
2364 /* BIOS */
2365 uint8_t *bios;
2366 bool is_atom_bios;
2367 uint16_t bios_header_start;
2368 struct radeon_bo *stolen_vga_memory;
2369 /* Register mmio */
2370 resource_size_t rmmio_base;
2371 resource_size_t rmmio_size;
2372 /* protects concurrent MM_INDEX/DATA based register access */
2373 spinlock_t mmio_idx_lock;
2374 /* protects concurrent SMC based register access */
2375 spinlock_t smc_idx_lock;
2376 /* protects concurrent PLL register access */
2377 spinlock_t pll_idx_lock;
2378 /* protects concurrent MC register access */
2379 spinlock_t mc_idx_lock;
2380 /* protects concurrent PCIE register access */
2381 spinlock_t pcie_idx_lock;
2382 /* protects concurrent PCIE_PORT register access */
2383 spinlock_t pciep_idx_lock;
2384 /* protects concurrent PIF register access */
2385 spinlock_t pif_idx_lock;
2386 /* protects concurrent CG register access */
2387 spinlock_t cg_idx_lock;
2388 /* protects concurrent UVD register access */
2389 spinlock_t uvd_idx_lock;
2390 /* protects concurrent RCU register access */
2391 spinlock_t rcu_idx_lock;
2392 /* protects concurrent DIDT register access */
2393 spinlock_t didt_idx_lock;
2394 /* protects concurrent ENDPOINT (audio) register access */
2395 spinlock_t end_idx_lock;
2396 bus_space_handle_t rmmio_bsh;
2397 void __iomem *rmmio;
2398 radeon_rreg_t mc_rreg;
2399 radeon_wreg_t mc_wreg;
2400 radeon_rreg_t pll_rreg;
2401 radeon_wreg_t pll_wreg;
2402 uint32_t pcie_reg_mask;
2403 radeon_rreg_t pciep_rreg;
2404 radeon_wreg_t pciep_wreg;
2405 /* io port */
2406 bus_space_handle_t rio_mem;
2407 resource_size_t rio_mem_size;
2408 struct radeon_clock clock;
2409 struct radeon_mc mc;
2410 struct radeon_gart gart;
2411 struct radeon_mode_info mode_info;
2412 struct radeon_scratch scratch;
2413 struct radeon_doorbell doorbell;
2414 struct radeon_mman mman;
2415 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2416 wait_queue_head_t fence_queue;
2417 u64 fence_context;
2418 struct rwlock ring_lock;
2419 struct radeon_ring ring[RADEON_NUM_RINGS];
2420 bool ib_pool_ready;
2421 struct radeon_sa_manager ring_tmp_bo;
2422 struct radeon_irq irq;
2423 struct radeon_asic *asic;
2424 struct radeon_gem gem;
2425 struct radeon_pm pm;
2426 struct radeon_uvd uvd;
2427 struct radeon_vce vce;
2428 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2429 struct radeon_wb wb;
2430 struct radeon_dummy_page dummy_page;
2431 bool shutdown;
2432 bool need_swiotlb;
2433 bool accel_working;
2434 bool fastfb_working; /* IGP feature*/
2435 bool needs_reset, in_reset;
2436 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2437 const struct firmware *me_fw; /* all family ME firmware */
2438 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2439 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2440 const struct firmware *mc_fw; /* NI MC firmware */
2441 const struct firmware *ce_fw; /* SI CE firmware */
2442 const struct firmware *mec_fw; /* CIK MEC firmware */
2443 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2444 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2445 const struct firmware *smc_fw; /* SMC firmware */
2446 const struct firmware *uvd_fw; /* UVD firmware */
2447 const struct firmware *vce_fw; /* VCE firmware */
2448 bool new_fw;
2449 struct r600_vram_scratch vram_scratch;
2450 int msi_enabled; /* msi enabled */
2451 struct r600_ih ih; /* r6/700 interrupt ring */
2452 struct radeon_rlc rlc;
2453 struct radeon_mec mec;
2454 struct delayed_work hotplug_work;
2455 struct work_struct dp_work;
2456 struct work_struct audio_work;
2457 int num_crtc; /* number of crtcs */
2458 struct rwlock dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2459 bool has_uvd;
2460 bool has_vce;
2461 struct r600_audio audio; /* audio stuff */
2462 struct notifier_block acpi_nb;
2463 /* only one userspace can use Hyperz features or CMASK at a time */
2464 struct drm_file *hyperz_filp;
2465 struct drm_file *cmask_filp;
2466 /* i2c buses */
2467 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2468 /* virtual memory */
2469 struct radeon_vm_manager vm_manager;
2470 struct rwlock gpu_clock_mutex;
2471 /* memory stats */
2472 atomic64_t num_bytes_moved;
2473 atomic_t gpu_reset_counter;
2474 /* ACPI interface */
2475 struct radeon_atif atif;
2476 struct radeon_atcs atcs;
2477 /* srbm instance registers */
2478 struct rwlock srbm_mutex;
2479 /* clock, powergating flags */
2480 u32 cg_flags;
2481 u32 pg_flags;
2482
2483 struct dev_pm_domain vga_pm_domain;
2484 bool have_disp_power_ref;
2485 u32 px_quirk_flags;
2486
2487 /* tracking pinned memory */
2488 u64 vram_pin_size;
2489 u64 gart_pin_size;
2490 };
2491
2492 bool radeon_is_px(struct drm_device *dev);
2493 int radeon_device_init(struct radeon_device *rdev,
2494 struct drm_device *ddev,
2495 struct pci_dev *pdev,
2496 uint32_t flags);
2497 void radeon_device_fini(struct radeon_device *rdev);
2498 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2499
2500 #define RADEON_MIN_MMIO_SIZE 0x10000
2501
2502 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2503 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
r100_mm_rreg(struct radeon_device * rdev,uint32_t reg,bool always_indirect)2504 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2505 bool always_indirect)
2506 {
2507 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2508 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2509 return readl(((void __iomem *)rdev->rmmio) + reg);
2510 else
2511 return r100_mm_rreg_slow(rdev, reg);
2512 }
r100_mm_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v,bool always_indirect)2513 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2514 bool always_indirect)
2515 {
2516 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2517 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2518 else
2519 r100_mm_wreg_slow(rdev, reg, v);
2520 }
2521
2522 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2523 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2524
2525 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2526 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2527
2528 /*
2529 * Cast helper
2530 */
2531 extern const struct dma_fence_ops radeon_fence_ops;
2532
to_radeon_fence(struct dma_fence * f)2533 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f)
2534 {
2535 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2536
2537 if (__f->base.ops == &radeon_fence_ops)
2538 return __f;
2539
2540 return NULL;
2541 }
2542
2543 /*
2544 * Registers read & write functions.
2545 */
2546 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2547 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2548 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2549 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2550 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2551 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2552 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
2553 r100_mm_rreg(rdev, (reg), false))
2554 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2555 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2556 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2557 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2558 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2559 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2560 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2561 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2562 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2563 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2564 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2565 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2566 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2567 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2568 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2569 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2570 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2571 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2572 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2573 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2574 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2575 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2576 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2577 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2578 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2579 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2580 #define WREG32_P(reg, val, mask) \
2581 do { \
2582 uint32_t tmp_ = RREG32(reg); \
2583 tmp_ &= (mask); \
2584 tmp_ |= ((val) & ~(mask)); \
2585 WREG32(reg, tmp_); \
2586 } while (0)
2587 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2588 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2589 #define WREG32_PLL_P(reg, val, mask) \
2590 do { \
2591 uint32_t tmp_ = RREG32_PLL(reg); \
2592 tmp_ &= (mask); \
2593 tmp_ |= ((val) & ~(mask)); \
2594 WREG32_PLL(reg, tmp_); \
2595 } while (0)
2596 #define WREG32_SMC_P(reg, val, mask) \
2597 do { \
2598 uint32_t tmp_ = RREG32_SMC(reg); \
2599 tmp_ &= (mask); \
2600 tmp_ |= ((val) & ~(mask)); \
2601 WREG32_SMC(reg, tmp_); \
2602 } while (0)
2603 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2604 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2605 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2606
2607 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2608 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2609
2610 /*
2611 * Indirect registers accessors.
2612 * They used to be inlined, but this increases code size by ~65 kbytes.
2613 * Since each performs a pair of MMIO ops
2614 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2615 * the cost of call+ret is almost negligible. MMIO and locking
2616 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2617 */
2618 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2619 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2620 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2621 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2622 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2623 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2624 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2625 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2626 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2627 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2628 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2629 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2630 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2631 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2632 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2633 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2634
2635 void r100_pll_errata_after_index(struct radeon_device *rdev);
2636
2637
2638 /*
2639 * ASICs helpers.
2640 */
2641 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2642 (rdev->pdev->device == 0x5969))
2643 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2644 (rdev->family == CHIP_RV200) || \
2645 (rdev->family == CHIP_RS100) || \
2646 (rdev->family == CHIP_RS200) || \
2647 (rdev->family == CHIP_RV250) || \
2648 (rdev->family == CHIP_RV280) || \
2649 (rdev->family == CHIP_RS300))
2650 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2651 (rdev->family == CHIP_RV350) || \
2652 (rdev->family == CHIP_R350) || \
2653 (rdev->family == CHIP_RV380) || \
2654 (rdev->family == CHIP_R420) || \
2655 (rdev->family == CHIP_R423) || \
2656 (rdev->family == CHIP_RV410) || \
2657 (rdev->family == CHIP_RS400) || \
2658 (rdev->family == CHIP_RS480))
2659 #define ASIC_IS_X2(rdev) ((rdev->pdev->device == 0x9441) || \
2660 (rdev->pdev->device == 0x9443) || \
2661 (rdev->pdev->device == 0x944B) || \
2662 (rdev->pdev->device == 0x9506) || \
2663 (rdev->pdev->device == 0x9509) || \
2664 (rdev->pdev->device == 0x950F) || \
2665 (rdev->pdev->device == 0x689C) || \
2666 (rdev->pdev->device == 0x689D))
2667 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2668 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2669 (rdev->family == CHIP_RS690) || \
2670 (rdev->family == CHIP_RS740) || \
2671 (rdev->family >= CHIP_R600))
2672 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2673 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2674 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2675 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2676 (rdev->flags & RADEON_IS_IGP))
2677 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2678 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2679 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2680 (rdev->flags & RADEON_IS_IGP))
2681 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2682 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2683 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2684 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2685 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2686 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2687 (rdev->family == CHIP_MULLINS))
2688
2689 #define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \
2690 (rdev->pdev->device == 0x6850) || \
2691 (rdev->pdev->device == 0x6858) || \
2692 (rdev->pdev->device == 0x6859) || \
2693 (rdev->pdev->device == 0x6840) || \
2694 (rdev->pdev->device == 0x6841) || \
2695 (rdev->pdev->device == 0x6842) || \
2696 (rdev->pdev->device == 0x6843))
2697
2698 /*
2699 * BIOS helpers.
2700 */
2701 #define RBIOS8(i) (rdev->bios[i])
2702 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2703 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2704
2705 int radeon_combios_init(struct radeon_device *rdev);
2706 void radeon_combios_fini(struct radeon_device *rdev);
2707 int radeon_atombios_init(struct radeon_device *rdev);
2708 void radeon_atombios_fini(struct radeon_device *rdev);
2709
2710
2711 /*
2712 * RING helpers.
2713 */
2714
2715 /**
2716 * radeon_ring_write - write a value to the ring
2717 *
2718 * @ring: radeon_ring structure holding ring information
2719 * @v: dword (dw) value to write
2720 *
2721 * Write a value to the requested ring buffer (all asics).
2722 */
radeon_ring_write(struct radeon_ring * ring,uint32_t v)2723 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2724 {
2725 if (ring->count_dw <= 0)
2726 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2727
2728 ring->ring[ring->wptr++] = v;
2729 ring->wptr &= ring->ptr_mask;
2730 ring->count_dw--;
2731 ring->ring_free_dw--;
2732 }
2733
2734 /*
2735 * ASICs macro.
2736 */
2737 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2738 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2739 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2740 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2741 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2742 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2743 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
2744 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2745 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2746 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2747 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2748 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2749 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2750 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2751 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2752 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2753 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2754 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2755 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2756 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2757 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2758 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2759 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2760 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2761 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2762 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2763 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2764 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2765 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2766 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2767 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2768 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2769 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2770 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2771 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2772 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2773 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2774 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2775 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2776 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2777 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2778 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2779 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2780 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2781 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2782 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2783 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2784 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2785 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2786 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2787 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2788 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2789 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2790 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2791 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2792 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2793 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2794 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2795 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2796 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2797 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2798 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2799 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2800 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2801 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
2802 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2803 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2804 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2805 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2806 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2807 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2808 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2809 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2810 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2811 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2812 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2813 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2814 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2815 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2816 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2817 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2818 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2819 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2820 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2821 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2822 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2823 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2824 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2825 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2826 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2827 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2828
2829 /* Common functions */
2830 /* AGP */
2831 extern int radeon_gpu_reset(struct radeon_device *rdev);
2832 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2833 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2834 extern void radeon_agp_disable(struct radeon_device *rdev);
2835 extern int radeon_modeset_init(struct radeon_device *rdev);
2836 extern void radeon_modeset_fini(struct radeon_device *rdev);
2837 extern bool radeon_card_posted(struct radeon_device *rdev);
2838 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2839 extern void radeon_update_display_priority(struct radeon_device *rdev);
2840 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2841 extern void radeon_scratch_init(struct radeon_device *rdev);
2842 extern void radeon_wb_fini(struct radeon_device *rdev);
2843 extern int radeon_wb_init(struct radeon_device *rdev);
2844 extern void radeon_wb_disable(struct radeon_device *rdev);
2845 extern void radeon_surface_init(struct radeon_device *rdev);
2846 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2847 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2848 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2849 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2850 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2851 extern int radeon_ttm_tt_set_userptr(struct radeon_device *rdev,
2852 struct ttm_tt *ttm, uint64_t addr,
2853 uint32_t flags);
2854 extern bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm);
2855 extern bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm);
2856 bool radeon_ttm_tt_is_bound(struct ttm_device *bdev, struct ttm_tt *ttm);
2857 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2858 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2859 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2860 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
2861 bool fbcon, bool freeze);
2862 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2863 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2864 const u32 *registers,
2865 const u32 array_size);
2866 struct radeon_device *radeon_get_rdev(struct ttm_device *bdev);
2867
2868 /* KMS */
2869
2870 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc);
2871 int radeon_enable_vblank_kms(struct drm_crtc *crtc);
2872 void radeon_disable_vblank_kms(struct drm_crtc *crtc);
2873
2874 /*
2875 * vm
2876 */
2877 int radeon_vm_manager_init(struct radeon_device *rdev);
2878 void radeon_vm_manager_fini(struct radeon_device *rdev);
2879 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2880 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2881 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2882 struct radeon_vm *vm,
2883 struct list_head *head);
2884 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2885 struct radeon_vm *vm, int ring);
2886 void radeon_vm_flush(struct radeon_device *rdev,
2887 struct radeon_vm *vm,
2888 int ring, struct radeon_fence *fence);
2889 void radeon_vm_fence(struct radeon_device *rdev,
2890 struct radeon_vm *vm,
2891 struct radeon_fence *fence);
2892 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2893 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2894 struct radeon_vm *vm);
2895 int radeon_vm_clear_freed(struct radeon_device *rdev,
2896 struct radeon_vm *vm);
2897 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2898 struct radeon_vm *vm);
2899 int radeon_vm_bo_update(struct radeon_device *rdev,
2900 struct radeon_bo_va *bo_va,
2901 struct ttm_resource *mem);
2902 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2903 struct radeon_bo *bo);
2904 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2905 struct radeon_bo *bo);
2906 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2907 struct radeon_vm *vm,
2908 struct radeon_bo *bo);
2909 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2910 struct radeon_bo_va *bo_va,
2911 uint64_t offset,
2912 uint32_t flags);
2913 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2914 struct radeon_bo_va *bo_va);
2915
2916 /* audio */
2917 void r600_audio_update_hdmi(struct work_struct *work);
2918 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2919 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2920 void r600_audio_enable(struct radeon_device *rdev,
2921 struct r600_audio_pin *pin,
2922 u8 enable_mask);
2923 void dce6_audio_enable(struct radeon_device *rdev,
2924 struct r600_audio_pin *pin,
2925 u8 enable_mask);
2926
2927 /*
2928 * R600 vram scratch functions
2929 */
2930 int r600_vram_scratch_init(struct radeon_device *rdev);
2931 void r600_vram_scratch_fini(struct radeon_device *rdev);
2932
2933 /*
2934 * r600 cs checking helper
2935 */
2936 unsigned r600_mip_minify(unsigned size, unsigned level);
2937 bool r600_fmt_is_valid_color(u32 format);
2938 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2939 int r600_fmt_get_blocksize(u32 format);
2940 int r600_fmt_get_nblocksx(u32 format, u32 w);
2941 int r600_fmt_get_nblocksy(u32 format, u32 h);
2942
2943 /*
2944 * r600 functions used by radeon_encoder.c
2945 */
2946 struct radeon_hdmi_acr {
2947 u32 clock;
2948
2949 int n_32khz;
2950 int cts_32khz;
2951
2952 int n_44_1khz;
2953 int cts_44_1khz;
2954
2955 int n_48khz;
2956 int cts_48khz;
2957
2958 };
2959
2960 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2961 u32 tiling_pipe_num,
2962 u32 max_rb_num,
2963 u32 total_max_rb_num,
2964 u32 enabled_rb_mask);
2965
2966 /*
2967 * evergreen functions used by radeon_encoder.c
2968 */
2969
2970 extern int ni_init_microcode(struct radeon_device *rdev);
2971 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2972
2973 /* radeon_acpi.c */
2974 #if defined(CONFIG_ACPI)
2975 extern int radeon_acpi_init(struct radeon_device *rdev);
2976 extern void radeon_acpi_fini(struct radeon_device *rdev);
2977 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2978 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2979 u8 perf_req, bool advertise);
2980 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2981 #else
radeon_acpi_init(struct radeon_device * rdev)2982 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
radeon_acpi_fini(struct radeon_device * rdev)2983 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2984 #endif
2985
2986 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2987 struct radeon_cs_packet *pkt,
2988 unsigned idx);
2989 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2990 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2991 struct radeon_cs_packet *pkt);
2992 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2993 struct radeon_bo_list **cs_reloc,
2994 int nomm);
2995 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2996 uint32_t *vline_start_end,
2997 uint32_t *vline_status);
2998
2999 /* interrupt control register helpers */
3000 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev,
3001 u32 reg, u32 mask,
3002 bool enable, const char *name,
3003 unsigned n);
3004
3005 /* Audio component binding */
3006 void radeon_audio_component_init(struct radeon_device *rdev);
3007 void radeon_audio_component_fini(struct radeon_device *rdev);
3008
3009 #include "radeon_object.h"
3010
3011 #endif
3012