1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrlcb33.finn 31 // 32 33 34 35 #include "nvcfg_sdk.h" 36 #include "ctrl/ctrlxxxx.h" 37 /* NV_CONF_COMPUTE control commands and parameters */ 38 39 #define NV_CONF_COMPUTE_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xCB33, NVCB33_CTRL_##cat, idx) 40 41 #define NVCB33_CTRL_RESERVED (0x00) 42 #define NVCB33_CTRL_CONF_COMPUTE (0x01) 43 44 /* 45 * NV_CONF_COMPUTE_CTRL_CMD_NULL 46 * 47 * This command does nothing. 48 * This command does not take any parameters. 49 * 50 * Possible return values: 51 * NV_OK 52 */ 53 #define NV_CONF_COMPUTE_CTRL_CMD_NULL (0xcb330000) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED_INTERFACE_ID << 8) | 0x0" */ 54 55 56 57 58 59 /* 60 * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES 61 * This control call returns overall system and gpu capabilities 62 * 63 * Final operating environment depends on a lot of factors: 64 * APM: Ampere Protected Memory 65 * HCC: Hopper Confidential Compute 66 * --------------------------------------------------------------------------- 67 * SrNo CPU TEE GPU TEE GPU Platform GPU mode SW Status System Env 68 * --------------------------------------------------------------------------- 69 * 1 AMD SEV APM/HCC Silicon Production Production Production 70 * 2 AMD SEV APM/HCC Silicon Production Development Simulation 71 * 3 <Any> APM/HCC <Any> Debug <Any> Simulation 72 * 4 Non SEV APM/HCC <Any> <Any> <Any> Simulation 73 * 5 <Any> APM/HCC FMOD/EMU/RTL <Any> <Any> Simulation 74 * --------------------------------------------------------------------------- 75 * 76 * Prameters: 77 * cpuCapability: [OUT] 78 * This indicates if cpu is capable of AMD SEV 79 * gpusCapability: [OUT] 80 * This indicates if all gpus in the system support APM/HCC. 81 * This field doesn't mean APM/HCC is enabled. 82 * environment: [OUT] 83 * System environment can be production or simulation 84 * ccFeature: [OUT] 85 * Specifies if all gpus in the system have APM/HCC feature enabled 86 * CC feature can be enabled/disabled using this control call: 87 * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_CC_FEATURE 88 * devToolsMode: [OUT] 89 * Dev tools mode is used for debugging/profiling 90 * Dev tools mode is set at system level and implies that all GPUs in 91 * the system have this mode enabled/disabled 92 * multiGpuMode: [OUT] 93 * Specifies the mode in which a multi gpu system is operating 94 * 95 * cpuCapability, gpusCapability & environment are determined by the 96 * driver and cannot be modified later on 97 * 98 * Possible return values: 99 * NV_OK 100 * NV_ERR_NOT_SUPPORTED 101 * NV_ERR_INVALID_ARGUMENT 102 * NV_ERR_INVALID_OBJECT_HANDLE 103 * NV_ERR_INVALID_CLIENT 104 * NV_ERR_OBJECT_NOT_FOUND 105 */ 106 #define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES (0xcb330101) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x1" */ 107 108 #define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE 0 109 #define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV 1 110 #define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX 2 111 112 #define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE 0 113 #define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM 1 114 #define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC 2 115 116 #define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE 0 117 #define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM 1 118 #define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD 2 119 120 #define NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED 0 121 #define NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED 1 122 #define NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED 2 123 124 #define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED 0 125 #define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED 1 126 127 #define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE 0 128 #define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE 1 129 130 typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS { 131 NvU8 cpuCapability; 132 NvU8 gpusCapability; 133 NvU8 environment; 134 NvU8 ccFeature; 135 NvU8 devToolsMode; 136 NvU8 multiGpuMode; 137 } NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS; 138 139 /* 140 * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE 141 * This control call can be used to determine if all GPUs are ready to accept 142 * work form clients. 143 * 144 * bAcceptClientRequest: [OUT] 145 * NV_TRUE: all gpus accepting client work requests 146 * NV_FALSE: all gpus blocking client work requests 147 * 148 * Possible return values: 149 * NV_OK 150 * NV_ERR_NOT_SUPPORTED 151 * NV_ERR_INVALID_ARGUMENT 152 * NV_ERR_INVALID_OBJECT_HANDLE 153 * NV_ERR_INVALID_CLIENT 154 * NV_ERR_OBJECT_NOT_FOUND 155 */ 156 #define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE (0xcb330104) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x4" */ 157 158 typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS { 159 NvBool bAcceptClientRequest; 160 } NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS; 161 162 /* 163 * NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE 164 * This control call can be used to set gpu state to accept client requests 165 * or to block client requests 166 * This is a PRIVILEGED control call and can be set via admin tools 167 * 168 * bAcceptClientRequest:[IN] 169 * NV_TRUE: set all gpus state to accept client work requests 170 * NV_FALSE: set all gpus state to block client work requests 171 * 172 * Possible return values: 173 * NV_OK 174 * NV_ERR_NOT_SUPPORTED 175 * NV_ERR_INVALID_ARGUMENT 176 * NV_ERR_INVALID_OBJECT_HANDLE 177 * NV_ERR_INVALID_CLIENT 178 * NV_ERR_OBJECT_NOT_FOUND 179 * NV_ERR_INSUFFICIENT_PERMISSIONS 180 */ 181 #define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE (0xcb330105) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x5" */ 182 183 typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS { 184 NvBool bAcceptClientRequest; 185 } NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS; 186 187 /* 188 * NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE 189 * This control call returns protected and unprotected vidmem size 190 * 191 * hSubDevice: [IN] 192 * subdevice handle for the gpu whose vidmem size is requested 193 * protectedMemSizeInKb: [OUT] 194 * total protected memory size in kB 195 * unprotectedMemSizeInKb: [OUT] 196 * total unprotected memory size in kB 197 * 198 * Possible return values: 199 * NV_OK 200 * NV_ERR_NOT_SUPPORTED 201 * NV_ERR_INVALID_ARGUMENT 202 * NV_ERR_INVALID_OBJECT_HANDLE 203 * NV_ERR_INVALID_CLIENT 204 * NV_ERR_OBJECT_NOT_FOUND 205 */ 206 #define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE (0xcb330106) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x6" */ 207 208 typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS { 209 NvHandle hSubDevice; 210 NV_DECLARE_ALIGNED(NvU64 protectedMemSizeInKb, 8); 211 NV_DECLARE_ALIGNED(NvU64 unprotectedMemSizeInKb, 8); 212 } NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS; 213 214 /* 215 * NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE 216 * This control call updates protected and unprotected vidmem size. 217 * All memory is protected if APM/HCC is enabled. User can override 218 * unprotectedMemSizeInKb and that will adjust protectedMemSizeInKb accordingly. 219 * This is a PRIVILEGED control call and can be set via tools like nvidia-smi. 220 * Vidmem size can be updated after driver load and before any client FB 221 * allocations are made. 222 * 223 * hSubDevice: [IN] 224 * subdevice handle for the gpu whose vidmem size is requested 225 * protectedMemSizeInKb: [OUT] 226 * total protected memory size in kB 227 * unprotectedMemSizeInKb: [IN/OUT] 228 * total unprotected memory size in kB 229 * 230 * Possible return values: 231 * NV_OK 232 * NV_ERR_NOT_SUPPORTED 233 * NV_ERR_INVALID_ARGUMENT 234 * NV_ERR_INVALID_OBJECT_HANDLE 235 * NV_ERR_INVALID_CLIENT 236 * NV_ERR_OBJECT_NOT_FOUND 237 * NV_ERR_INSUFFICIENT_PERMISSIONS 238 */ 239 #define NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE (0xcb330107) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x7" */ 240 241 typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS { 242 NvHandle hSubDevice; 243 NV_DECLARE_ALIGNED(NvU64 protectedMemSizeInKb, 8); 244 NV_DECLARE_ALIGNED(NvU64 unprotectedMemSizeInKb, 8); 245 } NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS; 246 247 /* 248 * NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS 249 * This control call returns the max number of AES capable channels SEC2 and CE support. 250 * 251 * hSubDevice: [IN] 252 * subdevice handle for the GPU queried 253 * numSupportedSec2CCSecureChannels: [OUT] 254 * Max number of AES capable channels SEC2 supports 255 * numSupportedCeCCSecureChannels: [OUT] 256 * Max number of channels CE supports with encrypt/decrypt 257 * 258 * Possible return values: 259 * NV_OK 260 * NV_ERR_NOT_SUPPORTED 261 * NV_ERR_INVALID_ARGUMENT 262 * NV_ERR_INVALID_OBJECT_HANDLE 263 * NV_ERR_INVALID_CLIENT 264 * NV_ERR_OBJECT_NOT_FOUND 265 */ 266 #define NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS (0xcb330108) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x8" */ 267 268 #define NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0x8U) 269 270 typedef struct NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS { 271 NvHandle hSubDevice; 272 NvU32 numSupportedSec2CCSecureChannels; 273 NvU32 numSupportedCeCCSecureChannels; 274 } NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS; 275 276 /* 277 * NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE 278 * This control call returns the GPU session certificate for the specified GPU. 279 * The certificate size is the maximum of the certificate size of APM and CC. 280 * 281 * hSubDevice: [IN] 282 * Subdevice handle for the GPU queried 283 * certChain: [OUT] 284 * Certificate chain for the GPU queried 285 * certChainSize: [OUT] 286 * Actual size of certChain data 287 * attestationCertChain: [OUT] 288 * Attestation certificate chain for the GPU queried 289 * attestationCertChainSize: [OUT] 290 * Actual size of attestationCertChain data 291 * 292 * Possible return values: 293 * NV_OK 294 * NV_ERR_NOT_SUPPORTED 295 * NV_ERR_INVALID_ARGUMENT 296 * NV_ERR_INVALID_OBJECT_HANDLE 297 * NV_ERR_INVALID_CLIENT 298 * NV_ERR_OBJECT_NOT_FOUND 299 */ 300 #define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE (0xcb330109) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x9" */ 301 302 #define NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE 0x1000 303 #define NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE 0x1400 304 305 #define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS_MESSAGE_ID (0x9U) 306 307 typedef struct NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS { 308 NvHandle hSubDevice; 309 NvU8 certChain[NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE]; 310 NvU32 certChainSize; 311 NvU8 attestationCertChain[NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE]; 312 NvU32 attestationCertChainSize; 313 } NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS; 314 315 /* 316 * NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION 317 * This control call returns the GPU attestation report for the specified GPU. 318 * The attestation report size is the maximum of the attestation report size of APM and CC. 319 * 320 * hSubDevice: [IN] 321 * Subdevice handle for the GPU queried 322 * nonce: [IN] 323 * spdm supports 32 bytes on nonce 324 * attestationReport: [OUT] 325 * Attestation report of the GPU queried 326 * attestationReportSize: [OUT] 327 * Actual size of the report 328 * isCecAttestationReportPresent : [OUT] 329 * Indicates if the next 2 feilds are valid 330 * cecAttestationReport: [OUT] 331 * Cec attestation report for the gpu queried 332 * cecAttestationReportSize: [OUT] 333 * Actual size of the cec attestation report 334 * 335 * Possible return values: 336 * NV_OK 337 * NV_ERR_NOT_SUPPORTED 338 * NV_ERR_INVALID_ARGUMENT 339 * NV_ERR_INVALID_OBJECT_HANDLE 340 * NV_ERR_INVALID_CLIENT 341 * NV_ERR_OBJECT_NOT_FOUND 342 */ 343 #define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT (0xcb33010a) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xA" */ 344 345 #define NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE 0x2000 346 #define NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE 0x1000 347 #define NV_CONF_COMPUTE_NONCE_SIZE 0x20 348 349 #define NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS_MESSAGE_ID (0xAU) 350 351 typedef struct NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS { 352 NvHandle hSubDevice; 353 NvU8 nonce[NV_CONF_COMPUTE_NONCE_SIZE]; 354 NvU8 attestationReport[NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE]; 355 NvU32 attestationReportSize; 356 NvBool isCecAttestationReportPresent; 357 NvU8 cecAttestationReport[NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE]; 358 NvU32 cecAttestationReportSize; 359 } NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS; 360 361 /* 362 * NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS 363 * This control call returns the max number of Conf Compute capable channels SEC2 and CE support. 364 * 365 * hSubDevice: [IN] 366 * subdevice handle for the GPU queried 367 * maxSec2Channels: [OUT] 368 * Max number of conf compute capable channels SEC2 supports 369 * maxCeChannels: [OUT] 370 * Max number of channels CE supports with encrypt/decrypt 371 * 372 * Possible return values: 373 * NV_OK 374 * NV_ERR_NOT_SUPPORTED 375 * NV_ERR_INVALID_ARGUMENT 376 * NV_ERR_INVALID_OBJECT_HANDLE 377 * NV_ERR_INVALID_CLIENT 378 * NV_ERR_OBJECT_NOT_FOUND 379 */ 380 #define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS (0xcb33010b) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xB" */ 381 382 #define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xBU) 383 384 typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS { 385 NvHandle hSubDevice; 386 NvU32 maxSec2Channels; 387 NvU32 maxCeChannels; 388 } NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS; 389 390 /* 391 * NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE 392 * This control call returns if key rotation is enabled. 393 * 394 * hSubDevice: [IN] 395 * subdevice handle for the GPU queried 396 * keyRotationState: [OUT] 397 * NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_* value 398 * 399 * Possible return values: 400 * NV_OK 401 * NV_ERR_NOT_SUPPORTED 402 * NV_ERR_INVALID_ARGUMENT 403 * NV_ERR_INVALID_OBJECT_HANDLE 404 * NV_ERR_INVALID_CLIENT 405 * NV_ERR_OBJECT_NOT_FOUND 406 */ 407 #define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE (0xcb33010c) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xC" */ 408 409 #define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_DISABLED 0 // key rotation is disabled 410 #define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_KERN_ENABLED 1 // key rotation enabled for kernel keys 411 #define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_USER_ENABLED 2 // key rotation enabled for user keys 412 #define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_BOTH_ENABLED 3 // key rotation enabled for both keys 413 414 #define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS_MESSAGE_ID (0xCU) 415 416 typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS { 417 NvHandle hSubDevice; 418 NvU32 keyRotationState; 419 } NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS; 420 421 /* _ctrlcb33_h_ */ 422 423