1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Renesas R8A77990 CPG MSSR driver
4 *
5 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
6 *
7 * Based on the following driver from Linux kernel:
8 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9 *
10 * Copyright (C) 2016 Glider bvba
11 */
12
13 #include <common.h>
14 #include <clk-uclass.h>
15 #include <dm.h>
16
17 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
18
19 #include "renesas-cpg-mssr.h"
20 #include "rcar-gen3-cpg.h"
21
22 enum clk_ids {
23 /* Core Clock Outputs exported to DT */
24 LAST_DT_CORE_CLK = R8A77990_CLK_CPEX,
25
26 /* External Input Clocks */
27 CLK_EXTAL,
28
29 /* Internal Core Clocks */
30 CLK_MAIN,
31 CLK_PLL0,
32 CLK_PLL1,
33 CLK_PLL3,
34 CLK_PLL0D4,
35 CLK_PLL0D6,
36 CLK_PLL0D8,
37 CLK_PLL0D20,
38 CLK_PLL0D24,
39 CLK_PLL1D2,
40 CLK_PE,
41 CLK_S0,
42 CLK_S1,
43 CLK_S2,
44 CLK_S3,
45 CLK_SDSRC,
46 CLK_RPCSRC,
47
48 /* Module Clocks */
49 MOD_CLK_BASE
pack_rgba24(GdkRGBA * rgba)50 };
51
52 static const struct cpg_core_clk r8a77990_core_clks[] = {
53 /* External Clock Inputs */
54 DEF_INPUT("extal", CLK_EXTAL),
55
56 /* Internal Core Clocks */
57 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
58 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
59 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
60
61 DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),
62 DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1),
63 DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1),
64 DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1),
unpack_rgba24(guint32 val,GdkRGBA * rgba)65 DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1),
66 DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1),
67 DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
68 DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1),
69 DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
70 DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
71 DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
72 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
73 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
74 DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
75
76 /* Core Clock Outputs */
77 DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
78 DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
79 DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1),
80 DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1),
81 DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1),
82 DEF_FIXED("s0d1", R8A77990_CLK_S0D1, CLK_S0, 1, 1),
83 DEF_FIXED("s0d3", R8A77990_CLK_S0D3, CLK_S0, 3, 1),
84 DEF_FIXED("s0d6", R8A77990_CLK_S0D6, CLK_S0, 6, 1),
85 DEF_FIXED("s0d12", R8A77990_CLK_S0D12, CLK_S0, 12, 1),
86 DEF_FIXED("s0d24", R8A77990_CLK_S0D24, CLK_S0, 24, 1),
87 DEF_FIXED("s1d1", R8A77990_CLK_S1D1, CLK_S1, 1, 1),
88 DEF_FIXED("s1d2", R8A77990_CLK_S1D2, CLK_S1, 2, 1),
89 DEF_FIXED("s1d4", R8A77990_CLK_S1D4, CLK_S1, 4, 1),
90 DEF_FIXED("s2d1", R8A77990_CLK_S2D1, CLK_S2, 1, 1),
91 DEF_FIXED("s2d2", R8A77990_CLK_S2D2, CLK_S2, 2, 1),
92 DEF_FIXED("s2d4", R8A77990_CLK_S2D4, CLK_S2, 4, 1),
93 DEF_FIXED("s3d1", R8A77990_CLK_S3D1, CLK_S3, 1, 1),
94 DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1),
95 DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1),
96
97 DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, CLK_SDSRC, 0x0074),
98 DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078),
99 DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c),
100
101 DEF_GEN3_RPC("rpc", R8A77990_CLK_RPC, CLK_RPCSRC, 0x238),
102
103 DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
104 DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
105 DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
106 DEF_FIXED("osc", R8A77990_CLK_OSC, CLK_EXTAL, 384, 1),
107 DEF_FIXED("r", R8A77990_CLK_R, CLK_EXTAL, 1536, 1),
108
109 DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 6),
110 DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
111 DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
112 DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
113
114 DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
115 DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
116 DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014),
117 };
118
119 static const struct mssr_mod_clk r8a77990_mod_clks[] = {
120 DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C),
121 DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C),
122 DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C),
123 DEF_MOD("scif1", 206, R8A77990_CLK_S3D4C),
124 DEF_MOD("scif0", 207, R8A77990_CLK_S3D4C),
125 DEF_MOD("msiof3", 208, R8A77990_CLK_MSO),
126 DEF_MOD("msiof2", 209, R8A77990_CLK_MSO),
127 DEF_MOD("msiof1", 210, R8A77990_CLK_MSO),
128 DEF_MOD("msiof0", 211, R8A77990_CLK_MSO),
129 DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
130 DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
131 DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
132
133 DEF_MOD("cmt3", 300, R8A77990_CLK_R),
134 DEF_MOD("cmt2", 301, R8A77990_CLK_R),
135 DEF_MOD("cmt1", 302, R8A77990_CLK_R),
136 DEF_MOD("cmt0", 303, R8A77990_CLK_R),
137 DEF_MOD("scif2", 310, R8A77990_CLK_S3D4C),
138 DEF_MOD("sdif3", 311, R8A77990_CLK_SD3),
139 DEF_MOD("sdif1", 313, R8A77990_CLK_SD1),
140 DEF_MOD("sdif0", 314, R8A77990_CLK_SD0),
141 DEF_MOD("pcie0", 319, R8A77990_CLK_S3D1),
142 DEF_MOD("usb3-if0", 328, R8A77990_CLK_S3D1),
143 DEF_MOD("usb-dmac0", 330, R8A77990_CLK_S3D1),
144 DEF_MOD("usb-dmac1", 331, R8A77990_CLK_S3D1),
145
146 DEF_MOD("rwdt", 402, R8A77990_CLK_R),
147 DEF_MOD("intc-ex", 407, R8A77990_CLK_CP),
148 DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
149
150 DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4),
151 DEF_MOD("drif7", 508, R8A77990_CLK_S3D2),
152 DEF_MOD("drif6", 509, R8A77990_CLK_S3D2),
153 DEF_MOD("drif5", 510, R8A77990_CLK_S3D2),
154 DEF_MOD("drif4", 511, R8A77990_CLK_S3D2),
155 DEF_MOD("drif3", 512, R8A77990_CLK_S3D2),
156 DEF_MOD("drif2", 513, R8A77990_CLK_S3D2),
157 DEF_MOD("drif1", 514, R8A77990_CLK_S3D2),
158 DEF_MOD("drif0", 515, R8A77990_CLK_S3D2),
159 DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C),
160 DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C),
161 DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C),
162 DEF_MOD("hscif1", 519, R8A77990_CLK_S3D1C),
163 DEF_MOD("hscif0", 520, R8A77990_CLK_S3D1C),
164 DEF_MOD("thermal", 522, R8A77990_CLK_CP),
165 DEF_MOD("pwm", 523, R8A77990_CLK_S3D4C),
166
167 DEF_MOD("fcpvd1", 602, R8A77990_CLK_S1D2),
168 DEF_MOD("fcpvd0", 603, R8A77990_CLK_S1D2),
169 DEF_MOD("fcpvb0", 607, R8A77990_CLK_S0D1),
170 DEF_MOD("fcpvi0", 611, R8A77990_CLK_S0D1),
171 DEF_MOD("fcpf0", 615, R8A77990_CLK_S0D1),
172 DEF_MOD("fcpcs", 619, R8A77990_CLK_S0D1),
173 DEF_MOD("vspd1", 622, R8A77990_CLK_S1D2),
174 DEF_MOD("vspd0", 623, R8A77990_CLK_S1D2),
175 DEF_MOD("vspb", 626, R8A77990_CLK_S0D1),
176 DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
177
178 DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
179 DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
180 DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
181 DEF_MOD("du1", 723, R8A77990_CLK_S2D1),
182 DEF_MOD("du0", 724, R8A77990_CLK_S2D1),
183 DEF_MOD("lvds", 727, R8A77990_CLK_S2D1),
184
185 DEF_MOD("vin7", 804, R8A77990_CLK_S1D2),
186 DEF_MOD("vin6", 805, R8A77990_CLK_S1D2),
187 DEF_MOD("vin5", 806, R8A77990_CLK_S1D2),
188 DEF_MOD("vin4", 807, R8A77990_CLK_S1D2),
189 DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2),
190
191 DEF_MOD("gpio6", 906, R8A77990_CLK_S3D4),
192 DEF_MOD("gpio5", 907, R8A77990_CLK_S3D4),
193 DEF_MOD("gpio4", 908, R8A77990_CLK_S3D4),
194 DEF_MOD("gpio3", 909, R8A77990_CLK_S3D4),
195 DEF_MOD("gpio2", 910, R8A77990_CLK_S3D4),
196 DEF_MOD("gpio1", 911, R8A77990_CLK_S3D4),
197 DEF_MOD("gpio0", 912, R8A77990_CLK_S3D4),
198 DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2),
199 DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4),
200 DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4),
201 DEF_MOD("rpc", 917, R8A77990_CLK_RPC),
202 DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2),
203 DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2),
204 DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP),
205 DEF_MOD("i2c4", 927, R8A77990_CLK_S3D2),
206 DEF_MOD("i2c3", 928, R8A77990_CLK_S3D2),
207 DEF_MOD("i2c2", 929, R8A77990_CLK_S3D2),
208 DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2),
209 DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2),
210
211 DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4),
212 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
213 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
214 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
215 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
216 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
217 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
218 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
219 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
220 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
221 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
222 DEF_MOD("scu-all", 1017, R8A77990_CLK_S3D4),
223 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
224 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
225 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
226 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
227 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
228 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
229 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
230 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
231 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
232 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
233 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
234 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
235 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
236 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
237 };
238
239 /*
240 * CPG Clock Data
241 */
242
243 /*
244 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
245 *--------------------------------------------------------------------
246 * 0 48 x 1 x100/4 x100/3 x100/3
247 * 1 48 x 1 x100/4 x100/3 x58/3
248 */
249 #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
250
251 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
252 /* EXTAL div PLL1 mult/div PLL3 mult/div */
253 { 1, 100, 3, 100, 3, },
254 { 1, 100, 3, 58, 3, },
255 };
256
257 static const struct mstp_stop_table r8a77990_mstp_table[] = {
258 { 0x00200000, 0x0, 0x00200000, 0 },
259 { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
260 { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
261 { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
262 { 0x80000184, 0x180, 0x80000184, 0 },
263 { 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
264 { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
265 { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
266 { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
267 { 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
268 { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
269 { 0x000000B7, 0x0, 0x000000B7, 0 },
270 };
271
272 static const void *r8a77990_get_pll_config(const u32 cpg_mode)
273 {
274 return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
275 }
276
277 static const struct cpg_mssr_info r8a77990_cpg_mssr_info = {
278 .core_clk = r8a77990_core_clks,
279 .core_clk_size = ARRAY_SIZE(r8a77990_core_clks),
280 .mod_clk = r8a77990_mod_clks,
281 .mod_clk_size = ARRAY_SIZE(r8a77990_mod_clks),
282 .mstp_table = r8a77990_mstp_table,
283 .mstp_table_size = ARRAY_SIZE(r8a77990_mstp_table),
284 .reset_node = "renesas,r8a77990-rst",
285 .mod_clk_base = MOD_CLK_BASE,
286 .clk_extal_id = CLK_EXTAL,
287 .clk_extalr_id = ~0,
288 .get_pll_config = r8a77990_get_pll_config,
289 };
290
291 static const struct udevice_id r8a77990_clk_ids[] = {
292 {
293 .compatible = "renesas,r8a77990-cpg-mssr",
294 .data = (ulong)&r8a77990_cpg_mssr_info
295 },
296 { }
297 };
298
299 U_BOOT_DRIVER(clk_r8a77990) = {
300 .name = "clk_r8a77990",
301 .id = UCLASS_CLK,
302 .of_match = r8a77990_clk_ids,
303 .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
304 .ops = &gen3_clk_ops,
305 .probe = gen3_clk_probe,
306 .remove = gen3_clk_remove,
307 };
308