1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022-2023 Intel Corporation 4 */ 5 6 #ifndef _XE_GT_TYPES_H_ 7 #define _XE_GT_TYPES_H_ 8 9 #include "xe_force_wake_types.h" 10 #include "xe_gt_idle_types.h" 11 #include "xe_gt_sriov_pf_types.h" 12 #include "xe_hw_engine_types.h" 13 #include "xe_hw_fence_types.h" 14 #include "xe_reg_sr_types.h" 15 #include "xe_sa_types.h" 16 #include "xe_uc_types.h" 17 18 struct xe_exec_queue_ops; 19 struct xe_migrate; 20 struct xe_ring_ops; 21 22 enum xe_gt_type { 23 XE_GT_TYPE_UNINITIALIZED, 24 XE_GT_TYPE_MAIN, 25 XE_GT_TYPE_MEDIA, 26 }; 27 28 #define XE_MAX_DSS_FUSE_REGS 3 29 #define XE_MAX_DSS_FUSE_BITS (32 * XE_MAX_DSS_FUSE_REGS) 30 #define XE_MAX_EU_FUSE_REGS 1 31 #define XE_MAX_EU_FUSE_BITS (32 * XE_MAX_EU_FUSE_REGS) 32 #define XE_MAX_L3_BANK_MASK_BITS 64 33 34 typedef unsigned long xe_dss_mask_t[BITS_TO_LONGS(XE_MAX_DSS_FUSE_BITS)]; 35 typedef unsigned long xe_eu_mask_t[BITS_TO_LONGS(XE_MAX_EU_FUSE_BITS)]; 36 typedef unsigned long xe_l3_bank_mask_t[BITS_TO_LONGS(XE_MAX_L3_BANK_MASK_BITS)]; 37 38 struct xe_mmio_range { 39 u32 start; 40 u32 end; 41 }; 42 43 /* 44 * The hardware has multiple kinds of multicast register ranges that need 45 * special register steering (and future platforms are expected to add 46 * additional types). 47 * 48 * During driver startup, we initialize the steering control register to 49 * direct reads to a slice/subslice that are valid for the 'subslice' class 50 * of multicast registers. If another type of steering does not have any 51 * overlap in valid steering targets with 'subslice' style registers, we will 52 * need to explicitly re-steer reads of registers of the other type. 53 * 54 * Only the replication types that may need additional non-default steering 55 * are listed here. 56 */ 57 enum xe_steering_type { 58 L3BANK, 59 MSLICE, 60 LNCF, 61 DSS, 62 OADDRM, 63 SQIDI_PSMI, 64 65 /* 66 * On some platforms there are multiple types of MCR registers that 67 * will always return a non-terminated value at instance (0, 0). We'll 68 * lump those all into a single category to keep things simple. 69 */ 70 INSTANCE0, 71 72 /* 73 * Register ranges that don't need special steering for each register: 74 * it's sufficient to keep the HW-default for the selector, or only 75 * change it once, on GT initialization. This needs to be the last 76 * steering type. 77 */ 78 IMPLICIT_STEERING, 79 NUM_STEERING_TYPES 80 }; 81 82 #define gt_to_tile(gt__) \ 83 _Generic(gt__, \ 84 const struct xe_gt * : (const struct xe_tile *)((gt__)->tile), \ 85 struct xe_gt * : (gt__)->tile) 86 87 #define gt_to_xe(gt__) \ 88 _Generic(gt__, \ 89 const struct xe_gt * : (const struct xe_device *)(gt_to_tile(gt__)->xe), \ 90 struct xe_gt * : gt_to_tile(gt__)->xe) 91 92 /** 93 * struct xe_gt - A "Graphics Technology" unit of the GPU 94 * 95 * A GT ("Graphics Technology") is the subset of a GPU primarily responsible 96 * for implementing the graphics, compute, and/or media IP. It encapsulates 97 * the hardware engines, programmable execution units, and GuC. Each GT has 98 * its own handling of power management (RC6+forcewake) and multicast register 99 * steering. 100 * 101 * A GPU/tile may have a single GT that supplies all graphics, compute, and 102 * media functionality, or the graphics/compute and media may be split into 103 * separate GTs within a tile. 104 */ 105 struct xe_gt { 106 /** @tile: Backpointer to GT's tile */ 107 struct xe_tile *tile; 108 109 /** @info: GT info */ 110 struct { 111 /** @info.type: type of GT */ 112 enum xe_gt_type type; 113 /** @info.id: Unique ID of this GT within the PCI Device */ 114 u8 id; 115 /** @info.reference_clock: clock frequency */ 116 u32 reference_clock; 117 /** @info.engine_mask: mask of engines present on GT */ 118 u64 engine_mask; 119 /** 120 * @info.__engine_mask: mask of engines present on GT read from 121 * xe_pci.c, used to fake reading the engine_mask from the 122 * hwconfig blob. 123 */ 124 u64 __engine_mask; 125 /** @info.gmdid: raw GMD_ID value from hardware */ 126 u32 gmdid; 127 } info; 128 129 /** 130 * @mmio: mmio info for GT. All GTs within a tile share the same 131 * register space, but have their own copy of GSI registers at a 132 * specific offset, as well as their own forcewake handling. 133 */ 134 struct { 135 /** @mmio.fw: force wake for GT */ 136 struct xe_force_wake fw; 137 /** 138 * @mmio.adj_limit: adjust MMIO address if address is below this 139 * value 140 */ 141 u32 adj_limit; 142 /** @mmio.adj_offset: offect to add to MMIO address when adjusting */ 143 u32 adj_offset; 144 } mmio; 145 146 /** @sriov: virtualization data related to GT */ 147 union { 148 /** @sriov.pf: PF data. Valid only if driver is running as PF */ 149 struct xe_gt_sriov_pf pf; 150 } sriov; 151 152 /** 153 * @reg_sr: table with registers to be restored on GT init/resume/reset 154 */ 155 struct xe_reg_sr reg_sr; 156 157 /** @reset: state for GT resets */ 158 struct { 159 /** 160 * @reset.worker: work so GT resets can done async allowing to reset 161 * code to safely flush all code paths 162 */ 163 struct work_struct worker; 164 } reset; 165 166 /** @tlb_invalidation: TLB invalidation state */ 167 struct { 168 /** @tlb_invalidation.seqno: TLB invalidation seqno, protected by CT lock */ 169 #define TLB_INVALIDATION_SEQNO_MAX 0x100000 170 int seqno; 171 /** 172 * @tlb_invalidation.seqno_recv: last received TLB invalidation seqno, 173 * protected by CT lock 174 */ 175 int seqno_recv; 176 /** 177 * @tlb_invalidation.pending_fences: list of pending fences waiting TLB 178 * invaliations, protected by CT lock 179 */ 180 struct list_head pending_fences; 181 /** 182 * @tlb_invalidation.pending_lock: protects @tlb_invalidation.pending_fences 183 * and updating @tlb_invalidation.seqno_recv. 184 */ 185 spinlock_t pending_lock; 186 /** 187 * @tlb_invalidation.fence_tdr: schedules a delayed call to 188 * xe_gt_tlb_fence_timeout after the timeut interval is over. 189 */ 190 struct delayed_work fence_tdr; 191 /** @tlb_invalidation.lock: protects TLB invalidation fences */ 192 spinlock_t lock; 193 } tlb_invalidation; 194 195 /** 196 * @ccs_mode: Number of compute engines enabled. 197 * Allows fixed mapping of available compute slices to compute engines. 198 * By default only the first available compute engine is enabled and all 199 * available compute slices are allocated to it. 200 */ 201 u32 ccs_mode; 202 203 /** @usm: unified shared memory state */ 204 struct { 205 /** 206 * @usm.bb_pool: Pool from which batchbuffers, for USM operations 207 * (e.g. migrations, fixing page tables), are allocated. 208 * Dedicated pool needed so USM operations to not get blocked 209 * behind any user operations which may have resulted in a 210 * fault. 211 */ 212 struct xe_sa_manager *bb_pool; 213 /** 214 * @usm.reserved_bcs_instance: reserved BCS instance used for USM 215 * operations (e.g. mmigrations, fixing page tables) 216 */ 217 u16 reserved_bcs_instance; 218 /** @usm.pf_wq: page fault work queue, unbound, high priority */ 219 struct workqueue_struct *pf_wq; 220 /** @usm.acc_wq: access counter work queue, unbound, high priority */ 221 struct workqueue_struct *acc_wq; 222 /** 223 * @usm.pf_queue: Page fault queue used to sync faults so faults can 224 * be processed not under the GuC CT lock. The queue is sized so 225 * it can sync all possible faults (1 per physical engine). 226 * Multiple queues exists for page faults from different VMs are 227 * be processed in parallel. 228 */ 229 struct pf_queue { 230 /** @usm.pf_queue.gt: back pointer to GT */ 231 struct xe_gt *gt; 232 #define PF_QUEUE_NUM_DW 128 233 /** @usm.pf_queue.data: data in the page fault queue */ 234 u32 data[PF_QUEUE_NUM_DW]; 235 /** 236 * @usm.pf_queue.tail: tail pointer in DWs for page fault queue, 237 * moved by worker which processes faults (consumer). 238 */ 239 u16 tail; 240 /** 241 * @usm.pf_queue.head: head pointer in DWs for page fault queue, 242 * moved by G2H handler (producer). 243 */ 244 u16 head; 245 /** @usm.pf_queue.lock: protects page fault queue */ 246 spinlock_t lock; 247 /** @usm.pf_queue.worker: to process page faults */ 248 struct work_struct worker; 249 #define NUM_PF_QUEUE 4 250 } pf_queue[NUM_PF_QUEUE]; 251 /** 252 * @usm.acc_queue: Same as page fault queue, cannot process access 253 * counters under CT lock. 254 */ 255 struct acc_queue { 256 /** @usm.acc_queue.gt: back pointer to GT */ 257 struct xe_gt *gt; 258 #define ACC_QUEUE_NUM_DW 128 259 /** @usm.acc_queue.data: data in the page fault queue */ 260 u32 data[ACC_QUEUE_NUM_DW]; 261 /** 262 * @usm.acc_queue.tail: tail pointer in DWs for access counter queue, 263 * moved by worker which processes counters 264 * (consumer). 265 */ 266 u16 tail; 267 /** 268 * @usm.acc_queue.head: head pointer in DWs for access counter queue, 269 * moved by G2H handler (producer). 270 */ 271 u16 head; 272 /** @usm.acc_queue.lock: protects page fault queue */ 273 spinlock_t lock; 274 /** @usm.acc_queue.worker: to process access counters */ 275 struct work_struct worker; 276 #define NUM_ACC_QUEUE 4 277 } acc_queue[NUM_ACC_QUEUE]; 278 } usm; 279 280 /** @ordered_wq: used to serialize GT resets and TDRs */ 281 struct workqueue_struct *ordered_wq; 282 283 /** @uc: micro controllers on the GT */ 284 struct xe_uc uc; 285 286 /** @gtidle: idle properties of GT */ 287 struct xe_gt_idle gtidle; 288 289 /** @exec_queue_ops: submission backend exec queue operations */ 290 const struct xe_exec_queue_ops *exec_queue_ops; 291 292 /** 293 * @ring_ops: ring operations for this hw engine (1 per engine class) 294 */ 295 const struct xe_ring_ops *ring_ops[XE_ENGINE_CLASS_MAX]; 296 297 /** @fence_irq: fence IRQs (1 per engine class) */ 298 struct xe_hw_fence_irq fence_irq[XE_ENGINE_CLASS_MAX]; 299 300 /** @default_lrc: default LRC state */ 301 void *default_lrc[XE_ENGINE_CLASS_MAX]; 302 303 /** @hw_engines: hardware engines on the GT */ 304 struct xe_hw_engine hw_engines[XE_NUM_HW_ENGINES]; 305 306 /** @eclass: per hardware engine class interface on the GT */ 307 struct xe_hw_engine_class_intf eclass[XE_ENGINE_CLASS_MAX]; 308 309 /** @pcode: GT's PCODE */ 310 struct { 311 /** @pcode.lock: protecting GT's PCODE mailbox data */ 312 struct mutex lock; 313 } pcode; 314 315 /** @sysfs: sysfs' kobj used by xe_gt_sysfs */ 316 struct kobject *sysfs; 317 318 /** @freq: Main GT freq sysfs control */ 319 struct kobject *freq; 320 321 /** @mocs: info */ 322 struct { 323 /** @mocs.uc_index: UC index */ 324 u8 uc_index; 325 /** @mocs.wb_index: WB index, only used on L3_CCS platforms */ 326 u8 wb_index; 327 } mocs; 328 329 /** @fuse_topo: GT topology reported by fuse registers */ 330 struct { 331 /** @fuse_topo.g_dss_mask: dual-subslices usable by geometry */ 332 xe_dss_mask_t g_dss_mask; 333 334 /** @fuse_topo.c_dss_mask: dual-subslices usable by compute */ 335 xe_dss_mask_t c_dss_mask; 336 337 /** @fuse_topo.eu_mask_per_dss: EU mask per DSS*/ 338 xe_eu_mask_t eu_mask_per_dss; 339 340 /** @fuse_topo.l3_bank_mask: L3 bank mask */ 341 xe_l3_bank_mask_t l3_bank_mask; 342 } fuse_topo; 343 344 /** @steering: register steering for individual HW units */ 345 struct { 346 /** @steering.ranges: register ranges used for this steering type */ 347 const struct xe_mmio_range *ranges; 348 349 /** @steering.group_target: target to steer accesses to */ 350 u16 group_target; 351 /** @steering.instance_target: instance to steer accesses to */ 352 u16 instance_target; 353 } steering[NUM_STEERING_TYPES]; 354 355 /** 356 * @mcr_lock: protects the MCR_SELECTOR register for the duration 357 * of a steered operation 358 */ 359 spinlock_t mcr_lock; 360 361 /** @wa_active: keep track of active workarounds */ 362 struct { 363 /** @wa_active.gt: bitmap with active GT workarounds */ 364 unsigned long *gt; 365 /** @wa_active.engine: bitmap with active engine workarounds */ 366 unsigned long *engine; 367 /** @wa_active.lrc: bitmap with active LRC workarounds */ 368 unsigned long *lrc; 369 /** @wa_active.oob: bitmap with active OOB workaroudns */ 370 unsigned long *oob; 371 } wa_active; 372 }; 373 374 #endif 375