1 /* $NetBSD: gtt.h,v 1.4 2021/12/19 11:15:49 riastradh Exp $ */
2
3 /*
4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Zhi Wang <zhi.a.wang@intel.com>
27 * Zhenyu Wang <zhenyuw@linux.intel.com>
28 * Xiao Zheng <xiao.zheng@intel.com>
29 *
30 * Contributors:
31 * Min He <min.he@intel.com>
32 * Bing Niu <bing.niu@intel.com>
33 *
34 */
35
36 #ifndef _GVT_GTT_H_
37 #define _GVT_GTT_H_
38
39 #define I915_GTT_PAGE_SHIFT 12
40
41 struct intel_vgpu_mm;
42
43 #define INTEL_GVT_INVALID_ADDR (~0UL)
44
45 struct intel_gvt_gtt_entry {
46 u64 val64;
47 int type;
48 };
49
50 struct intel_gvt_gtt_pte_ops {
51 int (*get_entry)(void *pt,
52 struct intel_gvt_gtt_entry *e,
53 unsigned long index,
54 bool hypervisor_access,
55 unsigned long gpa,
56 struct intel_vgpu *vgpu);
57 int (*set_entry)(void *pt,
58 struct intel_gvt_gtt_entry *e,
59 unsigned long index,
60 bool hypervisor_access,
61 unsigned long gpa,
62 struct intel_vgpu *vgpu);
63 bool (*test_present)(struct intel_gvt_gtt_entry *e);
64 void (*clear_present)(struct intel_gvt_gtt_entry *e);
65 void (*set_present)(struct intel_gvt_gtt_entry *e);
66 bool (*test_pse)(struct intel_gvt_gtt_entry *e);
67 void (*clear_pse)(struct intel_gvt_gtt_entry *e);
68 bool (*test_ips)(struct intel_gvt_gtt_entry *e);
69 void (*clear_ips)(struct intel_gvt_gtt_entry *e);
70 bool (*test_64k_splited)(struct intel_gvt_gtt_entry *e);
71 void (*clear_64k_splited)(struct intel_gvt_gtt_entry *e);
72 void (*set_64k_splited)(struct intel_gvt_gtt_entry *e);
73 void (*set_pfn)(struct intel_gvt_gtt_entry *e, unsigned long pfn);
74 unsigned long (*get_pfn)(struct intel_gvt_gtt_entry *e);
75 };
76
77 struct intel_gvt_gtt_gma_ops {
78 unsigned long (*gma_to_ggtt_pte_index)(unsigned long gma);
79 unsigned long (*gma_to_pte_index)(unsigned long gma);
80 unsigned long (*gma_to_pde_index)(unsigned long gma);
81 unsigned long (*gma_to_l3_pdp_index)(unsigned long gma);
82 unsigned long (*gma_to_l4_pdp_index)(unsigned long gma);
83 unsigned long (*gma_to_pml4_index)(unsigned long gma);
84 };
85
86 struct intel_gvt_gtt {
87 struct intel_gvt_gtt_pte_ops *pte_ops;
88 struct intel_gvt_gtt_gma_ops *gma_ops;
89 int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm);
90 void (*mm_free_page_table)(struct intel_vgpu_mm *mm);
91 struct list_head oos_page_use_list_head;
92 struct list_head oos_page_free_list_head;
93 struct mutex ppgtt_mm_lock;
94 struct list_head ppgtt_mm_lru_list_head;
95
96 struct page *scratch_page;
97 unsigned long scratch_mfn;
98 };
99
100 enum intel_gvt_gtt_type {
101 GTT_TYPE_INVALID = 0,
102
103 GTT_TYPE_GGTT_PTE,
104
105 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
106 GTT_TYPE_PPGTT_PTE_64K_ENTRY,
107 GTT_TYPE_PPGTT_PTE_2M_ENTRY,
108 GTT_TYPE_PPGTT_PTE_1G_ENTRY,
109
110 GTT_TYPE_PPGTT_PTE_ENTRY,
111
112 GTT_TYPE_PPGTT_PDE_ENTRY,
113 GTT_TYPE_PPGTT_PDP_ENTRY,
114 GTT_TYPE_PPGTT_PML4_ENTRY,
115
116 GTT_TYPE_PPGTT_ROOT_ENTRY,
117
118 GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
119 GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
120
121 GTT_TYPE_PPGTT_ENTRY,
122
123 GTT_TYPE_PPGTT_PTE_PT,
124 GTT_TYPE_PPGTT_PDE_PT,
125 GTT_TYPE_PPGTT_PDP_PT,
126 GTT_TYPE_PPGTT_PML4_PT,
127
128 GTT_TYPE_MAX,
129 };
130
131 enum intel_gvt_mm_type {
132 INTEL_GVT_MM_GGTT,
133 INTEL_GVT_MM_PPGTT,
134 };
135
136 #define GVT_RING_CTX_NR_PDPS GEN8_3LVL_PDPES
137
138 struct intel_gvt_partial_pte {
139 unsigned long offset;
140 u64 data;
141 struct list_head list;
142 };
143
144 struct intel_vgpu_mm {
145 enum intel_gvt_mm_type type;
146 struct intel_vgpu *vgpu;
147
148 struct kref ref;
149 atomic_t pincount;
150
151 union {
152 struct {
153 enum intel_gvt_gtt_type root_entry_type;
154 /*
155 * The 4 PDPs in ring context. For 48bit addressing,
156 * only PDP0 is valid and point to PML4. For 32it
157 * addressing, all 4 are used as true PDPs.
158 */
159 u64 guest_pdps[GVT_RING_CTX_NR_PDPS];
160 u64 shadow_pdps[GVT_RING_CTX_NR_PDPS];
161 bool shadowed;
162
163 struct list_head list;
164 struct list_head lru_list;
165 } ppgtt_mm;
166 struct {
167 void *virtual_ggtt;
168 struct list_head partial_pte_list;
169 } ggtt_mm;
170 };
171 };
172
173 struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu,
174 enum intel_gvt_gtt_type root_entry_type, u64 pdps[]);
175
intel_vgpu_mm_get(struct intel_vgpu_mm * mm)176 static inline void intel_vgpu_mm_get(struct intel_vgpu_mm *mm)
177 {
178 kref_get(&mm->ref);
179 }
180
181 void _intel_vgpu_mm_release(struct kref *mm_ref);
182
intel_vgpu_mm_put(struct intel_vgpu_mm * mm)183 static inline void intel_vgpu_mm_put(struct intel_vgpu_mm *mm)
184 {
185 kref_put(&mm->ref, _intel_vgpu_mm_release);
186 }
187
intel_vgpu_destroy_mm(struct intel_vgpu_mm * mm)188 static inline void intel_vgpu_destroy_mm(struct intel_vgpu_mm *mm)
189 {
190 intel_vgpu_mm_put(mm);
191 }
192
193 struct intel_vgpu_guest_page;
194
195 struct intel_vgpu_scratch_pt {
196 struct page *page;
197 unsigned long page_mfn;
198 };
199
200 struct intel_vgpu_gtt {
201 struct intel_vgpu_mm *ggtt_mm;
202 unsigned long active_ppgtt_mm_bitmap;
203 struct list_head ppgtt_mm_list_head;
204 struct radix_tree_root spt_tree;
205 struct list_head oos_page_list_head;
206 struct list_head post_shadow_list_head;
207 struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX];
208 };
209
210 int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
211 void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu);
212 void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old);
213 void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu);
214
215 int intel_gvt_init_gtt(struct intel_gvt *gvt);
216 void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu);
217 void intel_gvt_clean_gtt(struct intel_gvt *gvt);
218
219 struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,
220 int page_table_level,
221 void *root_entry);
222
223 struct intel_vgpu_oos_page {
224 struct intel_vgpu_ppgtt_spt *spt;
225 struct list_head list;
226 struct list_head vm_list;
227 int id;
228 void *mem;
229 };
230
231 #define GTT_ENTRY_NUM_IN_ONE_PAGE 512
232
233 /* Represent a vgpu shadow page table. */
234 struct intel_vgpu_ppgtt_spt {
235 atomic_t refcount;
236 struct intel_vgpu *vgpu;
237
238 struct {
239 enum intel_gvt_gtt_type type;
240 bool pde_ips; /* for 64KB PTEs */
241 void *vaddr;
242 struct page *page;
243 unsigned long mfn;
244 } shadow_page;
245
246 struct {
247 enum intel_gvt_gtt_type type;
248 bool pde_ips; /* for 64KB PTEs */
249 unsigned long gfn;
250 unsigned long write_cnt;
251 struct intel_vgpu_oos_page *oos_page;
252 } guest_page;
253
254 DECLARE_BITMAP(post_shadow_bitmap, GTT_ENTRY_NUM_IN_ONE_PAGE);
255 struct list_head post_shadow_list;
256 };
257
258 int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu);
259
260 int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu);
261
262 int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm);
263
264 void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm);
265
266 unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm,
267 unsigned long gma);
268
269 struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu,
270 u64 pdps[]);
271
272 struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu,
273 enum intel_gvt_gtt_type root_entry_type, u64 pdps[]);
274
275 int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[]);
276
277 int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
278 unsigned int off, void *p_data, unsigned int bytes);
279
280 int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
281 unsigned int off, void *p_data, unsigned int bytes);
282
283 #endif /* _GVT_GTT_H_ */
284