xref: /dragonfly/sys/dev/sound/pci/hda/hdac.c (revision 030b0c8c)
1 /*-
2  * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
3  * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
4  * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 /*
30  * Intel High Definition Audio (Controller) driver for FreeBSD.
31  */
32 
33 #ifdef HAVE_KERNEL_OPTION_HEADERS
34 #include "opt_snd.h"
35 #endif
36 
37 #include <dev/sound/pcm/sound.h>
38 #include <bus/pci/pcireg.h>
39 #include <bus/pci/pcivar.h>
40 
41 #include <sys/ctype.h>
42 #include <sys/taskqueue.h>
43 
44 #include <dev/sound/pci/hda/hdac_private.h>
45 #include <dev/sound/pci/hda/hdac_reg.h>
46 #include <dev/sound/pci/hda/hda_reg.h>
47 #include <dev/sound/pci/hda/hdac.h>
48 
49 #define HDA_DRV_TEST_REV	"20120126_0002"
50 
51 SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 275101 2014-11-26 04:23:21Z mav $");
52 
53 #define hdac_lock(sc)		snd_mtxlock((sc)->lock)
54 #define hdac_unlock(sc)		snd_mtxunlock((sc)->lock)
55 #define hdac_lockassert(sc)	snd_mtxassert((sc)->lock)
56 #define hdac_lockowned(sc)	(lockstatus((sc)->lock, curthread) == LK_EXCLUSIVE)
57 
58 #define HDAC_QUIRK_64BIT	(1 << 0)
59 #define HDAC_QUIRK_DMAPOS	(1 << 1)
60 #define HDAC_QUIRK_MSI		(1 << 2)
61 
62 static const struct {
63 	const char *key;
64 	uint32_t value;
65 } hdac_quirks_tab[] = {
66 	{ "64bit", HDAC_QUIRK_DMAPOS },
67 	{ "dmapos", HDAC_QUIRK_DMAPOS },
68 	{ "msi", HDAC_QUIRK_MSI },
69 };
70 
71 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller");
72 
73 static const struct {
74 	uint32_t	model;
75 	const char	*desc;
76 	char		quirks_on;
77 	char		quirks_off;
78 } hdac_devices[] = {
79 	{ HDA_INTEL_OAK,     "Intel Oaktrail",	0, 0 },
80 	{ HDA_INTEL_BAY,     "Intel BayTrail",	0, 0 },
81 	{ HDA_INTEL_HSW1,    "Intel Haswell",	0, 0 },
82 	{ HDA_INTEL_HSW2,    "Intel Haswell",	0, 0 },
83 	{ HDA_INTEL_HSW3,    "Intel Haswell",	0, 0 },
84 	{ HDA_INTEL_BDW1,    "Intel Broadwell",	0, 0 },
85 	{ HDA_INTEL_CPT,     "Intel Cougar Point",	0, 0 },
86 	{ HDA_INTEL_PATSBURG,"Intel Patsburg",  0, 0 },
87 	{ HDA_INTEL_PPT1,    "Intel Panther Point",	0, 0 },
88 	{ HDA_INTEL_LPT1,    "Intel Lynx Point",	0, 0 },
89 	{ HDA_INTEL_LPT2,    "Intel Lynx Point",	0, 0 },
90 	{ HDA_INTEL_WCPT,    "Intel Wildcat Point",	0, 0 },
91 	{ HDA_INTEL_WELLS1,  "Intel Wellsburg",	0, 0 },
92 	{ HDA_INTEL_WELLS2,  "Intel Wellsburg",	0, 0 },
93 	{ HDA_INTEL_LPTLP1,  "Intel Lynx Point-LP",	0, 0 },
94 	{ HDA_INTEL_LPTLP2,  "Intel Lynx Point-LP",	0, 0 },
95 	{ HDA_INTEL_WCPTLP,  "Intel Wildcat Point-LP",	0, 0 },
96 	{ HDA_INTEL_SRPTLP,  "Intel Sunrise Point-LP",	0, 0 },
97 	{ HDA_INTEL_KBLKLP,  "Intel Kabylake-LP",	0, 0 },
98 	{ HDA_INTEL_SRPT,    "Intel Sunrise Point",	0, 0 },
99 	{ HDA_INTEL_KBLK,    "Intel Kabylake",	0, 0 },
100 	{ HDA_INTEL_82801F,  "Intel 82801F",	0, 0 },
101 	{ HDA_INTEL_63XXESB, "Intel 631x/632xESB",	0, 0 },
102 	{ HDA_INTEL_82801G,  "Intel 82801G",	0, 0 },
103 	{ HDA_INTEL_82801H,  "Intel 82801H",	0, 0 },
104 	{ HDA_INTEL_82801I,  "Intel 82801I",	0, 0 },
105 	{ HDA_INTEL_82801JI, "Intel 82801JI",	0, 0 },
106 	{ HDA_INTEL_82801JD, "Intel 82801JD",	0, 0 },
107 	{ HDA_INTEL_PCH,     "Intel 5 Series/3400 Series",	0, 0 },
108 	{ HDA_INTEL_PCH2,    "Intel 5 Series/3400 Series",	0, 0 },
109 	{ HDA_INTEL_SCH,     "Intel SCH",	0, 0 },
110 	{ HDA_NVIDIA_MCP51,  "NVIDIA MCP51",	0, HDAC_QUIRK_MSI },
111 	{ HDA_NVIDIA_MCP55,  "NVIDIA MCP55",	0, HDAC_QUIRK_MSI },
112 	{ HDA_NVIDIA_MCP61_1, "NVIDIA MCP61",	0, 0 },
113 	{ HDA_NVIDIA_MCP61_2, "NVIDIA MCP61",	0, 0 },
114 	{ HDA_NVIDIA_MCP65_1, "NVIDIA MCP65",	0, 0 },
115 	{ HDA_NVIDIA_MCP65_2, "NVIDIA MCP65",	0, 0 },
116 	{ HDA_NVIDIA_MCP67_1, "NVIDIA MCP67",	0, 0 },
117 	{ HDA_NVIDIA_MCP67_2, "NVIDIA MCP67",	0, 0 },
118 	{ HDA_NVIDIA_MCP73_1, "NVIDIA MCP73",	0, 0 },
119 	{ HDA_NVIDIA_MCP73_2, "NVIDIA MCP73",	0, 0 },
120 	{ HDA_NVIDIA_MCP78_1, "NVIDIA MCP78",	0, HDAC_QUIRK_64BIT },
121 	{ HDA_NVIDIA_MCP78_2, "NVIDIA MCP78",	0, HDAC_QUIRK_64BIT },
122 	{ HDA_NVIDIA_MCP78_3, "NVIDIA MCP78",	0, HDAC_QUIRK_64BIT },
123 	{ HDA_NVIDIA_MCP78_4, "NVIDIA MCP78",	0, HDAC_QUIRK_64BIT },
124 	{ HDA_NVIDIA_MCP79_1, "NVIDIA MCP79",	0, 0 },
125 	{ HDA_NVIDIA_MCP79_2, "NVIDIA MCP79",	0, 0 },
126 	{ HDA_NVIDIA_MCP79_3, "NVIDIA MCP79",	0, 0 },
127 	{ HDA_NVIDIA_MCP79_4, "NVIDIA MCP79",	0, 0 },
128 	{ HDA_NVIDIA_MCP89_1, "NVIDIA MCP89",	0, 0 },
129 	{ HDA_NVIDIA_MCP89_2, "NVIDIA MCP89",	0, 0 },
130 	{ HDA_NVIDIA_MCP89_3, "NVIDIA MCP89",	0, 0 },
131 	{ HDA_NVIDIA_MCP89_4, "NVIDIA MCP89",	0, 0 },
132 	{ HDA_NVIDIA_0BE2,   "NVIDIA (0x0be2)",	0, HDAC_QUIRK_MSI },
133 	{ HDA_NVIDIA_0BE3,   "NVIDIA (0x0be3)",	0, HDAC_QUIRK_MSI },
134 	{ HDA_NVIDIA_0BE4,   "NVIDIA (0x0be4)",	0, HDAC_QUIRK_MSI },
135 	{ HDA_NVIDIA_GT100,  "NVIDIA GT100",	0, HDAC_QUIRK_MSI },
136 	{ HDA_NVIDIA_GT104,  "NVIDIA GT104",	0, HDAC_QUIRK_MSI },
137 	{ HDA_NVIDIA_GT106,  "NVIDIA GT106",	0, HDAC_QUIRK_MSI },
138 	{ HDA_NVIDIA_GT108,  "NVIDIA GT108",	0, HDAC_QUIRK_MSI },
139 	{ HDA_NVIDIA_GT116,  "NVIDIA GT116",	0, HDAC_QUIRK_MSI },
140 	{ HDA_NVIDIA_GF119,  "NVIDIA GF119",	0, 0 },
141 	{ HDA_NVIDIA_GF110_1, "NVIDIA GF110",	0, HDAC_QUIRK_MSI },
142 	{ HDA_NVIDIA_GF110_2, "NVIDIA GF110",	0, HDAC_QUIRK_MSI },
143 	{ HDA_ATI_SB450,     "ATI SB450",	0, 0 },
144 	{ HDA_ATI_SB600,     "ATI SB600",	0, 0 },
145 	{ HDA_ATI_RS600,     "ATI RS600",	0, 0 },
146 	{ HDA_ATI_RS690,     "ATI RS690",	0, 0 },
147 	{ HDA_ATI_RS780,     "ATI RS780",	0, 0 },
148 	{ HDA_ATI_R600,      "ATI R600",	0, 0 },
149 	{ HDA_ATI_RV610,     "ATI RV610",	0, 0 },
150 	{ HDA_ATI_RV620,     "ATI RV620",	0, 0 },
151 	{ HDA_ATI_RV630,     "ATI RV630",	0, 0 },
152 	{ HDA_ATI_RV635,     "ATI RV635",	0, 0 },
153 	{ HDA_ATI_RV710,     "ATI RV710",	0, 0 },
154 	{ HDA_ATI_RV730,     "ATI RV730",	0, 0 },
155 	{ HDA_ATI_RV740,     "ATI RV740",	0, 0 },
156 	{ HDA_ATI_RV770,     "ATI RV770",	0, 0 },
157 	{ HDA_ATI_RV810,     "ATI RV810",	0, 0 },
158 	{ HDA_ATI_RV830,     "ATI RV830",	0, 0 },
159 	{ HDA_ATI_RV840,     "ATI RV840",	0, 0 },
160 	{ HDA_ATI_RV870,     "ATI RV870",	0, 0 },
161 	{ HDA_ATI_RV910,     "ATI RV910",	0, 0 },
162 	{ HDA_ATI_RV930,     "ATI RV930",	0, 0 },
163 	{ HDA_ATI_RV940,     "ATI RV940",	0, 0 },
164 	{ HDA_ATI_RV970,     "ATI RV970",	0, 0 },
165 	{ HDA_ATI_R1000,     "ATI R1000",	0, 0 },
166 	{ HDA_AMD_HUDSON2,   "AMD Hudson-2",	0, 0 },
167 	{ HDA_RDC_M3010,     "RDC M3010",	0, 0 },
168 	{ HDA_VIA_VT82XX,    "VIA VT8251/8237A",0, 0 },
169 	{ HDA_SIS_966,       "SiS 966",		0, 0 },
170 	{ HDA_ULI_M5461,     "ULI M5461",	0, 0 },
171 	/* Unknown */
172 	{ HDA_INTEL_ALL,  "Intel",		0, 0 },
173 	{ HDA_NVIDIA_ALL, "NVIDIA",		0, 0 },
174 	{ HDA_ATI_ALL,    "ATI",		0, 0 },
175 	{ HDA_AMD_ALL,    "AMD",		0, 0 },
176 	{ HDA_VIA_ALL,    "VIA",		0, 0 },
177 	{ HDA_SIS_ALL,    "SiS",		0, 0 },
178 	{ HDA_ULI_ALL,    "ULI",		0, 0 },
179 };
180 
181 #if 0 /* unused */
182 static const struct {
183 	uint16_t vendor;
184 	uint8_t reg;
185 	uint8_t mask;
186 	uint8_t enable;
187 } hdac_pcie_snoop[] = {
188 	{  INTEL_VENDORID, 0x00, 0x00, 0x00 },
189 	{    ATI_VENDORID, 0x42, 0xf8, 0x02 },
190 	{ NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
191 };
192 #endif
193 
194 TASKQUEUE_DEFINE_THREAD(hdac);
195 
196 /****************************************************************************
197  * Function prototypes
198  ****************************************************************************/
199 static void	hdac_intr_handler(void *);
200 static int	hdac_reset(struct hdac_softc *, int);
201 static int	hdac_get_capabilities(struct hdac_softc *);
202 static void	hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
203 static int	hdac_dma_alloc(struct hdac_softc *,
204 					struct hdac_dma *, bus_size_t);
205 static void	hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
206 static int	hdac_mem_alloc(struct hdac_softc *);
207 static void	hdac_mem_free(struct hdac_softc *);
208 static int	hdac_irq_alloc(struct hdac_softc *);
209 static void	hdac_irq_free(struct hdac_softc *);
210 static void	hdac_corb_init(struct hdac_softc *);
211 static void	hdac_rirb_init(struct hdac_softc *);
212 static void	hdac_corb_start(struct hdac_softc *);
213 static void	hdac_rirb_start(struct hdac_softc *);
214 
215 static void	hdac_attach2(void *);
216 
217 static uint32_t	hdac_send_command(struct hdac_softc *, nid_t, uint32_t);
218 
219 static int	hdac_probe(device_t);
220 static int	hdac_attach(device_t);
221 static int	hdac_detach(device_t);
222 static int	hdac_suspend(device_t);
223 static int	hdac_resume(device_t);
224 
225 static int	hdac_rirb_flush(struct hdac_softc *sc);
226 static int	hdac_unsolq_flush(struct hdac_softc *sc);
227 
228 #define hdac_command(a1, a2, a3)	\
229 		hdac_send_command(a1, a3, a2)
230 
231 /* This function surely going to make its way into upper level someday. */
232 static void
hdac_config_fetch(struct hdac_softc * sc,uint32_t * on,uint32_t * off)233 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
234 {
235 	const char *res = NULL;
236 	int i = 0, j, k, len, inv;
237 
238 	if (resource_string_value(device_get_name(sc->dev),
239 	    device_get_unit(sc->dev), "config", &res) != 0)
240 		return;
241 	if (!(res != NULL && strlen(res) > 0))
242 		return;
243 	HDA_BOOTVERBOSE(
244 		device_printf(sc->dev, "Config options:");
245 	);
246 	for (;;) {
247 		while (res[i] != '\0' &&
248 		    (res[i] == ',' || isspace(res[i]) != 0))
249 			i++;
250 		if (res[i] == '\0') {
251 			HDA_BOOTVERBOSE(
252 				kprintf("\n");
253 			);
254 			return;
255 		}
256 		j = i;
257 		while (res[j] != '\0' &&
258 		    !(res[j] == ',' || isspace(res[j]) != 0))
259 			j++;
260 		len = j - i;
261 		if (len > 2 && strncmp(res + i, "no", 2) == 0)
262 			inv = 2;
263 		else
264 			inv = 0;
265 		for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) {
266 			if (strncmp(res + i + inv,
267 			    hdac_quirks_tab[k].key, len - inv) != 0)
268 				continue;
269 			if (len - inv != strlen(hdac_quirks_tab[k].key))
270 				continue;
271 			HDA_BOOTVERBOSE(
272 				kprintf(" %s%s", (inv != 0) ? "no" : "",
273 				    hdac_quirks_tab[k].key);
274 			);
275 			if (inv == 0) {
276 				*on |= hdac_quirks_tab[k].value;
277 				*on &= ~hdac_quirks_tab[k].value;
278 			} else if (inv != 0) {
279 				*off |= hdac_quirks_tab[k].value;
280 				*off &= ~hdac_quirks_tab[k].value;
281 			}
282 			break;
283 		}
284 		i = j;
285 	}
286 }
287 
288 /****************************************************************************
289  * void hdac_intr_handler(void *)
290  *
291  * Interrupt handler. Processes interrupts received from the hdac.
292  ****************************************************************************/
293 static void
hdac_intr_handler(void * context)294 hdac_intr_handler(void *context)
295 {
296 	struct hdac_softc *sc;
297 	device_t dev;
298 	uint32_t intsts;
299 	uint8_t rirbsts;
300 	int i;
301 
302 	sc = (struct hdac_softc *)context;
303 	hdac_lock(sc);
304 
305 	/* Do we have anything to do? */
306 	intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
307 	if ((intsts & HDAC_INTSTS_GIS) == 0) {
308 		hdac_unlock(sc);
309 		return;
310 	}
311 
312 	/* Was this a controller interrupt? */
313 	if (intsts & HDAC_INTSTS_CIS) {
314 		rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
315 		/* Get as many responses that we can */
316 		while (rirbsts & HDAC_RIRBSTS_RINTFL) {
317 			HDAC_WRITE_1(&sc->mem,
318 			    HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
319 			hdac_rirb_flush(sc);
320 			rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
321 		}
322 		if (sc->unsolq_rp != sc->unsolq_wp)
323 			taskqueue_enqueue(taskqueue_hdac, &sc->unsolq_task);
324 	}
325 
326 	if (intsts & HDAC_INTSTS_SIS_MASK) {
327 		for (i = 0; i < sc->num_ss; i++) {
328 			if ((intsts & (1 << i)) == 0)
329 				continue;
330 			HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS,
331 			    HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
332 			if ((dev = sc->streams[i].dev) != NULL) {
333 				HDAC_STREAM_INTR(dev,
334 				    sc->streams[i].dir, sc->streams[i].stream);
335 			}
336 		}
337 	}
338 
339 	HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts);
340 	hdac_unlock(sc);
341 }
342 
343 static void
hdac_poll_callback(void * arg)344 hdac_poll_callback(void *arg)
345 {
346 	struct hdac_softc *sc = arg;
347 
348 	if (sc == NULL)
349 		return;
350 
351 	hdac_lock(sc);
352 	if (sc->polling == 0) {
353 		hdac_unlock(sc);
354 		return;
355 	}
356 	callout_reset(&sc->poll_callout, sc->poll_ival,
357 	    hdac_poll_callback, sc);
358 	hdac_unlock(sc);
359 
360 	hdac_intr_handler(sc);
361 }
362 
363 /****************************************************************************
364  * int hdac_reset(hdac_softc *, int)
365  *
366  * Reset the hdac to a quiescent and known state.
367  ****************************************************************************/
368 static int
hdac_reset(struct hdac_softc * sc,int wakeup)369 hdac_reset(struct hdac_softc *sc, int wakeup)
370 {
371 	uint32_t gctl;
372 	uint32_t wee;
373 	int count, i;
374 
375 	/*
376 	 * Stop all Streams DMA engine
377 	 */
378 	for (i = 0; i < sc->num_iss; i++)
379 		HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
380 	for (i = 0; i < sc->num_oss; i++)
381 		HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
382 	for (i = 0; i < sc->num_bss; i++)
383 		HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
384 
385 	/*
386 	 * Stop Control DMA engines.
387 	 */
388 	HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
389 	HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
390 
391 	/*
392 	 * Reset DMA position buffer.
393 	 */
394 	HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
395 	HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
396 
397 	/*
398 	 * Reset the controller. The reset must remain asserted for
399 	 * a minimum of 100us.
400 	 */
401 	gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
402 	HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
403 	count = 10000;
404 	do {
405 		gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
406 		if (!(gctl & HDAC_GCTL_CRST))
407 			break;
408 		DELAY(10);
409 	} while	(--count);
410 	if (gctl & HDAC_GCTL_CRST) {
411 		device_printf(sc->dev, "Unable to put hdac in reset\n");
412 		return (ENXIO);
413 	}
414 
415 	/* If wakeup is not requested - leave the controller in reset state. */
416 	if (!wakeup)
417 		return (0);
418 
419 	DELAY(100);
420 	gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
421 	HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
422 	count = 10000;
423 	do {
424 		gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
425 		if (gctl & HDAC_GCTL_CRST)
426 			break;
427 		DELAY(10);
428 	} while (--count);
429 	if (!(gctl & HDAC_GCTL_CRST)) {
430 		device_printf(sc->dev, "Device stuck in reset\n");
431 		return (ENXIO);
432 	}
433 
434 	/*
435 	 * Wait for codecs to finish their own reset sequence. The delay here
436 	 * should be of 250us but for some reasons, on it's not enough on my
437 	 * computer. Let's use twice as much as necessary to make sure that
438 	 * it's reset properly.
439 	 */
440 	DELAY(1000);
441 
442 	/*
443 	 * BIOS May have left some wake bits enabled / pending, which can
444 	 *	force a continuous interrupt.  Make sure it is turned off.
445 	 */
446 	wee = HDAC_READ_2(&sc->mem, HDAC_WAKEEN);
447 	HDAC_WRITE_2(&sc->mem, HDAC_WAKEEN, wee & ~HDAC_WAKEEN_SDIWEN_MASK);
448 	/*HDAC_WRITE_2(&sc->mem, HDAC_STATESTS, HDAC_STATESTS_SDIWAKE_MASK);*/
449 
450 	return (0);
451 }
452 
453 
454 /****************************************************************************
455  * int hdac_get_capabilities(struct hdac_softc *);
456  *
457  * Retreive the general capabilities of the hdac;
458  *	Number of Input Streams
459  *	Number of Output Streams
460  *	Number of bidirectional Streams
461  *	64bit ready
462  *	CORB and RIRB sizes
463  ****************************************************************************/
464 static int
hdac_get_capabilities(struct hdac_softc * sc)465 hdac_get_capabilities(struct hdac_softc *sc)
466 {
467 	uint16_t gcap;
468 	uint8_t corbsize, rirbsize;
469 
470 	gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
471 	sc->num_iss = HDAC_GCAP_ISS(gcap);
472 	sc->num_oss = HDAC_GCAP_OSS(gcap);
473 	sc->num_bss = HDAC_GCAP_BSS(gcap);
474 	sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss;
475 	sc->num_sdo = HDAC_GCAP_NSDO(gcap);
476 	sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0;
477 	if (sc->quirks_on & HDAC_QUIRK_64BIT)
478 		sc->support_64bit = 1;
479 	else if (sc->quirks_off & HDAC_QUIRK_64BIT)
480 		sc->support_64bit = 0;
481 
482 	corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
483 	if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
484 	    HDAC_CORBSIZE_CORBSZCAP_256)
485 		sc->corb_size = 256;
486 	else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
487 	    HDAC_CORBSIZE_CORBSZCAP_16)
488 		sc->corb_size = 16;
489 	else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
490 	    HDAC_CORBSIZE_CORBSZCAP_2)
491 		sc->corb_size = 2;
492 	else {
493 		device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
494 		    __func__, corbsize);
495 		if (1) {
496 			device_printf(sc->dev, "Resetting corb size to 256\n");
497 			sc->corb_size = 256;
498 			corbsize =
499 			    HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
500 			HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
501 		}
502 		else
503 			return (ENXIO);
504 	}
505 
506 	rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
507 	if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
508 	    HDAC_RIRBSIZE_RIRBSZCAP_256)
509 		sc->rirb_size = 256;
510 	else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
511 	    HDAC_RIRBSIZE_RIRBSZCAP_16)
512 		sc->rirb_size = 16;
513 	else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
514 	    HDAC_RIRBSIZE_RIRBSZCAP_2)
515 		sc->rirb_size = 2;
516 	else {
517 		device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
518 		    __func__, rirbsize);
519 		if (1) {
520 			device_printf(sc->dev, "Resetting rirb size to 256\n");
521 			sc->rirb_size = 256;
522 			rirbsize =
523 			    HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
524 			HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
525 		}
526 		else
527 			return (ENXIO);
528 	}
529 
530 	HDA_BOOTVERBOSE(
531 		device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, "
532 		    "NSDO %d%s, CORB %d, RIRB %d\n",
533 		    sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo,
534 		    sc->support_64bit ? ", 64bit" : "",
535 		    sc->corb_size, sc->rirb_size);
536 	);
537 
538 	return (0);
539 }
540 
541 
542 /****************************************************************************
543  * void hdac_dma_cb
544  *
545  * This function is called by bus_dmamap_load when the mapping has been
546  * established. We just record the physical address of the mapping into
547  * the struct hdac_dma passed in.
548  ****************************************************************************/
549 static void
hdac_dma_cb(void * callback_arg,bus_dma_segment_t * segs,int nseg,int error)550 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
551 {
552 	struct hdac_dma *dma;
553 
554 	if (error == 0) {
555 		dma = (struct hdac_dma *)callback_arg;
556 		dma->dma_paddr = segs[0].ds_addr;
557 	}
558 }
559 
560 
561 /****************************************************************************
562  * int hdac_dma_alloc
563  *
564  * This function allocate and setup a dma region (struct hdac_dma).
565  * It must be freed by a corresponding hdac_dma_free.
566  ****************************************************************************/
567 static int
hdac_dma_alloc(struct hdac_softc * sc,struct hdac_dma * dma,bus_size_t size)568 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
569 {
570 	bus_size_t alignment, roundsz;
571 	int result;
572 
573 	if (sc->flags & HDAC_F_DMA_NOCACHE)
574 		alignment = roundup2(HDA_DMA_ALIGNMENT, PAGE_SIZE);
575 	else
576 		alignment = HDA_DMA_ALIGNMENT;
577 
578 	roundsz = roundup2(size, alignment);
579 	bzero(dma, sizeof(*dma));
580 
581 	/*
582 	 * Create a DMA tag
583 	 */
584 	result = bus_dma_tag_create(
585 	    bus_get_dma_tag(sc->dev),		/* parent */
586 	    alignment,				/* alignment */
587 	    0,					/* boundary */
588 	    (sc->support_64bit) ? BUS_SPACE_MAXADDR :
589 		BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
590 	    BUS_SPACE_MAXADDR,			/* highaddr */
591 	    roundsz, 				/* maxsize */
592 	    1,					/* nsegments */
593 	    roundsz, 				/* maxsegsz */
594 	    0,					/* flags */
595 	    &dma->dma_tag);			/* dmat */
596 	if (result != 0) {
597 		device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
598 		    __func__, result);
599 		goto hdac_dma_alloc_fail;
600 	}
601 
602 	/*
603 	 * Allocate DMA memory
604 	 */
605 	result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
606 	    BUS_DMA_NOWAIT | BUS_DMA_ZERO |
607 	    ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
608 	    &dma->dma_map);
609 	if (result != 0) {
610 		device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
611 		    __func__, result);
612 		goto hdac_dma_alloc_fail;
613 	}
614 
615 	dma->dma_size = roundsz;
616 
617 	/*
618 	 * Map the memory
619 	 */
620 	result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
621 	    (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
622 	if (result != 0 || dma->dma_paddr == 0) {
623 		if (result == 0)
624 			result = ENOMEM;
625 		device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
626 		    __func__, result);
627 		goto hdac_dma_alloc_fail;
628 	}
629 
630 	HDA_BOOTHVERBOSE(
631 		device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
632 		    __func__, (uintmax_t)size, (uintmax_t)roundsz);
633 	);
634 
635 	return (0);
636 
637 hdac_dma_alloc_fail:
638 	hdac_dma_free(sc, dma);
639 
640 	return (result);
641 }
642 
643 
644 /****************************************************************************
645  * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
646  *
647  * Free a struct dhac_dma that has been previously allocated via the
648  * hdac_dma_alloc function.
649  ****************************************************************************/
650 static void
hdac_dma_free(struct hdac_softc * sc,struct hdac_dma * dma)651 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
652 {
653 	if (dma->dma_paddr != 0) {
654 #if 0
655 		/* Flush caches */
656 		bus_dmamap_sync(dma->dma_tag, dma->dma_map,
657 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
658 #endif
659 		bus_dmamap_unload(dma->dma_tag, dma->dma_map);
660 		dma->dma_paddr = 0;
661 	}
662 	if (dma->dma_vaddr != NULL) {
663 		bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
664 		dma->dma_vaddr = NULL;
665 	}
666 	if (dma->dma_tag != NULL) {
667 		bus_dma_tag_destroy(dma->dma_tag);
668 		dma->dma_tag = NULL;
669 	}
670 	dma->dma_size = 0;
671 }
672 
673 /****************************************************************************
674  * int hdac_mem_alloc(struct hdac_softc *)
675  *
676  * Allocate all the bus resources necessary to speak with the physical
677  * controller.
678  ****************************************************************************/
679 static int
hdac_mem_alloc(struct hdac_softc * sc)680 hdac_mem_alloc(struct hdac_softc *sc)
681 {
682 	struct hdac_mem *mem;
683 
684 	mem = &sc->mem;
685 	mem->mem_rid = PCIR_BAR(0);
686 	mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
687 	    &mem->mem_rid, RF_ACTIVE);
688 	if (mem->mem_res == NULL) {
689 		device_printf(sc->dev,
690 		    "%s: Unable to allocate memory resource\n", __func__);
691 		return (ENOMEM);
692 	}
693 	mem->mem_tag = rman_get_bustag(mem->mem_res);
694 	mem->mem_handle = rman_get_bushandle(mem->mem_res);
695 
696 	return (0);
697 }
698 
699 /****************************************************************************
700  * void hdac_mem_free(struct hdac_softc *)
701  *
702  * Free up resources previously allocated by hdac_mem_alloc.
703  ****************************************************************************/
704 static void
hdac_mem_free(struct hdac_softc * sc)705 hdac_mem_free(struct hdac_softc *sc)
706 {
707 	struct hdac_mem *mem;
708 
709 	mem = &sc->mem;
710 	if (mem->mem_res != NULL)
711 		bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
712 		    mem->mem_res);
713 	mem->mem_res = NULL;
714 }
715 
716 /****************************************************************************
717  * int hdac_irq_alloc(struct hdac_softc *)
718  *
719  * Allocate and setup the resources necessary for interrupt handling.
720  ****************************************************************************/
721 static int
hdac_irq_alloc(struct hdac_softc * sc)722 hdac_irq_alloc(struct hdac_softc *sc)
723 {
724 	struct hdac_irq *irq;
725 	int result;
726 
727 	irq = &sc->irq;
728 	irq->irq_rid = 0x0;
729 
730 	if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 &&
731 	    (result = pci_msi_count(sc->dev)) == 1 &&
732 	    pci_alloc_msi(sc->dev, &result, 1, -1) == 0)
733 		irq->irq_rid = 0x1;
734 
735 	irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
736 	    &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
737 	if (irq->irq_res == NULL) {
738 		device_printf(sc->dev, "%s: Unable to allocate irq\n",
739 		    __func__);
740 		goto hdac_irq_alloc_fail;
741 	}
742 	result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE,
743 	    hdac_intr_handler, sc, &irq->irq_handle, NULL);
744 	if (result != 0) {
745 		device_printf(sc->dev,
746 		    "%s: Unable to setup interrupt handler (%x)\n",
747 		    __func__, result);
748 		goto hdac_irq_alloc_fail;
749 	}
750 
751 	return (0);
752 
753 hdac_irq_alloc_fail:
754 	hdac_irq_free(sc);
755 
756 	return (ENXIO);
757 }
758 
759 /****************************************************************************
760  * void hdac_irq_free(struct hdac_softc *)
761  *
762  * Free up resources previously allocated by hdac_irq_alloc.
763  ****************************************************************************/
764 static void
hdac_irq_free(struct hdac_softc * sc)765 hdac_irq_free(struct hdac_softc *sc)
766 {
767 	struct hdac_irq *irq;
768 
769 	irq = &sc->irq;
770 	if (irq->irq_res != NULL && irq->irq_handle != NULL)
771 		bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
772 	if (irq->irq_res != NULL)
773 		bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
774 		    irq->irq_res);
775 	if (irq->irq_rid == 0x1)
776 		pci_release_msi(sc->dev);
777 	irq->irq_handle = NULL;
778 	irq->irq_res = NULL;
779 	irq->irq_rid = 0x0;
780 }
781 
782 /****************************************************************************
783  * void hdac_corb_init(struct hdac_softc *)
784  *
785  * Initialize the corb registers for operations but do not start it up yet.
786  * The CORB engine must not be running when this function is called.
787  ****************************************************************************/
788 static void
hdac_corb_init(struct hdac_softc * sc)789 hdac_corb_init(struct hdac_softc *sc)
790 {
791 	uint8_t corbsize;
792 	uint64_t corbpaddr;
793 
794 	/* Setup the CORB size. */
795 	switch (sc->corb_size) {
796 	case 256:
797 		corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
798 		break;
799 	case 16:
800 		corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
801 		break;
802 	case 2:
803 		corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
804 		break;
805 	default:
806 		panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
807 	}
808 	HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
809 
810 	/* Setup the CORB Address in the hdac */
811 	corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
812 	HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
813 	HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
814 
815 	/* Set the WP and RP */
816 	sc->corb_wp = 0;
817 	HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
818 	HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
819 	/*
820 	 * The HDA specification indicates that the CORBRPRST bit will always
821 	 * read as zero. Unfortunately, it seems that at least the 82801G
822 	 * doesn't reset the bit to zero, which stalls the corb engine.
823 	 * manually reset the bit to zero before continuing.
824 	 */
825 	HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
826 
827 	/* Enable CORB error reporting */
828 #if 0
829 	HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
830 #endif
831 }
832 
833 /****************************************************************************
834  * void hdac_rirb_init(struct hdac_softc *)
835  *
836  * Initialize the rirb registers for operations but do not start it up yet.
837  * The RIRB engine must not be running when this function is called.
838  ****************************************************************************/
839 static void
hdac_rirb_init(struct hdac_softc * sc)840 hdac_rirb_init(struct hdac_softc *sc)
841 {
842 	uint8_t rirbsize;
843 	uint64_t rirbpaddr;
844 
845 	/* Setup the RIRB size. */
846 	switch (sc->rirb_size) {
847 	case 256:
848 		rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
849 		break;
850 	case 16:
851 		rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
852 		break;
853 	case 2:
854 		rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
855 		break;
856 	default:
857 		panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
858 	}
859 	HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
860 
861 	/* Setup the RIRB Address in the hdac */
862 	rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
863 	HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
864 	HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
865 
866 	/* Setup the WP and RP */
867 	sc->rirb_rp = 0;
868 	HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
869 
870 	/* Setup the interrupt threshold */
871 	HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
872 
873 	/* Enable Overrun and response received reporting */
874 #if 0
875 	HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
876 	    HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
877 #else
878 	HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
879 #endif
880 
881 #if 0
882 	/*
883 	 * Make sure that the Host CPU cache doesn't contain any dirty
884 	 * cache lines that falls in the rirb. If I understood correctly, it
885 	 * should be sufficient to do this only once as the rirb is purely
886 	 * read-only from now on.
887 	 */
888 	bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
889 	    BUS_DMASYNC_PREREAD);
890 #endif
891 }
892 
893 /****************************************************************************
894  * void hdac_corb_start(hdac_softc *)
895  *
896  * Startup the corb DMA engine
897  ****************************************************************************/
898 static void
hdac_corb_start(struct hdac_softc * sc)899 hdac_corb_start(struct hdac_softc *sc)
900 {
901 	uint32_t corbctl;
902 
903 	corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
904 	corbctl |= HDAC_CORBCTL_CORBRUN;
905 	HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
906 }
907 
908 /****************************************************************************
909  * void hdac_rirb_start(hdac_softc *)
910  *
911  * Startup the rirb DMA engine
912  ****************************************************************************/
913 static void
hdac_rirb_start(struct hdac_softc * sc)914 hdac_rirb_start(struct hdac_softc *sc)
915 {
916 	uint32_t rirbctl;
917 
918 	rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
919 	rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
920 	HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
921 }
922 
923 static int
hdac_rirb_flush(struct hdac_softc * sc)924 hdac_rirb_flush(struct hdac_softc *sc)
925 {
926 	struct hdac_rirb *rirb_base, *rirb;
927 	nid_t cad;
928 	uint32_t resp;
929 	uint8_t rirbwp;
930 	int ret;
931 
932 	rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
933 	rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
934 #if 0
935 	bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
936 	    BUS_DMASYNC_POSTREAD);
937 #endif
938 
939 	ret = 0;
940 	while (sc->rirb_rp != rirbwp) {
941 		sc->rirb_rp++;
942 		sc->rirb_rp %= sc->rirb_size;
943 		rirb = &rirb_base[sc->rirb_rp];
944 		cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
945 		resp = rirb->response;
946 		if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
947 			sc->unsolq[sc->unsolq_wp++] = resp;
948 			sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
949 			sc->unsolq[sc->unsolq_wp++] = cad;
950 			sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
951 		} else if (sc->codecs[cad].pending <= 0) {
952 			device_printf(sc->dev, "Unexpected unsolicited "
953 			    "response from address %d: %08x\n", cad, resp);
954 		} else {
955 			sc->codecs[cad].response = resp;
956 			sc->codecs[cad].pending--;
957 		}
958 		ret++;
959 	}
960 	return (ret);
961 }
962 
963 static int
hdac_unsolq_flush(struct hdac_softc * sc)964 hdac_unsolq_flush(struct hdac_softc *sc)
965 {
966 	device_t child;
967 	nid_t cad;
968 	uint32_t resp;
969 	int ret = 0;
970 
971 	if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
972 		sc->unsolq_st = HDAC_UNSOLQ_BUSY;
973 		while (sc->unsolq_rp != sc->unsolq_wp) {
974 			resp = sc->unsolq[sc->unsolq_rp++];
975 			sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
976 			cad = sc->unsolq[sc->unsolq_rp++];
977 			sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
978 			if ((child = sc->codecs[cad].dev) != NULL)
979 				HDAC_UNSOL_INTR(child, resp);
980 			ret++;
981 		}
982 		sc->unsolq_st = HDAC_UNSOLQ_READY;
983 	}
984 
985 	return (ret);
986 }
987 
988 /****************************************************************************
989  * uint32_t hdac_command_sendone_internal
990  *
991  * Wrapper function that sends only one command to a given codec
992  ****************************************************************************/
993 static uint32_t
hdac_send_command(struct hdac_softc * sc,nid_t cad,uint32_t verb)994 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb)
995 {
996 	int timeout;
997 	uint32_t *corb;
998 
999 	if (!hdac_lockowned(sc))
1000 		device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
1001 	verb &= ~HDA_CMD_CAD_MASK;
1002 	verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT;
1003 	sc->codecs[cad].response = HDA_INVALID;
1004 
1005 	sc->codecs[cad].pending++;
1006 	sc->corb_wp++;
1007 	sc->corb_wp %= sc->corb_size;
1008 	corb = (uint32_t *)sc->corb_dma.dma_vaddr;
1009 #if 0
1010 	bus_dmamap_sync(sc->corb_dma.dma_tag,
1011 	    sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
1012 #endif
1013 	corb[sc->corb_wp] = verb;
1014 #if 0
1015 	bus_dmamap_sync(sc->corb_dma.dma_tag,
1016 	    sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
1017 #endif
1018 	HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
1019 
1020 	timeout = 10000;
1021 	do {
1022 		if (hdac_rirb_flush(sc) == 0)
1023 			DELAY(10);
1024 	} while (sc->codecs[cad].pending != 0 && --timeout);
1025 
1026 	if (sc->codecs[cad].pending != 0) {
1027 		device_printf(sc->dev, "Command timeout on address %d\n", cad);
1028 		sc->codecs[cad].pending = 0;
1029 	}
1030 
1031 	if (sc->unsolq_rp != sc->unsolq_wp)
1032 		taskqueue_enqueue(taskqueue_hdac, &sc->unsolq_task);
1033 	return (sc->codecs[cad].response);
1034 }
1035 
1036 /****************************************************************************
1037  * Device Methods
1038  ****************************************************************************/
1039 
1040 /****************************************************************************
1041  * int hdac_probe(device_t)
1042  *
1043  * Probe for the presence of an hdac. If none is found, check for a generic
1044  * match using the subclass of the device.
1045  ****************************************************************************/
1046 static int
hdac_probe(device_t dev)1047 hdac_probe(device_t dev)
1048 {
1049 	int i, result;
1050 	uint32_t model;
1051 	uint16_t class, subclass;
1052 	char desc[64];
1053 
1054 	model = (uint32_t)pci_get_device(dev) << 16;
1055 	model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1056 	class = pci_get_class(dev);
1057 	subclass = pci_get_subclass(dev);
1058 
1059 	bzero(desc, sizeof(desc));
1060 	result = ENXIO;
1061 	for (i = 0; i < nitems(hdac_devices); i++) {
1062 		if (hdac_devices[i].model == model) {
1063 			strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
1064 			result = BUS_PROBE_DEFAULT;
1065 			break;
1066 		}
1067 		if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1068 		    class == PCIC_MULTIMEDIA &&
1069 		    subclass == PCIS_MULTIMEDIA_HDA) {
1070 			ksnprintf(desc, sizeof(desc),
1071 			    "%s (0x%04x)",
1072 			    hdac_devices[i].desc, pci_get_device(dev));
1073 			result = BUS_PROBE_GENERIC;
1074 			break;
1075 		}
1076 	}
1077 	if (result == ENXIO && class == PCIC_MULTIMEDIA &&
1078 	    subclass == PCIS_MULTIMEDIA_HDA) {
1079 		ksnprintf(desc, sizeof(desc), "Generic (0x%08x)", model);
1080 		result = BUS_PROBE_GENERIC;
1081 	}
1082 	if (result != ENXIO) {
1083 		strlcat(desc, " HDA Controller", sizeof(desc));
1084 		device_set_desc_copy(dev, desc);
1085 	}
1086 
1087 	return (result);
1088 }
1089 
1090 static void
hdac_unsolq_task(void * context,int pending)1091 hdac_unsolq_task(void *context, int pending)
1092 {
1093 	struct hdac_softc *sc;
1094 
1095 	sc = (struct hdac_softc *)context;
1096 
1097 	hdac_lock(sc);
1098 	hdac_unsolq_flush(sc);
1099 	hdac_unlock(sc);
1100 }
1101 
1102 /****************************************************************************
1103  * int hdac_attach(device_t)
1104  *
1105  * Attach the device into the kernel. Interrupts usually won't be enabled
1106  * when this function is called. Setup everything that doesn't require
1107  * interrupts and defer probing of codecs until interrupts are enabled.
1108  ****************************************************************************/
1109 static int
hdac_attach(device_t dev)1110 hdac_attach(device_t dev)
1111 {
1112 	struct hdac_softc *sc;
1113 	int result;
1114 	int i, devid = -1;
1115 	uint32_t model;
1116 	uint16_t class, subclass;
1117 	uint16_t vendor;
1118 	uint8_t v;
1119 
1120 	sc = device_get_softc(dev);
1121 	HDA_BOOTVERBOSE(
1122 		device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n",
1123 		    pci_get_subvendor(dev), pci_get_subdevice(dev));
1124 		device_printf(dev, "HDA Driver Revision: %s\n",
1125 		    HDA_DRV_TEST_REV);
1126 	);
1127 
1128 	model = (uint32_t)pci_get_device(dev) << 16;
1129 	model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1130 	class = pci_get_class(dev);
1131 	subclass = pci_get_subclass(dev);
1132 
1133 	for (i = 0; i < nitems(hdac_devices); i++) {
1134 		if (hdac_devices[i].model == model) {
1135 			devid = i;
1136 			break;
1137 		}
1138 		if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1139 		    class == PCIC_MULTIMEDIA &&
1140 		    subclass == PCIS_MULTIMEDIA_HDA) {
1141 			devid = i;
1142 			break;
1143 		}
1144 	}
1145 
1146 	sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex");
1147 	sc->dev = dev;
1148 	TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
1149 	callout_init_mp(&sc->poll_callout);
1150 	for (i = 0; i < HDAC_CODEC_MAX; i++)
1151 		sc->codecs[i].dev = NULL;
1152 	if (devid >= 0) {
1153 		sc->quirks_on = hdac_devices[devid].quirks_on;
1154 		sc->quirks_off = hdac_devices[devid].quirks_off;
1155 	} else {
1156 		sc->quirks_on = 0;
1157 		sc->quirks_off = 0;
1158 	}
1159 	hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off);
1160 	if (resource_int_value(device_get_name(dev),
1161 			       device_get_unit(dev), "msi", &i) == 0) {
1162 		if (i == 0) {
1163 			sc->quirks_on &= ~HDAC_QUIRK_MSI;
1164 			sc->quirks_off |= HDAC_QUIRK_MSI;
1165 		} else {
1166 			sc->quirks_on |= HDAC_QUIRK_MSI;
1167 			sc->quirks_off &= ~HDAC_QUIRK_MSI;
1168 		}
1169 	}
1170 	HDA_BOOTVERBOSE(
1171 		device_printf(sc->dev,
1172 		    "Config options: on=0x%08x off=0x%08x\n",
1173 		    sc->quirks_on, sc->quirks_off);
1174 	);
1175 	sc->poll_ival = hz;
1176 	if (resource_int_value(device_get_name(dev),
1177 	    device_get_unit(dev), "polling", &i) == 0 && i != 0)
1178 		sc->polling = 1;
1179 	else
1180 		sc->polling = 0;
1181 
1182 	pci_enable_busmaster(dev);
1183 
1184 	vendor = pci_get_vendor(dev);
1185 	if (vendor == INTEL_VENDORID) {
1186 		/* TCSEL -> TC0 */
1187 		v = pci_read_config(dev, 0x44, 1);
1188 		pci_write_config(dev, 0x44, v & 0xf8, 1);
1189 		HDA_BOOTHVERBOSE(
1190 			device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
1191 			    pci_read_config(dev, 0x44, 1));
1192 		);
1193 	}
1194 
1195 	sc->flags |= HDAC_F_DMA_NOCACHE;
1196 	/*
1197 	 * Try to enable PCIe snoop to avoid messing around with
1198 	 * uncacheable DMA attribute.
1199 	 */
1200 	if (pci_is_pcie(dev)) {
1201 		int pcie_cap = pci_get_pciecap_ptr(dev);
1202 		uint16_t dev_ctl;
1203 
1204 		dev_ctl = pci_read_config(dev,
1205 		    pcie_cap + PCIER_DEVCTRL, 2);
1206 		device_printf(dev, "link ctrl %#x\n", dev_ctl);
1207 
1208 		if (dev_ctl & PCIEM_DEVCTL_NOSNOOP) {
1209 			dev_ctl &= ~PCIEM_DEVCTL_NOSNOOP;
1210 			pci_write_config(dev,
1211 			    pcie_cap + PCIER_DEVCTRL, dev_ctl, 2);
1212 
1213 			device_printf(dev, "disable nosnoop\n");
1214 		}
1215 		sc->flags &= ~HDAC_F_DMA_NOCACHE;
1216 	}
1217 
1218 	HDA_BOOTHVERBOSE(
1219 		device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
1220 		    (sc->flags & HDAC_F_DMA_NOCACHE) ?
1221 		    "Uncacheable" : "PCIe snoop", vendor);
1222 	);
1223 
1224 	/* Allocate resources */
1225 	result = hdac_mem_alloc(sc);
1226 	if (result != 0)
1227 		goto hdac_attach_fail;
1228 	result = hdac_irq_alloc(sc);
1229 	if (result != 0)
1230 		goto hdac_attach_fail;
1231 
1232 	hdac_reset(sc, 1);
1233 
1234 	/* Get Capabilities */
1235 	result = hdac_get_capabilities(sc);
1236 	if (result != 0)
1237 		goto hdac_attach_fail;
1238 
1239 	/* Allocate CORB, RIRB, POS and BDLs dma memory */
1240 	result = hdac_dma_alloc(sc, &sc->corb_dma,
1241 	    sc->corb_size * sizeof(uint32_t));
1242 	if (result != 0)
1243 		goto hdac_attach_fail;
1244 	result = hdac_dma_alloc(sc, &sc->rirb_dma,
1245 	    sc->rirb_size * sizeof(struct hdac_rirb));
1246 	if (result != 0)
1247 		goto hdac_attach_fail;
1248 	sc->streams = kmalloc(sizeof(struct hdac_stream) * sc->num_ss,
1249 	    M_HDAC, M_ZERO | M_WAITOK);
1250 	for (i = 0; i < sc->num_ss; i++) {
1251 		result = hdac_dma_alloc(sc, &sc->streams[i].bdl,
1252 		    sizeof(struct hdac_bdle) * HDA_BDL_MAX);
1253 		if (result != 0)
1254 			goto hdac_attach_fail;
1255 	}
1256 	if (sc->quirks_on & HDAC_QUIRK_DMAPOS) {
1257 		if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) {
1258 			HDA_BOOTVERBOSE(
1259 				device_printf(dev, "Failed to "
1260 				    "allocate DMA pos buffer "
1261 				    "(non-fatal)\n");
1262 			);
1263 		} else {
1264 			uint64_t addr = sc->pos_dma.dma_paddr;
1265 
1266 			HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32);
1267 			HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
1268 			    (addr & HDAC_DPLBASE_DPLBASE_MASK) |
1269 			    HDAC_DPLBASE_DPLBASE_DMAPBE);
1270 		}
1271 	}
1272 
1273 	result = bus_dma_tag_create(
1274 	    bus_get_dma_tag(sc->dev),		/* parent */
1275 	    HDA_DMA_ALIGNMENT,			/* alignment */
1276 	    0,					/* boundary */
1277 	    (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1278 		BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
1279 	    BUS_SPACE_MAXADDR,			/* highaddr */
1280 	    HDA_BUFSZ_MAX, 			/* maxsize */
1281 	    1,					/* nsegments */
1282 	    HDA_BUFSZ_MAX, 			/* maxsegsz */
1283 	    0,					/* flags */
1284 	    &sc->chan_dmat);			/* dmat */
1285 	if (result != 0) {
1286 		device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
1287 		     __func__, result);
1288 		goto hdac_attach_fail;
1289 	}
1290 
1291 	/* Quiesce everything */
1292 	HDA_BOOTHVERBOSE(
1293 		device_printf(dev, "Reset controller...\n");
1294 	);
1295 	hdac_reset(sc, 1);
1296 
1297 	/* Initialize the CORB and RIRB */
1298 	hdac_corb_init(sc);
1299 	hdac_rirb_init(sc);
1300 
1301 	/* Defer remaining of initialization until interrupts are enabled */
1302 	sc->intrhook.ich_func = hdac_attach2;
1303 	sc->intrhook.ich_arg = (void *)sc;
1304 	sc->intrhook.ich_desc = "snd_hda";
1305 	if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
1306 		sc->intrhook.ich_func = NULL;
1307 		hdac_attach2((void *)sc);
1308 	}
1309 
1310 	return (0);
1311 
1312 hdac_attach_fail:
1313 	hdac_irq_free(sc);
1314 	for (i = 0; i < sc->num_ss; i++)
1315 		hdac_dma_free(sc, &sc->streams[i].bdl);
1316 	if (sc->streams != NULL)
1317 		kfree(sc->streams, M_HDAC);
1318 	hdac_dma_free(sc, &sc->rirb_dma);
1319 	hdac_dma_free(sc, &sc->corb_dma);
1320 	hdac_mem_free(sc);
1321 	snd_mtxfree(sc->lock);
1322 
1323 	return (ENXIO);
1324 }
1325 
1326 static int
sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)1327 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
1328 {
1329 	struct hdac_softc *sc;
1330 	device_t *devlist;
1331 	device_t dev;
1332 	int devcount, i, err, val;
1333 
1334 	dev = oidp->oid_arg1;
1335 	sc = device_get_softc(dev);
1336 	if (sc == NULL)
1337 		return (EINVAL);
1338 	val = 0;
1339 	err = sysctl_handle_int(oidp, &val, 0, req);
1340 	if (err != 0 || req->newptr == NULL || val == 0)
1341 		return (err);
1342 
1343 	/* XXX: Temporary. For debugging. */
1344 	if (val == 100) {
1345 		hdac_suspend(dev);
1346 		return (0);
1347 	} else if (val == 101) {
1348 		hdac_resume(dev);
1349 		return (0);
1350 	}
1351 
1352 	if ((err = device_get_children(dev, &devlist, &devcount)) != 0)
1353 		return (err);
1354 	hdac_lock(sc);
1355 	for (i = 0; i < devcount; i++)
1356 		HDAC_PINDUMP(devlist[i]);
1357 	hdac_unlock(sc);
1358 	kfree(devlist, M_TEMP);
1359 	return (0);
1360 }
1361 
1362 static int
hdac_mdata_rate(uint16_t fmt)1363 hdac_mdata_rate(uint16_t fmt)
1364 {
1365 	static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 };
1366 	int rate, bits;
1367 
1368 	if (fmt & (1 << 14))
1369 		rate = 44100;
1370 	else
1371 		rate = 48000;
1372 	rate *= ((fmt >> 11) & 0x07) + 1;
1373 	rate /= ((fmt >> 8) & 0x07) + 1;
1374 	bits = mbits[(fmt >> 4) & 0x03];
1375 	bits *= (fmt & 0x0f) + 1;
1376 	return (rate * bits);
1377 }
1378 
1379 static int
hdac_bdata_rate(uint16_t fmt,int output)1380 hdac_bdata_rate(uint16_t fmt, int output)
1381 {
1382 	static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 };
1383 	int rate, bits;
1384 
1385 	rate = 48000;
1386 	rate *= ((fmt >> 11) & 0x07) + 1;
1387 	bits = bbits[(fmt >> 4) & 0x03];
1388 	bits *= (fmt & 0x0f) + 1;
1389 	if (!output)
1390 		bits = ((bits + 7) & ~0x07) + 10;
1391 	return (rate * bits);
1392 }
1393 
1394 static void
hdac_poll_reinit(struct hdac_softc * sc)1395 hdac_poll_reinit(struct hdac_softc *sc)
1396 {
1397 	int i, pollticks, min = 1000000;
1398 	struct hdac_stream *s;
1399 
1400 	if (sc->polling == 0)
1401 		return;
1402 	if (sc->unsol_registered > 0)
1403 		min = hz / 2;
1404 	for (i = 0; i < sc->num_ss; i++) {
1405 		s = &sc->streams[i];
1406 		if (s->running == 0)
1407 			continue;
1408 		pollticks = ((uint64_t)hz * s->blksz) /
1409 		    (hdac_mdata_rate(s->format) / 8);
1410 		pollticks >>= 1;
1411 		if (pollticks > hz)
1412 			pollticks = hz;
1413 		if (pollticks < 1) {
1414 			HDA_BOOTVERBOSE(
1415 				device_printf(sc->dev,
1416 				    "poll interval < 1 tick !\n");
1417 			);
1418 			pollticks = 1;
1419 		}
1420 		if (min > pollticks)
1421 			min = pollticks;
1422 	}
1423 	HDA_BOOTVERBOSE(
1424 		device_printf(sc->dev,
1425 		    "poll interval %d -> %d ticks\n",
1426 		    sc->poll_ival, min);
1427 	);
1428 	sc->poll_ival = min;
1429 	if (min == 1000000)
1430 		callout_stop(&sc->poll_callout);
1431 	else
1432 		callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc);
1433 }
1434 
1435 static int
sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)1436 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
1437 {
1438 	struct hdac_softc *sc;
1439 	device_t dev;
1440 	uint32_t ctl;
1441 	int err, val;
1442 
1443 	dev = oidp->oid_arg1;
1444 	sc = device_get_softc(dev);
1445 	if (sc == NULL)
1446 		return (EINVAL);
1447 	hdac_lock(sc);
1448 	val = sc->polling;
1449 	hdac_unlock(sc);
1450 	err = sysctl_handle_int(oidp, &val, 0, req);
1451 
1452 	if (err != 0 || req->newptr == NULL)
1453 		return (err);
1454 	if (val < 0 || val > 1)
1455 		return (EINVAL);
1456 
1457 	hdac_lock(sc);
1458 	if (val != sc->polling) {
1459 		if (val == 0) {
1460 			callout_stop(&sc->poll_callout);
1461 			hdac_unlock(sc);
1462 			callout_drain(&sc->poll_callout);
1463 			hdac_lock(sc);
1464 			sc->polling = 0;
1465 			ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1466 			ctl |= HDAC_INTCTL_GIE;
1467 			HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1468 		} else {
1469 			ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1470 			ctl &= ~HDAC_INTCTL_GIE;
1471 			HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1472 			sc->polling = 1;
1473 			hdac_poll_reinit(sc);
1474 		}
1475 	}
1476 	hdac_unlock(sc);
1477 
1478 	return (err);
1479 }
1480 
1481 static void
hdac_attach2(void * arg)1482 hdac_attach2(void *arg)
1483 {
1484 	struct hdac_softc *sc;
1485 	device_t child;
1486 	uint32_t vendorid, revisionid;
1487 	int i;
1488 	uint16_t statests;
1489 
1490 	sc = (struct hdac_softc *)arg;
1491 
1492 	hdac_lock(sc);
1493 
1494 	/* Remove ourselves from the config hooks */
1495 	if (sc->intrhook.ich_func != NULL) {
1496 		config_intrhook_disestablish(&sc->intrhook);
1497 		sc->intrhook.ich_func = NULL;
1498 	}
1499 
1500 	HDA_BOOTHVERBOSE(
1501 		device_printf(sc->dev, "Starting CORB Engine...\n");
1502 	);
1503 	hdac_corb_start(sc);
1504 	HDA_BOOTHVERBOSE(
1505 		device_printf(sc->dev, "Starting RIRB Engine...\n");
1506 	);
1507 	hdac_rirb_start(sc);
1508 	HDA_BOOTHVERBOSE(
1509 		device_printf(sc->dev,
1510 		    "Enabling controller interrupt...\n");
1511 	);
1512 	HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1513 	    HDAC_GCTL_UNSOL);
1514 	if (sc->polling == 0) {
1515 		HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
1516 		    HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1517 	}
1518 	DELAY(1000);
1519 
1520 	HDA_BOOTHVERBOSE(
1521 		device_printf(sc->dev, "Scanning HDA codecs ...\n");
1522 	);
1523 	statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1524 	hdac_unlock(sc);
1525 	for (i = 0; i < HDAC_CODEC_MAX; i++) {
1526 		if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1527 			HDA_BOOTHVERBOSE(
1528 				device_printf(sc->dev,
1529 				    "Found CODEC at address %d\n", i);
1530 			);
1531 			hdac_lock(sc);
1532 			vendorid = hdac_send_command(sc, i,
1533 			    HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID));
1534 			revisionid = hdac_send_command(sc, i,
1535 			    HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID));
1536 			hdac_unlock(sc);
1537 			if (vendorid == HDA_INVALID &&
1538 			    revisionid == HDA_INVALID) {
1539 				device_printf(sc->dev,
1540 				    "CODEC is not responding!\n");
1541 				continue;
1542 			}
1543 			sc->codecs[i].vendor_id =
1544 			    HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1545 			sc->codecs[i].device_id =
1546 			    HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1547 			sc->codecs[i].revision_id =
1548 			    HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1549 			sc->codecs[i].stepping_id =
1550 			    HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1551 			child = device_add_child(sc->dev, "hdacc", -1);
1552 			if (child == NULL) {
1553 				device_printf(sc->dev,
1554 				    "Failed to add CODEC device\n");
1555 				continue;
1556 			}
1557 			device_set_ivars(child, (void *)(intptr_t)i);
1558 			sc->codecs[i].dev = child;
1559 		}
1560 	}
1561 	bus_generic_attach(sc->dev);
1562 
1563 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1564 	    SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1565 	    "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1566 	    sysctl_hdac_pindump, "I", "Dump pin states/data");
1567 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1568 	    SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1569 	    "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1570 	    sysctl_hdac_polling, "I", "Enable polling mode");
1571 }
1572 
1573 /****************************************************************************
1574  * int hdac_suspend(device_t)
1575  *
1576  * Suspend and power down HDA bus and codecs.
1577  ****************************************************************************/
1578 static int
hdac_suspend(device_t dev)1579 hdac_suspend(device_t dev)
1580 {
1581 	struct hdac_softc *sc = device_get_softc(dev);
1582 
1583 	HDA_BOOTHVERBOSE(
1584 		device_printf(dev, "Suspend...\n");
1585 	);
1586 	bus_generic_suspend(dev);
1587 
1588 	hdac_lock(sc);
1589 	HDA_BOOTHVERBOSE(
1590 		device_printf(dev, "Reset controller...\n");
1591 	);
1592 	callout_stop(&sc->poll_callout);
1593 	hdac_reset(sc, 0);
1594 	hdac_unlock(sc);
1595 	callout_drain(&sc->poll_callout);
1596 	taskqueue_drain(taskqueue_hdac, &sc->unsolq_task);
1597 	HDA_BOOTHVERBOSE(
1598 		device_printf(dev, "Suspend done\n");
1599 	);
1600 	return (0);
1601 }
1602 
1603 /****************************************************************************
1604  * int hdac_resume(device_t)
1605  *
1606  * Powerup and restore HDA bus and codecs state.
1607  ****************************************************************************/
1608 static int
hdac_resume(device_t dev)1609 hdac_resume(device_t dev)
1610 {
1611 	struct hdac_softc *sc = device_get_softc(dev);
1612 	int error;
1613 
1614 	HDA_BOOTHVERBOSE(
1615 		device_printf(dev, "Resume...\n");
1616 	);
1617 	hdac_lock(sc);
1618 
1619 	/* Quiesce everything */
1620 	HDA_BOOTHVERBOSE(
1621 		device_printf(dev, "Reset controller...\n");
1622 	);
1623 	hdac_reset(sc, 1);
1624 
1625 	/* Initialize the CORB and RIRB */
1626 	hdac_corb_init(sc);
1627 	hdac_rirb_init(sc);
1628 
1629 	HDA_BOOTHVERBOSE(
1630 		device_printf(dev, "Starting CORB Engine...\n");
1631 	);
1632 	hdac_corb_start(sc);
1633 	HDA_BOOTHVERBOSE(
1634 		device_printf(dev, "Starting RIRB Engine...\n");
1635 	);
1636 	hdac_rirb_start(sc);
1637 	HDA_BOOTHVERBOSE(
1638 		device_printf(dev, "Enabling controller interrupt...\n");
1639 	);
1640 	HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1641 	    HDAC_GCTL_UNSOL);
1642 	HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1643 	DELAY(1000);
1644 	hdac_poll_reinit(sc);
1645 	hdac_unlock(sc);
1646 
1647 	error = bus_generic_resume(dev);
1648 	HDA_BOOTHVERBOSE(
1649 		device_printf(dev, "Resume done\n");
1650 	);
1651 	return (error);
1652 }
1653 
1654 /****************************************************************************
1655  * int hdac_detach(device_t)
1656  *
1657  * Detach and free up resources utilized by the hdac device.
1658  ****************************************************************************/
1659 static int
hdac_detach(device_t dev)1660 hdac_detach(device_t dev)
1661 {
1662 	struct hdac_softc *sc = device_get_softc(dev);
1663 	device_t *devlist;
1664 	int cad, i, devcount, error;
1665 
1666 	if ((error = device_get_children(dev, &devlist, &devcount)) != 0)
1667 		return (error);
1668 	for (i = 0; i < devcount; i++) {
1669 		cad = (intptr_t)device_get_ivars(devlist[i]);
1670 		if ((error = device_delete_child(dev, devlist[i])) != 0) {
1671 			kfree(devlist, M_TEMP);
1672 			return (error);
1673 		}
1674 		sc->codecs[cad].dev = NULL;
1675 	}
1676 	kfree(devlist, M_TEMP);
1677 
1678 	hdac_lock(sc);
1679 	hdac_reset(sc, 0);
1680 	hdac_unlock(sc);
1681 	taskqueue_drain(taskqueue_hdac, &sc->unsolq_task);
1682 	hdac_irq_free(sc);
1683 
1684 	/* give pending interrupts stuck on the lock a chance to clear */
1685 	/* bad hack */
1686 	tsleep(&sc->irq, 0, "hdaslp", hz / 10);
1687 
1688 	for (i = 0; i < sc->num_ss; i++)
1689 		hdac_dma_free(sc, &sc->streams[i].bdl);
1690 	kfree(sc->streams, M_HDAC);
1691 	hdac_dma_free(sc, &sc->pos_dma);
1692 	hdac_dma_free(sc, &sc->rirb_dma);
1693 	hdac_dma_free(sc, &sc->corb_dma);
1694 	if (sc->chan_dmat != NULL) {
1695 		bus_dma_tag_destroy(sc->chan_dmat);
1696 		sc->chan_dmat = NULL;
1697 	}
1698 	hdac_mem_free(sc);
1699 	snd_mtxfree(sc->lock);
1700 	return (0);
1701 }
1702 
1703 static bus_dma_tag_t
hdac_get_dma_tag(device_t dev,device_t child)1704 hdac_get_dma_tag(device_t dev, device_t child)
1705 {
1706 	struct hdac_softc *sc = device_get_softc(dev);
1707 
1708 	return (sc->chan_dmat);
1709 }
1710 
1711 static int
hdac_print_child(device_t dev,device_t child)1712 hdac_print_child(device_t dev, device_t child)
1713 {
1714 	int retval;
1715 
1716 	retval = bus_print_child_header(dev, child);
1717 	retval += kprintf(" at cad %d",
1718 	    (int)(intptr_t)device_get_ivars(child));
1719 	retval += bus_print_child_footer(dev, child);
1720 
1721 	return (retval);
1722 }
1723 
1724 static int
hdac_child_location_str(device_t dev,device_t child,char * buf,size_t buflen)1725 hdac_child_location_str(device_t dev, device_t child, char *buf,
1726     size_t buflen)
1727 {
1728 
1729 	ksnprintf(buf, buflen, "cad=%d",
1730 	    (int)(intptr_t)device_get_ivars(child));
1731 	return (0);
1732 }
1733 
1734 static int
hdac_child_pnpinfo_str_method(device_t dev,device_t child,char * buf,size_t buflen)1735 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
1736     size_t buflen)
1737 {
1738 	struct hdac_softc *sc = device_get_softc(dev);
1739 	nid_t cad = (uintptr_t)device_get_ivars(child);
1740 
1741 	ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x "
1742 	    "stepping=0x%02x",
1743 	    sc->codecs[cad].vendor_id, sc->codecs[cad].device_id,
1744 	    sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id);
1745 	return (0);
1746 }
1747 
1748 static int
hdac_read_ivar(device_t dev,device_t child,int which,uintptr_t * result)1749 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1750 {
1751 	struct hdac_softc *sc = device_get_softc(dev);
1752 	nid_t cad = (uintptr_t)device_get_ivars(child);
1753 
1754 	switch (which) {
1755 	case HDA_IVAR_CODEC_ID:
1756 		*result = cad;
1757 		break;
1758 	case HDA_IVAR_VENDOR_ID:
1759 		*result = sc->codecs[cad].vendor_id;
1760 		break;
1761 	case HDA_IVAR_DEVICE_ID:
1762 		*result = sc->codecs[cad].device_id;
1763 		break;
1764 	case HDA_IVAR_REVISION_ID:
1765 		*result = sc->codecs[cad].revision_id;
1766 		break;
1767 	case HDA_IVAR_STEPPING_ID:
1768 		*result = sc->codecs[cad].stepping_id;
1769 		break;
1770 	case HDA_IVAR_SUBVENDOR_ID:
1771 		*result = pci_get_subvendor(dev);
1772 		break;
1773 	case HDA_IVAR_SUBDEVICE_ID:
1774 		*result = pci_get_subdevice(dev);
1775 		break;
1776 	case HDA_IVAR_DMA_NOCACHE:
1777 		*result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0;
1778 		break;
1779 	default:
1780 		return (ENOENT);
1781 	}
1782 	return (0);
1783 }
1784 
1785 static struct lock *
hdac_get_mtx(device_t dev,device_t child)1786 hdac_get_mtx(device_t dev, device_t child)
1787 {
1788 	struct hdac_softc *sc = device_get_softc(dev);
1789 
1790 	return (sc->lock);
1791 }
1792 
1793 static uint32_t
hdac_codec_command(device_t dev,device_t child,uint32_t verb)1794 hdac_codec_command(device_t dev, device_t child, uint32_t verb)
1795 {
1796 
1797 	return (hdac_send_command(device_get_softc(dev),
1798 	    (intptr_t)device_get_ivars(child), verb));
1799 }
1800 
1801 static int
hdac_find_stream(struct hdac_softc * sc,int dir,int stream)1802 hdac_find_stream(struct hdac_softc *sc, int dir, int stream)
1803 {
1804 	int i, ss;
1805 
1806 	ss = -1;
1807 	/* Allocate ISS/BSS first. */
1808 	if (dir == 0) {
1809 		for (i = 0; i < sc->num_iss; i++) {
1810 			if (sc->streams[i].stream == stream) {
1811 				ss = i;
1812 				break;
1813 			}
1814 		}
1815 	} else {
1816 		for (i = 0; i < sc->num_oss; i++) {
1817 			if (sc->streams[i + sc->num_iss].stream == stream) {
1818 				ss = i + sc->num_iss;
1819 				break;
1820 			}
1821 		}
1822 	}
1823 	/* Fallback to BSS. */
1824 	if (ss == -1) {
1825 		for (i = 0; i < sc->num_bss; i++) {
1826 			if (sc->streams[i + sc->num_iss + sc->num_oss].stream
1827 			    == stream) {
1828 				ss = i + sc->num_iss + sc->num_oss;
1829 				break;
1830 			}
1831 		}
1832 	}
1833 	return (ss);
1834 }
1835 
1836 static int
hdac_stream_alloc(device_t dev,device_t child,int dir,int format,int stripe,uint32_t ** dmapos)1837 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe,
1838     uint32_t **dmapos)
1839 {
1840 	struct hdac_softc *sc = device_get_softc(dev);
1841 	nid_t cad = (uintptr_t)device_get_ivars(child);
1842 	int stream, ss, bw, maxbw, prevbw;
1843 
1844 	/* Look for empty stream. */
1845 	ss = hdac_find_stream(sc, dir, 0);
1846 
1847 	/* Return if found nothing. */
1848 	if (ss < 0)
1849 		return (0);
1850 
1851 	/* Check bus bandwidth. */
1852 	bw = hdac_bdata_rate(format, dir);
1853 	if (dir == 1) {
1854 		bw *= 1 << (sc->num_sdo - stripe);
1855 		prevbw = sc->sdo_bw_used;
1856 		maxbw = 48000 * 960 * (1 << sc->num_sdo);
1857 	} else {
1858 		prevbw = sc->codecs[cad].sdi_bw_used;
1859 		maxbw = 48000 * 464;
1860 	}
1861 	HDA_BOOTHVERBOSE(
1862 		device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n",
1863 		    (bw + prevbw) / 1000, maxbw / 1000,
1864 		    bw + prevbw > maxbw ? " -- OVERFLOW!" : "");
1865 	);
1866 	if (bw + prevbw > maxbw)
1867 		return (0);
1868 	if (dir == 1)
1869 		sc->sdo_bw_used += bw;
1870 	else
1871 		sc->codecs[cad].sdi_bw_used += bw;
1872 
1873 	/* Allocate stream number */
1874 	if (ss >= sc->num_iss + sc->num_oss)
1875 		stream = 15 - (ss - sc->num_iss + sc->num_oss);
1876 	else if (ss >= sc->num_iss)
1877 		stream = ss - sc->num_iss + 1;
1878 	else
1879 		stream = ss + 1;
1880 
1881 	sc->streams[ss].dev = child;
1882 	sc->streams[ss].dir = dir;
1883 	sc->streams[ss].stream = stream;
1884 	sc->streams[ss].bw = bw;
1885 	sc->streams[ss].format = format;
1886 	sc->streams[ss].stripe = stripe;
1887 	if (dmapos != NULL) {
1888 		if (sc->pos_dma.dma_vaddr != NULL)
1889 			*dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8);
1890 		else
1891 			*dmapos = NULL;
1892 	}
1893 	return (stream);
1894 }
1895 
1896 static void
hdac_stream_free(device_t dev,device_t child,int dir,int stream)1897 hdac_stream_free(device_t dev, device_t child, int dir, int stream)
1898 {
1899 	struct hdac_softc *sc = device_get_softc(dev);
1900 	nid_t cad = (uintptr_t)device_get_ivars(child);
1901 	int ss;
1902 
1903 	ss = hdac_find_stream(sc, dir, stream);
1904 	KASSERT(ss >= 0,
1905 	    ("Free for not allocated stream (%d/%d)\n", dir, stream));
1906 	if (dir == 1)
1907 		sc->sdo_bw_used -= sc->streams[ss].bw;
1908 	else
1909 		sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw;
1910 	sc->streams[ss].stream = 0;
1911 	sc->streams[ss].dev = NULL;
1912 }
1913 
1914 static int
hdac_stream_start(device_t dev,device_t child,int dir,int stream,bus_addr_t buf,int blksz,int blkcnt)1915 hdac_stream_start(device_t dev, device_t child,
1916     int dir, int stream, bus_addr_t buf, int blksz, int blkcnt)
1917 {
1918 	struct hdac_softc *sc = device_get_softc(dev);
1919 	struct hdac_bdle *bdle;
1920 	uint64_t addr;
1921 	int i, ss, off;
1922 	uint32_t ctl;
1923 
1924 	ss = hdac_find_stream(sc, dir, stream);
1925 	KASSERT(ss >= 0,
1926 	    ("Start for not allocated stream (%d/%d)\n", dir, stream));
1927 
1928 	addr = (uint64_t)buf;
1929 	bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr;
1930 	for (i = 0; i < blkcnt; i++, bdle++) {
1931 		bdle->addrl = (uint32_t)addr;
1932 		bdle->addrh = (uint32_t)(addr >> 32);
1933 		bdle->len = blksz;
1934 		bdle->ioc = 1;
1935 		addr += blksz;
1936 	}
1937 
1938 	off = ss << 5;
1939 	HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt);
1940 	HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1);
1941 	addr = sc->streams[ss].bdl.dma_paddr;
1942 	HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr);
1943 	HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
1944 
1945 	ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2);
1946 	if (dir)
1947 		ctl |= HDAC_SDCTL2_DIR;
1948 	else
1949 		ctl &= ~HDAC_SDCTL2_DIR;
1950 	ctl &= ~HDAC_SDCTL2_STRM_MASK;
1951 	ctl |= stream << HDAC_SDCTL2_STRM_SHIFT;
1952 	ctl &= ~HDAC_SDCTL2_STRIPE_MASK;
1953 	ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT;
1954 	HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl);
1955 
1956 	HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format);
1957 
1958 	ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1959 	ctl |= 1 << ss;
1960 	HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1961 
1962 	HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS,
1963 	    HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS);
1964 	ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1965 	ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1966 	    HDAC_SDCTL_RUN;
1967 	HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1968 
1969 	sc->streams[ss].blksz = blksz;
1970 	sc->streams[ss].running = 1;
1971 	hdac_poll_reinit(sc);
1972 	return (0);
1973 }
1974 
1975 static void
hdac_stream_stop(device_t dev,device_t child,int dir,int stream)1976 hdac_stream_stop(device_t dev, device_t child, int dir, int stream)
1977 {
1978 	struct hdac_softc *sc = device_get_softc(dev);
1979 	int ss, off;
1980 	uint32_t ctl;
1981 
1982 	ss = hdac_find_stream(sc, dir, stream);
1983 	KASSERT(ss >= 0,
1984 	    ("Stop for not allocated stream (%d/%d)\n", dir, stream));
1985 
1986 	off = ss << 5;
1987 	ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1988 	ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1989 	    HDAC_SDCTL_RUN);
1990 	HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1991 
1992 	ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1993 	ctl &= ~(1 << ss);
1994 	HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1995 
1996 	sc->streams[ss].running = 0;
1997 	hdac_poll_reinit(sc);
1998 }
1999 
2000 static void
hdac_stream_reset(device_t dev,device_t child,int dir,int stream)2001 hdac_stream_reset(device_t dev, device_t child, int dir, int stream)
2002 {
2003 	struct hdac_softc *sc = device_get_softc(dev);
2004 	int timeout = 1000;
2005 	int to = timeout;
2006 	int ss, off;
2007 	uint32_t ctl;
2008 
2009 	ss = hdac_find_stream(sc, dir, stream);
2010 	KASSERT(ss >= 0,
2011 	    ("Reset for not allocated stream (%d/%d)\n", dir, stream));
2012 
2013 	off = ss << 5;
2014 	ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2015 	ctl |= HDAC_SDCTL_SRST;
2016 	HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2017 	do {
2018 		ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2019 		if (ctl & HDAC_SDCTL_SRST)
2020 			break;
2021 		DELAY(10);
2022 	} while (--to);
2023 	if (!(ctl & HDAC_SDCTL_SRST))
2024 		device_printf(dev, "Reset setting timeout\n");
2025 	ctl &= ~HDAC_SDCTL_SRST;
2026 	HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2027 	to = timeout;
2028 	do {
2029 		ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2030 		if (!(ctl & HDAC_SDCTL_SRST))
2031 			break;
2032 		DELAY(10);
2033 	} while (--to);
2034 	if (ctl & HDAC_SDCTL_SRST)
2035 		device_printf(dev, "Reset timeout!\n");
2036 }
2037 
2038 static uint32_t
hdac_stream_getptr(device_t dev,device_t child,int dir,int stream)2039 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream)
2040 {
2041 	struct hdac_softc *sc = device_get_softc(dev);
2042 	int ss, off;
2043 
2044 	ss = hdac_find_stream(sc, dir, stream);
2045 	KASSERT(ss >= 0,
2046 	    ("Reset for not allocated stream (%d/%d)\n", dir, stream));
2047 
2048 	off = ss << 5;
2049 	return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB));
2050 }
2051 
2052 static int
hdac_unsol_alloc(device_t dev,device_t child,int tag)2053 hdac_unsol_alloc(device_t dev, device_t child, int tag)
2054 {
2055 	struct hdac_softc *sc = device_get_softc(dev);
2056 
2057 	sc->unsol_registered++;
2058 	hdac_poll_reinit(sc);
2059 	return (tag);
2060 }
2061 
2062 static void
hdac_unsol_free(device_t dev,device_t child,int tag)2063 hdac_unsol_free(device_t dev, device_t child, int tag)
2064 {
2065 	struct hdac_softc *sc = device_get_softc(dev);
2066 
2067 	sc->unsol_registered--;
2068 	hdac_poll_reinit(sc);
2069 }
2070 
2071 static device_method_t hdac_methods[] = {
2072 	/* device interface */
2073 	DEVMETHOD(device_probe,		hdac_probe),
2074 	DEVMETHOD(device_attach,	hdac_attach),
2075 	DEVMETHOD(device_detach,	hdac_detach),
2076 	DEVMETHOD(device_suspend,	hdac_suspend),
2077 	DEVMETHOD(device_resume,	hdac_resume),
2078 	/* Bus interface */
2079 	DEVMETHOD(bus_get_dma_tag,	hdac_get_dma_tag),
2080 	DEVMETHOD(bus_print_child,	hdac_print_child),
2081 	DEVMETHOD(bus_child_location_str, hdac_child_location_str),
2082 	DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method),
2083 	DEVMETHOD(bus_read_ivar,	hdac_read_ivar),
2084 	DEVMETHOD(hdac_get_mtx,		hdac_get_mtx),
2085 	DEVMETHOD(hdac_codec_command,	hdac_codec_command),
2086 	DEVMETHOD(hdac_stream_alloc,	hdac_stream_alloc),
2087 	DEVMETHOD(hdac_stream_free,	hdac_stream_free),
2088 	DEVMETHOD(hdac_stream_start,	hdac_stream_start),
2089 	DEVMETHOD(hdac_stream_stop,	hdac_stream_stop),
2090 	DEVMETHOD(hdac_stream_reset,	hdac_stream_reset),
2091 	DEVMETHOD(hdac_stream_getptr,	hdac_stream_getptr),
2092 	DEVMETHOD(hdac_unsol_alloc,	hdac_unsol_alloc),
2093 	DEVMETHOD(hdac_unsol_free,	hdac_unsol_free),
2094 	DEVMETHOD_END
2095 };
2096 
2097 static driver_t hdac_driver = {
2098 	"hdac",
2099 	hdac_methods,
2100 	sizeof(struct hdac_softc),
2101 };
2102 
2103 static devclass_t hdac_devclass;
2104 
2105 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL);
2106