1 // SPDX-License-Identifier: GPL-2.0
2
3 /*
4 * Copyright 2016-2022 HabanaLabs, Ltd.
5 * All Rights Reserved.
6 */
7
8 #include <linux/slab.h>
9
10 #include "../habanalabs.h"
11
12 #include <trace/events/habanalabs.h>
13
14 /**
15 * hl_mmu_get_funcs() - get MMU functions structure
16 * @hdev: habanalabs device structure.
17 * @pgt_residency: page table residency.
18 * @is_dram_addr: true if we need HMMU functions
19 *
20 * @return appropriate MMU functions structure
21 */
hl_mmu_get_funcs(struct hl_device * hdev,int pgt_residency,bool is_dram_addr)22 static struct hl_mmu_funcs *hl_mmu_get_funcs(struct hl_device *hdev, int pgt_residency,
23 bool is_dram_addr)
24 {
25 return &hdev->mmu_func[pgt_residency];
26 }
27
hl_is_dram_va(struct hl_device * hdev,u64 virt_addr)28 bool hl_is_dram_va(struct hl_device *hdev, u64 virt_addr)
29 {
30 struct asic_fixed_properties *prop = &hdev->asic_prop;
31
32 return hl_mem_area_inside_range(virt_addr, prop->dmmu.page_size,
33 prop->dmmu.start_addr,
34 prop->dmmu.end_addr);
35 }
36
37 /**
38 * hl_mmu_init() - initialize the MMU module.
39 * @hdev: habanalabs device structure.
40 *
41 * Return: 0 for success, non-zero for failure.
42 */
hl_mmu_init(struct hl_device * hdev)43 int hl_mmu_init(struct hl_device *hdev)
44 {
45 int rc = -EOPNOTSUPP;
46
47 if (hdev->mmu_disable)
48 return 0;
49
50 mutex_init(&hdev->mmu_lock);
51
52 if (hdev->mmu_func[MMU_DR_PGT].init != NULL) {
53 rc = hdev->mmu_func[MMU_DR_PGT].init(hdev);
54 if (rc)
55 return rc;
56 }
57
58 if (hdev->mmu_func[MMU_HR_PGT].init != NULL) {
59 rc = hdev->mmu_func[MMU_HR_PGT].init(hdev);
60 if (rc)
61 goto fini_dr_mmu;
62 }
63
64 return 0;
65
66 fini_dr_mmu:
67 if (hdev->mmu_func[MMU_DR_PGT].fini != NULL)
68 hdev->mmu_func[MMU_DR_PGT].fini(hdev);
69
70 return rc;
71 }
72
73 /**
74 * hl_mmu_fini() - release the MMU module.
75 * @hdev: habanalabs device structure.
76 *
77 * This function does the following:
78 * - Disable MMU in H/W.
79 * - Free the pgt_infos pool.
80 *
81 * All contexts should be freed before calling this function.
82 */
hl_mmu_fini(struct hl_device * hdev)83 void hl_mmu_fini(struct hl_device *hdev)
84 {
85 if (hdev->mmu_disable)
86 return;
87
88 if (hdev->mmu_func[MMU_DR_PGT].fini != NULL)
89 hdev->mmu_func[MMU_DR_PGT].fini(hdev);
90
91 if (hdev->mmu_func[MMU_HR_PGT].fini != NULL)
92 hdev->mmu_func[MMU_HR_PGT].fini(hdev);
93
94 mutex_destroy(&hdev->mmu_lock);
95 }
96
97 /**
98 * hl_mmu_ctx_init() - initialize a context for using the MMU module.
99 * @ctx: pointer to the context structure to initialize.
100 *
101 * Initialize a mutex to protect the concurrent mapping flow, a hash to hold all
102 * page tables hops related to this context.
103 * Return: 0 on success, non-zero otherwise.
104 */
hl_mmu_ctx_init(struct hl_ctx * ctx)105 int hl_mmu_ctx_init(struct hl_ctx *ctx)
106 {
107 struct hl_device *hdev = ctx->hdev;
108 int rc = -EOPNOTSUPP;
109
110 if (hdev->mmu_disable)
111 return 0;
112
113 if (hdev->mmu_func[MMU_DR_PGT].ctx_init != NULL) {
114 rc = hdev->mmu_func[MMU_DR_PGT].ctx_init(ctx);
115 if (rc)
116 return rc;
117 }
118
119 if (hdev->mmu_func[MMU_HR_PGT].ctx_init != NULL) {
120 rc = hdev->mmu_func[MMU_HR_PGT].ctx_init(ctx);
121 if (rc)
122 goto fini_dr_ctx;
123 }
124
125 return 0;
126
127 fini_dr_ctx:
128 if (hdev->mmu_func[MMU_DR_PGT].fini != NULL)
129 hdev->mmu_func[MMU_DR_PGT].fini(hdev);
130
131 return rc;
132 }
133
134 /*
135 * hl_mmu_ctx_fini - disable a ctx from using the mmu module
136 *
137 * @ctx: pointer to the context structure
138 *
139 * This function does the following:
140 * - Free any pgts which were not freed yet
141 * - Free the mutex
142 * - Free DRAM default page mapping hops
143 */
hl_mmu_ctx_fini(struct hl_ctx * ctx)144 void hl_mmu_ctx_fini(struct hl_ctx *ctx)
145 {
146 struct hl_device *hdev = ctx->hdev;
147
148 if (hdev->mmu_disable)
149 return;
150
151 if (hdev->mmu_func[MMU_DR_PGT].ctx_fini != NULL)
152 hdev->mmu_func[MMU_DR_PGT].ctx_fini(ctx);
153
154 if (hdev->mmu_func[MMU_HR_PGT].ctx_fini != NULL)
155 hdev->mmu_func[MMU_HR_PGT].ctx_fini(ctx);
156 }
157
158 /*
159 * hl_mmu_get_real_page_size - get real page size to use in map/unmap operation
160 *
161 * @hdev: pointer to device data.
162 * @mmu_prop: MMU properties.
163 * @page_size: page size
164 * @real_page_size: set here the actual page size to use for the operation
165 * @is_dram_addr: true if DRAM address, otherwise false.
166 *
167 * @return 0 on success, otherwise non 0 error code
168 *
169 * note that this is general implementation that can fit most MMU arch. but as this is used as an
170 * MMU function:
171 * 1. it shall not be called directly- only from mmu_func structure instance
172 * 2. each MMU may modify the implementation internally
173 */
hl_mmu_get_real_page_size(struct hl_device * hdev,struct hl_mmu_properties * mmu_prop,u32 page_size,u32 * real_page_size,bool is_dram_addr)174 int hl_mmu_get_real_page_size(struct hl_device *hdev, struct hl_mmu_properties *mmu_prop,
175 u32 page_size, u32 *real_page_size, bool is_dram_addr)
176 {
177 /*
178 * The H/W handles mapping of specific page sizes. Hence if the page
179 * size is bigger, we break it to sub-pages and map them separately.
180 */
181 if ((page_size % mmu_prop->page_size) == 0) {
182 *real_page_size = mmu_prop->page_size;
183 return 0;
184 }
185
186 dev_err(hdev->dev, "page size of %u is not %uKB aligned, can't map\n",
187 page_size, mmu_prop->page_size >> 10);
188
189 return -EFAULT;
190 }
191
hl_mmu_get_prop(struct hl_device * hdev,u32 page_size,bool is_dram_addr)192 static struct hl_mmu_properties *hl_mmu_get_prop(struct hl_device *hdev, u32 page_size,
193 bool is_dram_addr)
194 {
195 struct asic_fixed_properties *prop = &hdev->asic_prop;
196
197 if (is_dram_addr)
198 return &prop->dmmu;
199 else if ((page_size % prop->pmmu_huge.page_size) == 0)
200 return &prop->pmmu_huge;
201
202 return &prop->pmmu;
203 }
204
205 /*
206 * hl_mmu_unmap_page - unmaps a virtual addr
207 *
208 * @ctx: pointer to the context structure
209 * @virt_addr: virt addr to map from
210 * @page_size: size of the page to unmap
211 * @flush_pte: whether to do a PCI flush
212 *
213 * This function does the following:
214 * - Check that the virt addr is mapped
215 * - Unmap the virt addr and frees pgts if possible
216 * - Returns 0 on success, -EINVAL if the given addr is not mapped
217 *
218 * Because this function changes the page tables in the device and because it
219 * changes the MMU hash, it must be protected by a lock.
220 * However, because it maps only a single page, the lock should be implemented
221 * in a higher level in order to protect the entire mapping of the memory area
222 *
223 * For optimization reasons PCI flush may be requested once after unmapping of
224 * large area.
225 */
hl_mmu_unmap_page(struct hl_ctx * ctx,u64 virt_addr,u32 page_size,bool flush_pte)226 int hl_mmu_unmap_page(struct hl_ctx *ctx, u64 virt_addr, u32 page_size, bool flush_pte)
227 {
228 struct hl_device *hdev = ctx->hdev;
229 struct hl_mmu_properties *mmu_prop;
230 struct hl_mmu_funcs *mmu_funcs;
231 int i, pgt_residency, rc = 0;
232 u32 real_page_size, npages;
233 u64 real_virt_addr;
234 bool is_dram_addr;
235
236 if (hdev->mmu_disable)
237 return 0;
238
239 is_dram_addr = hl_is_dram_va(hdev, virt_addr);
240 mmu_prop = hl_mmu_get_prop(hdev, page_size, is_dram_addr);
241
242 pgt_residency = mmu_prop->host_resident ? MMU_HR_PGT : MMU_DR_PGT;
243 mmu_funcs = hl_mmu_get_funcs(hdev, pgt_residency, is_dram_addr);
244
245 rc = hdev->asic_funcs->mmu_get_real_page_size(hdev, mmu_prop, page_size, &real_page_size,
246 is_dram_addr);
247 if (rc)
248 return rc;
249
250 npages = page_size / real_page_size;
251 real_virt_addr = virt_addr;
252
253 for (i = 0 ; i < npages ; i++) {
254 rc = mmu_funcs->unmap(ctx, real_virt_addr, is_dram_addr);
255 if (rc)
256 break;
257
258 real_virt_addr += real_page_size;
259 }
260
261 if (flush_pte)
262 mmu_funcs->flush(ctx);
263
264 if (trace_habanalabs_mmu_unmap_enabled() && !rc)
265 trace_habanalabs_mmu_unmap(hdev->dev, virt_addr, 0, page_size, flush_pte);
266
267 return rc;
268 }
269
270 /*
271 * hl_mmu_map_page - maps a virtual addr to physical addr
272 *
273 * @ctx: pointer to the context structure
274 * @virt_addr: virt addr to map from
275 * @phys_addr: phys addr to map to
276 * @page_size: physical page size
277 * @flush_pte: whether to do a PCI flush
278 *
279 * This function does the following:
280 * - Check that the virt addr is not mapped
281 * - Allocate pgts as necessary in order to map the virt addr to the phys
282 * - Returns 0 on success, -EINVAL if addr is already mapped, or -ENOMEM.
283 *
284 * Because this function changes the page tables in the device and because it
285 * changes the MMU hash, it must be protected by a lock.
286 * However, because it maps only a single page, the lock should be implemented
287 * in a higher level in order to protect the entire mapping of the memory area
288 *
289 * For optimization reasons PCI flush may be requested once after mapping of
290 * large area.
291 */
hl_mmu_map_page(struct hl_ctx * ctx,u64 virt_addr,u64 phys_addr,u32 page_size,bool flush_pte)292 int hl_mmu_map_page(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr, u32 page_size,
293 bool flush_pte)
294 {
295 int i, rc, pgt_residency, mapped_cnt = 0;
296 struct hl_device *hdev = ctx->hdev;
297 struct hl_mmu_properties *mmu_prop;
298 u64 real_virt_addr, real_phys_addr;
299 struct hl_mmu_funcs *mmu_funcs;
300 u32 real_page_size, npages;
301 bool is_dram_addr;
302
303
304 if (hdev->mmu_disable)
305 return 0;
306
307 is_dram_addr = hl_is_dram_va(hdev, virt_addr);
308 mmu_prop = hl_mmu_get_prop(hdev, page_size, is_dram_addr);
309
310 pgt_residency = mmu_prop->host_resident ? MMU_HR_PGT : MMU_DR_PGT;
311 mmu_funcs = hl_mmu_get_funcs(hdev, pgt_residency, is_dram_addr);
312
313 rc = hdev->asic_funcs->mmu_get_real_page_size(hdev, mmu_prop, page_size, &real_page_size,
314 is_dram_addr);
315 if (rc)
316 return rc;
317
318 /*
319 * Verify that the phys and virt addresses are aligned with the
320 * MMU page size (in dram this means checking the address and MMU
321 * after scrambling)
322 */
323 if ((is_dram_addr &&
324 ((hdev->asic_funcs->scramble_addr(hdev, phys_addr) &
325 (mmu_prop->page_size - 1)) ||
326 (hdev->asic_funcs->scramble_addr(hdev, virt_addr) &
327 (mmu_prop->page_size - 1)))) ||
328 (!is_dram_addr && ((phys_addr & (real_page_size - 1)) ||
329 (virt_addr & (real_page_size - 1)))))
330 dev_crit(hdev->dev,
331 "Mapping address 0x%llx with virtual address 0x%llx and page size of 0x%x is erroneous! Addresses must be divisible by page size",
332 phys_addr, virt_addr, real_page_size);
333
334 npages = page_size / real_page_size;
335 real_virt_addr = virt_addr;
336 real_phys_addr = phys_addr;
337
338 for (i = 0 ; i < npages ; i++) {
339 rc = mmu_funcs->map(ctx, real_virt_addr, real_phys_addr, real_page_size,
340 is_dram_addr);
341 if (rc)
342 goto err;
343
344 real_virt_addr += real_page_size;
345 real_phys_addr += real_page_size;
346 mapped_cnt++;
347 }
348
349 if (flush_pte)
350 mmu_funcs->flush(ctx);
351
352 trace_habanalabs_mmu_map(hdev->dev, virt_addr, phys_addr, page_size, flush_pte);
353
354 return 0;
355
356 err:
357 real_virt_addr = virt_addr;
358 for (i = 0 ; i < mapped_cnt ; i++) {
359 if (mmu_funcs->unmap(ctx, real_virt_addr, is_dram_addr))
360 dev_warn_ratelimited(hdev->dev,
361 "failed to unmap va: 0x%llx\n", real_virt_addr);
362
363 real_virt_addr += real_page_size;
364 }
365
366 mmu_funcs->flush(ctx);
367
368 return rc;
369 }
370
371 /*
372 * hl_mmu_map_contiguous - implements a wrapper for hl_mmu_map_page
373 * for mapping contiguous physical memory
374 *
375 * @ctx: pointer to the context structure
376 * @virt_addr: virt addr to map from
377 * @phys_addr: phys addr to map to
378 * @size: size to map
379 *
380 */
hl_mmu_map_contiguous(struct hl_ctx * ctx,u64 virt_addr,u64 phys_addr,u32 size)381 int hl_mmu_map_contiguous(struct hl_ctx *ctx, u64 virt_addr,
382 u64 phys_addr, u32 size)
383 {
384 struct hl_device *hdev = ctx->hdev;
385 struct asic_fixed_properties *prop = &hdev->asic_prop;
386 u64 curr_va, curr_pa;
387 u32 page_size;
388 bool flush_pte;
389 int rc = 0, off;
390
391 if (hl_mem_area_inside_range(virt_addr, size,
392 prop->dmmu.start_addr, prop->dmmu.end_addr))
393 page_size = prop->dmmu.page_size;
394 else if (hl_mem_area_inside_range(virt_addr, size,
395 prop->pmmu.start_addr, prop->pmmu.end_addr))
396 page_size = prop->pmmu.page_size;
397 else if (hl_mem_area_inside_range(virt_addr, size,
398 prop->pmmu_huge.start_addr, prop->pmmu_huge.end_addr))
399 page_size = prop->pmmu_huge.page_size;
400 else
401 return -EINVAL;
402
403 for (off = 0 ; off < size ; off += page_size) {
404 curr_va = virt_addr + off;
405 curr_pa = phys_addr + off;
406 flush_pte = (off + page_size) >= size;
407 rc = hl_mmu_map_page(ctx, curr_va, curr_pa, page_size,
408 flush_pte);
409 if (rc) {
410 dev_err(hdev->dev,
411 "Map failed for va 0x%llx to pa 0x%llx\n",
412 curr_va, curr_pa);
413 /* last mapping failed so don't try to unmap it - reduce off by page_size */
414 off -= page_size;
415 goto unmap;
416 }
417 }
418
419 return rc;
420
421 unmap:
422 for (; off >= 0 ; off -= page_size) {
423 curr_va = virt_addr + off;
424 flush_pte = (off - (s32) page_size) < 0;
425 if (hl_mmu_unmap_page(ctx, curr_va, page_size, flush_pte))
426 dev_warn_ratelimited(hdev->dev,
427 "failed to unmap va 0x%llx\n", curr_va);
428 }
429
430 return rc;
431 }
432
433 /*
434 * hl_mmu_unmap_contiguous - implements a wrapper for hl_mmu_unmap_page
435 * for unmapping contiguous physical memory
436 *
437 * @ctx: pointer to the context structure
438 * @virt_addr: virt addr to unmap
439 * @size: size to unmap
440 *
441 */
hl_mmu_unmap_contiguous(struct hl_ctx * ctx,u64 virt_addr,u32 size)442 int hl_mmu_unmap_contiguous(struct hl_ctx *ctx, u64 virt_addr, u32 size)
443 {
444 struct hl_device *hdev = ctx->hdev;
445 struct asic_fixed_properties *prop = &hdev->asic_prop;
446 u64 curr_va;
447 u32 page_size;
448 bool flush_pte;
449 int rc = 0, off;
450
451 if (hl_mem_area_inside_range(virt_addr, size,
452 prop->dmmu.start_addr, prop->dmmu.end_addr))
453 page_size = prop->dmmu.page_size;
454 else if (hl_mem_area_inside_range(virt_addr, size,
455 prop->pmmu.start_addr, prop->pmmu.end_addr))
456 page_size = prop->pmmu.page_size;
457 else if (hl_mem_area_inside_range(virt_addr, size,
458 prop->pmmu_huge.start_addr, prop->pmmu_huge.end_addr))
459 page_size = prop->pmmu_huge.page_size;
460 else
461 return -EINVAL;
462
463 for (off = 0 ; off < size ; off += page_size) {
464 curr_va = virt_addr + off;
465 flush_pte = (off + page_size) >= size;
466 rc = hl_mmu_unmap_page(ctx, curr_va, page_size, flush_pte);
467 if (rc)
468 dev_warn_ratelimited(hdev->dev,
469 "Unmap failed for va 0x%llx\n", curr_va);
470 }
471
472 return rc;
473 }
474
hl_mmu_pa_page_with_offset(struct hl_ctx * ctx,u64 virt_addr,struct hl_mmu_hop_info * hops,u64 * phys_addr)475 static void hl_mmu_pa_page_with_offset(struct hl_ctx *ctx, u64 virt_addr,
476 struct hl_mmu_hop_info *hops,
477 u64 *phys_addr)
478 {
479 struct asic_fixed_properties *prop = &ctx->hdev->asic_prop;
480 u64 offset_mask, addr_mask, hop_shift, tmp_phys_addr;
481 struct hl_mmu_properties *mmu_prop;
482
483 /* last hop holds the phys address and flags */
484 if (hops->unscrambled_paddr)
485 tmp_phys_addr = hops->unscrambled_paddr;
486 else
487 tmp_phys_addr = hops->hop_info[hops->used_hops - 1].hop_pte_val;
488
489 if (hops->range_type == HL_VA_RANGE_TYPE_HOST_HUGE)
490 mmu_prop = &prop->pmmu_huge;
491 else if (hops->range_type == HL_VA_RANGE_TYPE_HOST)
492 mmu_prop = &prop->pmmu;
493 else /* HL_VA_RANGE_TYPE_DRAM */
494 mmu_prop = &prop->dmmu;
495
496 if ((hops->range_type == HL_VA_RANGE_TYPE_DRAM) &&
497 !is_power_of_2(prop->dram_page_size)) {
498 u64 dram_page_size, dram_base, abs_phys_addr, abs_virt_addr,
499 page_id, page_start;
500 u32 page_off;
501
502 /*
503 * Bit arithmetic cannot be used for non power of two page
504 * sizes. In addition, since bit arithmetic is not used,
505 * we cannot ignore dram base. All that shall be considered.
506 */
507
508 dram_page_size = prop->dram_page_size;
509 dram_base = prop->dram_base_address;
510 abs_phys_addr = tmp_phys_addr - dram_base;
511 abs_virt_addr = virt_addr - dram_base;
512 page_id = DIV_ROUND_DOWN_ULL(abs_phys_addr, dram_page_size);
513 page_start = page_id * dram_page_size;
514 div_u64_rem(abs_virt_addr, dram_page_size, &page_off);
515
516 *phys_addr = page_start + page_off + dram_base;
517 } else {
518 /*
519 * find the correct hop shift field in hl_mmu_properties
520 * structure in order to determine the right masks
521 * for the page offset.
522 */
523 hop_shift = mmu_prop->hop_shifts[hops->used_hops - 1];
524 offset_mask = (1ull << hop_shift) - 1;
525 addr_mask = ~(offset_mask);
526 *phys_addr = (tmp_phys_addr & addr_mask) |
527 (virt_addr & offset_mask);
528 }
529 }
530
hl_mmu_va_to_pa(struct hl_ctx * ctx,u64 virt_addr,u64 * phys_addr)531 int hl_mmu_va_to_pa(struct hl_ctx *ctx, u64 virt_addr, u64 *phys_addr)
532 {
533 struct hl_mmu_hop_info hops;
534 int rc;
535
536 memset(&hops, 0, sizeof(hops));
537
538 rc = hl_mmu_get_tlb_info(ctx, virt_addr, &hops);
539 if (rc)
540 return rc;
541
542 hl_mmu_pa_page_with_offset(ctx, virt_addr, &hops, phys_addr);
543
544 return 0;
545 }
546
hl_mmu_get_tlb_info(struct hl_ctx * ctx,u64 virt_addr,struct hl_mmu_hop_info * hops)547 int hl_mmu_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr,
548 struct hl_mmu_hop_info *hops)
549 {
550 struct hl_device *hdev = ctx->hdev;
551 struct asic_fixed_properties *prop;
552 struct hl_mmu_properties *mmu_prop;
553 struct hl_mmu_funcs *mmu_funcs;
554 int pgt_residency, rc;
555 bool is_dram_addr;
556
557 if (hdev->mmu_disable)
558 return -EOPNOTSUPP;
559
560 prop = &hdev->asic_prop;
561 hops->scrambled_vaddr = virt_addr; /* assume no scrambling */
562
563 is_dram_addr = hl_mem_area_inside_range(virt_addr, prop->dmmu.page_size,
564 prop->dmmu.start_addr,
565 prop->dmmu.end_addr);
566
567 /* host-residency is the same in PMMU and PMMU huge, no need to distinguish here */
568 mmu_prop = is_dram_addr ? &prop->dmmu : &prop->pmmu;
569 pgt_residency = mmu_prop->host_resident ? MMU_HR_PGT : MMU_DR_PGT;
570 mmu_funcs = hl_mmu_get_funcs(hdev, pgt_residency, is_dram_addr);
571
572 mutex_lock(&hdev->mmu_lock);
573 rc = mmu_funcs->get_tlb_info(ctx, virt_addr, hops);
574 mutex_unlock(&hdev->mmu_lock);
575
576 if (rc)
577 return rc;
578
579 /* add page offset to physical address */
580 if (hops->unscrambled_paddr)
581 hl_mmu_pa_page_with_offset(ctx, virt_addr, hops, &hops->unscrambled_paddr);
582
583 return 0;
584 }
585
hl_mmu_if_set_funcs(struct hl_device * hdev)586 int hl_mmu_if_set_funcs(struct hl_device *hdev)
587 {
588 struct asic_fixed_properties *prop = &hdev->asic_prop;
589
590 if (hdev->mmu_disable)
591 return 0;
592
593 switch (hdev->asic_type) {
594 case ASIC_GOYA:
595 case ASIC_GAUDI:
596 case ASIC_GAUDI_SEC:
597 hl_mmu_v1_set_funcs(hdev, &hdev->mmu_func[MMU_DR_PGT]);
598 break;
599 case ASIC_GAUDI2:
600 case ASIC_GAUDI2B:
601 case ASIC_GAUDI2C:
602 hl_mmu_v2_set_funcs(hdev, &hdev->mmu_func[MMU_DR_PGT]);
603 if (prop->pmmu.host_resident)
604 hl_mmu_v2_hr_set_funcs(hdev, &hdev->mmu_func[MMU_HR_PGT]);
605 break;
606 default:
607 dev_err(hdev->dev, "Unrecognized ASIC type %d\n",
608 hdev->asic_type);
609 return -EOPNOTSUPP;
610 }
611
612 return 0;
613 }
614
615 /**
616 * hl_mmu_scramble_addr() - The generic mmu address scrambling routine.
617 * @hdev: pointer to device data.
618 * @addr: The address to scramble.
619 *
620 * Return: The scrambled address.
621 */
hl_mmu_scramble_addr(struct hl_device * hdev,u64 addr)622 u64 hl_mmu_scramble_addr(struct hl_device *hdev, u64 addr)
623 {
624 return addr;
625 }
626
627 /**
628 * hl_mmu_descramble_addr() - The generic mmu address descrambling
629 * routine.
630 * @hdev: pointer to device data.
631 * @addr: The address to descramble.
632 *
633 * Return: The un-scrambled address.
634 */
hl_mmu_descramble_addr(struct hl_device * hdev,u64 addr)635 u64 hl_mmu_descramble_addr(struct hl_device *hdev, u64 addr)
636 {
637 return addr;
638 }
639
hl_mmu_invalidate_cache(struct hl_device * hdev,bool is_hard,u32 flags)640 int hl_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, u32 flags)
641 {
642 int rc;
643
644 rc = hdev->asic_funcs->mmu_invalidate_cache(hdev, is_hard, flags);
645 if (rc)
646 dev_err_ratelimited(hdev->dev,
647 "%s cache invalidation failed, rc=%d\n",
648 flags == VM_TYPE_USERPTR ? "PMMU" : "HMMU", rc);
649
650 return rc;
651 }
652
hl_mmu_invalidate_cache_range(struct hl_device * hdev,bool is_hard,u32 flags,u32 asid,u64 va,u64 size)653 int hl_mmu_invalidate_cache_range(struct hl_device *hdev, bool is_hard,
654 u32 flags, u32 asid, u64 va, u64 size)
655 {
656 int rc;
657
658 rc = hdev->asic_funcs->mmu_invalidate_cache_range(hdev, is_hard, flags,
659 asid, va, size);
660 if (rc)
661 dev_err_ratelimited(hdev->dev,
662 "%s cache range invalidation failed: va=%#llx, size=%llu, rc=%d",
663 flags == VM_TYPE_USERPTR ? "PMMU" : "HMMU", va, size, rc);
664
665 return rc;
666 }
667
hl_mmu_prefetch_work_function(struct work_struct * work)668 static void hl_mmu_prefetch_work_function(struct work_struct *work)
669 {
670 struct hl_prefetch_work *pfw = container_of(work, struct hl_prefetch_work, prefetch_work);
671 struct hl_ctx *ctx = pfw->ctx;
672 struct hl_device *hdev = ctx->hdev;
673
674 if (!hl_device_operational(hdev, NULL))
675 goto put_ctx;
676
677 mutex_lock(&hdev->mmu_lock);
678
679 hdev->asic_funcs->mmu_prefetch_cache_range(ctx, pfw->flags, pfw->asid, pfw->va, pfw->size);
680
681 mutex_unlock(&hdev->mmu_lock);
682
683 put_ctx:
684 /*
685 * context was taken in the common mmu prefetch function- see comment there about
686 * context handling.
687 */
688 hl_ctx_put(ctx);
689 kfree(pfw);
690 }
691
hl_mmu_prefetch_cache_range(struct hl_ctx * ctx,u32 flags,u32 asid,u64 va,u64 size)692 int hl_mmu_prefetch_cache_range(struct hl_ctx *ctx, u32 flags, u32 asid, u64 va, u64 size)
693 {
694 struct hl_prefetch_work *handle_prefetch_work;
695
696 handle_prefetch_work = kmalloc(sizeof(*handle_prefetch_work), GFP_KERNEL);
697 if (!handle_prefetch_work)
698 return -ENOMEM;
699
700 INIT_WORK(&handle_prefetch_work->prefetch_work, hl_mmu_prefetch_work_function);
701 handle_prefetch_work->ctx = ctx;
702 handle_prefetch_work->va = va;
703 handle_prefetch_work->size = size;
704 handle_prefetch_work->flags = flags;
705 handle_prefetch_work->asid = asid;
706
707 /*
708 * as actual prefetch is done in a WQ we must get the context (and put it
709 * at the end of the work function)
710 */
711 hl_ctx_get(ctx);
712 queue_work(ctx->hdev->prefetch_wq, &handle_prefetch_work->prefetch_work);
713
714 return 0;
715 }
716
hl_mmu_get_next_hop_addr(struct hl_ctx * ctx,u64 curr_pte)717 u64 hl_mmu_get_next_hop_addr(struct hl_ctx *ctx, u64 curr_pte)
718 {
719 return (curr_pte & PAGE_PRESENT_MASK) ? (curr_pte & HOP_PHYS_ADDR_MASK) : ULLONG_MAX;
720 }
721
722 /**
723 * hl_mmu_get_hop_pte_phys_addr() - extract PTE address from HOP
724 * @ctx: pointer to the context structure to initialize.
725 * @mmu_prop: MMU properties.
726 * @hop_idx: HOP index.
727 * @hop_addr: HOP address.
728 * @virt_addr: virtual address for the translation.
729 *
730 * @return the matching PTE value on success, otherwise U64_MAX.
731 */
hl_mmu_get_hop_pte_phys_addr(struct hl_ctx * ctx,struct hl_mmu_properties * mmu_prop,u8 hop_idx,u64 hop_addr,u64 virt_addr)732 u64 hl_mmu_get_hop_pte_phys_addr(struct hl_ctx *ctx, struct hl_mmu_properties *mmu_prop,
733 u8 hop_idx, u64 hop_addr, u64 virt_addr)
734 {
735 u64 mask, shift;
736
737 if (hop_idx >= mmu_prop->num_hops) {
738 dev_err_ratelimited(ctx->hdev->dev, "Invalid hop index %d\n", hop_idx);
739 return U64_MAX;
740 }
741
742 shift = mmu_prop->hop_shifts[hop_idx];
743 mask = mmu_prop->hop_masks[hop_idx];
744
745 return hop_addr + ctx->hdev->asic_prop.mmu_pte_size * ((virt_addr & mask) >> shift);
746 }
747
mmu_dma_mem_free_from_chunk(struct gen_pool * pool,struct gen_pool_chunk * chunk,void * data)748 static void mmu_dma_mem_free_from_chunk(struct gen_pool *pool,
749 struct gen_pool_chunk *chunk,
750 void *data)
751 {
752 struct hl_device *hdev = data;
753
754 hl_asic_dma_free_coherent(hdev, (chunk->end_addr - chunk->start_addr) + 1,
755 (void *)chunk->start_addr, chunk->phys_addr);
756 }
757
hl_mmu_hr_flush(struct hl_ctx * ctx)758 void hl_mmu_hr_flush(struct hl_ctx *ctx)
759 {
760 /* a flush operation requires memory barrier */
761 mb();
762 }
763
764 /**
765 * hl_mmu_hr_pool_destroy() - destroy genpool
766 * @hdev: habanalabs device structure.
767 * @hr_priv: MMU HR private data.
768 * @hop_table_size: HOP table size.
769 *
770 * This function does the following:
771 * - free entries allocated for shadow HOP0
772 * - free pool chunks
773 * - free pool
774 */
hl_mmu_hr_pool_destroy(struct hl_device * hdev,struct hl_mmu_hr_priv * hr_priv,u32 hop_table_size)775 static void hl_mmu_hr_pool_destroy(struct hl_device *hdev, struct hl_mmu_hr_priv *hr_priv,
776 u32 hop_table_size)
777 {
778 struct asic_fixed_properties *prop = &hdev->asic_prop;
779 struct gen_pool **pool = &hr_priv->mmu_pgt_pool;
780 struct pgt_info *hop0_pgt;
781 int asid;
782
783 if (ZERO_OR_NULL_PTR(*pool))
784 return;
785
786 /* Free the Fixed allocation of HOPs0 */
787 if (hr_priv->mmu_asid_hop0) {
788 for (asid = 0 ; asid < prop->max_asid ; asid++) {
789 hop0_pgt = &hr_priv->mmu_asid_hop0[asid];
790 if (ZERO_OR_NULL_PTR(hop0_pgt->virt_addr))
791 continue;
792
793 gen_pool_free(*pool, (uintptr_t) hop0_pgt->virt_addr, hop_table_size);
794 }
795 }
796
797 gen_pool_for_each_chunk(*pool, mmu_dma_mem_free_from_chunk, hdev);
798 gen_pool_destroy(*pool);
799
800 /* Make sure that if we arrive here again without init was called we
801 * won't cause kernel panic. This can happen for example if we fail
802 * during hard reset code at certain points
803 */
804 *pool = NULL;
805 }
806
807 /**
808 * hl_mmu_hr_init() - initialize the MMU module.
809 * @hdev: habanalabs device structure.
810 * @hr_priv: MMU HR private data.
811 * @hop_table_size: HOP table size.
812 * @pgt_size: memory size allocated for the page table
813 *
814 * @return 0 on success otherwise non-zero error code
815 *
816 * This function does the following:
817 * - Create a pool of pages for pgt_infos.
818 * - Create a shadow table for pgt
819 */
hl_mmu_hr_init(struct hl_device * hdev,struct hl_mmu_hr_priv * hr_priv,u32 hop_table_size,u64 pgt_size)820 int hl_mmu_hr_init(struct hl_device *hdev, struct hl_mmu_hr_priv *hr_priv, u32 hop_table_size,
821 u64 pgt_size)
822 {
823 struct asic_fixed_properties *prop = &hdev->asic_prop;
824 size_t pool_chunk_size = SZ_4M;
825 struct pgt_info *hop0_pgt;
826 dma_addr_t dma_addr;
827 u64 virt_addr;
828 int i, rc;
829
830 /*
831 * we set alloc size as PAGE_SIZE (sine dma_alloc_coherent allocation order/size is
832 * PAGE_SHIFT/PAGE_SIZE) in order to be able to control the allocations alignment.
833 * This way we can call "DMA alloc align" according to dma_alloc granularity and supply
834 * allocations with higher-order alignment restrictions
835 */
836 hr_priv->mmu_pgt_pool = gen_pool_create(PAGE_SHIFT, -1);
837 if (ZERO_OR_NULL_PTR(hr_priv->mmu_pgt_pool)) {
838 dev_err(hdev->dev, "Failed to create hr page pool\n");
839 return -ENOMEM;
840 }
841
842 hr_priv->mmu_asid_hop0 = kvcalloc(prop->max_asid, sizeof(struct pgt_info), GFP_KERNEL);
843 if (ZERO_OR_NULL_PTR(hr_priv->mmu_asid_hop0)) {
844 dev_err(hdev->dev, "Failed to allocate hr-mmu hop0 table\n");
845 rc = -ENOMEM;
846 goto destroy_mmu_pgt_pool;
847 }
848
849 for (i = 0 ; i < pgt_size ; i += pool_chunk_size) {
850 virt_addr = (uintptr_t) hl_asic_dma_alloc_coherent(hdev, pool_chunk_size,
851 &dma_addr,
852 GFP_KERNEL | __GFP_ZERO);
853 if (ZERO_OR_NULL_PTR(virt_addr)) {
854 dev_err(hdev->dev,
855 "Failed to allocate memory for host-resident page pool\n");
856 rc = -ENOMEM;
857 goto destroy_mmu_pgt_pool;
858 }
859
860 rc = gen_pool_add_virt(hr_priv->mmu_pgt_pool, virt_addr, (phys_addr_t) dma_addr,
861 pool_chunk_size, -1);
862 if (rc) {
863 dev_err(hdev->dev, "Failed to fill host-resident page pool\n");
864 goto destroy_mmu_pgt_pool;
865 }
866 }
867
868 for (i = 0 ; i < prop->max_asid ; i++) {
869 hop0_pgt = &hr_priv->mmu_asid_hop0[i];
870 hop0_pgt->virt_addr = (uintptr_t)
871 gen_pool_dma_zalloc_align(hr_priv->mmu_pgt_pool,
872 hop_table_size,
873 (dma_addr_t *) &hop0_pgt->phys_addr,
874 hop_table_size);
875 if (!hop0_pgt->virt_addr) {
876 dev_err(hdev->dev, "Failed to allocate HOP from pgt pool\n");
877 rc = -ENOMEM;
878 goto destroy_mmu_pgt_pool;
879 }
880 }
881
882 /* MMU H/W init will be done in device hw_init() */
883
884 return 0;
885
886 destroy_mmu_pgt_pool:
887 hl_mmu_hr_pool_destroy(hdev, hr_priv, hop_table_size);
888 if (!ZERO_OR_NULL_PTR(hr_priv->mmu_asid_hop0))
889 kvfree(hr_priv->mmu_asid_hop0);
890
891 return rc;
892 }
893
894 /**
895 * hl_mmu_hr_fini() - release the MMU module.
896 * @hdev: habanalabs device structure.
897 * @hr_priv: MMU host resident private info.
898 * @hop_table_size: HOP table size
899 *
900 * This function does the following:
901 * - Disable MMU in H/W.
902 * - Free the pgt_infos pool.
903 *
904 * All contexts should be freed before calling this function.
905 */
hl_mmu_hr_fini(struct hl_device * hdev,struct hl_mmu_hr_priv * hr_priv,u32 hop_table_size)906 void hl_mmu_hr_fini(struct hl_device *hdev, struct hl_mmu_hr_priv *hr_priv, u32 hop_table_size)
907 {
908 /* MMU H/W fini was already done in device hw_fini() */
909
910 hl_mmu_hr_pool_destroy(hdev, hr_priv, hop_table_size);
911
912 if (!ZERO_OR_NULL_PTR(hr_priv->mmu_asid_hop0)) {
913 kvfree(hr_priv->mmu_asid_hop0);
914
915 /* Make sure that if we arrive here again without init was
916 * called we won't cause kernel panic. This can happen for
917 * example if we fail during hard reset code at certain points
918 */
919 hr_priv->mmu_asid_hop0 = NULL;
920 }
921 }
922
923 /**
924 * hl_mmu_hr_free_hop_remove_pgt() - free HOP and remove PGT from hash
925 * @pgt_info: page table info structure.
926 * @hr_priv: MMU HR private data.
927 * @hop_table_size: HOP table size.
928 */
hl_mmu_hr_free_hop_remove_pgt(struct pgt_info * pgt_info,struct hl_mmu_hr_priv * hr_priv,u32 hop_table_size)929 void hl_mmu_hr_free_hop_remove_pgt(struct pgt_info *pgt_info, struct hl_mmu_hr_priv *hr_priv,
930 u32 hop_table_size)
931 {
932 gen_pool_free(hr_priv->mmu_pgt_pool, pgt_info->virt_addr, hop_table_size);
933 hash_del(&pgt_info->node);
934 kfree(pgt_info);
935 }
936
937 /**
938 * hl_mmu_hr_pte_phys_to_virt() - translate PTE phys addr to virt addr
939 * @ctx: pointer to the context structure
940 * @pgt: pgt_info for the HOP hosting the PTE
941 * @phys_pte_addr: phys address of the PTE
942 * @hop_table_size: HOP table size
943 *
944 * @return PTE virtual address
945 *
946 * The function use the pgt_info to get HOP base virt addr and obtain the PTE's virt addr
947 * by adding the PTE offset.
948 */
hl_mmu_hr_pte_phys_to_virt(struct hl_ctx * ctx,struct pgt_info * pgt,u64 phys_pte_addr,u32 hop_table_size)949 u64 hl_mmu_hr_pte_phys_to_virt(struct hl_ctx *ctx, struct pgt_info *pgt,
950 u64 phys_pte_addr, u32 hop_table_size)
951 {
952 u64 page_mask = (hop_table_size - 1);
953 u64 pte_offset = phys_pte_addr & page_mask;
954
955 return pgt->virt_addr + pte_offset;
956 }
957
958 /**
959 * hl_mmu_hr_write_pte() - write HR PTE
960 * @ctx: pointer to the context structure
961 * @pgt_info: HOP's page table info structure
962 * @phys_pte_addr: phys PTE address
963 * @val: raw PTE data
964 * @hop_table_size: HOP table size
965 */
hl_mmu_hr_write_pte(struct hl_ctx * ctx,struct pgt_info * pgt_info,u64 phys_pte_addr,u64 val,u32 hop_table_size)966 void hl_mmu_hr_write_pte(struct hl_ctx *ctx, struct pgt_info *pgt_info, u64 phys_pte_addr,
967 u64 val, u32 hop_table_size)
968 {
969 /*
970 * The value to write is the phys address of the next hop +
971 * flags at the 12 LSBs.
972 */
973 u64 virt_addr = hl_mmu_hr_pte_phys_to_virt(ctx, pgt_info, phys_pte_addr, hop_table_size);
974
975 *((u64 *) (uintptr_t) virt_addr) = val;
976 }
977
978 /**
979 * hl_mmu_hr_clear_pte() - clear HR PTE
980 * @ctx: pointer to the context structure
981 * @pgt_info: HOP's page table info structure
982 * @phys_pte_addr: phys PTE address
983 * @hop_table_size: HOP table size
984 */
hl_mmu_hr_clear_pte(struct hl_ctx * ctx,struct pgt_info * pgt_info,u64 phys_pte_addr,u32 hop_table_size)985 void hl_mmu_hr_clear_pte(struct hl_ctx *ctx, struct pgt_info *pgt_info, u64 phys_pte_addr,
986 u32 hop_table_size)
987 {
988 /* no need to transform the value to physical address */
989 hl_mmu_hr_write_pte(ctx, pgt_info, phys_pte_addr, 0, hop_table_size);
990 }
991
992 /**
993 * hl_mmu_hr_put_pte() - put HR PTE and remove it if necessary (no more PTEs)
994 * @ctx: pointer to the context structure
995 * @pgt_info: HOP's page table info structure
996 * @hr_priv: HR MMU private info
997 * @hop_table_size: HOP table size
998 *
999 * @return number of PTEs still in the HOP
1000 */
hl_mmu_hr_put_pte(struct hl_ctx * ctx,struct pgt_info * pgt_info,struct hl_mmu_hr_priv * hr_priv,u32 hop_table_size)1001 int hl_mmu_hr_put_pte(struct hl_ctx *ctx, struct pgt_info *pgt_info,
1002 struct hl_mmu_hr_priv *hr_priv,
1003 u32 hop_table_size)
1004 {
1005 int num_of_ptes_left;
1006
1007 pgt_info->num_of_ptes--;
1008
1009 /*
1010 * Need to save the number of ptes left because free_hop might free
1011 * the pgt_info
1012 */
1013 num_of_ptes_left = pgt_info->num_of_ptes;
1014 if (!num_of_ptes_left)
1015 hl_mmu_hr_free_hop_remove_pgt(pgt_info, hr_priv, hop_table_size);
1016
1017 return num_of_ptes_left;
1018 }
1019
1020 /**
1021 * hl_mmu_hr_get_pte() - increase PGT PTE count
1022 * @ctx: pointer to the context structure
1023 * @hr_func: host resident functions
1024 * @phys_hop_addr: HOP phys address
1025 */
hl_mmu_hr_get_pte(struct hl_ctx * ctx,struct hl_hr_mmu_funcs * hr_func,u64 phys_hop_addr)1026 void hl_mmu_hr_get_pte(struct hl_ctx *ctx, struct hl_hr_mmu_funcs *hr_func, u64 phys_hop_addr)
1027 {
1028 hr_func->get_pgt_info(ctx, phys_hop_addr)->num_of_ptes++;
1029 }
1030
1031 /**
1032 * hl_mmu_hr_get_next_hop_pgt_info() - get pgt_info structure for the next HOP
1033 * @ctx: pointer to the context structure.
1034 * @hr_func: host resident functions.
1035 * @curr_pte: current PTE value.
1036 *
1037 * @return pgt_info structure on success, otherwise NULL.
1038 */
hl_mmu_hr_get_next_hop_pgt_info(struct hl_ctx * ctx,struct hl_hr_mmu_funcs * hr_func,u64 curr_pte)1039 struct pgt_info *hl_mmu_hr_get_next_hop_pgt_info(struct hl_ctx *ctx,
1040 struct hl_hr_mmu_funcs *hr_func,
1041 u64 curr_pte)
1042 {
1043 u64 next_hop_phys_addr = hl_mmu_get_next_hop_addr(ctx, curr_pte);
1044
1045 if (next_hop_phys_addr == ULLONG_MAX)
1046 return NULL;
1047
1048 return hr_func->get_pgt_info(ctx, next_hop_phys_addr);
1049 }
1050
1051 /**
1052 * hl_mmu_hr_alloc_hop() - allocate HOP
1053 * @ctx: pointer to the context structure.
1054 * @hr_priv: host resident private info structure.
1055 * @hr_func: host resident functions.
1056 * @mmu_prop: MMU properties.
1057 *
1058 * @return pgt_info structure associated with the allocated HOP on success, otherwise NULL.
1059 */
hl_mmu_hr_alloc_hop(struct hl_ctx * ctx,struct hl_mmu_hr_priv * hr_priv,struct hl_hr_mmu_funcs * hr_func,struct hl_mmu_properties * mmu_prop)1060 struct pgt_info *hl_mmu_hr_alloc_hop(struct hl_ctx *ctx, struct hl_mmu_hr_priv *hr_priv,
1061 struct hl_hr_mmu_funcs *hr_func,
1062 struct hl_mmu_properties *mmu_prop)
1063 {
1064 struct hl_device *hdev = ctx->hdev;
1065 struct pgt_info *pgt_info;
1066 dma_addr_t phys_addr;
1067 void *virt_addr;
1068 int i, retry = 1;
1069
1070 pgt_info = kmalloc(sizeof(*pgt_info), GFP_KERNEL);
1071 if (!pgt_info)
1072 return NULL;
1073
1074 for (i = 0; i <= retry; i++) {
1075 virt_addr = gen_pool_dma_zalloc_align(hr_priv->mmu_pgt_pool,
1076 mmu_prop->hop_table_size,
1077 &phys_addr,
1078 mmu_prop->hop_table_size);
1079 if (virt_addr)
1080 break;
1081
1082 /* No memory in pool - get some and try again */
1083 virt_addr = hl_asic_dma_alloc_coherent(hdev, SZ_2M, &phys_addr,
1084 GFP_KERNEL | __GFP_ZERO);
1085 if (ZERO_OR_NULL_PTR(virt_addr))
1086 break;
1087
1088 if (gen_pool_add_virt(hr_priv->mmu_pgt_pool, (unsigned long)virt_addr,
1089 phys_addr, SZ_2M, -1)) {
1090 hl_asic_dma_free_coherent(hdev, SZ_2M, virt_addr, phys_addr);
1091 virt_addr = NULL;
1092 break;
1093 }
1094 }
1095
1096 if (ZERO_OR_NULL_PTR(virt_addr)) {
1097 dev_err(hdev->dev, "failed to allocate page\n");
1098 goto pool_alloc_err;
1099 }
1100
1101 pgt_info->phys_addr = phys_addr;
1102 pgt_info->shadow_addr = (unsigned long) NULL;
1103 pgt_info->virt_addr = (unsigned long)virt_addr;
1104 pgt_info->ctx = ctx;
1105 pgt_info->num_of_ptes = 0;
1106 hr_func->add_pgt_info(ctx, pgt_info, phys_addr);
1107
1108 return pgt_info;
1109
1110 pool_alloc_err:
1111 kfree(pgt_info);
1112
1113 return NULL;
1114 }
1115
1116 /**
1117 * hl_mmu_hr_get_alloc_next_hop() - get the next HOP, allocate it if it does not exist
1118 * @ctx: pointer to the context structure.
1119 * @hr_priv: host resident private info structure.
1120 * @hr_func: host resident functions.
1121 * @mmu_prop: MMU properties.
1122 * @curr_pte: current PTE value.
1123 * @is_new_hop: set to true if HOP is new (caller responsibility to set it to false).
1124 *
1125 * @return pgt_info structure associated with the allocated HOP on success, otherwise NULL.
1126 */
hl_mmu_hr_get_alloc_next_hop(struct hl_ctx * ctx,struct hl_mmu_hr_priv * hr_priv,struct hl_hr_mmu_funcs * hr_func,struct hl_mmu_properties * mmu_prop,u64 curr_pte,bool * is_new_hop)1127 struct pgt_info *hl_mmu_hr_get_alloc_next_hop(struct hl_ctx *ctx,
1128 struct hl_mmu_hr_priv *hr_priv,
1129 struct hl_hr_mmu_funcs *hr_func,
1130 struct hl_mmu_properties *mmu_prop,
1131 u64 curr_pte, bool *is_new_hop)
1132 {
1133 u64 hop_addr = hl_mmu_get_next_hop_addr(ctx, curr_pte);
1134
1135 if (hop_addr != ULLONG_MAX)
1136 return hr_func->get_pgt_info(ctx, hop_addr);
1137
1138 *is_new_hop = true;
1139 return hl_mmu_hr_alloc_hop(ctx, hr_priv, hr_func, mmu_prop);
1140 }
1141
1142 /**
1143 * hl_mmu_hr_get_tlb_info() - get the TLB info (info for a specific mapping)
1144 * @ctx: pointer to the context structure.
1145 * @virt_addr: the virt address for which to get info.
1146 * @hops: HOPs info structure.
1147 * @hr_func: host resident functions.
1148 *
1149 * @return 0 on success, otherwise non 0 error code..
1150 */
hl_mmu_hr_get_tlb_info(struct hl_ctx * ctx,u64 virt_addr,struct hl_mmu_hop_info * hops,struct hl_hr_mmu_funcs * hr_func)1151 int hl_mmu_hr_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr, struct hl_mmu_hop_info *hops,
1152 struct hl_hr_mmu_funcs *hr_func)
1153 {
1154 /* using 6 HOPs as this is the maximum number of HOPs */
1155 struct pgt_info *hops_pgt_info[MMU_ARCH_6_HOPS] = { NULL };
1156 struct hl_device *hdev = ctx->hdev;
1157 struct hl_mmu_properties *mmu_prop;
1158 int rc, i, used_hops;
1159 bool is_huge;
1160
1161 rc = hr_func->get_tlb_mapping_params(hdev, &mmu_prop, hops, virt_addr, &is_huge);
1162 if (rc)
1163 return rc;
1164
1165 used_hops = mmu_prop->num_hops;
1166
1167 /* huge pages use one less hop */
1168 if (is_huge)
1169 used_hops--;
1170
1171 hops->scrambled_vaddr = hdev->asic_funcs->scramble_addr(hdev, virt_addr);
1172
1173 for (i = 0 ; i < used_hops ; i++) {
1174 if (i == 0)
1175 hops_pgt_info[i] = hr_func->get_hop0_pgt_info(ctx);
1176 else
1177 hops_pgt_info[i] = hl_mmu_hr_get_next_hop_pgt_info(ctx, hr_func,
1178 hops->hop_info[i - 1].hop_pte_val);
1179
1180 if (!hops_pgt_info[i])
1181 return -EFAULT;
1182
1183 hops->hop_info[i].hop_addr = hops_pgt_info[i]->phys_addr;
1184 hops->hop_info[i].hop_pte_addr =
1185 hl_mmu_get_hop_pte_phys_addr(ctx, mmu_prop, i,
1186 hops->hop_info[i].hop_addr,
1187 hops->scrambled_vaddr);
1188 hops->hop_info[i].hop_pte_val = *(u64 *) (uintptr_t)
1189 hl_mmu_hr_pte_phys_to_virt(ctx, hops_pgt_info[i],
1190 hops->hop_info[i].hop_pte_addr,
1191 mmu_prop->hop_table_size);
1192
1193 if (!(hops->hop_info[i].hop_pte_val & PAGE_PRESENT_MASK))
1194 return -EFAULT;
1195
1196 if (hops->hop_info[i].hop_pte_val & mmu_prop->last_mask)
1197 break;
1198 }
1199
1200 /* if passed over all hops then no last hop was found */
1201 if (i == mmu_prop->num_hops)
1202 return -EFAULT;
1203
1204 if (hops->scrambled_vaddr != virt_addr)
1205 hops->unscrambled_paddr = hdev->asic_funcs->descramble_addr
1206 (hdev, hops->hop_info[i].hop_pte_val);
1207 else
1208 hops->unscrambled_paddr = hops->hop_info[i].hop_pte_val;
1209
1210 hops->used_hops = i + 1;
1211
1212 return 0;
1213 }
1214
hl_mmu_dr_get_pgt_info(struct hl_ctx * ctx,u64 hop_addr)1215 struct pgt_info *hl_mmu_dr_get_pgt_info(struct hl_ctx *ctx, u64 hop_addr)
1216 {
1217 struct pgt_info *pgt_info = NULL;
1218
1219 hash_for_each_possible(ctx->mmu_shadow_hash, pgt_info, node,
1220 (unsigned long) hop_addr)
1221 if (hop_addr == pgt_info->shadow_addr)
1222 break;
1223
1224 return pgt_info;
1225 }
1226
hl_mmu_dr_free_hop(struct hl_ctx * ctx,u64 hop_addr)1227 void hl_mmu_dr_free_hop(struct hl_ctx *ctx, u64 hop_addr)
1228 {
1229 struct pgt_info *pgt_info = hl_mmu_dr_get_pgt_info(ctx, hop_addr);
1230
1231 hl_mmu_dr_free_pgt_node(ctx, pgt_info);
1232 }
1233
hl_mmu_dr_free_pgt_node(struct hl_ctx * ctx,struct pgt_info * pgt_info)1234 void hl_mmu_dr_free_pgt_node(struct hl_ctx *ctx, struct pgt_info *pgt_info)
1235 {
1236 struct hl_device *hdev = ctx->hdev;
1237
1238 gen_pool_free(hdev->mmu_priv.dr.mmu_pgt_pool, pgt_info->phys_addr,
1239 hdev->asic_prop.dmmu.hop_table_size);
1240 hash_del(&pgt_info->node);
1241 kfree((u64 *) (uintptr_t) pgt_info->shadow_addr);
1242 kfree(pgt_info);
1243 }
1244
hl_mmu_dr_get_phys_hop0_addr(struct hl_ctx * ctx)1245 u64 hl_mmu_dr_get_phys_hop0_addr(struct hl_ctx *ctx)
1246 {
1247 return ctx->hdev->asic_prop.mmu_pgt_addr +
1248 (ctx->asid * ctx->hdev->asic_prop.dmmu.hop_table_size);
1249 }
1250
hl_mmu_dr_get_hop0_addr(struct hl_ctx * ctx)1251 u64 hl_mmu_dr_get_hop0_addr(struct hl_ctx *ctx)
1252 {
1253 return (u64) (uintptr_t) ctx->hdev->mmu_priv.dr.mmu_shadow_hop0 +
1254 (ctx->asid * ctx->hdev->asic_prop.dmmu.hop_table_size);
1255 }
1256
hl_mmu_dr_get_phys_addr(struct hl_ctx * ctx,u64 shadow_addr)1257 u64 hl_mmu_dr_get_phys_addr(struct hl_ctx *ctx, u64 shadow_addr)
1258 {
1259 u64 page_mask = ctx->hdev->asic_prop.dmmu.hop_table_size - 1;
1260 u64 shadow_hop_addr = shadow_addr & (~page_mask);
1261 u64 pte_offset = shadow_addr & page_mask;
1262 u64 phys_hop_addr;
1263
1264 if (shadow_hop_addr != hl_mmu_dr_get_hop0_addr(ctx))
1265 phys_hop_addr = hl_mmu_dr_get_pgt_info(ctx, shadow_hop_addr)->phys_addr;
1266 else
1267 phys_hop_addr = hl_mmu_dr_get_phys_hop0_addr(ctx);
1268
1269 return phys_hop_addr + pte_offset;
1270 }
1271
hl_mmu_dr_write_pte(struct hl_ctx * ctx,u64 shadow_pte_addr,u64 val)1272 void hl_mmu_dr_write_pte(struct hl_ctx *ctx, u64 shadow_pte_addr, u64 val)
1273 {
1274 u64 phys_val = hl_mmu_dr_get_phys_addr(ctx, val);
1275
1276 ctx->hdev->asic_funcs->write_pte(ctx->hdev, hl_mmu_dr_get_phys_addr(ctx, shadow_pte_addr),
1277 phys_val);
1278
1279 *(u64 *) (uintptr_t) shadow_pte_addr = val;
1280 }
1281
hl_mmu_dr_write_final_pte(struct hl_ctx * ctx,u64 shadow_pte_addr,u64 val)1282 void hl_mmu_dr_write_final_pte(struct hl_ctx *ctx, u64 shadow_pte_addr, u64 val)
1283 {
1284 ctx->hdev->asic_funcs->write_pte(ctx->hdev,
1285 hl_mmu_dr_get_phys_addr(ctx, shadow_pte_addr), val);
1286 *(u64 *) (uintptr_t) shadow_pte_addr = val;
1287 }
1288
hl_mmu_dr_clear_pte(struct hl_ctx * ctx,u64 pte_addr)1289 void hl_mmu_dr_clear_pte(struct hl_ctx *ctx, u64 pte_addr)
1290 {
1291 hl_mmu_dr_write_final_pte(ctx, pte_addr, 0);
1292 }
1293
hl_mmu_dr_get_pte(struct hl_ctx * ctx,u64 hop_addr)1294 void hl_mmu_dr_get_pte(struct hl_ctx *ctx, u64 hop_addr)
1295 {
1296 hl_mmu_dr_get_pgt_info(ctx, hop_addr)->num_of_ptes++;
1297 }
1298
hl_mmu_dr_put_pte(struct hl_ctx * ctx,u64 hop_addr)1299 int hl_mmu_dr_put_pte(struct hl_ctx *ctx, u64 hop_addr)
1300 {
1301 struct pgt_info *pgt_info = hl_mmu_dr_get_pgt_info(ctx, hop_addr);
1302 int num_of_ptes_left;
1303
1304 pgt_info->num_of_ptes--;
1305
1306 /*
1307 * Need to save the number of ptes left because hl_mmu_free_hop might free
1308 * the pgt_info
1309 */
1310 num_of_ptes_left = pgt_info->num_of_ptes;
1311 if (!num_of_ptes_left)
1312 hl_mmu_dr_free_pgt_node(ctx, pgt_info);
1313
1314 return num_of_ptes_left;
1315 }
1316
hl_mmu_dr_alloc_hop(struct hl_ctx * ctx)1317 u64 hl_mmu_dr_alloc_hop(struct hl_ctx *ctx)
1318 {
1319 struct hl_device *hdev = ctx->hdev;
1320 struct asic_fixed_properties *prop = &hdev->asic_prop;
1321 struct pgt_info *pgt_info;
1322 u64 phys_addr, shadow_addr;
1323
1324 pgt_info = kmalloc(sizeof(*pgt_info), GFP_KERNEL);
1325 if (!pgt_info)
1326 return ULLONG_MAX;
1327
1328 phys_addr = (u64) gen_pool_alloc(hdev->mmu_priv.dr.mmu_pgt_pool,
1329 prop->dmmu.hop_table_size);
1330 if (!phys_addr) {
1331 dev_err(hdev->dev, "failed to allocate page\n");
1332 goto pool_add_err;
1333 }
1334
1335 shadow_addr = (u64) (uintptr_t) kzalloc(prop->dmmu.hop_table_size,
1336 GFP_KERNEL);
1337 if (!shadow_addr)
1338 goto shadow_err;
1339
1340 pgt_info->phys_addr = phys_addr;
1341 pgt_info->shadow_addr = shadow_addr;
1342 pgt_info->ctx = ctx;
1343 pgt_info->num_of_ptes = 0;
1344 hash_add(ctx->mmu_shadow_hash, &pgt_info->node, shadow_addr);
1345
1346 return shadow_addr;
1347
1348 shadow_err:
1349 gen_pool_free(hdev->mmu_priv.dr.mmu_pgt_pool,
1350 phys_addr, prop->dmmu.hop_table_size);
1351 pool_add_err:
1352 kfree(pgt_info);
1353
1354 return ULLONG_MAX;
1355 }
1356
hl_mmu_dr_get_alloc_next_hop_addr(struct hl_ctx * ctx,u64 curr_pte,bool * is_new_hop)1357 u64 hl_mmu_dr_get_alloc_next_hop_addr(struct hl_ctx *ctx, u64 curr_pte, bool *is_new_hop)
1358 {
1359 u64 hop_addr = hl_mmu_get_next_hop_addr(ctx, curr_pte);
1360
1361 if (hop_addr == ULLONG_MAX) {
1362 hop_addr = hl_mmu_dr_alloc_hop(ctx);
1363 *is_new_hop = (hop_addr != ULLONG_MAX);
1364 }
1365
1366 return hop_addr;
1367 }
1368
hl_mmu_dr_flush(struct hl_ctx * ctx)1369 void hl_mmu_dr_flush(struct hl_ctx *ctx)
1370 {
1371 /* flush all writes from all cores to reach PCI */
1372 mb();
1373 ctx->hdev->asic_funcs->read_pte(ctx->hdev, hl_mmu_dr_get_phys_hop0_addr(ctx));
1374 }
1375
hl_mmu_dr_init(struct hl_device * hdev)1376 int hl_mmu_dr_init(struct hl_device *hdev)
1377 {
1378 struct asic_fixed_properties *prop = &hdev->asic_prop;
1379 int rc;
1380
1381 hdev->mmu_priv.dr.mmu_pgt_pool =
1382 gen_pool_create(__ffs(prop->dmmu.hop_table_size), -1);
1383
1384 if (!hdev->mmu_priv.dr.mmu_pgt_pool) {
1385 dev_err(hdev->dev, "Failed to create page gen pool\n");
1386 return -ENOMEM;
1387 }
1388
1389 rc = gen_pool_add(hdev->mmu_priv.dr.mmu_pgt_pool, prop->mmu_pgt_addr +
1390 prop->dmmu.hop0_tables_total_size,
1391 prop->dmmu.pgt_size - prop->dmmu.hop0_tables_total_size,
1392 -1);
1393 if (rc) {
1394 dev_err(hdev->dev, "Failed to add memory to page gen pool\n");
1395 goto err_pool_add;
1396 }
1397
1398 hdev->mmu_priv.dr.mmu_shadow_hop0 = kvcalloc(prop->max_asid,
1399 prop->dmmu.hop_table_size, GFP_KERNEL);
1400 if (ZERO_OR_NULL_PTR(hdev->mmu_priv.dr.mmu_shadow_hop0)) {
1401 rc = -ENOMEM;
1402 goto err_pool_add;
1403 }
1404
1405 /* MMU H/W init will be done in device hw_init() */
1406
1407 return 0;
1408
1409 err_pool_add:
1410 gen_pool_destroy(hdev->mmu_priv.dr.mmu_pgt_pool);
1411
1412 return rc;
1413 }
1414
hl_mmu_dr_fini(struct hl_device * hdev)1415 void hl_mmu_dr_fini(struct hl_device *hdev)
1416 {
1417 /* MMU H/W fini was already done in device hw_fini() */
1418
1419 if (ZERO_OR_NULL_PTR(hdev->mmu_priv.dr.mmu_shadow_hop0))
1420 return;
1421
1422 kvfree(hdev->mmu_priv.dr.mmu_shadow_hop0);
1423 gen_pool_destroy(hdev->mmu_priv.dr.mmu_pgt_pool);
1424
1425 /* Make sure that if we arrive here again without init was
1426 * called we won't cause kernel panic. This can happen for
1427 * example if we fail during hard reset code at certain points
1428 */
1429 hdev->mmu_priv.dr.mmu_shadow_hop0 = NULL;
1430 }
1431