1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2018 The FreeBSD Foundation
5 * Copyright (c) 1992 Terrence R. Lambert.
6 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
11 *
12 * Portions of this software were developed by A. Joseph Koshy under
13 * sponsorship from the FreeBSD Foundation and Google, Inc.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 * SUCH DAMAGE.
42 */
43
44 #include <sys/cdefs.h>
45 #include "opt_apic.h"
46 #include "opt_atpic.h"
47 #include "opt_cpu.h"
48 #include "opt_ddb.h"
49 #include "opt_inet.h"
50 #include "opt_isa.h"
51 #include "opt_kstack_pages.h"
52 #include "opt_maxmem.h"
53 #include "opt_perfmon.h"
54 #include "opt_platform.h"
55
56 #include <sys/param.h>
57 #include <sys/proc.h>
58 #include <sys/systm.h>
59 #include <sys/bio.h>
60 #include <sys/buf.h>
61 #include <sys/bus.h>
62 #include <sys/callout.h>
63 #include <sys/cons.h>
64 #include <sys/cpu.h>
65 #include <sys/eventhandler.h>
66 #include <sys/exec.h>
67 #include <sys/imgact.h>
68 #include <sys/kdb.h>
69 #include <sys/kernel.h>
70 #include <sys/ktr.h>
71 #include <sys/linker.h>
72 #include <sys/lock.h>
73 #include <sys/malloc.h>
74 #include <sys/memrange.h>
75 #include <sys/msgbuf.h>
76 #include <sys/mutex.h>
77 #include <sys/pcpu.h>
78 #include <sys/ptrace.h>
79 #include <sys/reboot.h>
80 #include <sys/reg.h>
81 #include <sys/rwlock.h>
82 #include <sys/sched.h>
83 #include <sys/signalvar.h>
84 #include <sys/smp.h>
85 #include <sys/syscallsubr.h>
86 #include <sys/sysctl.h>
87 #include <sys/sysent.h>
88 #include <sys/sysproto.h>
89 #include <sys/ucontext.h>
90 #include <sys/vmmeter.h>
91
92 #include <vm/vm.h>
93 #include <vm/vm_param.h>
94 #include <vm/vm_extern.h>
95 #include <vm/vm_kern.h>
96 #include <vm/vm_page.h>
97 #include <vm/vm_map.h>
98 #include <vm/vm_object.h>
99 #include <vm/vm_pager.h>
100 #include <vm/vm_phys.h>
101 #include <vm/vm_dumpset.h>
102
103 #ifdef DDB
104 #ifndef KDB
105 #error KDB must be enabled in order for DDB to work!
106 #endif
107 #include <ddb/ddb.h>
108 #include <ddb/db_sym.h>
109 #endif
110
111 #include <isa/rtc.h>
112
113 #include <net/netisr.h>
114
115 #include <dev/smbios/smbios.h>
116
117 #include <machine/bootinfo.h>
118 #include <machine/clock.h>
119 #include <machine/cpu.h>
120 #include <machine/cputypes.h>
121 #include <machine/intr_machdep.h>
122 #include <x86/mca.h>
123 #include <machine/md_var.h>
124 #include <machine/metadata.h>
125 #include <machine/pc/bios.h>
126 #include <machine/pcb.h>
127 #include <machine/pcb_ext.h>
128 #include <machine/proc.h>
129 #include <machine/sigframe.h>
130 #include <machine/specialreg.h>
131 #include <machine/sysarch.h>
132 #include <machine/trap.h>
133 #include <x86/ucode.h>
134 #include <machine/vm86.h>
135 #include <x86/init.h>
136 #ifdef PERFMON
137 #include <machine/perfmon.h>
138 #endif
139 #ifdef SMP
140 #include <machine/smp.h>
141 #endif
142 #ifdef FDT
143 #include <x86/fdt.h>
144 #endif
145
146 #ifdef DEV_APIC
147 #include <x86/apicvar.h>
148 #endif
149
150 #ifdef DEV_ISA
151 #include <x86/isa/icu.h>
152 #endif
153
154 /* Sanity check for __curthread() */
155 CTASSERT(offsetof(struct pcpu, pc_curthread) == 0);
156
157 register_t init386(int first);
158 void dblfault_handler(void);
159 void identify_cpu(void);
160
161 static void cpu_startup(void *);
162 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
163
164 /* Intel ICH registers */
165 #define ICH_PMBASE 0x400
166 #define ICH_SMI_EN ICH_PMBASE + 0x30
167
168 int _udatasel, _ucodesel;
169 u_int basemem;
170 static int above4g_allow = 1;
171 static int above24g_allow = 0;
172
173 int cold = 1;
174
175 long Maxmem = 0;
176 long realmem = 0;
177 int late_console = 1;
178
179 #ifdef PAE
180 FEATURE(pae, "Physical Address Extensions");
181 #endif
182
183 struct kva_md_info kmi;
184
185 static struct trapframe proc0_tf;
186 struct pcpu __pcpu[MAXCPU];
187
188 static void i386_clock_source_init(void);
189
190 struct mtx icu_lock;
191
192 struct mem_range_softc mem_range_softc;
193
194 extern char start_exceptions[], end_exceptions[];
195
196 extern struct sysentvec elf32_freebsd_sysvec;
197
198 /* Default init_ops implementation. */
199 struct init_ops init_ops = {
200 .early_clock_source_init = i386_clock_source_init,
201 .early_delay = i8254_delay,
202 };
203
204 static void
i386_clock_source_init(void)205 i386_clock_source_init(void)
206 {
207 i8254_init();
208 }
209
210 static void
cpu_startup(void * dummy)211 cpu_startup(void *dummy)
212 {
213 uintmax_t memsize;
214 char *sysenv;
215
216 /*
217 * On MacBooks, we need to disallow the legacy USB circuit to
218 * generate an SMI# because this can cause several problems,
219 * namely: incorrect CPU frequency detection and failure to
220 * start the APs.
221 * We do this by disabling a bit in the SMI_EN (SMI Control and
222 * Enable register) of the Intel ICH LPC Interface Bridge.
223 */
224 sysenv = kern_getenv("smbios.system.product");
225 if (sysenv != NULL) {
226 if (strncmp(sysenv, "MacBook1,1", 10) == 0 ||
227 strncmp(sysenv, "MacBook3,1", 10) == 0 ||
228 strncmp(sysenv, "MacBook4,1", 10) == 0 ||
229 strncmp(sysenv, "MacBookPro1,1", 13) == 0 ||
230 strncmp(sysenv, "MacBookPro1,2", 13) == 0 ||
231 strncmp(sysenv, "MacBookPro3,1", 13) == 0 ||
232 strncmp(sysenv, "MacBookPro4,1", 13) == 0 ||
233 strncmp(sysenv, "Macmini1,1", 10) == 0) {
234 if (bootverbose)
235 printf("Disabling LEGACY_USB_EN bit on "
236 "Intel ICH.\n");
237 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8);
238 }
239 freeenv(sysenv);
240 }
241
242 /*
243 * Good {morning,afternoon,evening,night}.
244 */
245 startrtclock();
246 printcpuinfo();
247 panicifcpuunsupported();
248 #ifdef PERFMON
249 perfmon_init();
250 #endif
251
252 /*
253 * Display physical memory if SMBIOS reports reasonable amount.
254 */
255 memsize = 0;
256 sysenv = kern_getenv("smbios.memory.enabled");
257 if (sysenv != NULL) {
258 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10;
259 freeenv(sysenv);
260 }
261 if (memsize < ptoa((uintmax_t)vm_free_count()))
262 memsize = ptoa((uintmax_t)Maxmem);
263 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20);
264 realmem = atop(memsize);
265
266 /*
267 * Display any holes after the first chunk of extended memory.
268 */
269 if (bootverbose) {
270 int indx;
271
272 printf("Physical memory chunk(s):\n");
273 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
274 vm_paddr_t size;
275
276 size = phys_avail[indx + 1] - phys_avail[indx];
277 printf(
278 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n",
279 (uintmax_t)phys_avail[indx],
280 (uintmax_t)phys_avail[indx + 1] - 1,
281 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE);
282 }
283 }
284
285 vm_ksubmap_init(&kmi);
286
287 printf("avail memory = %ju (%ju MB)\n",
288 ptoa((uintmax_t)vm_free_count()),
289 ptoa((uintmax_t)vm_free_count()) / 1048576);
290
291 /*
292 * Set up buffers, so they can be used to read disk labels.
293 */
294 bufinit();
295 vm_pager_bufferinit();
296 cpu_setregs();
297 }
298
299 void
cpu_setregs(void)300 cpu_setregs(void)
301 {
302 unsigned int cr0;
303
304 cr0 = rcr0();
305
306 /*
307 * CR0_MP, CR0_NE and CR0_TS are set for NPX (FPU) support:
308 *
309 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
310 * instructions. We must set the CR0_MP bit and use the CR0_TS
311 * bit to control the trap, because setting the CR0_EM bit does
312 * not cause WAIT instructions to trap. It's important to trap
313 * WAIT instructions - otherwise the "wait" variants of no-wait
314 * control instructions would degenerate to the "no-wait" variants
315 * after FP context switches but work correctly otherwise. It's
316 * particularly important to trap WAITs when there is no NPX -
317 * otherwise the "wait" variants would always degenerate.
318 *
319 * Try setting CR0_NE to get correct error reporting on 486DX's.
320 * Setting it should fail or do nothing on lesser processors.
321 */
322 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM;
323 load_cr0(cr0);
324 load_gs(_udatasel);
325 }
326
327 u_long bootdev; /* not a struct cdev *- encoding is different */
328 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
329 CTLFLAG_RD, &bootdev, 0, "Maybe the Boot device (not in struct cdev *format)");
330
331 /*
332 * Initialize 386 and configure to run kernel
333 */
334
335 /*
336 * Initialize segments & interrupt table
337 */
338
339 int _default_ldt;
340
341 struct mtx dt_lock; /* lock for GDT and LDT */
342
343 union descriptor gdt0[NGDT]; /* initial global descriptor table */
344 union descriptor *gdt = gdt0; /* global descriptor table */
345
346 union descriptor *ldt; /* local descriptor table */
347
348 static struct gate_descriptor idt0[NIDT];
349 struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
350
351 static struct i386tss *dblfault_tss;
352 static char *dblfault_stack;
353
354 static struct i386tss common_tss0;
355
356 vm_offset_t proc0kstack;
357
358 /*
359 * software prototypes -- in more palatable form.
360 *
361 * GCODE_SEL through GUDATA_SEL must be in this order for syscall/sysret
362 * GUFS_SEL and GUGS_SEL must be in this order (swtch.s knows it)
363 */
364 struct soft_segment_descriptor gdt_segs[] = {
365 /* GNULL_SEL 0 Null Descriptor */
366 { .ssd_base = 0x0,
367 .ssd_limit = 0x0,
368 .ssd_type = 0,
369 .ssd_dpl = SEL_KPL,
370 .ssd_p = 0,
371 .ssd_xx = 0, .ssd_xx1 = 0,
372 .ssd_def32 = 0,
373 .ssd_gran = 0 },
374 /* GPRIV_SEL 1 SMP Per-Processor Private Data Descriptor */
375 { .ssd_base = 0x0,
376 .ssd_limit = 0xfffff,
377 .ssd_type = SDT_MEMRWA,
378 .ssd_dpl = SEL_KPL,
379 .ssd_p = 1,
380 .ssd_xx = 0, .ssd_xx1 = 0,
381 .ssd_def32 = 1,
382 .ssd_gran = 1 },
383 /* GUFS_SEL 2 %fs Descriptor for user */
384 { .ssd_base = 0x0,
385 .ssd_limit = 0xfffff,
386 .ssd_type = SDT_MEMRWA,
387 .ssd_dpl = SEL_UPL,
388 .ssd_p = 1,
389 .ssd_xx = 0, .ssd_xx1 = 0,
390 .ssd_def32 = 1,
391 .ssd_gran = 1 },
392 /* GUGS_SEL 3 %gs Descriptor for user */
393 { .ssd_base = 0x0,
394 .ssd_limit = 0xfffff,
395 .ssd_type = SDT_MEMRWA,
396 .ssd_dpl = SEL_UPL,
397 .ssd_p = 1,
398 .ssd_xx = 0, .ssd_xx1 = 0,
399 .ssd_def32 = 1,
400 .ssd_gran = 1 },
401 /* GCODE_SEL 4 Code Descriptor for kernel */
402 { .ssd_base = 0x0,
403 .ssd_limit = 0xfffff,
404 .ssd_type = SDT_MEMERA,
405 .ssd_dpl = SEL_KPL,
406 .ssd_p = 1,
407 .ssd_xx = 0, .ssd_xx1 = 0,
408 .ssd_def32 = 1,
409 .ssd_gran = 1 },
410 /* GDATA_SEL 5 Data Descriptor for kernel */
411 { .ssd_base = 0x0,
412 .ssd_limit = 0xfffff,
413 .ssd_type = SDT_MEMRWA,
414 .ssd_dpl = SEL_KPL,
415 .ssd_p = 1,
416 .ssd_xx = 0, .ssd_xx1 = 0,
417 .ssd_def32 = 1,
418 .ssd_gran = 1 },
419 /* GUCODE_SEL 6 Code Descriptor for user */
420 { .ssd_base = 0x0,
421 .ssd_limit = 0xfffff,
422 .ssd_type = SDT_MEMERA,
423 .ssd_dpl = SEL_UPL,
424 .ssd_p = 1,
425 .ssd_xx = 0, .ssd_xx1 = 0,
426 .ssd_def32 = 1,
427 .ssd_gran = 1 },
428 /* GUDATA_SEL 7 Data Descriptor for user */
429 { .ssd_base = 0x0,
430 .ssd_limit = 0xfffff,
431 .ssd_type = SDT_MEMRWA,
432 .ssd_dpl = SEL_UPL,
433 .ssd_p = 1,
434 .ssd_xx = 0, .ssd_xx1 = 0,
435 .ssd_def32 = 1,
436 .ssd_gran = 1 },
437 /* GBIOSLOWMEM_SEL 8 BIOS access to realmode segment 0x40, must be #8 in GDT */
438 { .ssd_base = 0x400,
439 .ssd_limit = 0xfffff,
440 .ssd_type = SDT_MEMRWA,
441 .ssd_dpl = SEL_KPL,
442 .ssd_p = 1,
443 .ssd_xx = 0, .ssd_xx1 = 0,
444 .ssd_def32 = 1,
445 .ssd_gran = 1 },
446 /* GPROC0_SEL 9 Proc 0 Tss Descriptor */
447 {
448 .ssd_base = 0x0,
449 .ssd_limit = sizeof(struct i386tss)-1,
450 .ssd_type = SDT_SYS386TSS,
451 .ssd_dpl = 0,
452 .ssd_p = 1,
453 .ssd_xx = 0, .ssd_xx1 = 0,
454 .ssd_def32 = 0,
455 .ssd_gran = 0 },
456 /* GLDT_SEL 10 LDT Descriptor */
457 { .ssd_base = 0,
458 .ssd_limit = sizeof(union descriptor) * NLDT - 1,
459 .ssd_type = SDT_SYSLDT,
460 .ssd_dpl = SEL_UPL,
461 .ssd_p = 1,
462 .ssd_xx = 0, .ssd_xx1 = 0,
463 .ssd_def32 = 0,
464 .ssd_gran = 0 },
465 /* GUSERLDT_SEL 11 User LDT Descriptor per process */
466 { .ssd_base = 0,
467 .ssd_limit = (512 * sizeof(union descriptor)-1),
468 .ssd_type = SDT_SYSLDT,
469 .ssd_dpl = 0,
470 .ssd_p = 1,
471 .ssd_xx = 0, .ssd_xx1 = 0,
472 .ssd_def32 = 0,
473 .ssd_gran = 0 },
474 /* GPANIC_SEL 12 Panic Tss Descriptor */
475 { .ssd_base = 0,
476 .ssd_limit = sizeof(struct i386tss)-1,
477 .ssd_type = SDT_SYS386TSS,
478 .ssd_dpl = 0,
479 .ssd_p = 1,
480 .ssd_xx = 0, .ssd_xx1 = 0,
481 .ssd_def32 = 0,
482 .ssd_gran = 0 },
483 /* GBIOSCODE32_SEL 13 BIOS 32-bit interface (32bit Code) */
484 { .ssd_base = 0,
485 .ssd_limit = 0xfffff,
486 .ssd_type = SDT_MEMERA,
487 .ssd_dpl = 0,
488 .ssd_p = 1,
489 .ssd_xx = 0, .ssd_xx1 = 0,
490 .ssd_def32 = 0,
491 .ssd_gran = 1 },
492 /* GBIOSCODE16_SEL 14 BIOS 32-bit interface (16bit Code) */
493 { .ssd_base = 0,
494 .ssd_limit = 0xfffff,
495 .ssd_type = SDT_MEMERA,
496 .ssd_dpl = 0,
497 .ssd_p = 1,
498 .ssd_xx = 0, .ssd_xx1 = 0,
499 .ssd_def32 = 0,
500 .ssd_gran = 1 },
501 /* GBIOSDATA_SEL 15 BIOS 32-bit interface (Data) */
502 { .ssd_base = 0,
503 .ssd_limit = 0xfffff,
504 .ssd_type = SDT_MEMRWA,
505 .ssd_dpl = 0,
506 .ssd_p = 1,
507 .ssd_xx = 0, .ssd_xx1 = 0,
508 .ssd_def32 = 1,
509 .ssd_gran = 1 },
510 /* GBIOSUTIL_SEL 16 BIOS 16-bit interface (Utility) */
511 { .ssd_base = 0,
512 .ssd_limit = 0xfffff,
513 .ssd_type = SDT_MEMRWA,
514 .ssd_dpl = 0,
515 .ssd_p = 1,
516 .ssd_xx = 0, .ssd_xx1 = 0,
517 .ssd_def32 = 0,
518 .ssd_gran = 1 },
519 /* GBIOSARGS_SEL 17 BIOS 16-bit interface (Arguments) */
520 { .ssd_base = 0,
521 .ssd_limit = 0xfffff,
522 .ssd_type = SDT_MEMRWA,
523 .ssd_dpl = 0,
524 .ssd_p = 1,
525 .ssd_xx = 0, .ssd_xx1 = 0,
526 .ssd_def32 = 0,
527 .ssd_gran = 1 },
528 /* GNDIS_SEL 18 NDIS Descriptor */
529 { .ssd_base = 0x0,
530 .ssd_limit = 0x0,
531 .ssd_type = 0,
532 .ssd_dpl = 0,
533 .ssd_p = 0,
534 .ssd_xx = 0, .ssd_xx1 = 0,
535 .ssd_def32 = 0,
536 .ssd_gran = 0 },
537 };
538
539 static struct soft_segment_descriptor ldt_segs[] = {
540 /* Null Descriptor - overwritten by call gate */
541 { .ssd_base = 0x0,
542 .ssd_limit = 0x0,
543 .ssd_type = 0,
544 .ssd_dpl = 0,
545 .ssd_p = 0,
546 .ssd_xx = 0, .ssd_xx1 = 0,
547 .ssd_def32 = 0,
548 .ssd_gran = 0 },
549 /* Null Descriptor - overwritten by call gate */
550 { .ssd_base = 0x0,
551 .ssd_limit = 0x0,
552 .ssd_type = 0,
553 .ssd_dpl = 0,
554 .ssd_p = 0,
555 .ssd_xx = 0, .ssd_xx1 = 0,
556 .ssd_def32 = 0,
557 .ssd_gran = 0 },
558 /* Null Descriptor - overwritten by call gate */
559 { .ssd_base = 0x0,
560 .ssd_limit = 0x0,
561 .ssd_type = 0,
562 .ssd_dpl = 0,
563 .ssd_p = 0,
564 .ssd_xx = 0, .ssd_xx1 = 0,
565 .ssd_def32 = 0,
566 .ssd_gran = 0 },
567 /* Code Descriptor for user */
568 { .ssd_base = 0x0,
569 .ssd_limit = 0xfffff,
570 .ssd_type = SDT_MEMERA,
571 .ssd_dpl = SEL_UPL,
572 .ssd_p = 1,
573 .ssd_xx = 0, .ssd_xx1 = 0,
574 .ssd_def32 = 1,
575 .ssd_gran = 1 },
576 /* Null Descriptor - overwritten by call gate */
577 { .ssd_base = 0x0,
578 .ssd_limit = 0x0,
579 .ssd_type = 0,
580 .ssd_dpl = 0,
581 .ssd_p = 0,
582 .ssd_xx = 0, .ssd_xx1 = 0,
583 .ssd_def32 = 0,
584 .ssd_gran = 0 },
585 /* Data Descriptor for user */
586 { .ssd_base = 0x0,
587 .ssd_limit = 0xfffff,
588 .ssd_type = SDT_MEMRWA,
589 .ssd_dpl = SEL_UPL,
590 .ssd_p = 1,
591 .ssd_xx = 0, .ssd_xx1 = 0,
592 .ssd_def32 = 1,
593 .ssd_gran = 1 },
594 };
595
596 size_t setidt_disp;
597
598 void
setidt(int idx,inthand_t * func,int typ,int dpl,int selec)599 setidt(int idx, inthand_t *func, int typ, int dpl, int selec)
600 {
601 uintptr_t off;
602
603 off = func != NULL ? (uintptr_t)func + setidt_disp : 0;
604 setidt_nodisp(idx, off, typ, dpl, selec);
605 }
606
607 void
setidt_nodisp(int idx,uintptr_t off,int typ,int dpl,int selec)608 setidt_nodisp(int idx, uintptr_t off, int typ, int dpl, int selec)
609 {
610 struct gate_descriptor *ip;
611
612 ip = idt + idx;
613 ip->gd_looffset = off;
614 ip->gd_selector = selec;
615 ip->gd_stkcpy = 0;
616 ip->gd_xx = 0;
617 ip->gd_type = typ;
618 ip->gd_dpl = dpl;
619 ip->gd_p = 1;
620 ip->gd_hioffset = ((u_int)off) >> 16 ;
621 }
622
623 extern inthand_t
624 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
625 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
626 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
627 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
628 IDTVEC(xmm),
629 #ifdef KDTRACE_HOOKS
630 IDTVEC(dtrace_ret),
631 #endif
632 #ifdef XENHVM
633 IDTVEC(xen_intr_upcall),
634 #endif
635 IDTVEC(int0x80_syscall);
636
637 #ifdef DDB
638 /*
639 * Display the index and function name of any IDT entries that don't use
640 * the default 'rsvd' entry point.
641 */
DB_SHOW_COMMAND_FLAGS(idt,db_show_idt,DB_CMD_MEMSAFE)642 DB_SHOW_COMMAND_FLAGS(idt, db_show_idt, DB_CMD_MEMSAFE)
643 {
644 struct gate_descriptor *ip;
645 int idx;
646 uintptr_t func, func_trm;
647 bool trm;
648
649 ip = idt;
650 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) {
651 if (ip->gd_type == SDT_SYSTASKGT) {
652 db_printf("%3d\t<TASK>\n", idx);
653 } else {
654 func = (ip->gd_hioffset << 16 | ip->gd_looffset);
655 if (func >= PMAP_TRM_MIN_ADDRESS) {
656 func_trm = func;
657 func -= setidt_disp;
658 trm = true;
659 } else
660 trm = false;
661 if (func != (uintptr_t)&IDTVEC(rsvd)) {
662 db_printf("%3d\t", idx);
663 db_printsym(func, DB_STGY_PROC);
664 if (trm)
665 db_printf(" (trampoline %#x)",
666 func_trm);
667 db_printf("\n");
668 }
669 }
670 ip++;
671 }
672 }
673
674 /* Show privileged registers. */
DB_SHOW_COMMAND_FLAGS(sysregs,db_show_sysregs,DB_CMD_MEMSAFE)675 DB_SHOW_COMMAND_FLAGS(sysregs, db_show_sysregs, DB_CMD_MEMSAFE)
676 {
677 uint64_t idtr, gdtr;
678
679 idtr = ridt();
680 db_printf("idtr\t0x%08x/%04x\n",
681 (u_int)(idtr >> 16), (u_int)idtr & 0xffff);
682 gdtr = rgdt();
683 db_printf("gdtr\t0x%08x/%04x\n",
684 (u_int)(gdtr >> 16), (u_int)gdtr & 0xffff);
685 db_printf("ldtr\t0x%04x\n", rldt());
686 db_printf("tr\t0x%04x\n", rtr());
687 db_printf("cr0\t0x%08x\n", rcr0());
688 db_printf("cr2\t0x%08x\n", rcr2());
689 db_printf("cr3\t0x%08x\n", rcr3());
690 db_printf("cr4\t0x%08x\n", rcr4());
691 if (rcr4() & CR4_XSAVE)
692 db_printf("xcr0\t0x%016llx\n", rxcr(0));
693 if (amd_feature & (AMDID_NX | AMDID_LM))
694 db_printf("EFER\t0x%016llx\n", rdmsr(MSR_EFER));
695 if (cpu_feature2 & (CPUID2_VMX | CPUID2_SMX))
696 db_printf("FEATURES_CTL\t0x%016llx\n",
697 rdmsr(MSR_IA32_FEATURE_CONTROL));
698 if (((cpu_vendor_id == CPU_VENDOR_INTEL ||
699 cpu_vendor_id == CPU_VENDOR_AMD) && CPUID_TO_FAMILY(cpu_id) >= 6) ||
700 cpu_vendor_id == CPU_VENDOR_HYGON)
701 db_printf("DEBUG_CTL\t0x%016llx\n", rdmsr(MSR_DEBUGCTLMSR));
702 if (cpu_feature & CPUID_PAT)
703 db_printf("PAT\t0x%016llx\n", rdmsr(MSR_PAT));
704 }
705
DB_SHOW_COMMAND_FLAGS(dbregs,db_show_dbregs,DB_CMD_MEMSAFE)706 DB_SHOW_COMMAND_FLAGS(dbregs, db_show_dbregs, DB_CMD_MEMSAFE)
707 {
708
709 db_printf("dr0\t0x%08x\n", rdr0());
710 db_printf("dr1\t0x%08x\n", rdr1());
711 db_printf("dr2\t0x%08x\n", rdr2());
712 db_printf("dr3\t0x%08x\n", rdr3());
713 db_printf("dr6\t0x%08x\n", rdr6());
714 db_printf("dr7\t0x%08x\n", rdr7());
715 }
716
DB_SHOW_COMMAND(frame,db_show_frame)717 DB_SHOW_COMMAND(frame, db_show_frame)
718 {
719 struct trapframe *frame;
720
721 frame = have_addr ? (struct trapframe *)addr : curthread->td_frame;
722 printf("ss %#x esp %#x efl %#x cs %#x eip %#x\n",
723 frame->tf_ss, frame->tf_esp, frame->tf_eflags, frame->tf_cs,
724 frame->tf_eip);
725 printf("err %#x trapno %d\n", frame->tf_err, frame->tf_trapno);
726 printf("ds %#x es %#x fs %#x\n",
727 frame->tf_ds, frame->tf_es, frame->tf_fs);
728 printf("eax %#x ecx %#x edx %#x ebx %#x\n",
729 frame->tf_eax, frame->tf_ecx, frame->tf_edx, frame->tf_ebx);
730 printf("ebp %#x esi %#x edi %#x\n",
731 frame->tf_ebp, frame->tf_esi, frame->tf_edi);
732
733 }
734 #endif
735
736 void
sdtossd(struct segment_descriptor * sd,struct soft_segment_descriptor * ssd)737 sdtossd(struct segment_descriptor *sd, struct soft_segment_descriptor *ssd)
738 {
739 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
740 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
741 ssd->ssd_type = sd->sd_type;
742 ssd->ssd_dpl = sd->sd_dpl;
743 ssd->ssd_p = sd->sd_p;
744 ssd->ssd_def32 = sd->sd_def32;
745 ssd->ssd_gran = sd->sd_gran;
746 }
747
748 static int
add_physmap_entry(uint64_t base,uint64_t length,vm_paddr_t * physmap,int * physmap_idxp)749 add_physmap_entry(uint64_t base, uint64_t length, vm_paddr_t *physmap,
750 int *physmap_idxp)
751 {
752 uint64_t lim, ign;
753 int i, insert_idx, physmap_idx;
754
755 physmap_idx = *physmap_idxp;
756
757 if (length == 0)
758 return (1);
759
760 lim = 0x100000000; /* 4G */
761 if (pae_mode && above4g_allow)
762 lim = above24g_allow ? -1ULL : 0x600000000; /* 24G */
763 if (base >= lim) {
764 printf("%uK of memory above %uGB ignored, pae %d "
765 "above4g_allow %d above24g_allow %d\n",
766 (u_int)(length / 1024), (u_int)(lim >> 30), pae_mode,
767 above4g_allow, above24g_allow);
768 return (1);
769 }
770 if (base + length >= lim) {
771 ign = base + length - lim;
772 length -= ign;
773 printf("%uK of memory above %uGB ignored, pae %d "
774 "above4g_allow %d above24g_allow %d\n",
775 (u_int)(ign / 1024), (u_int)(lim >> 30), pae_mode,
776 above4g_allow, above24g_allow);
777 }
778
779 /*
780 * Find insertion point while checking for overlap. Start off by
781 * assuming the new entry will be added to the end.
782 */
783 insert_idx = physmap_idx + 2;
784 for (i = 0; i <= physmap_idx; i += 2) {
785 if (base < physmap[i + 1]) {
786 if (base + length <= physmap[i]) {
787 insert_idx = i;
788 break;
789 }
790 if (boothowto & RB_VERBOSE)
791 printf(
792 "Overlapping memory regions, ignoring second region\n");
793 return (1);
794 }
795 }
796
797 /* See if we can prepend to the next entry. */
798 if (insert_idx <= physmap_idx && base + length == physmap[insert_idx]) {
799 physmap[insert_idx] = base;
800 return (1);
801 }
802
803 /* See if we can append to the previous entry. */
804 if (insert_idx > 0 && base == physmap[insert_idx - 1]) {
805 physmap[insert_idx - 1] += length;
806 return (1);
807 }
808
809 physmap_idx += 2;
810 *physmap_idxp = physmap_idx;
811 if (physmap_idx == PHYS_AVAIL_ENTRIES) {
812 printf(
813 "Too many segments in the physical address map, giving up\n");
814 return (0);
815 }
816
817 /*
818 * Move the last 'N' entries down to make room for the new
819 * entry if needed.
820 */
821 for (i = physmap_idx; i > insert_idx; i -= 2) {
822 physmap[i] = physmap[i - 2];
823 physmap[i + 1] = physmap[i - 1];
824 }
825
826 /* Insert the new entry. */
827 physmap[insert_idx] = base;
828 physmap[insert_idx + 1] = base + length;
829 return (1);
830 }
831
832 static int
add_smap_entry(struct bios_smap * smap,vm_paddr_t * physmap,int * physmap_idxp)833 add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp)
834 {
835 if (boothowto & RB_VERBOSE)
836 printf("SMAP type=%02x base=%016llx len=%016llx\n",
837 smap->type, smap->base, smap->length);
838
839 if (smap->type != SMAP_TYPE_MEMORY)
840 return (1);
841
842 return (add_physmap_entry(smap->base, smap->length, physmap,
843 physmap_idxp));
844 }
845
846 static void
add_smap_entries(struct bios_smap * smapbase,vm_paddr_t * physmap,int * physmap_idxp)847 add_smap_entries(struct bios_smap *smapbase, vm_paddr_t *physmap,
848 int *physmap_idxp)
849 {
850 struct bios_smap *smap, *smapend;
851 u_int32_t smapsize;
852 /*
853 * Memory map from INT 15:E820.
854 *
855 * subr_module.c says:
856 * "Consumer may safely assume that size value precedes data."
857 * ie: an int32_t immediately precedes SMAP.
858 */
859 smapsize = *((u_int32_t *)smapbase - 1);
860 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
861
862 for (smap = smapbase; smap < smapend; smap++)
863 if (!add_smap_entry(smap, physmap, physmap_idxp))
864 break;
865 }
866
867 static void
basemem_setup(void)868 basemem_setup(void)
869 {
870
871 if (basemem > 640) {
872 printf("Preposterous BIOS basemem of %uK, truncating to 640K\n",
873 basemem);
874 basemem = 640;
875 }
876
877 pmap_basemem_setup(basemem);
878 }
879
880 /*
881 * Populate the (physmap) array with base/bound pairs describing the
882 * available physical memory in the system, then test this memory and
883 * build the phys_avail array describing the actually-available memory.
884 *
885 * If we cannot accurately determine the physical memory map, then use
886 * value from the 0xE801 call, and failing that, the RTC.
887 *
888 * Total memory size may be set by the kernel environment variable
889 * hw.physmem or the compile-time define MAXMEM.
890 *
891 * XXX first should be vm_paddr_t.
892 */
893 static void
getmemsize(int first)894 getmemsize(int first)
895 {
896 int has_smap, off, physmap_idx, pa_indx, da_indx;
897 u_long memtest;
898 vm_paddr_t physmap[PHYS_AVAIL_ENTRIES];
899 quad_t dcons_addr, dcons_size, physmem_tunable;
900 int hasbrokenint12, i, res __diagused;
901 u_int extmem;
902 struct vm86frame vmf;
903 struct vm86context vmc;
904 vm_paddr_t pa;
905 struct bios_smap *smap, *smapbase;
906 caddr_t kmdp;
907
908 has_smap = 0;
909 bzero(&vmf, sizeof(vmf));
910 bzero(physmap, sizeof(physmap));
911 basemem = 0;
912
913 /*
914 * Tell the physical memory allocator about pages used to store
915 * the kernel and preloaded data. See kmem_bootstrap_free().
916 */
917 vm_phys_early_add_seg((vm_paddr_t)KERNLOAD, trunc_page(first));
918
919 TUNABLE_INT_FETCH("hw.above4g_allow", &above4g_allow);
920 TUNABLE_INT_FETCH("hw.above24g_allow", &above24g_allow);
921
922 /*
923 * Check if the loader supplied an SMAP memory map. If so,
924 * use that and do not make any VM86 calls.
925 */
926 physmap_idx = 0;
927 kmdp = preload_search_by_type("elf kernel");
928 if (kmdp == NULL)
929 kmdp = preload_search_by_type("elf32 kernel");
930 smapbase = (struct bios_smap *)preload_search_info(kmdp,
931 MODINFO_METADATA | MODINFOMD_SMAP);
932 if (smapbase != NULL) {
933 add_smap_entries(smapbase, physmap, &physmap_idx);
934 has_smap = 1;
935 goto have_smap;
936 }
937
938 /*
939 * Some newer BIOSes have a broken INT 12H implementation
940 * which causes a kernel panic immediately. In this case, we
941 * need use the SMAP to determine the base memory size.
942 */
943 hasbrokenint12 = 0;
944 TUNABLE_INT_FETCH("hw.hasbrokenint12", &hasbrokenint12);
945 if (hasbrokenint12 == 0) {
946 /* Use INT12 to determine base memory size. */
947 vm86_intcall(0x12, &vmf);
948 basemem = vmf.vmf_ax;
949 basemem_setup();
950 }
951
952 /*
953 * Fetch the memory map with INT 15:E820. Map page 1 R/W into
954 * the kernel page table so we can use it as a buffer. The
955 * kernel will unmap this page later.
956 */
957 vmc.npages = 0;
958 smap = (void *)vm86_addpage(&vmc, 1, PMAP_MAP_LOW + ptoa(1));
959 res = vm86_getptr(&vmc, (vm_offset_t)smap, &vmf.vmf_es, &vmf.vmf_di);
960 KASSERT(res != 0, ("vm86_getptr() failed: address not found"));
961
962 vmf.vmf_ebx = 0;
963 do {
964 vmf.vmf_eax = 0xE820;
965 vmf.vmf_edx = SMAP_SIG;
966 vmf.vmf_ecx = sizeof(struct bios_smap);
967 i = vm86_datacall(0x15, &vmf, &vmc);
968 if (i || vmf.vmf_eax != SMAP_SIG)
969 break;
970 has_smap = 1;
971 if (!add_smap_entry(smap, physmap, &physmap_idx))
972 break;
973 } while (vmf.vmf_ebx != 0);
974
975 have_smap:
976 /*
977 * If we didn't fetch the "base memory" size from INT12,
978 * figure it out from the SMAP (or just guess).
979 */
980 if (basemem == 0) {
981 for (i = 0; i <= physmap_idx; i += 2) {
982 if (physmap[i] == 0x00000000) {
983 basemem = physmap[i + 1] / 1024;
984 break;
985 }
986 }
987
988 /* XXX: If we couldn't find basemem from SMAP, just guess. */
989 if (basemem == 0)
990 basemem = 640;
991 basemem_setup();
992 }
993
994 if (physmap[1] != 0)
995 goto physmap_done;
996
997 /*
998 * If we failed to find an SMAP, figure out the extended
999 * memory size. We will then build a simple memory map with
1000 * two segments, one for "base memory" and the second for
1001 * "extended memory". Note that "extended memory" starts at a
1002 * physical address of 1MB and that both basemem and extmem
1003 * are in units of 1KB.
1004 *
1005 * First, try to fetch the extended memory size via INT 15:E801.
1006 */
1007 vmf.vmf_ax = 0xE801;
1008 if (vm86_intcall(0x15, &vmf) == 0) {
1009 extmem = vmf.vmf_cx + vmf.vmf_dx * 64;
1010 } else {
1011 /*
1012 * If INT15:E801 fails, this is our last ditch effort
1013 * to determine the extended memory size. Currently
1014 * we prefer the RTC value over INT15:88.
1015 */
1016 #if 0
1017 vmf.vmf_ah = 0x88;
1018 vm86_intcall(0x15, &vmf);
1019 extmem = vmf.vmf_ax;
1020 #else
1021 extmem = rtcin(RTC_EXTLO) + (rtcin(RTC_EXTHI) << 8);
1022 #endif
1023 }
1024
1025 /*
1026 * Special hack for chipsets that still remap the 384k hole when
1027 * there's 16MB of memory - this really confuses people that
1028 * are trying to use bus mastering ISA controllers with the
1029 * "16MB limit"; they only have 16MB, but the remapping puts
1030 * them beyond the limit.
1031 *
1032 * If extended memory is between 15-16MB (16-17MB phys address range),
1033 * chop it to 15MB.
1034 */
1035 if ((extmem > 15 * 1024) && (extmem < 16 * 1024))
1036 extmem = 15 * 1024;
1037
1038 physmap[0] = 0;
1039 physmap[1] = basemem * 1024;
1040 physmap_idx = 2;
1041 physmap[physmap_idx] = 0x100000;
1042 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024;
1043
1044 physmap_done:
1045 /*
1046 * Now, physmap contains a map of physical memory.
1047 */
1048
1049 #ifdef SMP
1050 /* make hole for AP bootstrap code */
1051 alloc_ap_trampoline(physmap, &physmap_idx);
1052 #endif
1053
1054 /*
1055 * Maxmem isn't the "maximum memory", it's one larger than the
1056 * highest page of the physical address space. It should be
1057 * called something like "Maxphyspage". We may adjust this
1058 * based on ``hw.physmem'' and the results of the memory test.
1059 *
1060 * This is especially confusing when it is much larger than the
1061 * memory size and is displayed as "realmem".
1062 */
1063 Maxmem = atop(physmap[physmap_idx + 1]);
1064
1065 #ifdef MAXMEM
1066 Maxmem = MAXMEM / 4;
1067 #endif
1068
1069 if (TUNABLE_QUAD_FETCH("hw.physmem", &physmem_tunable))
1070 Maxmem = atop(physmem_tunable);
1071
1072 /*
1073 * If we have an SMAP, don't allow MAXMEM or hw.physmem to extend
1074 * the amount of memory in the system.
1075 */
1076 if (has_smap && Maxmem > atop(physmap[physmap_idx + 1]))
1077 Maxmem = atop(physmap[physmap_idx + 1]);
1078
1079 /*
1080 * The boot memory test is disabled by default, as it takes a
1081 * significant amount of time on large-memory systems, and is
1082 * unfriendly to virtual machines as it unnecessarily touches all
1083 * pages.
1084 *
1085 * A general name is used as the code may be extended to support
1086 * additional tests beyond the current "page present" test.
1087 */
1088 memtest = 0;
1089 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest);
1090
1091 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1092 (boothowto & RB_VERBOSE))
1093 printf("Physical memory use set to %ldK\n", Maxmem * 4);
1094
1095 /*
1096 * If Maxmem has been increased beyond what the system has detected,
1097 * extend the last memory segment to the new limit.
1098 */
1099 if (atop(physmap[physmap_idx + 1]) < Maxmem)
1100 physmap[physmap_idx + 1] = ptoa((vm_paddr_t)Maxmem);
1101
1102 /* call pmap initialization to make new kernel address space */
1103 pmap_bootstrap(first);
1104
1105 /*
1106 * Size up each available chunk of physical memory.
1107 */
1108 physmap[0] = PAGE_SIZE; /* mask off page 0 */
1109 pa_indx = 0;
1110 da_indx = 1;
1111 phys_avail[pa_indx++] = physmap[0];
1112 phys_avail[pa_indx] = physmap[0];
1113 dump_avail[da_indx] = physmap[0];
1114
1115 /*
1116 * Get dcons buffer address
1117 */
1118 if (getenv_quad("dcons.addr", &dcons_addr) == 0 ||
1119 getenv_quad("dcons.size", &dcons_size) == 0)
1120 dcons_addr = 0;
1121
1122 /*
1123 * physmap is in bytes, so when converting to page boundaries,
1124 * round up the start address and round down the end address.
1125 */
1126 for (i = 0; i <= physmap_idx; i += 2) {
1127 vm_paddr_t end;
1128
1129 end = ptoa((vm_paddr_t)Maxmem);
1130 if (physmap[i + 1] < end)
1131 end = trunc_page(physmap[i + 1]);
1132 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
1133 int *ptr;
1134 int tmp;
1135 bool full, page_bad;
1136
1137 full = false;
1138 /*
1139 * block out kernel memory as not available.
1140 */
1141 if (pa >= KERNLOAD && pa < first)
1142 goto do_dump_avail;
1143
1144 /*
1145 * block out dcons buffer
1146 */
1147 if (dcons_addr > 0
1148 && pa >= trunc_page(dcons_addr)
1149 && pa < dcons_addr + dcons_size)
1150 goto do_dump_avail;
1151
1152 page_bad = false;
1153 if (memtest == 0)
1154 goto skip_memtest;
1155
1156 /*
1157 * map page into kernel: valid, read/write,non-cacheable
1158 */
1159 ptr = (int *)pmap_cmap3(pa, PG_V | PG_RW | PG_N);
1160
1161 tmp = *(int *)ptr;
1162 /*
1163 * Test for alternating 1's and 0's
1164 */
1165 *(volatile int *)ptr = 0xaaaaaaaa;
1166 if (*(volatile int *)ptr != 0xaaaaaaaa)
1167 page_bad = true;
1168 /*
1169 * Test for alternating 0's and 1's
1170 */
1171 *(volatile int *)ptr = 0x55555555;
1172 if (*(volatile int *)ptr != 0x55555555)
1173 page_bad = true;
1174 /*
1175 * Test for all 1's
1176 */
1177 *(volatile int *)ptr = 0xffffffff;
1178 if (*(volatile int *)ptr != 0xffffffff)
1179 page_bad = true;
1180 /*
1181 * Test for all 0's
1182 */
1183 *(volatile int *)ptr = 0x0;
1184 if (*(volatile int *)ptr != 0x0)
1185 page_bad = true;
1186 /*
1187 * Restore original value.
1188 */
1189 *(int *)ptr = tmp;
1190
1191 skip_memtest:
1192 /*
1193 * Adjust array of valid/good pages.
1194 */
1195 if (page_bad == true)
1196 continue;
1197 /*
1198 * If this good page is a continuation of the
1199 * previous set of good pages, then just increase
1200 * the end pointer. Otherwise start a new chunk.
1201 * Note that "end" points one higher than end,
1202 * making the range >= start and < end.
1203 * If we're also doing a speculative memory
1204 * test and we at or past the end, bump up Maxmem
1205 * so that we keep going. The first bad page
1206 * will terminate the loop.
1207 */
1208 if (phys_avail[pa_indx] == pa) {
1209 phys_avail[pa_indx] += PAGE_SIZE;
1210 } else {
1211 pa_indx++;
1212 if (pa_indx == PHYS_AVAIL_ENTRIES) {
1213 printf(
1214 "Too many holes in the physical address space, giving up\n");
1215 pa_indx--;
1216 full = true;
1217 goto do_dump_avail;
1218 }
1219 phys_avail[pa_indx++] = pa; /* start */
1220 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
1221 }
1222 physmem++;
1223 do_dump_avail:
1224 if (dump_avail[da_indx] == pa) {
1225 dump_avail[da_indx] += PAGE_SIZE;
1226 } else {
1227 da_indx++;
1228 if (da_indx == PHYS_AVAIL_ENTRIES) {
1229 da_indx--;
1230 goto do_next;
1231 }
1232 dump_avail[da_indx++] = pa; /* start */
1233 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */
1234 }
1235 do_next:
1236 if (full)
1237 break;
1238 }
1239 }
1240 pmap_cmap3(0, 0);
1241
1242 /*
1243 * XXX
1244 * The last chunk must contain at least one page plus the message
1245 * buffer to avoid complicating other code (message buffer address
1246 * calculation, etc.).
1247 */
1248 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
1249 round_page(msgbufsize) >= phys_avail[pa_indx]) {
1250 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1251 phys_avail[pa_indx--] = 0;
1252 phys_avail[pa_indx--] = 0;
1253 }
1254
1255 Maxmem = atop(phys_avail[pa_indx]);
1256
1257 /* Trim off space for the message buffer. */
1258 phys_avail[pa_indx] -= round_page(msgbufsize);
1259
1260 /* Map the message buffer. */
1261 for (off = 0; off < round_page(msgbufsize); off += PAGE_SIZE)
1262 pmap_kenter((vm_offset_t)msgbufp + off, phys_avail[pa_indx] +
1263 off);
1264 }
1265
1266 static void
i386_kdb_init(void)1267 i386_kdb_init(void)
1268 {
1269 #ifdef DDB
1270 db_fetch_ksymtab(bootinfo.bi_symtab, bootinfo.bi_esymtab, 0);
1271 #endif
1272 kdb_init();
1273 #ifdef KDB
1274 if (boothowto & RB_KDB)
1275 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
1276 #endif
1277 }
1278
1279 static void
fixup_idt(void)1280 fixup_idt(void)
1281 {
1282 struct gate_descriptor *ip;
1283 uintptr_t off;
1284 int x;
1285
1286 for (x = 0; x < NIDT; x++) {
1287 ip = &idt[x];
1288 if (ip->gd_type != SDT_SYS386IGT &&
1289 ip->gd_type != SDT_SYS386TGT)
1290 continue;
1291 off = ip->gd_looffset + (((u_int)ip->gd_hioffset) << 16);
1292 KASSERT(off >= (uintptr_t)start_exceptions &&
1293 off < (uintptr_t)end_exceptions,
1294 ("IDT[%d] type %d off %#x", x, ip->gd_type, off));
1295 off += setidt_disp;
1296 MPASS(off >= PMAP_TRM_MIN_ADDRESS &&
1297 off < PMAP_TRM_MAX_ADDRESS);
1298 ip->gd_looffset = off;
1299 ip->gd_hioffset = off >> 16;
1300 }
1301 }
1302
1303 static void
i386_setidt1(void)1304 i386_setidt1(void)
1305 {
1306 int x;
1307
1308 /* exceptions */
1309 for (x = 0; x < NIDT; x++)
1310 setidt(x, &IDTVEC(rsvd), SDT_SYS386IGT, SEL_KPL,
1311 GSEL(GCODE_SEL, SEL_KPL));
1312 setidt(IDT_DE, &IDTVEC(div), SDT_SYS386IGT, SEL_KPL,
1313 GSEL(GCODE_SEL, SEL_KPL));
1314 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYS386IGT, SEL_KPL,
1315 GSEL(GCODE_SEL, SEL_KPL));
1316 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYS386IGT, SEL_KPL,
1317 GSEL(GCODE_SEL, SEL_KPL));
1318 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYS386IGT, SEL_UPL,
1319 GSEL(GCODE_SEL, SEL_KPL));
1320 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYS386IGT, SEL_UPL,
1321 GSEL(GCODE_SEL, SEL_KPL));
1322 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYS386IGT, SEL_KPL,
1323 GSEL(GCODE_SEL, SEL_KPL));
1324 setidt(IDT_UD, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL,
1325 GSEL(GCODE_SEL, SEL_KPL));
1326 setidt(IDT_NM, &IDTVEC(dna), SDT_SYS386IGT, SEL_KPL,
1327 GSEL(GCODE_SEL, SEL_KPL));
1328 setidt(IDT_DF, 0, SDT_SYSTASKGT, SEL_KPL, GSEL(GPANIC_SEL,
1329 SEL_KPL));
1330 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYS386IGT,
1331 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1332 setidt(IDT_TS, &IDTVEC(tss), SDT_SYS386IGT, SEL_KPL,
1333 GSEL(GCODE_SEL, SEL_KPL));
1334 setidt(IDT_NP, &IDTVEC(missing), SDT_SYS386IGT, SEL_KPL,
1335 GSEL(GCODE_SEL, SEL_KPL));
1336 setidt(IDT_SS, &IDTVEC(stk), SDT_SYS386IGT, SEL_KPL,
1337 GSEL(GCODE_SEL, SEL_KPL));
1338 setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL,
1339 GSEL(GCODE_SEL, SEL_KPL));
1340 setidt(IDT_PF, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL,
1341 GSEL(GCODE_SEL, SEL_KPL));
1342 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYS386IGT, SEL_KPL,
1343 GSEL(GCODE_SEL, SEL_KPL));
1344 setidt(IDT_AC, &IDTVEC(align), SDT_SYS386IGT, SEL_KPL,
1345 GSEL(GCODE_SEL, SEL_KPL));
1346 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYS386IGT, SEL_KPL,
1347 GSEL(GCODE_SEL, SEL_KPL));
1348 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYS386IGT, SEL_KPL,
1349 GSEL(GCODE_SEL, SEL_KPL));
1350 setidt(IDT_SYSCALL, &IDTVEC(int0x80_syscall),
1351 SDT_SYS386IGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
1352 #ifdef KDTRACE_HOOKS
1353 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret),
1354 SDT_SYS386IGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
1355 #endif
1356 #ifdef XENHVM
1357 setidt(IDT_EVTCHN, &IDTVEC(xen_intr_upcall),
1358 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1359 #endif
1360 }
1361
1362 static void
i386_setidt2(void)1363 i386_setidt2(void)
1364 {
1365
1366 setidt(IDT_UD, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL,
1367 GSEL(GCODE_SEL, SEL_KPL));
1368 setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL,
1369 GSEL(GCODE_SEL, SEL_KPL));
1370 }
1371
1372 #if defined(DEV_ISA) && !defined(DEV_ATPIC)
1373 static void
i386_setidt3(void)1374 i386_setidt3(void)
1375 {
1376
1377 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint),
1378 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1379 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint),
1380 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1381 }
1382 #endif
1383
1384 register_t
init386(int first)1385 init386(int first)
1386 {
1387 struct region_descriptor r_gdt, r_idt; /* table descriptors */
1388 int gsel_tss, metadata_missing, x, pa;
1389 struct pcpu *pc;
1390 struct xstate_hdr *xhdr;
1391 caddr_t kmdp;
1392 vm_offset_t addend;
1393 size_t ucode_len;
1394
1395 thread0.td_kstack = proc0kstack;
1396 thread0.td_kstack_pages = TD0_KSTACK_PAGES;
1397
1398 /*
1399 * This may be done better later if it gets more high level
1400 * components in it. If so just link td->td_proc here.
1401 */
1402 proc_linkup0(&proc0, &thread0);
1403
1404 if (bootinfo.bi_modulep) {
1405 metadata_missing = 0;
1406 addend = (vm_paddr_t)bootinfo.bi_modulep < KERNBASE ?
1407 PMAP_MAP_LOW : 0;
1408 preload_metadata = (caddr_t)bootinfo.bi_modulep + addend;
1409 preload_bootstrap_relocate(addend);
1410 } else {
1411 metadata_missing = 1;
1412 }
1413
1414 if (bootinfo.bi_envp != 0) {
1415 addend = (vm_paddr_t)bootinfo.bi_envp < KERNBASE ?
1416 PMAP_MAP_LOW : 0;
1417 init_static_kenv((char *)bootinfo.bi_envp + addend, 0);
1418 } else {
1419 init_static_kenv(NULL, 0);
1420 }
1421
1422 /*
1423 * Re-evaluate CPU features if we loaded a microcode update.
1424 */
1425 ucode_len = ucode_load_bsp(first);
1426 if (ucode_len != 0) {
1427 identify_cpu();
1428 first = roundup2(first + ucode_len, PAGE_SIZE);
1429 }
1430
1431 identify_hypervisor();
1432 identify_hypervisor_smbios();
1433
1434 /* Init basic tunables, hz etc */
1435 init_param1();
1436
1437 /* Set bootmethod to BIOS: it's the only supported on i386. */
1438 strlcpy(bootmethod, "BIOS", sizeof(bootmethod));
1439
1440 /*
1441 * Make gdt memory segments. All segments cover the full 4GB
1442 * of address space and permissions are enforced at page level.
1443 */
1444 gdt_segs[GCODE_SEL].ssd_limit = atop(0 - 1);
1445 gdt_segs[GDATA_SEL].ssd_limit = atop(0 - 1);
1446 gdt_segs[GUCODE_SEL].ssd_limit = atop(0 - 1);
1447 gdt_segs[GUDATA_SEL].ssd_limit = atop(0 - 1);
1448 gdt_segs[GUFS_SEL].ssd_limit = atop(0 - 1);
1449 gdt_segs[GUGS_SEL].ssd_limit = atop(0 - 1);
1450
1451 pc = &__pcpu[0];
1452 gdt_segs[GPRIV_SEL].ssd_limit = atop(0 - 1);
1453 gdt_segs[GPRIV_SEL].ssd_base = (int)pc;
1454 gdt_segs[GPROC0_SEL].ssd_base = (int)&common_tss0;
1455
1456 for (x = 0; x < NGDT; x++)
1457 ssdtosd(&gdt_segs[x], &gdt0[x].sd);
1458
1459 r_gdt.rd_limit = NGDT * sizeof(gdt0[0]) - 1;
1460 r_gdt.rd_base = (int)gdt0;
1461 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_SPIN);
1462 lgdt(&r_gdt);
1463
1464 pcpu_init(pc, 0, sizeof(struct pcpu));
1465 for (pa = first; pa < first + DPCPU_SIZE; pa += PAGE_SIZE)
1466 pmap_kenter(pa, pa);
1467 dpcpu_init((void *)first, 0);
1468 first += DPCPU_SIZE;
1469 PCPU_SET(prvspace, pc);
1470 PCPU_SET(curthread, &thread0);
1471 /* Non-late cninit() and printf() can be moved up to here. */
1472
1473 /*
1474 * Initialize mutexes.
1475 *
1476 * icu_lock: in order to allow an interrupt to occur in a critical
1477 * section, to set pcpu->ipending (etc...) properly, we
1478 * must be able to get the icu lock, so it can't be
1479 * under witness.
1480 */
1481 mutex_init();
1482 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS | MTX_NOPROFILE);
1483
1484 i386_setidt1();
1485
1486 r_idt.rd_limit = sizeof(idt0) - 1;
1487 r_idt.rd_base = (int) idt;
1488 lidt(&r_idt);
1489
1490 finishidentcpu(); /* Final stage of CPU initialization */
1491
1492 /*
1493 * Initialize the clock before the console so that console
1494 * initialization can use DELAY().
1495 */
1496 clock_init();
1497
1498 i386_setidt2();
1499 pmap_set_nx();
1500 initializecpu(); /* Initialize CPU registers */
1501 initializecpucache();
1502
1503 /* pointer to selector slot for %fs/%gs */
1504 PCPU_SET(fsgs_gdt, &gdt[GUFS_SEL].sd);
1505
1506 /* Initialize the tss (except for the final esp0) early for vm86. */
1507 common_tss0.tss_esp0 = thread0.td_kstack + thread0.td_kstack_pages *
1508 PAGE_SIZE - VM86_STACK_SPACE;
1509 common_tss0.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
1510 common_tss0.tss_ioopt = sizeof(struct i386tss) << 16;
1511 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
1512 PCPU_SET(tss_gdt, &gdt[GPROC0_SEL].sd);
1513 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
1514 ltr(gsel_tss);
1515
1516 /* Initialize the PIC early for vm86 calls. */
1517 #ifdef DEV_ISA
1518 #ifdef DEV_ATPIC
1519 elcr_probe();
1520 atpic_startup();
1521 #else
1522 /* Reset and mask the atpics and leave them shut down. */
1523 atpic_reset();
1524
1525 /*
1526 * Point the ICU spurious interrupt vectors at the APIC spurious
1527 * interrupt handler.
1528 */
1529 i386_setidt3();
1530 #endif
1531 #endif
1532
1533 /*
1534 * The console and kdb should be initialized even earlier than here,
1535 * but some console drivers don't work until after getmemsize().
1536 * Default to late console initialization to support these drivers.
1537 * This loses mainly printf()s in getmemsize() and early debugging.
1538 */
1539 TUNABLE_INT_FETCH("debug.late_console", &late_console);
1540 if (!late_console) {
1541 cninit();
1542 i386_kdb_init();
1543 }
1544
1545 if (cpu_fxsr && (cpu_feature2 & CPUID2_XSAVE) != 0) {
1546 use_xsave = 1;
1547 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
1548 }
1549
1550 kmdp = preload_search_by_type("elf kernel");
1551 link_elf_ireloc(kmdp);
1552
1553 vm86_initialize();
1554 getmemsize(first);
1555 init_param2(physmem);
1556
1557 /* now running on new page tables, configured,and u/iom is accessible */
1558
1559 if (late_console)
1560 cninit();
1561
1562 if (metadata_missing)
1563 printf("WARNING: loader(8) metadata is missing!\n");
1564
1565 if (late_console)
1566 i386_kdb_init();
1567
1568 msgbufinit(msgbufp, msgbufsize);
1569 npxinit(true);
1570
1571 /*
1572 * Set up thread0 pcb after npxinit calculated pcb + fpu save
1573 * area size. Zero out the extended state header in fpu save
1574 * area.
1575 */
1576 thread0.td_pcb = get_pcb_td(&thread0);
1577 thread0.td_pcb->pcb_save = get_pcb_user_save_td(&thread0);
1578 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size);
1579 if (use_xsave) {
1580 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) +
1581 1);
1582 xhdr->xstate_bv = xsave_mask;
1583 }
1584 PCPU_SET(curpcb, thread0.td_pcb);
1585 /* Move esp0 in the tss to its final place. */
1586 /* Note: -16 is so we can grow the trapframe if we came from vm86 */
1587 common_tss0.tss_esp0 = (vm_offset_t)thread0.td_pcb - VM86_STACK_SPACE;
1588 PCPU_SET(kesp0, common_tss0.tss_esp0);
1589 gdt[GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; /* clear busy bit */
1590 ltr(gsel_tss);
1591
1592 /* transfer to user mode */
1593
1594 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
1595 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
1596
1597 /* setup proc 0's pcb */
1598 thread0.td_pcb->pcb_flags = 0;
1599 thread0.td_pcb->pcb_cr3 = pmap_get_kcr3();
1600 thread0.td_pcb->pcb_ext = 0;
1601 thread0.td_frame = &proc0_tf;
1602
1603 #ifdef FDT
1604 x86_init_fdt();
1605 #endif
1606
1607 /* Location of kernel stack for locore */
1608 return ((register_t)thread0.td_pcb);
1609 }
1610
1611 static void
machdep_init_trampoline(void)1612 machdep_init_trampoline(void)
1613 {
1614 struct region_descriptor r_gdt, r_idt;
1615 struct i386tss *tss;
1616 char *copyout_buf, *trampoline, *tramp_stack_base;
1617 int x;
1618
1619 gdt = pmap_trm_alloc(sizeof(union descriptor) * NGDT * mp_ncpus,
1620 M_NOWAIT | M_ZERO);
1621 bcopy(gdt0, gdt, sizeof(union descriptor) * NGDT);
1622 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1623 r_gdt.rd_base = (int)gdt;
1624 lgdt(&r_gdt);
1625
1626 tss = pmap_trm_alloc(sizeof(struct i386tss) * mp_ncpus,
1627 M_NOWAIT | M_ZERO);
1628 bcopy(&common_tss0, tss, sizeof(struct i386tss));
1629 gdt[GPROC0_SEL].sd.sd_lobase = (int)tss;
1630 gdt[GPROC0_SEL].sd.sd_hibase = (u_int)tss >> 24;
1631 gdt[GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
1632
1633 PCPU_SET(fsgs_gdt, &gdt[GUFS_SEL].sd);
1634 PCPU_SET(tss_gdt, &gdt[GPROC0_SEL].sd);
1635 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
1636 PCPU_SET(common_tssp, tss);
1637 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1638
1639 trampoline = pmap_trm_alloc(end_exceptions - start_exceptions,
1640 M_NOWAIT);
1641 bcopy(start_exceptions, trampoline, end_exceptions - start_exceptions);
1642 tramp_stack_base = pmap_trm_alloc(TRAMP_STACK_SZ, M_NOWAIT);
1643 PCPU_SET(trampstk, (uintptr_t)tramp_stack_base + TRAMP_STACK_SZ -
1644 VM86_STACK_SPACE);
1645 tss[0].tss_esp0 = PCPU_GET(trampstk);
1646
1647 idt = pmap_trm_alloc(sizeof(idt0), M_NOWAIT | M_ZERO);
1648 bcopy(idt0, idt, sizeof(idt0));
1649
1650 /* Re-initialize new IDT since the handlers were relocated */
1651 setidt_disp = trampoline - start_exceptions;
1652 if (bootverbose)
1653 printf("Trampoline disposition %#zx\n", setidt_disp);
1654 fixup_idt();
1655
1656 r_idt.rd_limit = sizeof(struct gate_descriptor) * NIDT - 1;
1657 r_idt.rd_base = (int)idt;
1658 lidt(&r_idt);
1659
1660 /* dblfault TSS */
1661 dblfault_tss = pmap_trm_alloc(sizeof(struct i386tss), M_NOWAIT | M_ZERO);
1662 dblfault_stack = pmap_trm_alloc(PAGE_SIZE, M_NOWAIT);
1663 dblfault_tss->tss_esp = dblfault_tss->tss_esp0 =
1664 dblfault_tss->tss_esp1 = dblfault_tss->tss_esp2 =
1665 (int)dblfault_stack + PAGE_SIZE;
1666 dblfault_tss->tss_ss = dblfault_tss->tss_ss0 = dblfault_tss->tss_ss1 =
1667 dblfault_tss->tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
1668 dblfault_tss->tss_cr3 = pmap_get_kcr3();
1669 dblfault_tss->tss_eip = (int)dblfault_handler;
1670 dblfault_tss->tss_eflags = PSL_KERNEL;
1671 dblfault_tss->tss_ds = dblfault_tss->tss_es =
1672 dblfault_tss->tss_gs = GSEL(GDATA_SEL, SEL_KPL);
1673 dblfault_tss->tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
1674 dblfault_tss->tss_cs = GSEL(GCODE_SEL, SEL_KPL);
1675 dblfault_tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
1676 gdt[GPANIC_SEL].sd.sd_lobase = (int)dblfault_tss;
1677 gdt[GPANIC_SEL].sd.sd_hibase = (u_int)dblfault_tss >> 24;
1678
1679 /* make ldt memory segments */
1680 ldt = pmap_trm_alloc(sizeof(union descriptor) * NLDT,
1681 M_NOWAIT | M_ZERO);
1682 gdt[GLDT_SEL].sd.sd_lobase = (int)ldt;
1683 gdt[GLDT_SEL].sd.sd_hibase = (u_int)ldt >> 24;
1684 ldt_segs[LUCODE_SEL].ssd_limit = atop(0 - 1);
1685 ldt_segs[LUDATA_SEL].ssd_limit = atop(0 - 1);
1686 for (x = 0; x < nitems(ldt_segs); x++)
1687 ssdtosd(&ldt_segs[x], &ldt[x].sd);
1688
1689 _default_ldt = GSEL(GLDT_SEL, SEL_KPL);
1690 lldt(_default_ldt);
1691 PCPU_SET(currentldt, _default_ldt);
1692
1693 copyout_buf = pmap_trm_alloc(TRAMP_COPYOUT_SZ, M_NOWAIT);
1694 PCPU_SET(copyout_buf, copyout_buf);
1695 copyout_init_tramp();
1696 }
1697 SYSINIT(vm_mem, SI_SUB_VM, SI_ORDER_SECOND, machdep_init_trampoline, NULL);
1698
1699 #ifdef COMPAT_43
1700 static void
i386_setup_lcall_gate(void)1701 i386_setup_lcall_gate(void)
1702 {
1703 struct sysentvec *sv;
1704 struct user_segment_descriptor desc;
1705 u_int lcall_addr;
1706
1707 sv = &elf32_freebsd_sysvec;
1708 lcall_addr = (uintptr_t)sv->sv_psstrings - sz_lcall_tramp;
1709
1710 bzero(&desc, sizeof(desc));
1711 desc.sd_type = SDT_MEMERA;
1712 desc.sd_dpl = SEL_UPL;
1713 desc.sd_p = 1;
1714 desc.sd_def32 = 1;
1715 desc.sd_gran = 1;
1716 desc.sd_lolimit = 0xffff;
1717 desc.sd_hilimit = 0xf;
1718 desc.sd_lobase = lcall_addr;
1719 desc.sd_hibase = lcall_addr >> 24;
1720 bcopy(&desc, &ldt[LSYS5CALLS_SEL], sizeof(desc));
1721 }
1722 SYSINIT(elf32, SI_SUB_EXEC, SI_ORDER_ANY, i386_setup_lcall_gate, NULL);
1723 #endif
1724
1725 void
cpu_pcpu_init(struct pcpu * pcpu,int cpuid,size_t size)1726 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
1727 {
1728
1729 pcpu->pc_acpi_id = 0xffffffff;
1730 }
1731
1732 static int
smap_sysctl_handler(SYSCTL_HANDLER_ARGS)1733 smap_sysctl_handler(SYSCTL_HANDLER_ARGS)
1734 {
1735 struct bios_smap *smapbase;
1736 struct bios_smap_xattr smap;
1737 caddr_t kmdp;
1738 uint32_t *smapattr;
1739 int count, error, i;
1740
1741 /* Retrieve the system memory map from the loader. */
1742 kmdp = preload_search_by_type("elf kernel");
1743 if (kmdp == NULL)
1744 kmdp = preload_search_by_type("elf32 kernel");
1745 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1746 MODINFO_METADATA | MODINFOMD_SMAP);
1747 if (smapbase == NULL)
1748 return (0);
1749 smapattr = (uint32_t *)preload_search_info(kmdp,
1750 MODINFO_METADATA | MODINFOMD_SMAP_XATTR);
1751 count = *((u_int32_t *)smapbase - 1) / sizeof(*smapbase);
1752 error = 0;
1753 for (i = 0; i < count; i++) {
1754 smap.base = smapbase[i].base;
1755 smap.length = smapbase[i].length;
1756 smap.type = smapbase[i].type;
1757 if (smapattr != NULL)
1758 smap.xattr = smapattr[i];
1759 else
1760 smap.xattr = 0;
1761 error = SYSCTL_OUT(req, &smap, sizeof(smap));
1762 }
1763 return (error);
1764 }
1765 SYSCTL_PROC(_machdep, OID_AUTO, smap,
1766 CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
1767 smap_sysctl_handler, "S,bios_smap_xattr",
1768 "Raw BIOS SMAP data");
1769
1770 void
spinlock_enter(void)1771 spinlock_enter(void)
1772 {
1773 struct thread *td;
1774 register_t flags;
1775
1776 td = curthread;
1777 if (td->td_md.md_spinlock_count == 0) {
1778 flags = intr_disable();
1779 td->td_md.md_spinlock_count = 1;
1780 td->td_md.md_saved_flags = flags;
1781 critical_enter();
1782 } else
1783 td->td_md.md_spinlock_count++;
1784 }
1785
1786 void
spinlock_exit(void)1787 spinlock_exit(void)
1788 {
1789 struct thread *td;
1790 register_t flags;
1791
1792 td = curthread;
1793 flags = td->td_md.md_saved_flags;
1794 td->td_md.md_spinlock_count--;
1795 if (td->td_md.md_spinlock_count == 0) {
1796 critical_exit();
1797 intr_restore(flags);
1798 }
1799 }
1800
1801 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
1802 static void f00f_hack(void *unused);
1803 SYSINIT(f00f_hack, SI_SUB_INTRINSIC, SI_ORDER_FIRST, f00f_hack, NULL);
1804
1805 static void
f00f_hack(void * unused)1806 f00f_hack(void *unused)
1807 {
1808 struct region_descriptor r_idt;
1809 struct gate_descriptor *new_idt;
1810 vm_offset_t tmp;
1811
1812 if (!has_f00f_bug)
1813 return;
1814
1815 printf("Intel Pentium detected, installing workaround for F00F bug\n");
1816
1817 tmp = (vm_offset_t)pmap_trm_alloc(PAGE_SIZE * 3, M_NOWAIT | M_ZERO);
1818 if (tmp == 0)
1819 panic("kmem_malloc returned 0");
1820 tmp = round_page(tmp);
1821
1822 /* Put the problematic entry (#6) at the end of the lower page. */
1823 new_idt = (struct gate_descriptor *)
1824 (tmp + PAGE_SIZE - 7 * sizeof(struct gate_descriptor));
1825 bcopy(idt, new_idt, sizeof(idt0));
1826 r_idt.rd_base = (u_int)new_idt;
1827 r_idt.rd_limit = sizeof(idt0) - 1;
1828 lidt(&r_idt);
1829 /* SMP machines do not need the F00F hack. */
1830 idt = new_idt;
1831 pmap_protect(kernel_pmap, tmp, tmp + PAGE_SIZE, VM_PROT_READ);
1832 }
1833 #endif /* defined(I586_CPU) && !NO_F00F_HACK */
1834
1835 /*
1836 * Construct a PCB from a trapframe. This is called from kdb_trap() where
1837 * we want to start a backtrace from the function that caused us to enter
1838 * the debugger. We have the context in the trapframe, but base the trace
1839 * on the PCB. The PCB doesn't have to be perfect, as long as it contains
1840 * enough for a backtrace.
1841 */
1842 void
makectx(struct trapframe * tf,struct pcb * pcb)1843 makectx(struct trapframe *tf, struct pcb *pcb)
1844 {
1845
1846 pcb->pcb_edi = tf->tf_edi;
1847 pcb->pcb_esi = tf->tf_esi;
1848 pcb->pcb_ebp = tf->tf_ebp;
1849 pcb->pcb_ebx = tf->tf_ebx;
1850 pcb->pcb_eip = tf->tf_eip;
1851 pcb->pcb_esp = (ISPL(tf->tf_cs)) ? tf->tf_esp : (int)(tf + 1) - 8;
1852 pcb->pcb_gs = rgs();
1853 }
1854
1855 #ifdef KDB
1856
1857 /*
1858 * Provide inb() and outb() as functions. They are normally only available as
1859 * inline functions, thus cannot be called from the debugger.
1860 */
1861
1862 /* silence compiler warnings */
1863 u_char inb_(u_short);
1864 void outb_(u_short, u_char);
1865
1866 u_char
inb_(u_short port)1867 inb_(u_short port)
1868 {
1869 return inb(port);
1870 }
1871
1872 void
outb_(u_short port,u_char data)1873 outb_(u_short port, u_char data)
1874 {
1875 outb(port, data);
1876 }
1877
1878 #endif /* KDB */
1879