xref: /netbsd/sys/arch/arm/xscale/i80200_icu.c (revision 1b0b818d)
1 /*	$NetBSD: i80200_icu.c,v 1.10 2012/08/02 15:56:07 skrll Exp $	*/
2 
3 /*
4  * Copyright (c) 2002 Wasabi Systems, Inc.
5  * All rights reserved.
6  *
7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *	This product includes software developed for the NetBSD Project by
20  *	Wasabi Systems, Inc.
21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22  *    or promote products derived from this software without specific prior
23  *    written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35  * POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 /*
39  * Intel i80200 Interrupt Controller Unit support.
40  */
41 
42 #include <sys/cdefs.h>
43 __KERNEL_RCSID(0, "$NetBSD: i80200_icu.c,v 1.10 2012/08/02 15:56:07 skrll Exp $");
44 
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 
48 #include <arm/cpufunc.h>
49 
50 #include <arm/xscale/i80200reg.h>
51 #include <arm/xscale/i80200var.h>
52 
53 /* Software shadow copy of INTCTL. */
54 static volatile uint32_t intctl;
55 
56 /* Pointer to board-specific external IRQ dispatcher. */
57 void	(*i80200_extirq_dispatch)(struct trapframe *);
58 
59 static void
i80200_default_extirq_dispatch(struct trapframe * framep)60 i80200_default_extirq_dispatch(struct trapframe *framep)
61 {
62 
63 	panic("external IRQ with no dispatch routine");
64 }
65 
66 /*
67  * i80200_icu_init:
68  *
69  *	Initialize the i80200 ICU.
70  */
71 void
i80200_icu_init(void)72 i80200_icu_init(void)
73 {
74 
75 	/* Disable all interrupt sources. */
76 	intctl = 0;
77 	__asm volatile("mcr p13, 0, %0, c0, c0"
78 		:
79 		: "r" (intctl));
80 
81 	/* Steer PMU and BMU to IRQ. */
82 	__asm volatile("mcr p13, 0, %0, c8, c0"
83 		:
84 		: "r" (0));
85 
86 	i80200_extirq_dispatch = i80200_default_extirq_dispatch;
87 }
88 
89 /*
90  * i80200_intr_enable:
91  *
92  *	Enable an interrupt source in the i80200 ICU.
93  */
94 void
i80200_intr_enable(uint32_t intr)95 i80200_intr_enable(uint32_t intr)
96 {
97 	u_int oldirqstate;
98 
99 	oldirqstate = disable_interrupts(I32_bit|F32_bit);
100 
101 	intctl |= intr;
102 	__asm volatile("mcr p13, 0, %0, c0, c0"
103 		:
104 		: "r" (intctl));
105 
106 	restore_interrupts(oldirqstate);
107 }
108 
109 /*
110  * i80200_intr_disable:
111  *
112  *	Disable an interrupt source in the i80200 ICU.
113  */
114 void
i80200_intr_disable(uint32_t intr)115 i80200_intr_disable(uint32_t intr)
116 {
117 	u_int oldirqstate;
118 
119 	oldirqstate = disable_interrupts(I32_bit|F32_bit);
120 
121 	intctl &= ~intr;
122 	__asm volatile("mcr p13, 0, %0, c0, c0"
123 		:
124 		: "r" (intctl));
125 
126 	restore_interrupts(oldirqstate);
127 }
128