1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright © 2019 Intel Corporation
4 */
5
6 #include <linux/string_helpers.h>
7
8 #include "i915_drv.h"
9 #include "i915_irq.h"
10 #include "i915_reg.h"
11 #include "intel_backlight_regs.h"
12 #include "intel_cdclk.h"
13 #include "intel_clock_gating.h"
14 #include "intel_combo_phy.h"
15 #include "intel_de.h"
16 #include "intel_display_power.h"
17 #include "intel_display_power_map.h"
18 #include "intel_display_power_well.h"
19 #include "intel_display_types.h"
20 #include "intel_dmc.h"
21 #include "intel_mchbar_regs.h"
22 #include "intel_pch_refclk.h"
23 #include "intel_pcode.h"
24 #include "intel_pmdemand.h"
25 #include "intel_pps_regs.h"
26 #include "intel_snps_phy.h"
27 #include "skl_watermark.h"
28 #include "skl_watermark_regs.h"
29 #include "vlv_sideband.h"
30
31 #define for_each_power_domain_well(__dev_priv, __power_well, __domain) \
32 for_each_power_well(__dev_priv, __power_well) \
33 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
34
35 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \
36 for_each_power_well_reverse(__dev_priv, __power_well) \
37 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
38
39 const char *
intel_display_power_domain_str(enum intel_display_power_domain domain)40 intel_display_power_domain_str(enum intel_display_power_domain domain)
41 {
42 switch (domain) {
43 case POWER_DOMAIN_DISPLAY_CORE:
44 return "DISPLAY_CORE";
45 case POWER_DOMAIN_PIPE_A:
46 return "PIPE_A";
47 case POWER_DOMAIN_PIPE_B:
48 return "PIPE_B";
49 case POWER_DOMAIN_PIPE_C:
50 return "PIPE_C";
51 case POWER_DOMAIN_PIPE_D:
52 return "PIPE_D";
53 case POWER_DOMAIN_PIPE_PANEL_FITTER_A:
54 return "PIPE_PANEL_FITTER_A";
55 case POWER_DOMAIN_PIPE_PANEL_FITTER_B:
56 return "PIPE_PANEL_FITTER_B";
57 case POWER_DOMAIN_PIPE_PANEL_FITTER_C:
58 return "PIPE_PANEL_FITTER_C";
59 case POWER_DOMAIN_PIPE_PANEL_FITTER_D:
60 return "PIPE_PANEL_FITTER_D";
61 case POWER_DOMAIN_TRANSCODER_A:
62 return "TRANSCODER_A";
63 case POWER_DOMAIN_TRANSCODER_B:
64 return "TRANSCODER_B";
65 case POWER_DOMAIN_TRANSCODER_C:
66 return "TRANSCODER_C";
67 case POWER_DOMAIN_TRANSCODER_D:
68 return "TRANSCODER_D";
69 case POWER_DOMAIN_TRANSCODER_EDP:
70 return "TRANSCODER_EDP";
71 case POWER_DOMAIN_TRANSCODER_DSI_A:
72 return "TRANSCODER_DSI_A";
73 case POWER_DOMAIN_TRANSCODER_DSI_C:
74 return "TRANSCODER_DSI_C";
75 case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
76 return "TRANSCODER_VDSC_PW2";
77 case POWER_DOMAIN_PORT_DDI_LANES_A:
78 return "PORT_DDI_LANES_A";
79 case POWER_DOMAIN_PORT_DDI_LANES_B:
80 return "PORT_DDI_LANES_B";
81 case POWER_DOMAIN_PORT_DDI_LANES_C:
82 return "PORT_DDI_LANES_C";
83 case POWER_DOMAIN_PORT_DDI_LANES_D:
84 return "PORT_DDI_LANES_D";
85 case POWER_DOMAIN_PORT_DDI_LANES_E:
86 return "PORT_DDI_LANES_E";
87 case POWER_DOMAIN_PORT_DDI_LANES_F:
88 return "PORT_DDI_LANES_F";
89 case POWER_DOMAIN_PORT_DDI_LANES_TC1:
90 return "PORT_DDI_LANES_TC1";
91 case POWER_DOMAIN_PORT_DDI_LANES_TC2:
92 return "PORT_DDI_LANES_TC2";
93 case POWER_DOMAIN_PORT_DDI_LANES_TC3:
94 return "PORT_DDI_LANES_TC3";
95 case POWER_DOMAIN_PORT_DDI_LANES_TC4:
96 return "PORT_DDI_LANES_TC4";
97 case POWER_DOMAIN_PORT_DDI_LANES_TC5:
98 return "PORT_DDI_LANES_TC5";
99 case POWER_DOMAIN_PORT_DDI_LANES_TC6:
100 return "PORT_DDI_LANES_TC6";
101 case POWER_DOMAIN_PORT_DDI_IO_A:
102 return "PORT_DDI_IO_A";
103 case POWER_DOMAIN_PORT_DDI_IO_B:
104 return "PORT_DDI_IO_B";
105 case POWER_DOMAIN_PORT_DDI_IO_C:
106 return "PORT_DDI_IO_C";
107 case POWER_DOMAIN_PORT_DDI_IO_D:
108 return "PORT_DDI_IO_D";
109 case POWER_DOMAIN_PORT_DDI_IO_E:
110 return "PORT_DDI_IO_E";
111 case POWER_DOMAIN_PORT_DDI_IO_F:
112 return "PORT_DDI_IO_F";
113 case POWER_DOMAIN_PORT_DDI_IO_TC1:
114 return "PORT_DDI_IO_TC1";
115 case POWER_DOMAIN_PORT_DDI_IO_TC2:
116 return "PORT_DDI_IO_TC2";
117 case POWER_DOMAIN_PORT_DDI_IO_TC3:
118 return "PORT_DDI_IO_TC3";
119 case POWER_DOMAIN_PORT_DDI_IO_TC4:
120 return "PORT_DDI_IO_TC4";
121 case POWER_DOMAIN_PORT_DDI_IO_TC5:
122 return "PORT_DDI_IO_TC5";
123 case POWER_DOMAIN_PORT_DDI_IO_TC6:
124 return "PORT_DDI_IO_TC6";
125 case POWER_DOMAIN_PORT_DSI:
126 return "PORT_DSI";
127 case POWER_DOMAIN_PORT_CRT:
128 return "PORT_CRT";
129 case POWER_DOMAIN_PORT_OTHER:
130 return "PORT_OTHER";
131 case POWER_DOMAIN_VGA:
132 return "VGA";
133 case POWER_DOMAIN_AUDIO_MMIO:
134 return "AUDIO_MMIO";
135 case POWER_DOMAIN_AUDIO_PLAYBACK:
136 return "AUDIO_PLAYBACK";
137 case POWER_DOMAIN_AUX_IO_A:
138 return "AUX_IO_A";
139 case POWER_DOMAIN_AUX_IO_B:
140 return "AUX_IO_B";
141 case POWER_DOMAIN_AUX_IO_C:
142 return "AUX_IO_C";
143 case POWER_DOMAIN_AUX_IO_D:
144 return "AUX_IO_D";
145 case POWER_DOMAIN_AUX_IO_E:
146 return "AUX_IO_E";
147 case POWER_DOMAIN_AUX_IO_F:
148 return "AUX_IO_F";
149 case POWER_DOMAIN_AUX_A:
150 return "AUX_A";
151 case POWER_DOMAIN_AUX_B:
152 return "AUX_B";
153 case POWER_DOMAIN_AUX_C:
154 return "AUX_C";
155 case POWER_DOMAIN_AUX_D:
156 return "AUX_D";
157 case POWER_DOMAIN_AUX_E:
158 return "AUX_E";
159 case POWER_DOMAIN_AUX_F:
160 return "AUX_F";
161 case POWER_DOMAIN_AUX_USBC1:
162 return "AUX_USBC1";
163 case POWER_DOMAIN_AUX_USBC2:
164 return "AUX_USBC2";
165 case POWER_DOMAIN_AUX_USBC3:
166 return "AUX_USBC3";
167 case POWER_DOMAIN_AUX_USBC4:
168 return "AUX_USBC4";
169 case POWER_DOMAIN_AUX_USBC5:
170 return "AUX_USBC5";
171 case POWER_DOMAIN_AUX_USBC6:
172 return "AUX_USBC6";
173 case POWER_DOMAIN_AUX_TBT1:
174 return "AUX_TBT1";
175 case POWER_DOMAIN_AUX_TBT2:
176 return "AUX_TBT2";
177 case POWER_DOMAIN_AUX_TBT3:
178 return "AUX_TBT3";
179 case POWER_DOMAIN_AUX_TBT4:
180 return "AUX_TBT4";
181 case POWER_DOMAIN_AUX_TBT5:
182 return "AUX_TBT5";
183 case POWER_DOMAIN_AUX_TBT6:
184 return "AUX_TBT6";
185 case POWER_DOMAIN_GMBUS:
186 return "GMBUS";
187 case POWER_DOMAIN_INIT:
188 return "INIT";
189 case POWER_DOMAIN_MODESET:
190 return "MODESET";
191 case POWER_DOMAIN_GT_IRQ:
192 return "GT_IRQ";
193 case POWER_DOMAIN_DC_OFF:
194 return "DC_OFF";
195 case POWER_DOMAIN_TC_COLD_OFF:
196 return "TC_COLD_OFF";
197 default:
198 MISSING_CASE(domain);
199 return "?";
200 }
201 }
202
203 /**
204 * __intel_display_power_is_enabled - unlocked check for a power domain
205 * @dev_priv: i915 device instance
206 * @domain: power domain to check
207 *
208 * This is the unlocked version of intel_display_power_is_enabled() and should
209 * only be used from error capture and recovery code where deadlocks are
210 * possible.
211 *
212 * Returns:
213 * True when the power domain is enabled, false otherwise.
214 */
__intel_display_power_is_enabled(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)215 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
216 enum intel_display_power_domain domain)
217 {
218 struct i915_power_well *power_well;
219 bool is_enabled;
220
221 if (dev_priv->runtime_pm.suspended)
222 return false;
223
224 is_enabled = true;
225
226 for_each_power_domain_well_reverse(dev_priv, power_well, domain) {
227 if (intel_power_well_is_always_on(power_well))
228 continue;
229
230 if (!intel_power_well_is_enabled_cached(power_well)) {
231 is_enabled = false;
232 break;
233 }
234 }
235
236 return is_enabled;
237 }
238
239 /**
240 * intel_display_power_is_enabled - check for a power domain
241 * @dev_priv: i915 device instance
242 * @domain: power domain to check
243 *
244 * This function can be used to check the hw power domain state. It is mostly
245 * used in hardware state readout functions. Everywhere else code should rely
246 * upon explicit power domain reference counting to ensure that the hardware
247 * block is powered up before accessing it.
248 *
249 * Callers must hold the relevant modesetting locks to ensure that concurrent
250 * threads can't disable the power well while the caller tries to read a few
251 * registers.
252 *
253 * Returns:
254 * True when the power domain is enabled, false otherwise.
255 */
intel_display_power_is_enabled(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)256 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
257 enum intel_display_power_domain domain)
258 {
259 struct i915_power_domains *power_domains;
260 bool ret;
261
262 power_domains = &dev_priv->display.power.domains;
263
264 mutex_lock(&power_domains->lock);
265 ret = __intel_display_power_is_enabled(dev_priv, domain);
266 mutex_unlock(&power_domains->lock);
267
268 return ret;
269 }
270
271 static u32
sanitize_target_dc_state(struct drm_i915_private * i915,u32 target_dc_state)272 sanitize_target_dc_state(struct drm_i915_private *i915,
273 u32 target_dc_state)
274 {
275 struct i915_power_domains *power_domains = &i915->display.power.domains;
276 static const u32 states[] = {
277 DC_STATE_EN_UPTO_DC6,
278 DC_STATE_EN_UPTO_DC5,
279 DC_STATE_EN_DC3CO,
280 DC_STATE_DISABLE,
281 };
282 int i;
283
284 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
285 if (target_dc_state != states[i])
286 continue;
287
288 if (power_domains->allowed_dc_mask & target_dc_state)
289 break;
290
291 target_dc_state = states[i + 1];
292 }
293
294 return target_dc_state;
295 }
296
297 /**
298 * intel_display_power_set_target_dc_state - Set target dc state.
299 * @dev_priv: i915 device
300 * @state: state which needs to be set as target_dc_state.
301 *
302 * This function set the "DC off" power well target_dc_state,
303 * based upon this target_dc_stste, "DC off" power well will
304 * enable desired DC state.
305 */
intel_display_power_set_target_dc_state(struct drm_i915_private * dev_priv,u32 state)306 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
307 u32 state)
308 {
309 struct i915_power_well *power_well;
310 bool dc_off_enabled;
311 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
312
313 mutex_lock(&power_domains->lock);
314 power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF);
315
316 if (drm_WARN_ON(&dev_priv->drm, !power_well))
317 goto unlock;
318
319 state = sanitize_target_dc_state(dev_priv, state);
320
321 if (state == power_domains->target_dc_state)
322 goto unlock;
323
324 dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well);
325 /*
326 * If DC off power well is disabled, need to enable and disable the
327 * DC off power well to effect target DC state.
328 */
329 if (!dc_off_enabled)
330 intel_power_well_enable(dev_priv, power_well);
331
332 power_domains->target_dc_state = state;
333
334 if (!dc_off_enabled)
335 intel_power_well_disable(dev_priv, power_well);
336
337 unlock:
338 mutex_unlock(&power_domains->lock);
339 }
340
341 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
342
__async_put_domains_mask(struct i915_power_domains * power_domains,struct intel_power_domain_mask * mask)343 static void __async_put_domains_mask(struct i915_power_domains *power_domains,
344 struct intel_power_domain_mask *mask)
345 {
346 bitmap_or(mask->bits,
347 power_domains->async_put_domains[0].bits,
348 power_domains->async_put_domains[1].bits,
349 POWER_DOMAIN_NUM);
350 }
351
352 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
353
354 static bool
assert_async_put_domain_masks_disjoint(struct i915_power_domains * power_domains)355 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
356 {
357 struct drm_i915_private *i915 = container_of(power_domains,
358 struct drm_i915_private,
359 display.power.domains);
360
361 return !drm_WARN_ON(&i915->drm,
362 bitmap_intersects(power_domains->async_put_domains[0].bits,
363 power_domains->async_put_domains[1].bits,
364 POWER_DOMAIN_NUM));
365 }
366
367 static bool
__async_put_domains_state_ok(struct i915_power_domains * power_domains)368 __async_put_domains_state_ok(struct i915_power_domains *power_domains)
369 {
370 struct drm_i915_private *i915 = container_of(power_domains,
371 struct drm_i915_private,
372 display.power.domains);
373 struct intel_power_domain_mask async_put_mask;
374 enum intel_display_power_domain domain;
375 bool err = false;
376
377 err |= !assert_async_put_domain_masks_disjoint(power_domains);
378 __async_put_domains_mask(power_domains, &async_put_mask);
379 err |= drm_WARN_ON(&i915->drm,
380 !!power_domains->async_put_wakeref !=
381 !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM));
382
383 for_each_power_domain(domain, &async_put_mask)
384 err |= drm_WARN_ON(&i915->drm,
385 power_domains->domain_use_count[domain] != 1);
386
387 return !err;
388 }
389
print_power_domains(struct i915_power_domains * power_domains,const char * prefix,struct intel_power_domain_mask * mask)390 static void print_power_domains(struct i915_power_domains *power_domains,
391 const char *prefix, struct intel_power_domain_mask *mask)
392 {
393 struct drm_i915_private *i915 = container_of(power_domains,
394 struct drm_i915_private,
395 display.power.domains);
396 enum intel_display_power_domain domain;
397
398 drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
399 for_each_power_domain(domain, mask)
400 drm_dbg(&i915->drm, "%s use_count %d\n",
401 intel_display_power_domain_str(domain),
402 power_domains->domain_use_count[domain]);
403 }
404
405 static void
print_async_put_domains_state(struct i915_power_domains * power_domains)406 print_async_put_domains_state(struct i915_power_domains *power_domains)
407 {
408 struct drm_i915_private *i915 = container_of(power_domains,
409 struct drm_i915_private,
410 display.power.domains);
411
412 drm_dbg(&i915->drm, "async_put_wakeref %u\n",
413 power_domains->async_put_wakeref);
414
415 print_power_domains(power_domains, "async_put_domains[0]",
416 &power_domains->async_put_domains[0]);
417 print_power_domains(power_domains, "async_put_domains[1]",
418 &power_domains->async_put_domains[1]);
419 }
420
421 static void
verify_async_put_domains_state(struct i915_power_domains * power_domains)422 verify_async_put_domains_state(struct i915_power_domains *power_domains)
423 {
424 if (!__async_put_domains_state_ok(power_domains))
425 print_async_put_domains_state(power_domains);
426 }
427
428 #else
429
430 static void
assert_async_put_domain_masks_disjoint(struct i915_power_domains * power_domains)431 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
432 {
433 }
434
435 static void
verify_async_put_domains_state(struct i915_power_domains * power_domains)436 verify_async_put_domains_state(struct i915_power_domains *power_domains)
437 {
438 }
439
440 #endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */
441
async_put_domains_mask(struct i915_power_domains * power_domains,struct intel_power_domain_mask * mask)442 static void async_put_domains_mask(struct i915_power_domains *power_domains,
443 struct intel_power_domain_mask *mask)
444
445 {
446 assert_async_put_domain_masks_disjoint(power_domains);
447
448 __async_put_domains_mask(power_domains, mask);
449 }
450
451 static void
async_put_domains_clear_domain(struct i915_power_domains * power_domains,enum intel_display_power_domain domain)452 async_put_domains_clear_domain(struct i915_power_domains *power_domains,
453 enum intel_display_power_domain domain)
454 {
455 assert_async_put_domain_masks_disjoint(power_domains);
456
457 clear_bit(domain, power_domains->async_put_domains[0].bits);
458 clear_bit(domain, power_domains->async_put_domains[1].bits);
459 }
460
461 static void
cancel_async_put_work(struct i915_power_domains * power_domains,bool sync)462 cancel_async_put_work(struct i915_power_domains *power_domains, bool sync)
463 {
464 if (sync)
465 cancel_delayed_work_sync(&power_domains->async_put_work);
466 else
467 cancel_delayed_work(&power_domains->async_put_work);
468
469 power_domains->async_put_next_delay = 0;
470 }
471
472 static bool
intel_display_power_grab_async_put_ref(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)473 intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
474 enum intel_display_power_domain domain)
475 {
476 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
477 struct intel_power_domain_mask async_put_mask;
478 bool ret = false;
479
480 async_put_domains_mask(power_domains, &async_put_mask);
481 if (!test_bit(domain, async_put_mask.bits))
482 goto out_verify;
483
484 async_put_domains_clear_domain(power_domains, domain);
485
486 ret = true;
487
488 async_put_domains_mask(power_domains, &async_put_mask);
489 if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM))
490 goto out_verify;
491
492 cancel_async_put_work(power_domains, false);
493 intel_runtime_pm_put_raw(&dev_priv->runtime_pm,
494 fetch_and_zero(&power_domains->async_put_wakeref));
495 out_verify:
496 verify_async_put_domains_state(power_domains);
497
498 return ret;
499 }
500
501 static void
__intel_display_power_get_domain(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)502 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
503 enum intel_display_power_domain domain)
504 {
505 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
506 struct i915_power_well *power_well;
507
508 if (intel_display_power_grab_async_put_ref(dev_priv, domain))
509 return;
510
511 for_each_power_domain_well(dev_priv, power_well, domain)
512 intel_power_well_get(dev_priv, power_well);
513
514 power_domains->domain_use_count[domain]++;
515 }
516
517 /**
518 * intel_display_power_get - grab a power domain reference
519 * @dev_priv: i915 device instance
520 * @domain: power domain to reference
521 *
522 * This function grabs a power domain reference for @domain and ensures that the
523 * power domain and all its parents are powered up. Therefore users should only
524 * grab a reference to the innermost power domain they need.
525 *
526 * Any power domain reference obtained by this function must have a symmetric
527 * call to intel_display_power_put() to release the reference again.
528 */
intel_display_power_get(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)529 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
530 enum intel_display_power_domain domain)
531 {
532 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
533 intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
534
535 mutex_lock(&power_domains->lock);
536 __intel_display_power_get_domain(dev_priv, domain);
537 mutex_unlock(&power_domains->lock);
538
539 return wakeref;
540 }
541
542 /**
543 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
544 * @dev_priv: i915 device instance
545 * @domain: power domain to reference
546 *
547 * This function grabs a power domain reference for @domain and ensures that the
548 * power domain and all its parents are powered up. Therefore users should only
549 * grab a reference to the innermost power domain they need.
550 *
551 * Any power domain reference obtained by this function must have a symmetric
552 * call to intel_display_power_put() to release the reference again.
553 */
554 intel_wakeref_t
intel_display_power_get_if_enabled(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)555 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
556 enum intel_display_power_domain domain)
557 {
558 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
559 intel_wakeref_t wakeref;
560 bool is_enabled;
561
562 wakeref = intel_runtime_pm_get_if_in_use(&dev_priv->runtime_pm);
563 if (!wakeref)
564 return false;
565
566 mutex_lock(&power_domains->lock);
567
568 if (__intel_display_power_is_enabled(dev_priv, domain)) {
569 __intel_display_power_get_domain(dev_priv, domain);
570 is_enabled = true;
571 } else {
572 is_enabled = false;
573 }
574
575 mutex_unlock(&power_domains->lock);
576
577 if (!is_enabled) {
578 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
579 wakeref = 0;
580 }
581
582 return wakeref;
583 }
584
585 static void
__intel_display_power_put_domain(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)586 __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
587 enum intel_display_power_domain domain)
588 {
589 struct i915_power_domains *power_domains;
590 struct i915_power_well *power_well;
591 const char *name = intel_display_power_domain_str(domain);
592 struct intel_power_domain_mask async_put_mask;
593
594 power_domains = &dev_priv->display.power.domains;
595
596 drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain],
597 "Use count on domain %s is already zero\n",
598 name);
599 async_put_domains_mask(power_domains, &async_put_mask);
600 drm_WARN(&dev_priv->drm,
601 test_bit(domain, async_put_mask.bits),
602 "Async disabling of domain %s is pending\n",
603 name);
604
605 power_domains->domain_use_count[domain]--;
606
607 for_each_power_domain_well_reverse(dev_priv, power_well, domain)
608 intel_power_well_put(dev_priv, power_well);
609 }
610
__intel_display_power_put(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)611 static void __intel_display_power_put(struct drm_i915_private *dev_priv,
612 enum intel_display_power_domain domain)
613 {
614 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
615
616 mutex_lock(&power_domains->lock);
617 __intel_display_power_put_domain(dev_priv, domain);
618 mutex_unlock(&power_domains->lock);
619 }
620
621 static void
queue_async_put_domains_work(struct i915_power_domains * power_domains,intel_wakeref_t wakeref,int delay_ms)622 queue_async_put_domains_work(struct i915_power_domains *power_domains,
623 intel_wakeref_t wakeref,
624 int delay_ms)
625 {
626 struct drm_i915_private *i915 = container_of(power_domains,
627 struct drm_i915_private,
628 display.power.domains);
629 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref);
630 power_domains->async_put_wakeref = wakeref;
631 drm_WARN_ON(&i915->drm, !queue_delayed_work(system_unbound_wq,
632 &power_domains->async_put_work,
633 msecs_to_jiffies(delay_ms)));
634 }
635
636 static void
release_async_put_domains(struct i915_power_domains * power_domains,struct intel_power_domain_mask * mask)637 release_async_put_domains(struct i915_power_domains *power_domains,
638 struct intel_power_domain_mask *mask)
639 {
640 struct drm_i915_private *dev_priv =
641 container_of(power_domains, struct drm_i915_private,
642 display.power.domains);
643 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
644 enum intel_display_power_domain domain;
645 intel_wakeref_t wakeref;
646
647 /*
648 * The caller must hold already raw wakeref, upgrade that to a proper
649 * wakeref to make the state checker happy about the HW access during
650 * power well disabling.
651 */
652 assert_rpm_raw_wakeref_held(rpm);
653 wakeref = intel_runtime_pm_get(rpm);
654
655 for_each_power_domain(domain, mask) {
656 /* Clear before put, so put's sanity check is happy. */
657 async_put_domains_clear_domain(power_domains, domain);
658 __intel_display_power_put_domain(dev_priv, domain);
659 }
660
661 intel_runtime_pm_put(rpm, wakeref);
662 }
663
664 static void
intel_display_power_put_async_work(struct work_struct * work)665 intel_display_power_put_async_work(struct work_struct *work)
666 {
667 struct drm_i915_private *dev_priv =
668 container_of(work, struct drm_i915_private,
669 display.power.domains.async_put_work.work);
670 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
671 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
672 intel_wakeref_t new_work_wakeref = intel_runtime_pm_get_raw(rpm);
673 intel_wakeref_t old_work_wakeref = 0;
674
675 mutex_lock(&power_domains->lock);
676
677 /*
678 * Bail out if all the domain refs pending to be released were grabbed
679 * by subsequent gets or a flush_work.
680 */
681 old_work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref);
682 if (!old_work_wakeref)
683 goto out_verify;
684
685 release_async_put_domains(power_domains,
686 &power_domains->async_put_domains[0]);
687
688 /* Requeue the work if more domains were async put meanwhile. */
689 if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) {
690 bitmap_copy(power_domains->async_put_domains[0].bits,
691 power_domains->async_put_domains[1].bits,
692 POWER_DOMAIN_NUM);
693 bitmap_zero(power_domains->async_put_domains[1].bits,
694 POWER_DOMAIN_NUM);
695 queue_async_put_domains_work(power_domains,
696 fetch_and_zero(&new_work_wakeref),
697 power_domains->async_put_next_delay);
698 power_domains->async_put_next_delay = 0;
699 } else {
700 /*
701 * Cancel the work that got queued after this one got dequeued,
702 * since here we released the corresponding async-put reference.
703 */
704 cancel_async_put_work(power_domains, false);
705 }
706
707 out_verify:
708 verify_async_put_domains_state(power_domains);
709
710 mutex_unlock(&power_domains->lock);
711
712 if (old_work_wakeref)
713 intel_runtime_pm_put_raw(rpm, old_work_wakeref);
714 if (new_work_wakeref)
715 intel_runtime_pm_put_raw(rpm, new_work_wakeref);
716 }
717
718 /**
719 * __intel_display_power_put_async - release a power domain reference asynchronously
720 * @i915: i915 device instance
721 * @domain: power domain to reference
722 * @wakeref: wakeref acquired for the reference that is being released
723 * @delay_ms: delay of powering down the power domain
724 *
725 * This function drops the power domain reference obtained by
726 * intel_display_power_get*() and schedules a work to power down the
727 * corresponding hardware block if this is the last reference.
728 * The power down is delayed by @delay_ms if this is >= 0, or by a default
729 * 100 ms otherwise.
730 */
__intel_display_power_put_async(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref,int delay_ms)731 void __intel_display_power_put_async(struct drm_i915_private *i915,
732 enum intel_display_power_domain domain,
733 intel_wakeref_t wakeref,
734 int delay_ms)
735 {
736 struct i915_power_domains *power_domains = &i915->display.power.domains;
737 struct intel_runtime_pm *rpm = &i915->runtime_pm;
738 intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(rpm);
739
740 delay_ms = delay_ms >= 0 ? delay_ms : 100;
741
742 mutex_lock(&power_domains->lock);
743
744 if (power_domains->domain_use_count[domain] > 1) {
745 __intel_display_power_put_domain(i915, domain);
746
747 goto out_verify;
748 }
749
750 drm_WARN_ON(&i915->drm, power_domains->domain_use_count[domain] != 1);
751
752 /* Let a pending work requeue itself or queue a new one. */
753 if (power_domains->async_put_wakeref) {
754 set_bit(domain, power_domains->async_put_domains[1].bits);
755 power_domains->async_put_next_delay = max(power_domains->async_put_next_delay,
756 delay_ms);
757 } else {
758 set_bit(domain, power_domains->async_put_domains[0].bits);
759 queue_async_put_domains_work(power_domains,
760 fetch_and_zero(&work_wakeref),
761 delay_ms);
762 }
763
764 out_verify:
765 verify_async_put_domains_state(power_domains);
766
767 mutex_unlock(&power_domains->lock);
768
769 if (work_wakeref)
770 intel_runtime_pm_put_raw(rpm, work_wakeref);
771
772 intel_runtime_pm_put(rpm, wakeref);
773 }
774
775 /**
776 * intel_display_power_flush_work - flushes the async display power disabling work
777 * @i915: i915 device instance
778 *
779 * Flushes any pending work that was scheduled by a preceding
780 * intel_display_power_put_async() call, completing the disabling of the
781 * corresponding power domains.
782 *
783 * Note that the work handler function may still be running after this
784 * function returns; to ensure that the work handler isn't running use
785 * intel_display_power_flush_work_sync() instead.
786 */
intel_display_power_flush_work(struct drm_i915_private * i915)787 void intel_display_power_flush_work(struct drm_i915_private *i915)
788 {
789 struct i915_power_domains *power_domains = &i915->display.power.domains;
790 struct intel_power_domain_mask async_put_mask;
791 intel_wakeref_t work_wakeref;
792
793 mutex_lock(&power_domains->lock);
794
795 work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref);
796 if (!work_wakeref)
797 goto out_verify;
798
799 async_put_domains_mask(power_domains, &async_put_mask);
800 release_async_put_domains(power_domains, &async_put_mask);
801 cancel_async_put_work(power_domains, false);
802
803 out_verify:
804 verify_async_put_domains_state(power_domains);
805
806 mutex_unlock(&power_domains->lock);
807
808 if (work_wakeref)
809 intel_runtime_pm_put_raw(&i915->runtime_pm, work_wakeref);
810 }
811
812 /**
813 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work
814 * @i915: i915 device instance
815 *
816 * Like intel_display_power_flush_work(), but also ensure that the work
817 * handler function is not running any more when this function returns.
818 */
819 static void
intel_display_power_flush_work_sync(struct drm_i915_private * i915)820 intel_display_power_flush_work_sync(struct drm_i915_private *i915)
821 {
822 struct i915_power_domains *power_domains = &i915->display.power.domains;
823
824 intel_display_power_flush_work(i915);
825 cancel_async_put_work(power_domains, true);
826
827 verify_async_put_domains_state(power_domains);
828
829 drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref);
830 }
831
832 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
833 /**
834 * intel_display_power_put - release a power domain reference
835 * @dev_priv: i915 device instance
836 * @domain: power domain to reference
837 * @wakeref: wakeref acquired for the reference that is being released
838 *
839 * This function drops the power domain reference obtained by
840 * intel_display_power_get() and might power down the corresponding hardware
841 * block right away if this is the last reference.
842 */
intel_display_power_put(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain,intel_wakeref_t wakeref)843 void intel_display_power_put(struct drm_i915_private *dev_priv,
844 enum intel_display_power_domain domain,
845 intel_wakeref_t wakeref)
846 {
847 __intel_display_power_put(dev_priv, domain);
848 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
849 }
850 #else
851 /**
852 * intel_display_power_put_unchecked - release an unchecked power domain reference
853 * @dev_priv: i915 device instance
854 * @domain: power domain to reference
855 *
856 * This function drops the power domain reference obtained by
857 * intel_display_power_get() and might power down the corresponding hardware
858 * block right away if this is the last reference.
859 *
860 * This function is only for the power domain code's internal use to suppress wakeref
861 * tracking when the correspondig debug kconfig option is disabled, should not
862 * be used otherwise.
863 */
intel_display_power_put_unchecked(struct drm_i915_private * dev_priv,enum intel_display_power_domain domain)864 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
865 enum intel_display_power_domain domain)
866 {
867 __intel_display_power_put(dev_priv, domain);
868 intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm);
869 }
870 #endif
871
872 void
intel_display_power_get_in_set(struct drm_i915_private * i915,struct intel_display_power_domain_set * power_domain_set,enum intel_display_power_domain domain)873 intel_display_power_get_in_set(struct drm_i915_private *i915,
874 struct intel_display_power_domain_set *power_domain_set,
875 enum intel_display_power_domain domain)
876 {
877 intel_wakeref_t __maybe_unused wf;
878
879 drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
880
881 wf = intel_display_power_get(i915, domain);
882 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
883 power_domain_set->wakerefs[domain] = wf;
884 #endif
885 set_bit(domain, power_domain_set->mask.bits);
886 }
887
888 bool
intel_display_power_get_in_set_if_enabled(struct drm_i915_private * i915,struct intel_display_power_domain_set * power_domain_set,enum intel_display_power_domain domain)889 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
890 struct intel_display_power_domain_set *power_domain_set,
891 enum intel_display_power_domain domain)
892 {
893 intel_wakeref_t wf;
894
895 drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
896
897 wf = intel_display_power_get_if_enabled(i915, domain);
898 if (!wf)
899 return false;
900
901 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
902 power_domain_set->wakerefs[domain] = wf;
903 #endif
904 set_bit(domain, power_domain_set->mask.bits);
905
906 return true;
907 }
908
909 void
intel_display_power_put_mask_in_set(struct drm_i915_private * i915,struct intel_display_power_domain_set * power_domain_set,struct intel_power_domain_mask * mask)910 intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
911 struct intel_display_power_domain_set *power_domain_set,
912 struct intel_power_domain_mask *mask)
913 {
914 enum intel_display_power_domain domain;
915
916 #ifdef notyet
917 drm_WARN_ON(&i915->drm,
918 !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
919 #endif
920
921 for_each_power_domain(domain, mask) {
922 intel_wakeref_t __maybe_unused wf = -1;
923
924 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
925 wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
926 #endif
927 intel_display_power_put(i915, domain, wf);
928 clear_bit(domain, power_domain_set->mask.bits);
929 }
930 }
931
932 static int
sanitize_disable_power_well_option(const struct drm_i915_private * dev_priv,int disable_power_well)933 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
934 int disable_power_well)
935 {
936 if (disable_power_well >= 0)
937 return !!disable_power_well;
938
939 return 1;
940 }
941
get_allowed_dc_mask(const struct drm_i915_private * dev_priv,int enable_dc)942 static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
943 int enable_dc)
944 {
945 u32 mask;
946 int requested_dc;
947 int max_dc;
948
949 if (!HAS_DISPLAY(dev_priv))
950 return 0;
951
952 if (IS_DG2(dev_priv))
953 max_dc = 1;
954 else if (IS_DG1(dev_priv))
955 max_dc = 3;
956 else if (DISPLAY_VER(dev_priv) >= 12)
957 max_dc = 4;
958 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
959 max_dc = 1;
960 else if (DISPLAY_VER(dev_priv) >= 9)
961 max_dc = 2;
962 else
963 max_dc = 0;
964
965 /*
966 * DC9 has a separate HW flow from the rest of the DC states,
967 * not depending on the DMC firmware. It's needed by system
968 * suspend/resume, so allow it unconditionally.
969 */
970 mask = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
971 DISPLAY_VER(dev_priv) >= 11 ?
972 DC_STATE_EN_DC9 : 0;
973
974 if (!dev_priv->params.disable_power_well)
975 max_dc = 0;
976
977 if (enable_dc >= 0 && enable_dc <= max_dc) {
978 requested_dc = enable_dc;
979 } else if (enable_dc == -1) {
980 requested_dc = max_dc;
981 } else if (enable_dc > max_dc && enable_dc <= 4) {
982 drm_dbg_kms(&dev_priv->drm,
983 "Adjusting requested max DC state (%d->%d)\n",
984 enable_dc, max_dc);
985 requested_dc = max_dc;
986 } else {
987 drm_err(&dev_priv->drm,
988 "Unexpected value for enable_dc (%d)\n", enable_dc);
989 requested_dc = max_dc;
990 }
991
992 switch (requested_dc) {
993 case 4:
994 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
995 break;
996 case 3:
997 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
998 break;
999 case 2:
1000 mask |= DC_STATE_EN_UPTO_DC6;
1001 break;
1002 case 1:
1003 mask |= DC_STATE_EN_UPTO_DC5;
1004 break;
1005 }
1006
1007 drm_dbg_kms(&dev_priv->drm, "Allowed DC state mask %02x\n", mask);
1008
1009 return mask;
1010 }
1011
1012 /**
1013 * intel_power_domains_init - initializes the power domain structures
1014 * @dev_priv: i915 device instance
1015 *
1016 * Initializes the power domain structures for @dev_priv depending upon the
1017 * supported platform.
1018 */
intel_power_domains_init(struct drm_i915_private * dev_priv)1019 int intel_power_domains_init(struct drm_i915_private *dev_priv)
1020 {
1021 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1022
1023 dev_priv->params.disable_power_well =
1024 sanitize_disable_power_well_option(dev_priv,
1025 dev_priv->params.disable_power_well);
1026 power_domains->allowed_dc_mask =
1027 get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
1028
1029 power_domains->target_dc_state =
1030 sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
1031
1032 rw_init(&power_domains->lock, "ipdl");
1033
1034 INIT_DELAYED_WORK(&power_domains->async_put_work,
1035 intel_display_power_put_async_work);
1036
1037 return intel_display_power_map_init(power_domains);
1038 }
1039
1040 /**
1041 * intel_power_domains_cleanup - clean up power domains resources
1042 * @dev_priv: i915 device instance
1043 *
1044 * Release any resources acquired by intel_power_domains_init()
1045 */
intel_power_domains_cleanup(struct drm_i915_private * dev_priv)1046 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
1047 {
1048 intel_display_power_map_cleanup(&dev_priv->display.power.domains);
1049 }
1050
intel_power_domains_sync_hw(struct drm_i915_private * dev_priv)1051 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
1052 {
1053 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1054 struct i915_power_well *power_well;
1055
1056 mutex_lock(&power_domains->lock);
1057 for_each_power_well(dev_priv, power_well)
1058 intel_power_well_sync_hw(dev_priv, power_well);
1059 mutex_unlock(&power_domains->lock);
1060 }
1061
gen9_dbuf_slice_set(struct drm_i915_private * dev_priv,enum dbuf_slice slice,bool enable)1062 static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
1063 enum dbuf_slice slice, bool enable)
1064 {
1065 i915_reg_t reg = DBUF_CTL_S(slice);
1066 bool state;
1067
1068 intel_de_rmw(dev_priv, reg, DBUF_POWER_REQUEST,
1069 enable ? DBUF_POWER_REQUEST : 0);
1070 intel_de_posting_read(dev_priv, reg);
1071 udelay(10);
1072
1073 state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE;
1074 drm_WARN(&dev_priv->drm, enable != state,
1075 "DBuf slice %d power %s timeout!\n",
1076 slice, str_enable_disable(enable));
1077 }
1078
gen9_dbuf_slices_update(struct drm_i915_private * dev_priv,u8 req_slices)1079 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
1080 u8 req_slices)
1081 {
1082 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1083 u8 slice_mask = DISPLAY_INFO(dev_priv)->dbuf.slice_mask;
1084 enum dbuf_slice slice;
1085
1086 drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
1087 "Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n",
1088 req_slices, slice_mask);
1089
1090 drm_dbg_kms(&dev_priv->drm, "Updating dbuf slices to 0x%x\n",
1091 req_slices);
1092
1093 /*
1094 * Might be running this in parallel to gen9_dc_off_power_well_enable
1095 * being called from intel_dp_detect for instance,
1096 * which causes assertion triggered by race condition,
1097 * as gen9_assert_dbuf_enabled might preempt this when registers
1098 * were already updated, while dev_priv was not.
1099 */
1100 mutex_lock(&power_domains->lock);
1101
1102 for_each_dbuf_slice(dev_priv, slice)
1103 gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice));
1104
1105 dev_priv->display.dbuf.enabled_slices = req_slices;
1106
1107 mutex_unlock(&power_domains->lock);
1108 }
1109
gen9_dbuf_enable(struct drm_i915_private * dev_priv)1110 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
1111 {
1112 u8 slices_mask;
1113
1114 dev_priv->display.dbuf.enabled_slices =
1115 intel_enabled_dbuf_slices_mask(dev_priv);
1116
1117 slices_mask = BIT(DBUF_S1) | dev_priv->display.dbuf.enabled_slices;
1118
1119 if (DISPLAY_VER(dev_priv) >= 14)
1120 intel_pmdemand_program_dbuf(dev_priv, slices_mask);
1121
1122 /*
1123 * Just power up at least 1 slice, we will
1124 * figure out later which slices we have and what we need.
1125 */
1126 gen9_dbuf_slices_update(dev_priv, slices_mask);
1127 }
1128
gen9_dbuf_disable(struct drm_i915_private * dev_priv)1129 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
1130 {
1131 gen9_dbuf_slices_update(dev_priv, 0);
1132
1133 if (DISPLAY_VER(dev_priv) >= 14)
1134 intel_pmdemand_program_dbuf(dev_priv, 0);
1135 }
1136
gen12_dbuf_slices_config(struct drm_i915_private * dev_priv)1137 static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
1138 {
1139 enum dbuf_slice slice;
1140
1141 if (IS_ALDERLAKE_P(dev_priv))
1142 return;
1143
1144 for_each_dbuf_slice(dev_priv, slice)
1145 intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
1146 DBUF_TRACKER_STATE_SERVICE_MASK,
1147 DBUF_TRACKER_STATE_SERVICE(8));
1148 }
1149
icl_mbus_init(struct drm_i915_private * dev_priv)1150 static void icl_mbus_init(struct drm_i915_private *dev_priv)
1151 {
1152 unsigned long abox_regs = DISPLAY_INFO(dev_priv)->abox_mask;
1153 u32 mask, val, i;
1154
1155 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
1156 return;
1157
1158 mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
1159 MBUS_ABOX_BT_CREDIT_POOL2_MASK |
1160 MBUS_ABOX_B_CREDIT_MASK |
1161 MBUS_ABOX_BW_CREDIT_MASK;
1162 val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
1163 MBUS_ABOX_BT_CREDIT_POOL2(16) |
1164 MBUS_ABOX_B_CREDIT(1) |
1165 MBUS_ABOX_BW_CREDIT(1);
1166
1167 /*
1168 * gen12 platforms that use abox1 and abox2 for pixel data reads still
1169 * expect us to program the abox_ctl0 register as well, even though
1170 * we don't have to program other instance-0 registers like BW_BUDDY.
1171 */
1172 if (DISPLAY_VER(dev_priv) == 12)
1173 abox_regs |= BIT(0);
1174
1175 for_each_set_bit(i, &abox_regs, sizeof(abox_regs))
1176 intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val);
1177 }
1178
hsw_assert_cdclk(struct drm_i915_private * dev_priv)1179 static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
1180 {
1181 u32 val = intel_de_read(dev_priv, LCPLL_CTL);
1182
1183 /*
1184 * The LCPLL register should be turned on by the BIOS. For now
1185 * let's just check its state and print errors in case
1186 * something is wrong. Don't even try to turn it on.
1187 */
1188
1189 if (val & LCPLL_CD_SOURCE_FCLK)
1190 drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n");
1191
1192 if (val & LCPLL_PLL_DISABLE)
1193 drm_err(&dev_priv->drm, "LCPLL is disabled\n");
1194
1195 if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC)
1196 drm_err(&dev_priv->drm, "LCPLL not using non-SSC reference\n");
1197 }
1198
assert_can_disable_lcpll(struct drm_i915_private * dev_priv)1199 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
1200 {
1201 struct intel_crtc *crtc;
1202
1203 for_each_intel_crtc(&dev_priv->drm, crtc)
1204 I915_STATE_WARN(dev_priv, crtc->active,
1205 "CRTC for pipe %c enabled\n",
1206 pipe_name(crtc->pipe));
1207
1208 I915_STATE_WARN(dev_priv, intel_de_read(dev_priv, HSW_PWR_WELL_CTL2),
1209 "Display power well on\n");
1210 I915_STATE_WARN(dev_priv,
1211 intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE,
1212 "SPLL enabled\n");
1213 I915_STATE_WARN(dev_priv,
1214 intel_de_read(dev_priv, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,
1215 "WRPLL1 enabled\n");
1216 I915_STATE_WARN(dev_priv,
1217 intel_de_read(dev_priv, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,
1218 "WRPLL2 enabled\n");
1219 I915_STATE_WARN(dev_priv,
1220 intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON,
1221 "Panel power on\n");
1222 I915_STATE_WARN(dev_priv,
1223 intel_de_read(dev_priv, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
1224 "CPU PWM1 enabled\n");
1225 if (IS_HASWELL(dev_priv))
1226 I915_STATE_WARN(dev_priv,
1227 intel_de_read(dev_priv, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
1228 "CPU PWM2 enabled\n");
1229 I915_STATE_WARN(dev_priv,
1230 intel_de_read(dev_priv, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
1231 "PCH PWM1 enabled\n");
1232 I915_STATE_WARN(dev_priv,
1233 (intel_de_read(dev_priv, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),
1234 "Utility pin enabled in PWM mode\n");
1235 I915_STATE_WARN(dev_priv,
1236 intel_de_read(dev_priv, PCH_GTC_CTL) & PCH_GTC_ENABLE,
1237 "PCH GTC enabled\n");
1238
1239 /*
1240 * In theory we can still leave IRQs enabled, as long as only the HPD
1241 * interrupts remain enabled. We used to check for that, but since it's
1242 * gen-specific and since we only disable LCPLL after we fully disable
1243 * the interrupts, the check below should be enough.
1244 */
1245 I915_STATE_WARN(dev_priv, intel_irqs_enabled(dev_priv),
1246 "IRQs enabled\n");
1247 }
1248
hsw_read_dcomp(struct drm_i915_private * dev_priv)1249 static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
1250 {
1251 if (IS_HASWELL(dev_priv))
1252 return intel_de_read(dev_priv, D_COMP_HSW);
1253 else
1254 return intel_de_read(dev_priv, D_COMP_BDW);
1255 }
1256
hsw_write_dcomp(struct drm_i915_private * dev_priv,u32 val)1257 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
1258 {
1259 if (IS_HASWELL(dev_priv)) {
1260 if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val))
1261 drm_dbg_kms(&dev_priv->drm,
1262 "Failed to write to D_COMP\n");
1263 } else {
1264 intel_de_write(dev_priv, D_COMP_BDW, val);
1265 intel_de_posting_read(dev_priv, D_COMP_BDW);
1266 }
1267 }
1268
1269 /*
1270 * This function implements pieces of two sequences from BSpec:
1271 * - Sequence for display software to disable LCPLL
1272 * - Sequence for display software to allow package C8+
1273 * The steps implemented here are just the steps that actually touch the LCPLL
1274 * register. Callers should take care of disabling all the display engine
1275 * functions, doing the mode unset, fixing interrupts, etc.
1276 */
hsw_disable_lcpll(struct drm_i915_private * dev_priv,bool switch_to_fclk,bool allow_power_down)1277 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
1278 bool switch_to_fclk, bool allow_power_down)
1279 {
1280 u32 val;
1281
1282 assert_can_disable_lcpll(dev_priv);
1283
1284 val = intel_de_read(dev_priv, LCPLL_CTL);
1285
1286 if (switch_to_fclk) {
1287 val |= LCPLL_CD_SOURCE_FCLK;
1288 intel_de_write(dev_priv, LCPLL_CTL, val);
1289
1290 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
1291 LCPLL_CD_SOURCE_FCLK_DONE, 1))
1292 drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
1293
1294 val = intel_de_read(dev_priv, LCPLL_CTL);
1295 }
1296
1297 val |= LCPLL_PLL_DISABLE;
1298 intel_de_write(dev_priv, LCPLL_CTL, val);
1299 intel_de_posting_read(dev_priv, LCPLL_CTL);
1300
1301 if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
1302 drm_err(&dev_priv->drm, "LCPLL still locked\n");
1303
1304 val = hsw_read_dcomp(dev_priv);
1305 val |= D_COMP_COMP_DISABLE;
1306 hsw_write_dcomp(dev_priv, val);
1307 ndelay(100);
1308
1309 if (wait_for((hsw_read_dcomp(dev_priv) &
1310 D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
1311 drm_err(&dev_priv->drm, "D_COMP RCOMP still in progress\n");
1312
1313 if (allow_power_down) {
1314 intel_de_rmw(dev_priv, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW);
1315 intel_de_posting_read(dev_priv, LCPLL_CTL);
1316 }
1317 }
1318
1319 /*
1320 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
1321 * source.
1322 */
hsw_restore_lcpll(struct drm_i915_private * dev_priv)1323 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
1324 {
1325 u32 val;
1326
1327 val = intel_de_read(dev_priv, LCPLL_CTL);
1328
1329 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
1330 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
1331 return;
1332
1333 /*
1334 * Make sure we're not on PC8 state before disabling PC8, otherwise
1335 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
1336 */
1337 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
1338
1339 if (val & LCPLL_POWER_DOWN_ALLOW) {
1340 val &= ~LCPLL_POWER_DOWN_ALLOW;
1341 intel_de_write(dev_priv, LCPLL_CTL, val);
1342 intel_de_posting_read(dev_priv, LCPLL_CTL);
1343 }
1344
1345 val = hsw_read_dcomp(dev_priv);
1346 val |= D_COMP_COMP_FORCE;
1347 val &= ~D_COMP_COMP_DISABLE;
1348 hsw_write_dcomp(dev_priv, val);
1349
1350 val = intel_de_read(dev_priv, LCPLL_CTL);
1351 val &= ~LCPLL_PLL_DISABLE;
1352 intel_de_write(dev_priv, LCPLL_CTL, val);
1353
1354 if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
1355 drm_err(&dev_priv->drm, "LCPLL not locked yet\n");
1356
1357 if (val & LCPLL_CD_SOURCE_FCLK) {
1358 intel_de_rmw(dev_priv, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0);
1359
1360 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
1361 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
1362 drm_err(&dev_priv->drm,
1363 "Switching back to LCPLL failed\n");
1364 }
1365
1366 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
1367
1368 intel_update_cdclk(dev_priv);
1369 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
1370 }
1371
1372 /*
1373 * Package states C8 and deeper are really deep PC states that can only be
1374 * reached when all the devices on the system allow it, so even if the graphics
1375 * device allows PC8+, it doesn't mean the system will actually get to these
1376 * states. Our driver only allows PC8+ when going into runtime PM.
1377 *
1378 * The requirements for PC8+ are that all the outputs are disabled, the power
1379 * well is disabled and most interrupts are disabled, and these are also
1380 * requirements for runtime PM. When these conditions are met, we manually do
1381 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
1382 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
1383 * hang the machine.
1384 *
1385 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1386 * the state of some registers, so when we come back from PC8+ we need to
1387 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1388 * need to take care of the registers kept by RC6. Notice that this happens even
1389 * if we don't put the device in PCI D3 state (which is what currently happens
1390 * because of the runtime PM support).
1391 *
1392 * For more, read "Display Sequences for Package C8" on the hardware
1393 * documentation.
1394 */
hsw_enable_pc8(struct drm_i915_private * dev_priv)1395 static void hsw_enable_pc8(struct drm_i915_private *dev_priv)
1396 {
1397 drm_dbg_kms(&dev_priv->drm, "Enabling package C8+\n");
1398
1399 if (HAS_PCH_LPT_LP(dev_priv))
1400 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
1401 PCH_LP_PARTITION_LEVEL_DISABLE, 0);
1402
1403 lpt_disable_clkout_dp(dev_priv);
1404 hsw_disable_lcpll(dev_priv, true, true);
1405 }
1406
hsw_disable_pc8(struct drm_i915_private * dev_priv)1407 static void hsw_disable_pc8(struct drm_i915_private *dev_priv)
1408 {
1409 drm_dbg_kms(&dev_priv->drm, "Disabling package C8+\n");
1410
1411 hsw_restore_lcpll(dev_priv);
1412 intel_init_pch_refclk(dev_priv);
1413
1414 /* Many display registers don't survive PC8+ */
1415 intel_clock_gating_init(dev_priv);
1416 }
1417
intel_pch_reset_handshake(struct drm_i915_private * dev_priv,bool enable)1418 static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
1419 bool enable)
1420 {
1421 i915_reg_t reg;
1422 u32 reset_bits;
1423
1424 if (IS_IVYBRIDGE(dev_priv)) {
1425 reg = GEN7_MSG_CTL;
1426 reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;
1427 } else {
1428 reg = HSW_NDE_RSTWRN_OPT;
1429 reset_bits = RESET_PCH_HANDSHAKE_ENABLE;
1430 }
1431
1432 if (DISPLAY_VER(dev_priv) >= 14)
1433 reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN;
1434
1435 intel_de_rmw(dev_priv, reg, reset_bits, enable ? reset_bits : 0);
1436 }
1437
skl_display_core_init(struct drm_i915_private * dev_priv,bool resume)1438 static void skl_display_core_init(struct drm_i915_private *dev_priv,
1439 bool resume)
1440 {
1441 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1442 struct i915_power_well *well;
1443
1444 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1445
1446 /* enable PCH reset handshake */
1447 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
1448
1449 if (!HAS_DISPLAY(dev_priv))
1450 return;
1451
1452 /* enable PG1 and Misc I/O */
1453 mutex_lock(&power_domains->lock);
1454
1455 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1456 intel_power_well_enable(dev_priv, well);
1457
1458 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1459 intel_power_well_enable(dev_priv, well);
1460
1461 mutex_unlock(&power_domains->lock);
1462
1463 intel_cdclk_init_hw(dev_priv);
1464
1465 gen9_dbuf_enable(dev_priv);
1466
1467 if (resume)
1468 intel_dmc_load_program(dev_priv);
1469 }
1470
skl_display_core_uninit(struct drm_i915_private * dev_priv)1471 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
1472 {
1473 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1474 struct i915_power_well *well;
1475
1476 if (!HAS_DISPLAY(dev_priv))
1477 return;
1478
1479 gen9_disable_dc_states(dev_priv);
1480 /* TODO: disable DMC program */
1481
1482 gen9_dbuf_disable(dev_priv);
1483
1484 intel_cdclk_uninit_hw(dev_priv);
1485
1486 /* The spec doesn't call for removing the reset handshake flag */
1487 /* disable PG1 and Misc I/O */
1488
1489 mutex_lock(&power_domains->lock);
1490
1491 /*
1492 * BSpec says to keep the MISC IO power well enabled here, only
1493 * remove our request for power well 1.
1494 * Note that even though the driver's request is removed power well 1
1495 * may stay enabled after this due to DMC's own request on it.
1496 */
1497 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1498 intel_power_well_disable(dev_priv, well);
1499
1500 mutex_unlock(&power_domains->lock);
1501
1502 usleep_range(10, 30); /* 10 us delay per Bspec */
1503 }
1504
bxt_display_core_init(struct drm_i915_private * dev_priv,bool resume)1505 static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume)
1506 {
1507 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1508 struct i915_power_well *well;
1509
1510 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1511
1512 /*
1513 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
1514 * or else the reset will hang because there is no PCH to respond.
1515 * Move the handshake programming to initialization sequence.
1516 * Previously was left up to BIOS.
1517 */
1518 intel_pch_reset_handshake(dev_priv, false);
1519
1520 if (!HAS_DISPLAY(dev_priv))
1521 return;
1522
1523 /* Enable PG1 */
1524 mutex_lock(&power_domains->lock);
1525
1526 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1527 intel_power_well_enable(dev_priv, well);
1528
1529 mutex_unlock(&power_domains->lock);
1530
1531 intel_cdclk_init_hw(dev_priv);
1532
1533 gen9_dbuf_enable(dev_priv);
1534
1535 if (resume)
1536 intel_dmc_load_program(dev_priv);
1537 }
1538
bxt_display_core_uninit(struct drm_i915_private * dev_priv)1539 static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
1540 {
1541 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1542 struct i915_power_well *well;
1543
1544 if (!HAS_DISPLAY(dev_priv))
1545 return;
1546
1547 gen9_disable_dc_states(dev_priv);
1548 /* TODO: disable DMC program */
1549
1550 gen9_dbuf_disable(dev_priv);
1551
1552 intel_cdclk_uninit_hw(dev_priv);
1553
1554 /* The spec doesn't call for removing the reset handshake flag */
1555
1556 /*
1557 * Disable PW1 (PG1).
1558 * Note that even though the driver's request is removed power well 1
1559 * may stay enabled after this due to DMC's own request on it.
1560 */
1561 mutex_lock(&power_domains->lock);
1562
1563 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1564 intel_power_well_disable(dev_priv, well);
1565
1566 mutex_unlock(&power_domains->lock);
1567
1568 usleep_range(10, 30); /* 10 us delay per Bspec */
1569 }
1570
1571 struct buddy_page_mask {
1572 u32 page_mask;
1573 u8 type;
1574 u8 num_channels;
1575 };
1576
1577 static const struct buddy_page_mask tgl_buddy_page_masks[] = {
1578 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF },
1579 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0xF },
1580 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C },
1581 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1C },
1582 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F },
1583 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x1E },
1584 { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 },
1585 { .num_channels = 4, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x38 },
1586 {}
1587 };
1588
1589 static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = {
1590 { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 },
1591 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0x1 },
1592 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0x1 },
1593 { .num_channels = 1, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1 },
1594 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 },
1595 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x3 },
1596 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x3 },
1597 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x3 },
1598 {}
1599 };
1600
tgl_bw_buddy_init(struct drm_i915_private * dev_priv)1601 static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
1602 {
1603 enum intel_dram_type type = dev_priv->dram_info.type;
1604 u8 num_channels = dev_priv->dram_info.num_channels;
1605 const struct buddy_page_mask *table;
1606 unsigned long abox_mask = DISPLAY_INFO(dev_priv)->abox_mask;
1607 int config, i;
1608
1609 /* BW_BUDDY registers are not used on dgpu's beyond DG1 */
1610 if (IS_DGFX(dev_priv) && !IS_DG1(dev_priv))
1611 return;
1612
1613 if (IS_ALDERLAKE_S(dev_priv) ||
1614 (IS_ROCKETLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)))
1615 /* Wa_1409767108 */
1616 table = wa_1409767108_buddy_page_masks;
1617 else
1618 table = tgl_buddy_page_masks;
1619
1620 for (config = 0; table[config].page_mask != 0; config++)
1621 if (table[config].num_channels == num_channels &&
1622 table[config].type == type)
1623 break;
1624
1625 if (table[config].page_mask == 0) {
1626 drm_dbg(&dev_priv->drm,
1627 "Unknown memory configuration; disabling address buddy logic.\n");
1628 for_each_set_bit(i, &abox_mask, sizeof(abox_mask))
1629 intel_de_write(dev_priv, BW_BUDDY_CTL(i),
1630 BW_BUDDY_DISABLE);
1631 } else {
1632 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) {
1633 intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
1634 table[config].page_mask);
1635
1636 /* Wa_22010178259:tgl,dg1,rkl,adl-s */
1637 if (DISPLAY_VER(dev_priv) == 12)
1638 intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
1639 BW_BUDDY_TLB_REQ_TIMER_MASK,
1640 BW_BUDDY_TLB_REQ_TIMER(0x8));
1641 }
1642 }
1643 }
1644
icl_display_core_init(struct drm_i915_private * dev_priv,bool resume)1645 static void icl_display_core_init(struct drm_i915_private *dev_priv,
1646 bool resume)
1647 {
1648 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1649 struct i915_power_well *well;
1650
1651 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1652
1653 /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
1654 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
1655 INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
1656 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
1657 PCH_DPMGUNIT_CLOCK_GATE_DISABLE);
1658
1659 /* 1. Enable PCH reset handshake. */
1660 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
1661
1662 if (!HAS_DISPLAY(dev_priv))
1663 return;
1664
1665 /* 2. Initialize all combo phys */
1666 intel_combo_phy_init(dev_priv);
1667
1668 /*
1669 * 3. Enable Power Well 1 (PG1).
1670 * The AUX IO power wells will be enabled on demand.
1671 */
1672 mutex_lock(&power_domains->lock);
1673 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1674 intel_power_well_enable(dev_priv, well);
1675 mutex_unlock(&power_domains->lock);
1676
1677 if (DISPLAY_VER(dev_priv) == 14)
1678 intel_de_rmw(dev_priv, DC_STATE_EN,
1679 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0);
1680
1681 /* 4. Enable CDCLK. */
1682 intel_cdclk_init_hw(dev_priv);
1683
1684 if (DISPLAY_VER(dev_priv) >= 12)
1685 gen12_dbuf_slices_config(dev_priv);
1686
1687 /* 5. Enable DBUF. */
1688 gen9_dbuf_enable(dev_priv);
1689
1690 /* 6. Setup MBUS. */
1691 icl_mbus_init(dev_priv);
1692
1693 /* 7. Program arbiter BW_BUDDY registers */
1694 if (DISPLAY_VER(dev_priv) >= 12)
1695 tgl_bw_buddy_init(dev_priv);
1696
1697 /* 8. Ensure PHYs have completed calibration and adaptation */
1698 if (IS_DG2(dev_priv))
1699 intel_snps_phy_wait_for_calibration(dev_priv);
1700
1701 if (resume)
1702 intel_dmc_load_program(dev_priv);
1703
1704 /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p */
1705 if (DISPLAY_VER(dev_priv) >= 12)
1706 intel_de_rmw(dev_priv, GEN11_CHICKEN_DCPR_2, 0,
1707 DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
1708 DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR);
1709
1710 /* Wa_14011503030:xelpd */
1711 if (DISPLAY_VER(dev_priv) >= 13)
1712 intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
1713 }
1714
icl_display_core_uninit(struct drm_i915_private * dev_priv)1715 static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
1716 {
1717 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1718 struct i915_power_well *well;
1719
1720 if (!HAS_DISPLAY(dev_priv))
1721 return;
1722
1723 gen9_disable_dc_states(dev_priv);
1724 intel_dmc_disable_program(dev_priv);
1725
1726 /* 1. Disable all display engine functions -> aready done */
1727
1728 /* 2. Disable DBUF */
1729 gen9_dbuf_disable(dev_priv);
1730
1731 /* 3. Disable CD clock */
1732 intel_cdclk_uninit_hw(dev_priv);
1733
1734 if (DISPLAY_VER(dev_priv) == 14)
1735 intel_de_rmw(dev_priv, DC_STATE_EN, 0,
1736 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH);
1737
1738 /*
1739 * 4. Disable Power Well 1 (PG1).
1740 * The AUX IO power wells are toggled on demand, so they are already
1741 * disabled at this point.
1742 */
1743 mutex_lock(&power_domains->lock);
1744 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1745 intel_power_well_disable(dev_priv, well);
1746 mutex_unlock(&power_domains->lock);
1747
1748 /* 5. */
1749 intel_combo_phy_uninit(dev_priv);
1750 }
1751
chv_phy_control_init(struct drm_i915_private * dev_priv)1752 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
1753 {
1754 struct i915_power_well *cmn_bc =
1755 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1756 struct i915_power_well *cmn_d =
1757 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
1758
1759 /*
1760 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
1761 * workaround never ever read DISPLAY_PHY_CONTROL, and
1762 * instead maintain a shadow copy ourselves. Use the actual
1763 * power well state and lane status to reconstruct the
1764 * expected initial value.
1765 */
1766 dev_priv->display.power.chv_phy_control =
1767 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
1768 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
1769 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
1770 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
1771 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
1772
1773 /*
1774 * If all lanes are disabled we leave the override disabled
1775 * with all power down bits cleared to match the state we
1776 * would use after disabling the port. Otherwise enable the
1777 * override and set the lane powerdown bits accding to the
1778 * current lane status.
1779 */
1780 if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
1781 u32 status = intel_de_read(dev_priv, DPLL(PIPE_A));
1782 unsigned int mask;
1783
1784 mask = status & DPLL_PORTB_READY_MASK;
1785 if (mask == 0xf)
1786 mask = 0x0;
1787 else
1788 dev_priv->display.power.chv_phy_control |=
1789 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
1790
1791 dev_priv->display.power.chv_phy_control |=
1792 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
1793
1794 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
1795 if (mask == 0xf)
1796 mask = 0x0;
1797 else
1798 dev_priv->display.power.chv_phy_control |=
1799 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
1800
1801 dev_priv->display.power.chv_phy_control |=
1802 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
1803
1804 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
1805
1806 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = false;
1807 } else {
1808 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true;
1809 }
1810
1811 if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
1812 u32 status = intel_de_read(dev_priv, DPIO_PHY_STATUS);
1813 unsigned int mask;
1814
1815 mask = status & DPLL_PORTD_READY_MASK;
1816
1817 if (mask == 0xf)
1818 mask = 0x0;
1819 else
1820 dev_priv->display.power.chv_phy_control |=
1821 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
1822
1823 dev_priv->display.power.chv_phy_control |=
1824 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
1825
1826 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
1827
1828 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = false;
1829 } else {
1830 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = true;
1831 }
1832
1833 drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n",
1834 dev_priv->display.power.chv_phy_control);
1835
1836 /* Defer application of initial phy_control to enabling the powerwell */
1837 }
1838
vlv_cmnlane_wa(struct drm_i915_private * dev_priv)1839 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
1840 {
1841 struct i915_power_well *cmn =
1842 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1843 struct i915_power_well *disp2d =
1844 lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D);
1845
1846 /* If the display might be already active skip this */
1847 if (intel_power_well_is_enabled(dev_priv, cmn) &&
1848 intel_power_well_is_enabled(dev_priv, disp2d) &&
1849 intel_de_read(dev_priv, DPIO_CTL) & DPIO_CMNRST)
1850 return;
1851
1852 drm_dbg_kms(&dev_priv->drm, "toggling display PHY side reset\n");
1853
1854 /* cmnlane needs DPLL registers */
1855 intel_power_well_enable(dev_priv, disp2d);
1856
1857 /*
1858 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1859 * Need to assert and de-assert PHY SB reset by gating the
1860 * common lane power, then un-gating it.
1861 * Simply ungating isn't enough to reset the PHY enough to get
1862 * ports and lanes running.
1863 */
1864 intel_power_well_disable(dev_priv, cmn);
1865 }
1866
vlv_punit_is_power_gated(struct drm_i915_private * dev_priv,u32 reg0)1867 static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0)
1868 {
1869 bool ret;
1870
1871 vlv_punit_get(dev_priv);
1872 ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE;
1873 vlv_punit_put(dev_priv);
1874
1875 return ret;
1876 }
1877
assert_ved_power_gated(struct drm_i915_private * dev_priv)1878 static void assert_ved_power_gated(struct drm_i915_private *dev_priv)
1879 {
1880 drm_WARN(&dev_priv->drm,
1881 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0),
1882 "VED not power gated\n");
1883 }
1884
assert_isp_power_gated(struct drm_i915_private * dev_priv)1885 static void assert_isp_power_gated(struct drm_i915_private *dev_priv)
1886 {
1887 #ifdef notyet
1888 static const struct pci_device_id isp_ids[] = {
1889 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)},
1890 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x22b8)},
1891 {}
1892 };
1893
1894 drm_WARN(&dev_priv->drm, !pci_dev_present(isp_ids) &&
1895 !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0),
1896 "ISP not power gated\n");
1897 #endif
1898 }
1899
1900 static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1901
1902 /**
1903 * intel_power_domains_init_hw - initialize hardware power domain state
1904 * @i915: i915 device instance
1905 * @resume: Called from resume code paths or not
1906 *
1907 * This function initializes the hardware power domain state and enables all
1908 * power wells belonging to the INIT power domain. Power wells in other
1909 * domains (and not in the INIT domain) are referenced or disabled by
1910 * intel_modeset_readout_hw_state(). After that the reference count of each
1911 * power well must match its HW enabled state, see
1912 * intel_power_domains_verify_state().
1913 *
1914 * It will return with power domains disabled (to be enabled later by
1915 * intel_power_domains_enable()) and must be paired with
1916 * intel_power_domains_driver_remove().
1917 */
intel_power_domains_init_hw(struct drm_i915_private * i915,bool resume)1918 void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
1919 {
1920 struct i915_power_domains *power_domains = &i915->display.power.domains;
1921
1922 power_domains->initializing = true;
1923
1924 if (DISPLAY_VER(i915) >= 11) {
1925 icl_display_core_init(i915, resume);
1926 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
1927 bxt_display_core_init(i915, resume);
1928 } else if (DISPLAY_VER(i915) == 9) {
1929 skl_display_core_init(i915, resume);
1930 } else if (IS_CHERRYVIEW(i915)) {
1931 mutex_lock(&power_domains->lock);
1932 chv_phy_control_init(i915);
1933 mutex_unlock(&power_domains->lock);
1934 assert_isp_power_gated(i915);
1935 } else if (IS_VALLEYVIEW(i915)) {
1936 mutex_lock(&power_domains->lock);
1937 vlv_cmnlane_wa(i915);
1938 mutex_unlock(&power_domains->lock);
1939 assert_ved_power_gated(i915);
1940 assert_isp_power_gated(i915);
1941 } else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) {
1942 hsw_assert_cdclk(i915);
1943 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
1944 } else if (IS_IVYBRIDGE(i915)) {
1945 intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
1946 }
1947
1948 /*
1949 * Keep all power wells enabled for any dependent HW access during
1950 * initialization and to make sure we keep BIOS enabled display HW
1951 * resources powered until display HW readout is complete. We drop
1952 * this reference in intel_power_domains_enable().
1953 */
1954 drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
1955 power_domains->init_wakeref =
1956 intel_display_power_get(i915, POWER_DOMAIN_INIT);
1957
1958 /* Disable power support if the user asked so. */
1959 if (!i915->params.disable_power_well) {
1960 drm_WARN_ON(&i915->drm, power_domains->disable_wakeref);
1961 i915->display.power.domains.disable_wakeref = intel_display_power_get(i915,
1962 POWER_DOMAIN_INIT);
1963 }
1964 intel_power_domains_sync_hw(i915);
1965
1966 power_domains->initializing = false;
1967 }
1968
1969 /**
1970 * intel_power_domains_driver_remove - deinitialize hw power domain state
1971 * @i915: i915 device instance
1972 *
1973 * De-initializes the display power domain HW state. It also ensures that the
1974 * device stays powered up so that the driver can be reloaded.
1975 *
1976 * It must be called with power domains already disabled (after a call to
1977 * intel_power_domains_disable()) and must be paired with
1978 * intel_power_domains_init_hw().
1979 */
intel_power_domains_driver_remove(struct drm_i915_private * i915)1980 void intel_power_domains_driver_remove(struct drm_i915_private *i915)
1981 {
1982 intel_wakeref_t wakeref __maybe_unused =
1983 fetch_and_zero(&i915->display.power.domains.init_wakeref);
1984
1985 /* Remove the refcount we took to keep power well support disabled. */
1986 if (!i915->params.disable_power_well)
1987 intel_display_power_put(i915, POWER_DOMAIN_INIT,
1988 fetch_and_zero(&i915->display.power.domains.disable_wakeref));
1989
1990 intel_display_power_flush_work_sync(i915);
1991
1992 intel_power_domains_verify_state(i915);
1993
1994 /* Keep the power well enabled, but cancel its rpm wakeref. */
1995 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1996 }
1997
1998 /**
1999 * intel_power_domains_sanitize_state - sanitize power domains state
2000 * @i915: i915 device instance
2001 *
2002 * Sanitize the power domains state during driver loading and system resume.
2003 * The function will disable all display power wells that BIOS has enabled
2004 * without a user for it (any user for a power well has taken a reference
2005 * on it by the time this function is called, after the state of all the
2006 * pipe, encoder, etc. HW resources have been sanitized).
2007 */
intel_power_domains_sanitize_state(struct drm_i915_private * i915)2008 void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
2009 {
2010 struct i915_power_domains *power_domains = &i915->display.power.domains;
2011 struct i915_power_well *power_well;
2012
2013 mutex_lock(&power_domains->lock);
2014
2015 for_each_power_well_reverse(i915, power_well) {
2016 if (power_well->desc->always_on || power_well->count ||
2017 !intel_power_well_is_enabled(i915, power_well))
2018 continue;
2019
2020 drm_dbg_kms(&i915->drm,
2021 "BIOS left unused %s power well enabled, disabling it\n",
2022 intel_power_well_name(power_well));
2023 intel_power_well_disable(i915, power_well);
2024 }
2025
2026 mutex_unlock(&power_domains->lock);
2027 }
2028
2029 /**
2030 * intel_power_domains_enable - enable toggling of display power wells
2031 * @i915: i915 device instance
2032 *
2033 * Enable the ondemand enabling/disabling of the display power wells. Note that
2034 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled
2035 * only at specific points of the display modeset sequence, thus they are not
2036 * affected by the intel_power_domains_enable()/disable() calls. The purpose
2037 * of these function is to keep the rest of power wells enabled until the end
2038 * of display HW readout (which will acquire the power references reflecting
2039 * the current HW state).
2040 */
intel_power_domains_enable(struct drm_i915_private * i915)2041 void intel_power_domains_enable(struct drm_i915_private *i915)
2042 {
2043 intel_wakeref_t wakeref __maybe_unused =
2044 fetch_and_zero(&i915->display.power.domains.init_wakeref);
2045
2046 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
2047 intel_power_domains_verify_state(i915);
2048 }
2049
2050 /**
2051 * intel_power_domains_disable - disable toggling of display power wells
2052 * @i915: i915 device instance
2053 *
2054 * Disable the ondemand enabling/disabling of the display power wells. See
2055 * intel_power_domains_enable() for which power wells this call controls.
2056 */
intel_power_domains_disable(struct drm_i915_private * i915)2057 void intel_power_domains_disable(struct drm_i915_private *i915)
2058 {
2059 struct i915_power_domains *power_domains = &i915->display.power.domains;
2060
2061 drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
2062 power_domains->init_wakeref =
2063 intel_display_power_get(i915, POWER_DOMAIN_INIT);
2064
2065 intel_power_domains_verify_state(i915);
2066 }
2067
2068 /**
2069 * intel_power_domains_suspend - suspend power domain state
2070 * @i915: i915 device instance
2071 * @s2idle: specifies whether we go to idle, or deeper sleep
2072 *
2073 * This function prepares the hardware power domain state before entering
2074 * system suspend.
2075 *
2076 * It must be called with power domains already disabled (after a call to
2077 * intel_power_domains_disable()) and paired with intel_power_domains_resume().
2078 */
intel_power_domains_suspend(struct drm_i915_private * i915,bool s2idle)2079 void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle)
2080 {
2081 struct i915_power_domains *power_domains = &i915->display.power.domains;
2082 intel_wakeref_t wakeref __maybe_unused =
2083 fetch_and_zero(&power_domains->init_wakeref);
2084
2085 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
2086
2087 /*
2088 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9
2089 * support don't manually deinit the power domains. This also means the
2090 * DMC firmware will stay active, it will power down any HW
2091 * resources as required and also enable deeper system power states
2092 * that would be blocked if the firmware was inactive.
2093 */
2094 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle &&
2095 intel_dmc_has_payload(i915)) {
2096 intel_display_power_flush_work(i915);
2097 intel_power_domains_verify_state(i915);
2098 return;
2099 }
2100
2101 /*
2102 * Even if power well support was disabled we still want to disable
2103 * power wells if power domains must be deinitialized for suspend.
2104 */
2105 if (!i915->params.disable_power_well)
2106 intel_display_power_put(i915, POWER_DOMAIN_INIT,
2107 fetch_and_zero(&i915->display.power.domains.disable_wakeref));
2108
2109 intel_display_power_flush_work(i915);
2110 intel_power_domains_verify_state(i915);
2111
2112 if (DISPLAY_VER(i915) >= 11)
2113 icl_display_core_uninit(i915);
2114 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
2115 bxt_display_core_uninit(i915);
2116 else if (DISPLAY_VER(i915) == 9)
2117 skl_display_core_uninit(i915);
2118
2119 power_domains->display_core_suspended = true;
2120 }
2121
2122 /**
2123 * intel_power_domains_resume - resume power domain state
2124 * @i915: i915 device instance
2125 *
2126 * This function resume the hardware power domain state during system resume.
2127 *
2128 * It will return with power domain support disabled (to be enabled later by
2129 * intel_power_domains_enable()) and must be paired with
2130 * intel_power_domains_suspend().
2131 */
intel_power_domains_resume(struct drm_i915_private * i915)2132 void intel_power_domains_resume(struct drm_i915_private *i915)
2133 {
2134 struct i915_power_domains *power_domains = &i915->display.power.domains;
2135
2136 if (power_domains->display_core_suspended) {
2137 intel_power_domains_init_hw(i915, true);
2138 power_domains->display_core_suspended = false;
2139 } else {
2140 drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
2141 power_domains->init_wakeref =
2142 intel_display_power_get(i915, POWER_DOMAIN_INIT);
2143 }
2144
2145 intel_power_domains_verify_state(i915);
2146 }
2147
2148 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2149
intel_power_domains_dump_info(struct drm_i915_private * i915)2150 static void intel_power_domains_dump_info(struct drm_i915_private *i915)
2151 {
2152 struct i915_power_domains *power_domains = &i915->display.power.domains;
2153 struct i915_power_well *power_well;
2154
2155 for_each_power_well(i915, power_well) {
2156 enum intel_display_power_domain domain;
2157
2158 drm_dbg(&i915->drm, "%-25s %d\n",
2159 intel_power_well_name(power_well), intel_power_well_refcount(power_well));
2160
2161 for_each_power_domain(domain, intel_power_well_domains(power_well))
2162 drm_dbg(&i915->drm, " %-23s %d\n",
2163 intel_display_power_domain_str(domain),
2164 power_domains->domain_use_count[domain]);
2165 }
2166 }
2167
2168 /**
2169 * intel_power_domains_verify_state - verify the HW/SW state for all power wells
2170 * @i915: i915 device instance
2171 *
2172 * Verify if the reference count of each power well matches its HW enabled
2173 * state and the total refcount of the domains it belongs to. This must be
2174 * called after modeset HW state sanitization, which is responsible for
2175 * acquiring reference counts for any power wells in use and disabling the
2176 * ones left on by BIOS but not required by any active output.
2177 */
intel_power_domains_verify_state(struct drm_i915_private * i915)2178 static void intel_power_domains_verify_state(struct drm_i915_private *i915)
2179 {
2180 struct i915_power_domains *power_domains = &i915->display.power.domains;
2181 struct i915_power_well *power_well;
2182 bool dump_domain_info;
2183
2184 mutex_lock(&power_domains->lock);
2185
2186 verify_async_put_domains_state(power_domains);
2187
2188 dump_domain_info = false;
2189 for_each_power_well(i915, power_well) {
2190 enum intel_display_power_domain domain;
2191 int domains_count;
2192 bool enabled;
2193
2194 enabled = intel_power_well_is_enabled(i915, power_well);
2195 if ((intel_power_well_refcount(power_well) ||
2196 intel_power_well_is_always_on(power_well)) !=
2197 enabled)
2198 drm_err(&i915->drm,
2199 "power well %s state mismatch (refcount %d/enabled %d)",
2200 intel_power_well_name(power_well),
2201 intel_power_well_refcount(power_well), enabled);
2202
2203 domains_count = 0;
2204 for_each_power_domain(domain, intel_power_well_domains(power_well))
2205 domains_count += power_domains->domain_use_count[domain];
2206
2207 if (intel_power_well_refcount(power_well) != domains_count) {
2208 drm_err(&i915->drm,
2209 "power well %s refcount/domain refcount mismatch "
2210 "(refcount %d/domains refcount %d)\n",
2211 intel_power_well_name(power_well),
2212 intel_power_well_refcount(power_well),
2213 domains_count);
2214 dump_domain_info = true;
2215 }
2216 }
2217
2218 if (dump_domain_info) {
2219 static bool dumped;
2220
2221 if (!dumped) {
2222 intel_power_domains_dump_info(i915);
2223 dumped = true;
2224 }
2225 }
2226
2227 mutex_unlock(&power_domains->lock);
2228 }
2229
2230 #else
2231
intel_power_domains_verify_state(struct drm_i915_private * i915)2232 static void intel_power_domains_verify_state(struct drm_i915_private *i915)
2233 {
2234 }
2235
2236 #endif
2237
intel_display_power_suspend_late(struct drm_i915_private * i915)2238 void intel_display_power_suspend_late(struct drm_i915_private *i915)
2239 {
2240 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
2241 IS_BROXTON(i915)) {
2242 bxt_enable_dc9(i915);
2243 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2244 hsw_enable_pc8(i915);
2245 }
2246
2247 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
2248 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
2249 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
2250 }
2251
intel_display_power_resume_early(struct drm_i915_private * i915)2252 void intel_display_power_resume_early(struct drm_i915_private *i915)
2253 {
2254 if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
2255 IS_BROXTON(i915)) {
2256 gen9_sanitize_dc_state(i915);
2257 bxt_disable_dc9(i915);
2258 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2259 hsw_disable_pc8(i915);
2260 }
2261
2262 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
2263 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
2264 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
2265 }
2266
intel_display_power_suspend(struct drm_i915_private * i915)2267 void intel_display_power_suspend(struct drm_i915_private *i915)
2268 {
2269 if (DISPLAY_VER(i915) >= 11) {
2270 icl_display_core_uninit(i915);
2271 bxt_enable_dc9(i915);
2272 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
2273 bxt_display_core_uninit(i915);
2274 bxt_enable_dc9(i915);
2275 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2276 hsw_enable_pc8(i915);
2277 }
2278 }
2279
intel_display_power_resume(struct drm_i915_private * i915)2280 void intel_display_power_resume(struct drm_i915_private *i915)
2281 {
2282 struct i915_power_domains *power_domains = &i915->display.power.domains;
2283
2284 if (DISPLAY_VER(i915) >= 11) {
2285 bxt_disable_dc9(i915);
2286 icl_display_core_init(i915, true);
2287 if (intel_dmc_has_payload(i915)) {
2288 if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
2289 skl_enable_dc6(i915);
2290 else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
2291 gen9_enable_dc5(i915);
2292 }
2293 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
2294 bxt_disable_dc9(i915);
2295 bxt_display_core_init(i915, true);
2296 if (intel_dmc_has_payload(i915) &&
2297 (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2298 gen9_enable_dc5(i915);
2299 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2300 hsw_disable_pc8(i915);
2301 }
2302 }
2303
intel_display_power_debug(struct drm_i915_private * i915,struct seq_file * m)2304 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m)
2305 {
2306 struct i915_power_domains *power_domains = &i915->display.power.domains;
2307 int i;
2308
2309 mutex_lock(&power_domains->lock);
2310
2311 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2312 for (i = 0; i < power_domains->power_well_count; i++) {
2313 struct i915_power_well *power_well;
2314 enum intel_display_power_domain power_domain;
2315
2316 power_well = &power_domains->power_wells[i];
2317 seq_printf(m, "%-25s %d\n", intel_power_well_name(power_well),
2318 intel_power_well_refcount(power_well));
2319
2320 for_each_power_domain(power_domain, intel_power_well_domains(power_well))
2321 seq_printf(m, " %-23s %d\n",
2322 intel_display_power_domain_str(power_domain),
2323 power_domains->domain_use_count[power_domain]);
2324 }
2325
2326 mutex_unlock(&power_domains->lock);
2327 }
2328
2329 struct intel_ddi_port_domains {
2330 enum port port_start;
2331 enum port port_end;
2332 enum aux_ch aux_ch_start;
2333 enum aux_ch aux_ch_end;
2334
2335 enum intel_display_power_domain ddi_lanes;
2336 enum intel_display_power_domain ddi_io;
2337 enum intel_display_power_domain aux_io;
2338 enum intel_display_power_domain aux_legacy_usbc;
2339 enum intel_display_power_domain aux_tbt;
2340 };
2341
2342 static const struct intel_ddi_port_domains
2343 i9xx_port_domains[] = {
2344 {
2345 .port_start = PORT_A,
2346 .port_end = PORT_F,
2347 .aux_ch_start = AUX_CH_A,
2348 .aux_ch_end = AUX_CH_F,
2349
2350 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2351 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2352 .aux_io = POWER_DOMAIN_AUX_IO_A,
2353 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2354 .aux_tbt = POWER_DOMAIN_INVALID,
2355 },
2356 };
2357
2358 static const struct intel_ddi_port_domains
2359 d11_port_domains[] = {
2360 {
2361 .port_start = PORT_A,
2362 .port_end = PORT_B,
2363 .aux_ch_start = AUX_CH_A,
2364 .aux_ch_end = AUX_CH_B,
2365
2366 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2367 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2368 .aux_io = POWER_DOMAIN_AUX_IO_A,
2369 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2370 .aux_tbt = POWER_DOMAIN_INVALID,
2371 }, {
2372 .port_start = PORT_C,
2373 .port_end = PORT_F,
2374 .aux_ch_start = AUX_CH_C,
2375 .aux_ch_end = AUX_CH_F,
2376
2377 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C,
2378 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_C,
2379 .aux_io = POWER_DOMAIN_AUX_IO_C,
2380 .aux_legacy_usbc = POWER_DOMAIN_AUX_C,
2381 .aux_tbt = POWER_DOMAIN_AUX_TBT1,
2382 },
2383 };
2384
2385 static const struct intel_ddi_port_domains
2386 d12_port_domains[] = {
2387 {
2388 .port_start = PORT_A,
2389 .port_end = PORT_C,
2390 .aux_ch_start = AUX_CH_A,
2391 .aux_ch_end = AUX_CH_C,
2392
2393 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2394 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2395 .aux_io = POWER_DOMAIN_AUX_IO_A,
2396 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2397 .aux_tbt = POWER_DOMAIN_INVALID,
2398 }, {
2399 .port_start = PORT_TC1,
2400 .port_end = PORT_TC6,
2401 .aux_ch_start = AUX_CH_USBC1,
2402 .aux_ch_end = AUX_CH_USBC6,
2403
2404 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
2405 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
2406 .aux_io = POWER_DOMAIN_INVALID,
2407 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
2408 .aux_tbt = POWER_DOMAIN_AUX_TBT1,
2409 },
2410 };
2411
2412 static const struct intel_ddi_port_domains
2413 d13_port_domains[] = {
2414 {
2415 .port_start = PORT_A,
2416 .port_end = PORT_C,
2417 .aux_ch_start = AUX_CH_A,
2418 .aux_ch_end = AUX_CH_C,
2419
2420 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
2421 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
2422 .aux_io = POWER_DOMAIN_AUX_IO_A,
2423 .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
2424 .aux_tbt = POWER_DOMAIN_INVALID,
2425 }, {
2426 .port_start = PORT_TC1,
2427 .port_end = PORT_TC4,
2428 .aux_ch_start = AUX_CH_USBC1,
2429 .aux_ch_end = AUX_CH_USBC4,
2430
2431 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
2432 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
2433 .aux_io = POWER_DOMAIN_INVALID,
2434 .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
2435 .aux_tbt = POWER_DOMAIN_AUX_TBT1,
2436 }, {
2437 .port_start = PORT_D_XELPD,
2438 .port_end = PORT_E_XELPD,
2439 .aux_ch_start = AUX_CH_D_XELPD,
2440 .aux_ch_end = AUX_CH_E_XELPD,
2441
2442 .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D,
2443 .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D,
2444 .aux_io = POWER_DOMAIN_AUX_IO_D,
2445 .aux_legacy_usbc = POWER_DOMAIN_AUX_D,
2446 .aux_tbt = POWER_DOMAIN_INVALID,
2447 },
2448 };
2449
2450 static void
intel_port_domains_for_platform(struct drm_i915_private * i915,const struct intel_ddi_port_domains ** domains,int * domains_size)2451 intel_port_domains_for_platform(struct drm_i915_private *i915,
2452 const struct intel_ddi_port_domains **domains,
2453 int *domains_size)
2454 {
2455 if (DISPLAY_VER(i915) >= 13) {
2456 *domains = d13_port_domains;
2457 *domains_size = ARRAY_SIZE(d13_port_domains);
2458 } else if (DISPLAY_VER(i915) >= 12) {
2459 *domains = d12_port_domains;
2460 *domains_size = ARRAY_SIZE(d12_port_domains);
2461 } else if (DISPLAY_VER(i915) >= 11) {
2462 *domains = d11_port_domains;
2463 *domains_size = ARRAY_SIZE(d11_port_domains);
2464 } else {
2465 *domains = i9xx_port_domains;
2466 *domains_size = ARRAY_SIZE(i9xx_port_domains);
2467 }
2468 }
2469
2470 static const struct intel_ddi_port_domains *
intel_port_domains_for_port(struct drm_i915_private * i915,enum port port)2471 intel_port_domains_for_port(struct drm_i915_private *i915, enum port port)
2472 {
2473 const struct intel_ddi_port_domains *domains;
2474 int domains_size;
2475 int i;
2476
2477 intel_port_domains_for_platform(i915, &domains, &domains_size);
2478 for (i = 0; i < domains_size; i++)
2479 if (port >= domains[i].port_start && port <= domains[i].port_end)
2480 return &domains[i];
2481
2482 return NULL;
2483 }
2484
2485 enum intel_display_power_domain
intel_display_power_ddi_io_domain(struct drm_i915_private * i915,enum port port)2486 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port)
2487 {
2488 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port);
2489
2490 if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID))
2491 return POWER_DOMAIN_PORT_DDI_IO_A;
2492
2493 return domains->ddi_io + (int)(port - domains->port_start);
2494 }
2495
2496 enum intel_display_power_domain
intel_display_power_ddi_lanes_domain(struct drm_i915_private * i915,enum port port)2497 intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port)
2498 {
2499 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port);
2500
2501 if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID))
2502 return POWER_DOMAIN_PORT_DDI_LANES_A;
2503
2504 return domains->ddi_lanes + (int)(port - domains->port_start);
2505 }
2506
2507 static const struct intel_ddi_port_domains *
intel_port_domains_for_aux_ch(struct drm_i915_private * i915,enum aux_ch aux_ch)2508 intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch)
2509 {
2510 const struct intel_ddi_port_domains *domains;
2511 int domains_size;
2512 int i;
2513
2514 intel_port_domains_for_platform(i915, &domains, &domains_size);
2515 for (i = 0; i < domains_size; i++)
2516 if (aux_ch >= domains[i].aux_ch_start && aux_ch <= domains[i].aux_ch_end)
2517 return &domains[i];
2518
2519 return NULL;
2520 }
2521
2522 enum intel_display_power_domain
intel_display_power_aux_io_domain(struct drm_i915_private * i915,enum aux_ch aux_ch)2523 intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
2524 {
2525 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
2526
2527 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID))
2528 return POWER_DOMAIN_AUX_IO_A;
2529
2530 return domains->aux_io + (int)(aux_ch - domains->aux_ch_start);
2531 }
2532
2533 enum intel_display_power_domain
intel_display_power_legacy_aux_domain(struct drm_i915_private * i915,enum aux_ch aux_ch)2534 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
2535 {
2536 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
2537
2538 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID))
2539 return POWER_DOMAIN_AUX_A;
2540
2541 return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start);
2542 }
2543
2544 enum intel_display_power_domain
intel_display_power_tbt_aux_domain(struct drm_i915_private * i915,enum aux_ch aux_ch)2545 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
2546 {
2547 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
2548
2549 if (drm_WARN_ON(&i915->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID))
2550 return POWER_DOMAIN_AUX_TBT1;
2551
2552 return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start);
2553 }
2554