1 /*
2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
3 *
4 * This file is part of libFirm.
5 *
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
10 *
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
14 *
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE.
18 */
19
20 /**
21 * @file
22 * @brief ia32 architecture variants
23 * @author Michael Beck, Matthias Braun
24 */
25 #include "config.h"
26
27 #include <stdbool.h>
28 #include "lc_opts.h"
29 #include "lc_opts_enum.h"
30
31 #include "irtools.h"
32
33 #include "bearch_ia32_t.h"
34 #include "ia32_architecture.h"
35
36 #undef NATIVE_X86
37
38 #ifdef _MSC_VER
39 #if defined(_M_IX86) || defined(_M_X64)
40 #include <intrin.h>
41 #define NATIVE_X86
42 #endif
43 #else
44 #if defined(__i386__) || defined(__x86_64__)
45 #define NATIVE_X86
46 #endif
47 #endif
48
49 ia32_code_gen_config_t ia32_cg_config;
50
51 /**
52 * CPU architectures and features.
53 */
54 typedef enum cpu_arch_features {
55 arch_generic32 = 0x00000001, /**< no specific architecture */
56
57 arch_i386 = 0x00000002, /**< i386 architecture */
58 arch_i486 = 0x00000004, /**< i486 architecture */
59 arch_pentium = 0x00000008, /**< Pentium architecture */
60 arch_ppro = 0x00000010, /**< PentiumPro architecture */
61 arch_netburst = 0x00000020, /**< Netburst architecture */
62 arch_nocona = 0x00000040, /**< Nocona architecture */
63 arch_core2 = 0x00000080, /**< Core2 architecture */
64 arch_atom = 0x00000100, /**< Atom architecture */
65
66 arch_k6 = 0x00000200, /**< k6 architecture */
67 arch_geode = 0x00000400, /**< Geode architecture */
68 arch_athlon = 0x00000800, /**< Athlon architecture */
69 arch_k8 = 0x00001000, /**< K8/Opteron architecture */
70 arch_k10 = 0x00002000, /**< K10/Barcelona architecture */
71
72 arch_mask = 0x00003FFF,
73
74 arch_athlon_plus = arch_athlon | arch_k8 | arch_k10,
75 arch_all_amd = arch_k6 | arch_geode | arch_athlon_plus,
76
77 arch_feature_mmx = 0x00004000, /**< MMX instructions */
78 arch_feature_cmov = 0x00008000, /**< cmov instructions */
79 arch_feature_p6_insn = 0x00010000, /**< PentiumPro instructions */
80 arch_feature_sse1 = 0x00020000, /**< SSE1 instructions */
81 arch_feature_sse2 = 0x00040000, /**< SSE2 instructions */
82 arch_feature_sse3 = 0x00080000, /**< SSE3 instructions */
83 arch_feature_ssse3 = 0x00100000, /**< SSSE3 instructions */
84 arch_feature_3DNow = 0x00200000, /**< 3DNow! instructions */
85 arch_feature_3DNowE = 0x00400000, /**< Enhanced 3DNow! instructions */
86 arch_feature_64bit = 0x00800000, /**< x86_64 support */
87 arch_feature_sse4_1 = 0x01000000, /**< SSE4.1 instructions */
88 arch_feature_sse4_2 = 0x02000000, /**< SSE4.2 instructions */
89 arch_feature_sse4a = 0x04000000, /**< SSE4a instructions */
90 arch_feature_popcnt = 0x08000000, /**< popcnt instruction */
91
92 arch_mmx_insn = arch_feature_mmx, /**< MMX instructions */
93 arch_sse1_insn = arch_feature_sse1 | arch_mmx_insn, /**< SSE1 instructions, include MMX */
94 arch_sse2_insn = arch_feature_sse2 | arch_sse1_insn, /**< SSE2 instructions, include SSE1 */
95 arch_sse3_insn = arch_feature_sse3 | arch_sse2_insn, /**< SSE3 instructions, include SSE2 */
96 arch_ssse3_insn = arch_feature_ssse3 | arch_sse3_insn, /**< SSSE3 instructions, include SSE3 */
97 arch_sse4_1_insn = arch_feature_sse4_1 | arch_ssse3_insn, /**< SSE4.1 instructions, include SSSE3 */
98 arch_sse4_2_insn = arch_feature_sse4_2 | arch_sse4_1_insn, /**< SSE4.2 instructions, include SSE4.1 */
99 arch_sse4a_insn = arch_feature_sse4a | arch_ssse3_insn, /**< SSE4a instructions, include SSSE3 */
100
101 arch_3DNow_insn = arch_feature_3DNow | arch_feature_mmx, /**< 3DNow! instructions, including MMX */
102 arch_3DNowE_insn = arch_feature_3DNowE | arch_3DNow_insn, /**< Enhanced 3DNow! instructions */
103 arch_64bit_insn = arch_feature_64bit | arch_sse2_insn, /**< x86_64 support, includes SSE2 */
104
105 cpu_generic = arch_generic32,
106
107 /* intel CPUs */
108 cpu_i386 = arch_i386,
109 cpu_i486 = arch_i486,
110 cpu_pentium = arch_pentium,
111 cpu_pentium_mmx = arch_pentium | arch_mmx_insn,
112 cpu_pentium_pro_generic = arch_ppro | arch_feature_p6_insn,
113 cpu_pentium_pro = arch_ppro | arch_feature_cmov | arch_feature_p6_insn,
114 cpu_pentium_2 = arch_ppro | arch_feature_cmov | arch_feature_p6_insn | arch_mmx_insn,
115 cpu_pentium_3 = arch_ppro | arch_feature_cmov | arch_feature_p6_insn | arch_sse1_insn,
116 cpu_pentium_m = arch_ppro | arch_feature_cmov | arch_feature_p6_insn | arch_sse2_insn,
117 cpu_netburst_generic = arch_netburst | arch_feature_p6_insn,
118 cpu_pentium_4 = arch_netburst | arch_feature_cmov | arch_feature_p6_insn | arch_sse2_insn,
119 cpu_prescott = arch_nocona | arch_feature_cmov | arch_feature_p6_insn | arch_sse3_insn,
120 cpu_nocona = arch_nocona | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
121 cpu_core2_generic = arch_core2 | arch_feature_p6_insn,
122 cpu_core2 = arch_core2 | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_ssse3_insn,
123 cpu_penryn = arch_core2 | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_sse4_1_insn,
124 cpu_atom_generic = arch_atom | arch_feature_p6_insn,
125 cpu_atom = arch_atom | arch_feature_cmov | arch_feature_p6_insn | arch_ssse3_insn,
126
127 /* AMD CPUs */
128 cpu_k6_generic = arch_k6,
129 cpu_k6 = arch_k6 | arch_mmx_insn,
130 cpu_k6_PLUS = arch_k6 | arch_3DNow_insn,
131 cpu_geode_generic = arch_geode,
132 cpu_geode = arch_geode | arch_sse1_insn | arch_3DNowE_insn,
133 cpu_athlon_generic = arch_athlon | arch_feature_p6_insn,
134 cpu_athlon_old = arch_athlon | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn,
135 cpu_athlon = arch_athlon | arch_sse1_insn | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn,
136 cpu_athlon64 = arch_athlon | arch_sse2_insn | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn,
137 cpu_k8_generic = arch_k8 | arch_feature_p6_insn,
138 cpu_k8 = arch_k8 | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn,
139 cpu_k8_sse3 = arch_k8 | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
140 cpu_k10_generic = arch_k10 | arch_feature_p6_insn,
141 cpu_k10 = arch_k10 | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_feature_popcnt | arch_64bit_insn | arch_sse4a_insn,
142
143 /* other CPUs */
144 cpu_winchip_c6 = arch_i486 | arch_feature_mmx,
145 cpu_winchip2 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
146 cpu_c3 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
147 cpu_c3_2 = arch_ppro | arch_feature_cmov | arch_feature_p6_insn | arch_sse1_insn, /* really no 3DNow! */
148
149 cpu_autodetect = 0,
150 } cpu_arch_features;
151 ENUM_BITSET(cpu_arch_features)
152
153 static int opt_size = 0;
154 static int emit_machcode = 0;
155 static cpu_arch_features arch = cpu_generic;
156 static cpu_arch_features opt_arch = cpu_generic;
157 static int fpu_arch = 0;
158 static int opt_cc = 1;
159 static int opt_unsafe_floatconv = 0;
160
161 /* instruction set architectures. */
162 static const lc_opt_enum_int_items_t arch_items[] = {
163 { "i386", cpu_i386 },
164 { "i486", cpu_i486 },
165 { "i586", cpu_pentium },
166 { "pentium", cpu_pentium },
167 { "pentium-mmx", cpu_pentium_mmx },
168 { "i686", cpu_pentium_pro },
169 { "pentiumpro", cpu_pentium_pro },
170 { "pentium2", cpu_pentium_2 },
171 { "p2", cpu_pentium_2 },
172 { "pentium3", cpu_pentium_3 },
173 { "pentium3m", cpu_pentium_3 },
174 { "p3", cpu_pentium_3 },
175 { "pentium-m", cpu_pentium_m },
176 { "pm", cpu_pentium_m },
177 { "pentium4", cpu_pentium_4 },
178 { "pentium4m", cpu_pentium_4 },
179 { "p4", cpu_pentium_4 },
180 { "prescott", cpu_prescott },
181 { "nocona", cpu_nocona },
182 { "merom", cpu_core2 },
183 { "core2", cpu_core2 },
184 { "penryn", cpu_penryn },
185 { "atom", cpu_atom },
186
187 { "k6", cpu_k6 },
188 { "k6-2", cpu_k6_PLUS },
189 { "k6-3", cpu_k6_PLUS },
190 { "geode", cpu_geode },
191 { "athlon", cpu_athlon_old },
192 { "athlon-tbird", cpu_athlon },
193 { "athlon-4", cpu_athlon },
194 { "athlon-xp", cpu_athlon },
195 { "athlon-mp", cpu_athlon },
196 { "athlon64", cpu_athlon64 },
197 { "k8", cpu_k8 },
198 { "opteron", cpu_k8 },
199 { "athlon-fx", cpu_k8 },
200 { "k8-sse3", cpu_k8_sse3 },
201 { "opteron-sse3", cpu_k8_sse3 },
202 { "k10", cpu_k10 },
203 { "barcelona", cpu_k10 },
204 { "amdfam10", cpu_k10 },
205
206 { "winchip-c6", cpu_winchip_c6, },
207 { "winchip2", cpu_winchip2 },
208 { "c3", cpu_c3 },
209 { "c3-2", cpu_c3_2 },
210
211 { "generic", cpu_generic },
212 { "generic32", cpu_generic },
213
214 #ifdef NATIVE_X86
215 { "native", cpu_autodetect },
216 #endif
217
218 { NULL, 0 }
219 };
220
221 static lc_opt_enum_int_var_t arch_var = {
222 (int*) &arch, arch_items
223 };
224
225 static lc_opt_enum_int_var_t opt_arch_var = {
226 (int*) &opt_arch, arch_items
227 };
228
229 static const lc_opt_enum_int_items_t fp_unit_items[] = {
230 { "x87" , IA32_FPU_ARCH_X87 },
231 { "sse2", IA32_FPU_ARCH_SSE2 },
232 { "softfloat", IA32_FPU_ARCH_SOFTFLOAT },
233 { NULL, IA32_FPU_ARCH_NONE }
234 };
235
236 static lc_opt_enum_int_var_t fp_unit_var = {
237 &fpu_arch, fp_unit_items
238 };
239
240 static const lc_opt_table_entry_t ia32_architecture_options[] = {
241 LC_OPT_ENT_BOOL ("size", "optimize for size", &opt_size),
242 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
243 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
244 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
245 LC_OPT_ENT_NEGBOOL ("nooptcc", "do not optimize calling convention", &opt_cc),
246 LC_OPT_ENT_BOOL ("unsafe_floatconv", "do unsafe floating point controlword optimisations", &opt_unsafe_floatconv),
247 LC_OPT_ENT_BOOL ("machcode", "output machine code instead of assembler", &emit_machcode),
248 LC_OPT_LAST
249 };
250
251 typedef struct insn_const {
252 int add_cost; /**< cost of an add instruction */
253 int lea_cost; /**< cost of a lea instruction */
254 int const_shf_cost; /**< cost of a constant shift instruction */
255 int cost_mul_start; /**< starting cost of a multiply instruction */
256 int cost_mul_bit; /**< cost of multiply for every set bit */
257 unsigned function_alignment; /**< logarithm for alignment of function labels */
258 unsigned label_alignment; /**< logarithm for alignment of loops labels */
259 unsigned label_alignment_max_skip; /**< maximum skip for alignment of loops labels */
260 } insn_const;
261
262 /* costs for optimizing for size */
263 static const insn_const size_cost = {
264 2, /* cost of an add instruction */
265 3, /* cost of a lea instruction */
266 3, /* cost of a constant shift instruction */
267 4, /* starting cost of a multiply instruction */
268 0, /* cost of multiply for every set bit */
269 0, /* logarithm for alignment of function labels */
270 0, /* logarithm for alignment of loops labels */
271 0, /* maximum skip for alignment of loops labels */
272 };
273
274 /* costs for the i386 */
275 static const insn_const i386_cost = {
276 1, /* cost of an add instruction */
277 1, /* cost of a lea instruction */
278 3, /* cost of a constant shift instruction */
279 9, /* starting cost of a multiply instruction */
280 1, /* cost of multiply for every set bit */
281 2, /* logarithm for alignment of function labels */
282 2, /* logarithm for alignment of loops labels */
283 3, /* maximum skip for alignment of loops labels */
284 };
285
286 /* costs for the i486 */
287 static const insn_const i486_cost = {
288 1, /* cost of an add instruction */
289 1, /* cost of a lea instruction */
290 2, /* cost of a constant shift instruction */
291 12, /* starting cost of a multiply instruction */
292 1, /* cost of multiply for every set bit */
293 4, /* logarithm for alignment of function labels */
294 4, /* logarithm for alignment of loops labels */
295 15, /* maximum skip for alignment of loops labels */
296 };
297
298 /* costs for the Pentium */
299 static const insn_const pentium_cost = {
300 1, /* cost of an add instruction */
301 1, /* cost of a lea instruction */
302 1, /* cost of a constant shift instruction */
303 11, /* starting cost of a multiply instruction */
304 0, /* cost of multiply for every set bit */
305 4, /* logarithm for alignment of function labels */
306 4, /* logarithm for alignment of loops labels */
307 7, /* maximum skip for alignment of loops labels */
308 };
309
310 /* costs for the Pentium Pro */
311 static const insn_const pentiumpro_cost = {
312 1, /* cost of an add instruction */
313 1, /* cost of a lea instruction */
314 1, /* cost of a constant shift instruction */
315 4, /* starting cost of a multiply instruction */
316 0, /* cost of multiply for every set bit */
317 4, /* logarithm for alignment of function labels */
318 4, /* logarithm for alignment of loops labels */
319 10, /* maximum skip for alignment of loops labels */
320 };
321
322 /* costs for the K6 */
323 static const insn_const k6_cost = {
324 1, /* cost of an add instruction */
325 2, /* cost of a lea instruction */
326 1, /* cost of a constant shift instruction */
327 3, /* starting cost of a multiply instruction */
328 0, /* cost of multiply for every set bit */
329 5, /* logarithm for alignment of function labels */
330 5, /* logarithm for alignment of loops labels */
331 7, /* maximum skip for alignment of loops labels */
332 };
333
334 /* costs for the Geode */
335 static const insn_const geode_cost = {
336 1, /* cost of an add instruction */
337 1, /* cost of a lea instruction */
338 1, /* cost of a constant shift instruction */
339 7, /* starting cost of a multiply instruction */
340 0, /* cost of multiply for every set bit */
341 0, /* logarithm for alignment of function labels */
342 0, /* logarithm for alignment of loops labels */
343 0, /* maximum skip for alignment of loops labels */
344 };
345
346 /* costs for the Athlon */
347 static const insn_const athlon_cost = {
348 1, /* cost of an add instruction */
349 2, /* cost of a lea instruction */
350 1, /* cost of a constant shift instruction */
351 5, /* starting cost of a multiply instruction */
352 0, /* cost of multiply for every set bit */
353 4, /* logarithm for alignment of function labels */
354 4, /* logarithm for alignment of loops labels */
355 7, /* maximum skip for alignment of loops labels */
356 };
357
358 /* costs for the Opteron/K8 */
359 static const insn_const k8_cost = {
360 1, /* cost of an add instruction */
361 2, /* cost of a lea instruction */
362 1, /* cost of a constant shift instruction */
363 3, /* starting cost of a multiply instruction */
364 0, /* cost of multiply for every set bit */
365 #if 0 /* TEST */
366 4, /* logarithm for alignment of function labels */
367 4, /* logarithm for alignment of loops labels */
368 7, /* maximum skip for alignment of loops labels */
369 #else
370 0,
371 0,
372 0
373 #endif
374 };
375
376 /* costs for the K10 */
377 static const insn_const k10_cost = {
378 1, /* cost of an add instruction */
379 2, /* cost of a lea instruction */
380 1, /* cost of a constant shift instruction */
381 3, /* starting cost of a multiply instruction */
382 0, /* cost of multiply for every set bit */
383 5, /* logarithm for alignment of function labels */
384 5, /* logarithm for alignment of loops labels */
385 7, /* maximum skip for alignment of loops labels */
386 };
387
388 /* costs for the Pentium 4 */
389 static const insn_const netburst_cost = {
390 1, /* cost of an add instruction */
391 3, /* cost of a lea instruction */
392 4, /* cost of a constant shift instruction */
393 15, /* starting cost of a multiply instruction */
394 0, /* cost of multiply for every set bit */
395 4, /* logarithm for alignment of function labels */
396 4, /* logarithm for alignment of loops labels */
397 7, /* maximum skip for alignment of loops labels */
398 };
399
400 /* costs for the Nocona and Core */
401 static const insn_const nocona_cost = {
402 1, /* cost of an add instruction */
403 1, /* cost of a lea instruction */
404 1, /* cost of a constant shift instruction */
405 10, /* starting cost of a multiply instruction */
406 0, /* cost of multiply for every set bit */
407 4, /* logarithm for alignment of function labels */
408 4, /* logarithm for alignment of loops labels */
409 7, /* maximum skip for alignment of loops labels */
410 };
411
412 /* costs for the Core2 */
413 static const insn_const core2_cost = {
414 1, /* cost of an add instruction */
415 1, /* cost of a lea instruction */
416 1, /* cost of a constant shift instruction */
417 3, /* starting cost of a multiply instruction */
418 0, /* cost of multiply for every set bit */
419 4, /* logarithm for alignment of function labels */
420 4, /* logarithm for alignment of loops labels */
421 10, /* maximum skip for alignment of loops labels */
422 };
423
424 /* costs for the generic32 */
425 static const insn_const generic32_cost = {
426 1, /* cost of an add instruction */
427 2, /* cost of a lea instruction */
428 1, /* cost of a constant shift instruction */
429 4, /* starting cost of a multiply instruction */
430 0, /* cost of multiply for every set bit */
431 4, /* logarithm for alignment of function labels */
432 4, /* logarithm for alignment of loops labels */
433 7, /* maximum skip for alignment of loops labels */
434 };
435
436 static const insn_const *arch_costs = &generic32_cost;
437
set_arch_costs(void)438 static void set_arch_costs(void)
439 {
440 if (opt_size) {
441 arch_costs = &size_cost;
442 return;
443 }
444 switch (opt_arch & arch_mask) {
445 case arch_i386: arch_costs = &i386_cost; break;
446 case arch_i486: arch_costs = &i486_cost; break;
447 case arch_pentium: arch_costs = &pentium_cost; break;
448 case arch_ppro: arch_costs = &pentiumpro_cost; break;
449 case arch_netburst: arch_costs = &netburst_cost; break;
450 case arch_nocona: arch_costs = &nocona_cost; break;
451 case arch_core2: arch_costs = &core2_cost; break;
452 case arch_k6: arch_costs = &k6_cost; break;
453 case arch_geode: arch_costs = &geode_cost; break;
454 case arch_athlon: arch_costs = &athlon_cost; break;
455 case arch_k8: arch_costs = &k8_cost; break;
456 case arch_k10: arch_costs = &k10_cost; break;
457 default:
458 case arch_generic32: arch_costs = &generic32_cost; break;
459 }
460 }
461
462 /* Evaluate the costs of an instruction. */
ia32_evaluate_insn(insn_kind kind,const ir_mode * mode,ir_tarval * tv)463 int ia32_evaluate_insn(insn_kind kind, const ir_mode *mode, ir_tarval *tv)
464 {
465 int cost;
466
467 switch (kind) {
468 case MUL:
469 cost = arch_costs->cost_mul_start;
470 if (arch_costs->cost_mul_bit > 0) {
471 char *bitstr = get_tarval_bitpattern(tv);
472 int i;
473
474 for (i = 0; bitstr[i] != '\0'; ++i) {
475 if (bitstr[i] == '1') {
476 cost += arch_costs->cost_mul_bit;
477 }
478 }
479 free(bitstr);
480 }
481 if (get_mode_size_bits(mode) <= 32)
482 return cost;
483 /* 64bit mul supported, approx 4times of a 32bit mul*/
484 return 4 * cost;
485 case LEA:
486 /* lea is only supported for 32 bit */
487 if (get_mode_size_bits(mode) <= 32)
488 return arch_costs->lea_cost;
489 /* in 64bit mode, the Lea cost are at wort 2 shifts and one add */
490 return 2 * arch_costs->add_cost + 2 * (2 * arch_costs->const_shf_cost);
491 case ADD:
492 case SUB:
493 if (get_mode_size_bits(mode) <= 32)
494 return arch_costs->add_cost;
495 /* 64bit add/sub supported, double the cost */
496 return 2 * arch_costs->add_cost;
497 case SHIFT:
498 if (get_mode_size_bits(mode) <= 32)
499 return arch_costs->const_shf_cost;
500 /* 64bit shift supported, double the cost */
501 return 2 * arch_costs->const_shf_cost;
502 case ZERO:
503 return arch_costs->add_cost;
504 default:
505 return 1;
506 }
507 }
508
509 /* auto detection code only works if we're on an x86 cpu obviously */
510 #ifdef NATIVE_X86
511 typedef struct x86_cpu_info_t {
512 unsigned char cpu_stepping;
513 unsigned char cpu_model;
514 unsigned char cpu_family;
515 unsigned char cpu_type;
516 unsigned char cpu_ext_model;
517 unsigned char cpu_ext_family;
518 unsigned edx_features;
519 unsigned ecx_features;
520 unsigned add_features;
521 } x86_cpu_info_t;
522
523 enum {
524 CPUID_FEAT_ECX_SSE3 = 1 << 0,
525 CPUID_FEAT_ECX_PCLMUL = 1 << 1,
526 CPUID_FEAT_ECX_DTES64 = 1 << 2,
527 CPUID_FEAT_ECX_MONITOR = 1 << 3,
528 CPUID_FEAT_ECX_DS_CPL = 1 << 4,
529 CPUID_FEAT_ECX_VMX = 1 << 5,
530 CPUID_FEAT_ECX_SMX = 1 << 6,
531 CPUID_FEAT_ECX_EST = 1 << 7,
532 CPUID_FEAT_ECX_TM2 = 1 << 8,
533 CPUID_FEAT_ECX_SSSE3 = 1 << 9,
534 CPUID_FEAT_ECX_CID = 1 << 10,
535 CPUID_FEAT_ECX_FMA = 1 << 12,
536 CPUID_FEAT_ECX_CX16 = 1 << 13,
537 CPUID_FEAT_ECX_ETPRD = 1 << 14,
538 CPUID_FEAT_ECX_PDCM = 1 << 15,
539 CPUID_FEAT_ECX_DCA = 1 << 18,
540 CPUID_FEAT_ECX_SSE4_1 = 1 << 19,
541 CPUID_FEAT_ECX_SSE4_2 = 1 << 20,
542 CPUID_FEAT_ECX_x2APIC = 1 << 21,
543 CPUID_FEAT_ECX_MOVBE = 1 << 22,
544 CPUID_FEAT_ECX_POPCNT = 1 << 23,
545 CPUID_FEAT_ECX_AES = 1 << 25,
546 CPUID_FEAT_ECX_XSAVE = 1 << 26,
547 CPUID_FEAT_ECX_OSXSAVE = 1 << 27,
548 CPUID_FEAT_ECX_AVX = 1 << 28,
549
550 CPUID_FEAT_EDX_FPU = 1 << 0,
551 CPUID_FEAT_EDX_VME = 1 << 1,
552 CPUID_FEAT_EDX_DE = 1 << 2,
553 CPUID_FEAT_EDX_PSE = 1 << 3,
554 CPUID_FEAT_EDX_TSC = 1 << 4,
555 CPUID_FEAT_EDX_MSR = 1 << 5,
556 CPUID_FEAT_EDX_PAE = 1 << 6,
557 CPUID_FEAT_EDX_MCE = 1 << 7,
558 CPUID_FEAT_EDX_CX8 = 1 << 8,
559 CPUID_FEAT_EDX_APIC = 1 << 9,
560 CPUID_FEAT_EDX_SEP = 1 << 11,
561 CPUID_FEAT_EDX_MTRR = 1 << 12,
562 CPUID_FEAT_EDX_PGE = 1 << 13,
563 CPUID_FEAT_EDX_MCA = 1 << 14,
564 CPUID_FEAT_EDX_CMOV = 1 << 15,
565 CPUID_FEAT_EDX_PAT = 1 << 16,
566 CPUID_FEAT_EDX_PSE36 = 1 << 17,
567 CPUID_FEAT_EDX_PSN = 1 << 18,
568 CPUID_FEAT_EDX_CLF = 1 << 19,
569 CPUID_FEAT_EDX_DTES = 1 << 21,
570 CPUID_FEAT_EDX_ACPI = 1 << 22,
571 CPUID_FEAT_EDX_MMX = 1 << 23,
572 CPUID_FEAT_EDX_FXSR = 1 << 24,
573 CPUID_FEAT_EDX_SSE = 1 << 25,
574 CPUID_FEAT_EDX_SSE2 = 1 << 26,
575 CPUID_FEAT_EDX_SS = 1 << 27,
576 CPUID_FEAT_EDX_HTT = 1 << 28,
577 CPUID_FEAT_EDX_TM1 = 1 << 29,
578 CPUID_FEAT_EDX_IA64 = 1 << 30,
579 CPUID_FEAT_EDX_PBE = 1 << 31
580 };
581
auto_detect_Intel(x86_cpu_info_t const * info)582 static cpu_arch_features auto_detect_Intel(x86_cpu_info_t const *info)
583 {
584 cpu_arch_features auto_arch = cpu_generic;
585
586 unsigned family = info->cpu_ext_family + info->cpu_family;
587 unsigned model = (info->cpu_ext_model << 4) | info->cpu_model;
588
589 switch (family) {
590 case 4:
591 auto_arch = cpu_i486;
592 break;
593 case 5:
594 auto_arch = cpu_pentium;
595 break;
596 case 6:
597 switch (model) {
598 case 0x01: /* PentiumPro */
599 case 0x03: /* Pentium II Model 3 */
600 case 0x05: /* Pentium II Model 5 */
601 case 0x06: /* Celeron Model 6 */
602 case 0x07: /* Pentium III Model 7 */
603 case 0x08: /* Pentium III Model 8 */
604 case 0x09: /* Pentium M Model 9 */
605 case 0x0A: /* Pentium III Model 0A */
606 case 0x0B: /* Pentium III Model 0B */
607 case 0x0D: /* Pentium M Model 0D */
608 case 0x0E: /* Core Model 0E */
609 auto_arch = cpu_pentium_pro_generic;
610 break;
611 case 0x0F: /* Core2 Model 0F */
612 case 0x15: /* Intel EP80579 */
613 case 0x16: /* Celeron Model 16 */
614 case 0x17: /* Core2 Model 17 */
615 auto_arch = cpu_core2_generic;
616 break;
617 default:
618 /* unknown */
619 break;
620 }
621 break;
622 case 15:
623 switch (model) {
624 case 0x00: /* Pentium 4 Model 00 */
625 case 0x01: /* Pentium 4 Model 01 */
626 case 0x02: /* Pentium 4 Model 02 */
627 case 0x03: /* Pentium 4 Model 03 */
628 case 0x04: /* Pentium 4 Model 04 */
629 case 0x06: /* Pentium 4 Model 06 */
630 auto_arch = cpu_netburst_generic;
631 break;
632 case 0x1A: /* Core i7 */
633 auto_arch = cpu_core2_generic;
634 break;
635 case 0x1C: /* Atom */
636 auto_arch = cpu_atom_generic;
637 break;
638 case 0x1D: /* Xeon MP */
639 auto_arch = cpu_core2_generic;
640 break;
641 default:
642 /* unknown */
643 break;
644 }
645 break;
646 default:
647 /* unknown */
648 break;
649 }
650
651 return auto_arch;
652 }
653
auto_detect_AMD(x86_cpu_info_t const * info)654 static cpu_arch_features auto_detect_AMD(x86_cpu_info_t const *info)
655 {
656 cpu_arch_features auto_arch = cpu_generic;
657
658 unsigned family, model;
659
660 if (info->cpu_family == 0x0F) {
661 family = info->cpu_ext_family + info->cpu_family;
662 model = (info->cpu_ext_model << 4) | info->cpu_model;
663 } else {
664 family = info->cpu_family;
665 model = info->cpu_model;
666 }
667
668 switch (family) {
669 case 0x04:
670 auto_arch = cpu_i486;
671 break;
672 case 0x05:
673 switch (model) {
674 case 0x00: /* K5 Model 0 */
675 case 0x01: /* K5 Model 1 */
676 case 0x02: /* K5 Model 2 */
677 case 0x03: /* K5 Model 3 */
678 auto_arch = cpu_pentium;
679 break;
680 case 0x06: /* K6 Model 6 */
681 case 0x07: /* K6 Model 7 */
682 case 0x08: /* K6-2 Model 8 */
683 case 0x09: /* K6-III Model 9 */
684 case 0x0D: /* K6-2+ or K6-III+ */
685 auto_arch = cpu_k6_generic;
686 break;
687 case 0x0A: /* Geode LX */
688 auto_arch = cpu_geode_generic;
689 break;
690 default:
691 /* unknown K6 */
692 auto_arch = cpu_k6_generic;
693 break;
694 }
695 break;
696 case 0x06:
697 switch (model) {
698 case 0x01: /* Athlon Model 1 */
699 case 0x02: /* Athlon Model 2 */
700 case 0x03: /* Duron Model 3 */
701 case 0x04: /* Athlon Model 4 */
702 case 0x06: /* Athlon MP/Mobile Athlon Model 6 */
703 case 0x07: /* Mobile Duron Model 7 */
704 case 0x08: /* Athlon (TH/AP core) including Geode NX */
705 case 0x0A: /* Athlon (BT core) */
706 default: /* unknown K7 */
707 auto_arch = cpu_athlon_generic;
708 break;
709 }
710 break;
711 case 0x0F:
712 auto_arch = cpu_k8_generic;
713 break;
714 case 0x10:
715 case 0x11: /* AMD Family 11h */
716 case 0x12: /* AMD Family 12h */
717 case 0x14: /* AMD Family 14h */
718 case 0x15: /* AMD Family 15h */
719 auto_arch = cpu_k10_generic;
720 break;
721 default:
722 /* unknown */
723 break;
724 }
725
726 return auto_arch;
727 }
728
729 typedef union {
730 struct {
731 unsigned eax;
732 unsigned ebx;
733 unsigned ecx;
734 unsigned edx;
735 } r;
736 int bulk[4];
737 } cpuid_registers;
738
x86_cpuid(cpuid_registers * regs,unsigned level)739 static void x86_cpuid(cpuid_registers *regs, unsigned level)
740 {
741 #if defined(__GNUC__)
742 # if defined(__PIC__) && !defined(__amd64) // GCC cannot handle EBX in PIC
743 __asm (
744 "pushl %%ebx\n\t"
745 "cpuid\n\t"
746 "movl %%ebx, %1\n\t"
747 "popl %%ebx"
748 : "=a" (regs->r.eax), "=r" (regs->r.ebx), "=c" (regs->r.ecx), "=d" (regs->r.edx)
749 : "a" (level)
750 );
751 # else
752 __asm ("cpuid\n\t"
753 : "=a" (regs->r.eax), "=b" (regs->r.ebx), "=c" (regs->r.ecx), "=d" (regs->r.edx)
754 : "a" (level)
755 );
756 # endif
757 #elif defined(_MSC_VER)
758 __cpuid(regs->bulk, level);
759 #else
760 # error CPUID is missing
761 #endif
762 }
763
x86_toogle_cpuid(void)764 static bool x86_toogle_cpuid(void)
765 {
766 unsigned eflags_before = 0;
767 unsigned eflags_after = 0;
768
769 #if defined(__GNUC__)
770 #ifdef __i386__
771 /* If bit 21 of the EFLAGS register can be changed, the cpuid instruction is available */
772 __asm__(
773 "pushf\n\t"
774 "popl %0\n\t"
775 "movl %0, %1\n\t"
776 "xorl $0x00200000, %1\n\t"
777 "pushl %1\n\t"
778 "popf\n\t"
779 "pushf\n\t"
780 "popl %1"
781 : "=r" (eflags_before), "=r" (eflags_after) :: "cc"
782 );
783 #else
784 eflags_after = 0x00200000;
785 #endif
786 #elif defined(_MSC_VER)
787 #if defined(_M_IX86)
788 __asm {
789 pushfd
790 pop eax
791 mov eflags_before, eax
792 xor eax, 0x00200000
793 push eax
794 popfd
795 pushfd
796 pop eax
797 mov eflags_after, eax
798 }
799 #else
800 eflags_after = 0x00200000;
801 #endif
802 #endif
803 return (eflags_before ^ eflags_after) & 0x00200000;
804 }
805
autodetect_arch(void)806 static void autodetect_arch(void)
807 {
808 cpu_arch_features auto_arch = cpu_generic;
809
810 /* We use the cpuid instruction to detect the CPU features */
811 if (x86_toogle_cpuid()) {
812 cpuid_registers regs;
813 char vendorid[13];
814 x86_cpu_info_t cpu_info;
815
816 /* get vendor ID */
817 x86_cpuid(®s, 0);
818 memcpy(&vendorid[0], ®s.r.ebx, 4);
819 memcpy(&vendorid[4], ®s.r.edx, 4);
820 memcpy(&vendorid[8], ®s.r.ecx, 4);
821 vendorid[12] = '\0';
822
823 /* get processor info and feature bits */
824 x86_cpuid(®s, 1);
825
826 cpu_info.cpu_stepping = (regs.r.eax >> 0) & 0x0F;
827 cpu_info.cpu_model = (regs.r.eax >> 4) & 0x0F;
828 cpu_info.cpu_family = (regs.r.eax >> 8) & 0x0F;
829 cpu_info.cpu_type = (regs.r.eax >> 12) & 0x03;
830 cpu_info.cpu_ext_model = (regs.r.eax >> 16) & 0x0F;
831 cpu_info.cpu_ext_family = (regs.r.eax >> 20) & 0xFF;
832 cpu_info.edx_features = regs.r.edx;
833 cpu_info.ecx_features = regs.r.ecx;
834 cpu_info.add_features = regs.r.ebx;
835
836 if (0 == strcmp(vendorid, "GenuineIntel")) {
837 auto_arch = auto_detect_Intel(&cpu_info);
838 } else if (0 == strcmp(vendorid, "AuthenticAMD")) {
839 auto_arch = auto_detect_AMD(&cpu_info);
840 } else if (0 == strcmp(vendorid, "Geode by NSC")) {
841 auto_arch = cpu_geode_generic;
842 }
843
844 if (cpu_info.edx_features & CPUID_FEAT_EDX_CMOV)
845 auto_arch |= arch_feature_cmov;
846 if (cpu_info.edx_features & CPUID_FEAT_EDX_MMX)
847 auto_arch |= arch_feature_mmx;
848 if (cpu_info.edx_features & CPUID_FEAT_EDX_SSE)
849 auto_arch |= arch_feature_sse1;
850 if (cpu_info.edx_features & CPUID_FEAT_EDX_SSE2)
851 auto_arch |= arch_feature_sse2;
852
853 if (cpu_info.ecx_features & CPUID_FEAT_ECX_SSE3)
854 auto_arch |= arch_feature_sse3;
855 if (cpu_info.ecx_features & CPUID_FEAT_ECX_SSSE3)
856 auto_arch |= arch_feature_ssse3;
857 if (cpu_info.ecx_features & CPUID_FEAT_ECX_SSE4_1)
858 auto_arch |= arch_feature_sse4_1;
859 if (cpu_info.ecx_features & CPUID_FEAT_ECX_SSE4_2)
860 auto_arch |= arch_feature_sse4_2;
861 if (cpu_info.ecx_features & CPUID_FEAT_ECX_POPCNT)
862 auto_arch |= arch_feature_popcnt;
863 }
864
865 arch = auto_arch;
866 opt_arch = auto_arch;
867 }
868 #endif /* NATIVE_X86 */
869
flags(cpu_arch_features features,cpu_arch_features flags)870 static bool flags(cpu_arch_features features, cpu_arch_features flags)
871 {
872 return (features & flags) != 0;
873 }
874
ia32_setup_cg_config(void)875 void ia32_setup_cg_config(void)
876 {
877 ia32_code_gen_config_t *const c = &ia32_cg_config;
878 memset(c, 0, sizeof(*c));
879
880 set_arch_costs();
881
882 #ifdef NATIVE_X86
883 if (arch == cpu_autodetect)
884 autodetect_arch();
885 #endif
886
887 c->optimize_size = opt_size != 0;
888 /* on newer intel cpus mov, pop is often faster than leave although it has a
889 * longer opcode */
890 c->use_leave = flags(opt_arch, arch_i386 | arch_all_amd | arch_core2) || opt_size;
891 /* P4s don't like inc/decs because they only partially write the flags
892 * register which produces false dependencies */
893 c->use_incdec = !flags(opt_arch, arch_netburst | arch_nocona | arch_core2 | arch_geode) || opt_size;
894 c->use_softfloat = (fpu_arch & IA32_FPU_ARCH_SOFTFLOAT) != 0;
895 c->use_sse2 = (fpu_arch & IA32_FPU_ARCH_SSE2) != 0 && flags(arch, arch_feature_sse2);
896 c->use_ffreep = flags(opt_arch, arch_athlon_plus);
897 /* valgrind can't cope with femms yet and the usefulness of the optimization
898 * is questionable anyway */
899 #if 0
900 c->use_femms = flags(opt_arch, arch_athlon_plus) &&
901 flags(arch, arch_feature_mmx | arch_all_amd);
902 #else
903 c->use_femms = 0;
904 #endif
905 c->use_fucomi = flags(arch, arch_feature_p6_insn);
906 c->use_cmov = flags(arch, arch_feature_cmov);
907 c->use_modeD_moves = flags(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode);
908 c->use_add_esp_4 = flags(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_geode) && !opt_size;
909 c->use_add_esp_8 = flags(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode | arch_i386 | arch_i486) && !opt_size;
910 c->use_sub_esp_4 = flags(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro) && !opt_size;
911 c->use_sub_esp_8 = flags(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_i386 | arch_i486) && !opt_size;
912 c->use_imul_mem_imm32 = !flags(opt_arch, arch_k8 | arch_k10) || opt_size;
913 c->use_pxor = flags(opt_arch, arch_netburst);
914 c->use_mov_0 = flags(opt_arch, arch_k6) && !opt_size;
915 c->use_short_sex_eax = !flags(opt_arch, arch_k6) && !opt_size;
916 c->use_pad_return = flags(opt_arch, arch_athlon_plus) && !opt_size;
917 c->use_bt = flags(opt_arch, arch_core2 | arch_athlon_plus) || opt_size;
918 c->use_fisttp = flags(opt_arch & arch, arch_feature_sse3);
919 c->use_sse_prefetch = flags(arch, (arch_feature_3DNowE | arch_feature_sse1));
920 c->use_3dnow_prefetch = flags(arch, arch_feature_3DNow);
921 c->use_popcnt = flags(arch, arch_feature_popcnt);
922 c->use_bswap = (arch & arch_mask) >= arch_i486;
923 c->optimize_cc = opt_cc;
924 c->use_unsafe_floatconv = opt_unsafe_floatconv;
925 c->emit_machcode = emit_machcode;
926
927 c->function_alignment = arch_costs->function_alignment;
928 c->label_alignment = arch_costs->label_alignment;
929 c->label_alignment_max_skip = arch_costs->label_alignment_max_skip;
930
931 c->label_alignment_factor =
932 flags(opt_arch, arch_i386 | arch_i486) || opt_size ? 0 :
933 opt_arch & arch_all_amd ? 3 :
934 2;
935 }
936
ia32_init_architecture(void)937 void ia32_init_architecture(void)
938 {
939 lc_opt_entry_t *be_grp, *ia32_grp;
940
941 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
942
943 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
944 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
945
946 lc_opt_add_table(ia32_grp, ia32_architecture_options);
947 }
948