1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2003 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7// Also check that SystemC is ordering properly
8// verilator lint_on IMPERFECTSCH
9
10module t (/*AUTOARG*/
11   // Outputs
12   o1, o8, o16, o32, o64, o65, o128, o513, o1a2, o94a3, obv1, obv16, obv1_vlt, obv16_vlt,
13   // Inputs
14   clk, i1, i8, i16, i32, i64, i65, i128, i513, i1a2, i94a3, ibv1, ibv16, ibv1_vlt, ibv16_vlt
15   );
16
17   input clk;
18
19   input 	 i1;
20   input [7:0]	 i8;
21   input [15:0]	 i16;
22   input [31:0]	 i32;
23   input [63:0]	 i64;
24   input [64:0]	 i65;
25   input [127:0] i128;
26   input [512:0] i513;
27   input 	 i1a2 [1:0];
28   input [93:0]  i94a3 [2:0];
29
30   output logic 	  o1;
31   output logic [7:0]   o8;
32   output logic [15:0]  o16;
33   output logic [31:0]  o32;
34   output logic [63:0]  o64;
35   output logic [64:0]  o65;
36   output logic [127:0] o128;
37   output logic [512:0] o513;
38   output logic 	  o1a2 [1:0];
39   output logic [93:0]  o94a3 [2:0];
40
41   input [0:0] 	 ibv1 /*verilator sc_bv*/;
42   input [15:0]    ibv16 /*verilator sc_bv*/;
43   input [0:0]     ibv1_vlt;
44   input [15:0]     ibv16_vlt;
45
46   output logic [0:0]   obv1 /*verilator sc_bv*/;
47   output logic [15:0]  obv16 /*verilator sc_bv*/;
48   output logic [0:0]   obv1_vlt;
49   output logic [15:0]  obv16_vlt;
50
51   always @ (posedge clk) begin
52      o1 <= i1;
53      o8 <= i8;
54      o16 <= i16;
55      o32 <= i32;
56      o64 <= i64;
57      o65 <= i65;
58      o128 <= i128;
59      o513 <= i513;
60      obv1 <= ibv1;
61      obv16 <= ibv16;
62      obv1_vlt <= ibv1_vlt;
63      obv16_vlt <= ibv16_vlt;
64      o1a2 <= i1a2;
65      o94a3 <= i94a3;
66   end
67
68endmodule
69