1 /* $OpenBSD: pciidevar.h,v 1.22 2024/05/13 01:15:51 jsg Exp $ */ 2 /* $NetBSD: pciidevar.h,v 1.6 2001/01/12 16:04:00 bouyer Exp $ */ 3 4 /* 5 * Copyright (c) 1998 Christopher G. Demetriou. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Christopher G. Demetriou 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_PCI_PCIIDEVAR_H_ 35 #define _DEV_PCI_PCIIDEVAR_H_ 36 37 /* 38 * PCI IDE driver exported software structures. 39 * 40 * Author: Christopher G. Demetriou, March 2, 1998. 41 */ 42 43 #include <dev/ata/atavar.h> 44 #include <dev/ic/wdcreg.h> 45 #include <dev/ic/wdcvar.h> 46 47 /* 48 * While standard PCI IDE controllers only have 2 channels, it is 49 * common for PCI SATA controllers to have more. Here we define 50 * the maximum number of channels that any one PCI IDE device can 51 * have. 52 */ 53 #define PCIIDE_MAX_CHANNELS 4 54 55 struct pciide_softc { 56 struct wdc_softc sc_wdcdev; /* common wdc definitions */ 57 pci_chipset_tag_t sc_pc; /* PCI registers info */ 58 pcitag_t sc_tag; 59 void *sc_pci_ih; /* PCI interrupt handle */ 60 int sc_dma_ok; /* bus-master DMA info */ 61 bus_space_tag_t sc_dma_iot; 62 bus_space_handle_t sc_dma_ioh; 63 bus_size_t sc_dma_iosz; 64 bus_dma_tag_t sc_dmat; 65 66 /* 67 * Some controllers might have DMA restrictions other than 68 * the norm. 69 */ 70 bus_size_t sc_dma_maxsegsz; 71 bus_size_t sc_dma_boundary; 72 73 /* 74 * Used as a register save space by pciide_activate() 75 * 76 * sc_save[] is for the 6 pci regs starting at PCI_MAPREG_END + 0x18 -- 77 * most IDE chipsets need a subset of those saved. sc_save2 is for 78 * up to 6 other registers, which specific chips might need saved. 79 */ 80 pcireg_t sc_save[6]; 81 pcireg_t sc_save2[6]; 82 83 /* Chip description */ 84 const struct pciide_product_desc *sc_pp; 85 /* unmap/detach */ 86 void (*chip_unmap)(struct pciide_softc *, int); 87 /* Chip revision */ 88 int sc_rev; 89 /* common definitions */ 90 struct channel_softc *wdc_chanarray[PCIIDE_MAX_CHANNELS]; 91 /* internal bookkeeping */ 92 struct pciide_channel { /* per-channel data */ 93 struct channel_softc wdc_channel; /* generic part */ 94 const char *name; 95 int hw_ok; /* hardware mapped & OK? */ 96 int compat; /* is it compat? */ 97 int dma_in_progress; 98 void *ih; /* compat or pci handle */ 99 bus_space_handle_t ctl_baseioh; /* ctrl regs blk, native mode */ 100 /* DMA tables and DMA map for xfer, for each drive */ 101 struct pciide_dma_maps { 102 bus_dmamap_t dmamap_table; 103 struct idedma_table *dma_table; 104 bus_dmamap_t dmamap_xfer; 105 int dma_flags; 106 } dma_maps[2]; 107 /* 108 * Some controllers require certain bits to 109 * always be set for proper operation of the 110 * controller. Set those bits here, if they're 111 * required. 112 */ 113 uint8_t idedma_cmd; 114 } pciide_channels[PCIIDE_MAX_CHANNELS]; 115 116 /* Chip-specific private data */ 117 void *sc_cookie; 118 size_t sc_cookielen; 119 120 /* DMA registers access functions */ 121 u_int8_t (*sc_dmacmd_read)(struct pciide_softc *, int); 122 void (*sc_dmacmd_write)(struct pciide_softc *, int, u_int8_t); 123 u_int8_t (*sc_dmactl_read)(struct pciide_softc *, int); 124 void (*sc_dmactl_write)(struct pciide_softc *, int, u_int8_t); 125 void (*sc_dmatbl_write)(struct pciide_softc *, int, u_int32_t); 126 }; 127 128 #define PCIIDE_DMACMD_READ(sc, chan) \ 129 (sc)->sc_dmacmd_read((sc), (chan)) 130 #define PCIIDE_DMACMD_WRITE(sc, chan, val) \ 131 (sc)->sc_dmacmd_write((sc), (chan), (val)) 132 #define PCIIDE_DMACTL_READ(sc, chan) \ 133 (sc)->sc_dmactl_read((sc), (chan)) 134 #define PCIIDE_DMACTL_WRITE(sc, chan, val) \ 135 (sc)->sc_dmactl_write((sc), (chan), (val)) 136 #define PCIIDE_DMATBL_WRITE(sc, chan, val) \ 137 (sc)->sc_dmatbl_write((sc), (chan), (val)) 138 139 int pciide_mapregs_compat( struct pci_attach_args *, 140 struct pciide_channel *, int, bus_size_t *, bus_size_t *); 141 int pciide_mapregs_native(struct pci_attach_args *, 142 struct pciide_channel *, bus_size_t *, bus_size_t *, 143 int (*pci_intr)(void *)); 144 void pciide_mapreg_dma(struct pciide_softc *, 145 struct pci_attach_args *); 146 int pciide_chansetup(struct pciide_softc *, int, pcireg_t); 147 void pciide_mapchan(struct pci_attach_args *, 148 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 149 int (*pci_intr)(void *)); 150 int pciide_chan_candisable(struct pciide_channel *); 151 void pciide_map_compat_intr( struct pci_attach_args *, 152 struct pciide_channel *, int, int); 153 void pciide_unmap_compat_intr( struct pci_attach_args *, 154 struct pciide_channel *, int, int); 155 int pciide_compat_intr(void *); 156 int pciide_pci_intr(void *); 157 int pciide_intr_flag(struct pciide_channel *); 158 159 u_int8_t pciide_dmacmd_read(struct pciide_softc *, int); 160 void pciide_dmacmd_write(struct pciide_softc *, int, u_int8_t); 161 u_int8_t pciide_dmactl_read(struct pciide_softc *, int); 162 void pciide_dmactl_write(struct pciide_softc *, int, u_int8_t); 163 void pciide_dmatbl_write(struct pciide_softc *, int, u_int32_t); 164 165 void pciide_channel_dma_setup(struct pciide_channel *); 166 int pciide_dma_table_setup(struct pciide_softc *, int, int); 167 int pciide_dma_init(void *, int, int, void *, size_t, int); 168 void pciide_dma_start(void *, int, int); 169 int pciide_dma_finish(void *, int, int, int); 170 void pciide_irqack(struct channel_softc *); 171 void pciide_print_modes(struct pciide_channel *); 172 void pciide_print_channels(int, pcireg_t); 173 174 void default_chip_unmap(struct pciide_softc *, int); 175 void pciide_unmapreg_dma(struct pciide_softc *); 176 void pciide_chanfree(struct pciide_softc *, int); 177 void pciide_unmap_chan(struct pciide_softc *, struct pciide_channel *, int); 178 int pciide_unmapregs_compat(struct pciide_softc *, 179 struct pciide_channel *); 180 int pciide_unmapregs_native(struct pciide_softc *, 181 struct pciide_channel *); 182 183 /* 184 * Functions defined by machine-dependent code. 185 */ 186 187 #ifdef __i386__ 188 void gcsc_chip_map(struct pciide_softc *, struct pci_attach_args *); 189 #endif 190 191 /* Attach compat interrupt handler, returning handle or NULL if failed. */ 192 #if !defined(pciide_machdep_compat_intr_establish) 193 void *pciide_machdep_compat_intr_establish(struct device *, 194 struct pci_attach_args *, int, int (*)(void *), void *); 195 void pciide_machdep_compat_intr_disestablish(pci_chipset_tag_t pc, 196 void *); 197 #endif 198 199 #endif /* !_DEV_PCI_PCIIDEVAR_H_ */ 200