1 /* $NetBSD: ifpga_pci.c,v 1.25 2018/11/26 12:21:32 jmcneill Exp $ */
2
3 /*
4 * Copyright (c) 2001 ARM Ltd
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the company may not be used to endorse or promote
16 * products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * Copyright (c) 1997,1998 Mark Brinicombe.
32 * Copyright (c) 1997,1998 Causality Limited
33 * All rights reserved.
34 *
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
37 * are met:
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
43 * 3. All advertising materials mentioning features or use of this software
44 * must display the following acknowledgement:
45 * This product includes software developed by Mark Brinicombe
46 * for the NetBSD Project.
47 * 4. The name of the company nor the name of the author may be used to
48 * endorse or promote products derived from this software without specific
49 * prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
52 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
53 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
54 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
61 * SUCH DAMAGE.
62 */
63
64 #define _ARM32_BUS_DMA_PRIVATE
65
66 #include <sys/cdefs.h>
67 __KERNEL_RCSID(0, "$NetBSD: ifpga_pci.c,v 1.25 2018/11/26 12:21:32 jmcneill Exp $");
68
69 #include <sys/param.h>
70 #include <sys/systm.h>
71 #include <sys/conf.h>
72 #include <sys/malloc.h>
73 #include <sys/device.h>
74
75 #include <evbarm/integrator/int_bus_dma.h>
76
77 #include <machine/intr.h>
78
79 #include <dev/pci/pcireg.h>
80 #include <dev/pci/pcivar.h>
81
82 #include <evbarm/ifpga/ifpgareg.h>
83 #include <evbarm/ifpga/ifpgamem.h>
84 #include <evbarm/ifpga/ifpga_pcivar.h>
85 #include <evbarm/dev/v360reg.h>
86
87
88 void ifpga_pci_attach_hook (device_t, device_t,
89 struct pcibus_attach_args *);
90 int ifpga_pci_bus_maxdevs (void *, int);
91 pcitag_t ifpga_pci_make_tag (void *, int, int, int);
92 void ifpga_pci_decompose_tag (void *, pcitag_t, int *, int *,
93 int *);
94 pcireg_t ifpga_pci_conf_read (void *, pcitag_t, int);
95 void ifpga_pci_conf_write (void *, pcitag_t, int, pcireg_t);
96 int ifpga_pci_intr_map (const struct pci_attach_args *,
97 pci_intr_handle_t *);
98 const char *ifpga_pci_intr_string (void *, pci_intr_handle_t, char *, size_t);
99 const struct evcnt *ifpga_pci_intr_evcnt (void *, pci_intr_handle_t);
100 void *ifpga_pci_intr_establish (void *, pci_intr_handle_t, int,
101 int (*)(void *), void *, const char *);
102 void ifpga_pci_intr_disestablish (void *, void *);
103
104 struct arm32_pci_chipset ifpga_pci_chipset = {
105 .pc_attach_hook = ifpga_pci_attach_hook,
106 .pc_bus_maxdevs = ifpga_pci_bus_maxdevs,
107 .pc_make_tag = ifpga_pci_make_tag,
108 .pc_decompose_tag = ifpga_pci_decompose_tag,
109 .pc_conf_read = ifpga_pci_conf_read,
110 .pc_conf_write = ifpga_pci_conf_write,
111 .pc_intr_map = ifpga_pci_intr_map,
112 .pc_intr_string = ifpga_pci_intr_string,
113 .pc_intr_evcnt = ifpga_pci_intr_evcnt,
114 .pc_intr_establish = ifpga_pci_intr_establish,
115 .pc_intr_disestablish = ifpga_pci_intr_disestablish,
116 .pc_conf_interrupt = ifpga_pci_conf_interrupt,
117 };
118
119 /*
120 * Use the integrator-specific bus_dma routines.
121 */
122 struct arm32_bus_dma_tag ifpga_pci_bus_dma_tag = {
123 0,
124 0,
125 NULL,
126 _bus_dmamap_create,
127 _bus_dmamap_destroy,
128 _bus_dmamap_load,
129 _bus_dmamap_load_mbuf,
130 _bus_dmamap_load_uio,
131 _bus_dmamap_load_raw,
132 _bus_dmamap_unload,
133 _bus_dmamap_sync, /* pre */
134 NULL, /* post */
135 _bus_dmamem_alloc,
136 _bus_dmamem_free,
137 _bus_dmamem_map,
138 _bus_dmamem_unmap,
139 _bus_dmamem_mmap,
140 };
141
142 /*
143 * Currently we only support 12 devices as we select directly in the
144 * type 0 config cycle
145 * (See conf_{read,write} for more detail
146 */
147 #define MAX_PCI_DEVICES 21
148
149 /*static int
150 pci_intr(void *arg)
151 {
152 printf("pci int %x\n", (int)arg);
153 return 0;
154 }*/
155
156
157 void
ifpga_pci_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)158 ifpga_pci_attach_hook(device_t parent, device_t self,
159 struct pcibus_attach_args *pba)
160 {
161 #ifdef PCI_DEBUG
162 printf("ifpga_pci_attach_hook()\n");
163 #endif
164 }
165
166 int
ifpga_pci_bus_maxdevs(void * pcv,int busno)167 ifpga_pci_bus_maxdevs(void *pcv, int busno)
168 {
169 #ifdef PCI_DEBUG
170 printf("ifpga_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno);
171 #endif
172 return MAX_PCI_DEVICES;
173 }
174
175 pcitag_t
ifpga_pci_make_tag(void * pcv,int bus,int device,int function)176 ifpga_pci_make_tag(void *pcv, int bus, int device, int function)
177 {
178 #ifdef PCI_DEBUG
179 printf("ifpga_pci_make_tag(pcv=%p, bus=%d, device=%d, function=%d)\n",
180 pcv, bus, device, function);
181 #endif
182 return (bus << 16) | (device << 11) | (function << 8);
183 }
184
185 void
ifpga_pci_decompose_tag(void * pcv,pcitag_t tag,int * busp,int * devicep,int * functionp)186 ifpga_pci_decompose_tag(void *pcv, pcitag_t tag, int *busp, int *devicep,
187 int *functionp)
188 {
189 #ifdef PCI_DEBUG
190 printf("ifpga_pci_decompose_tag(pcv=%p, tag=0x%08lx, bp=%p, dp=%p, "
191 "fp=%p)\n", pcv, tag, busp, devicep, functionp);
192 #endif
193
194 if (busp != NULL)
195 *busp = (tag >> 16) & 0xff;
196 if (devicep != NULL)
197 *devicep = (tag >> 11) & 0x1f;
198 if (functionp != NULL)
199 *functionp = (tag >> 8) & 0x7;
200 }
201
202 pcireg_t
ifpga_pci_conf_read(void * pcv,pcitag_t tag,int reg)203 ifpga_pci_conf_read(void *pcv, pcitag_t tag, int reg)
204 {
205 pcireg_t data;
206 struct ifpga_pci_softc *sc = (struct ifpga_pci_softc *)pcv;
207 int bus, device, function;
208 u_int address;
209
210 if ((unsigned int)reg >= PCI_CONF_SIZE)
211 return (pcireg_t) -1;
212
213 ifpga_pci_decompose_tag(pcv, tag, &bus, &device, &function);
214
215 /* Reset the appertures so that we can talk to the register space. */
216 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0,
217 IFPGA_PCI_APP0_512MB_BASE);
218 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1,
219 IFPGA_PCI_APP1_CONF_BASE);
220
221 if (bus == 0) {
222 address = (1 << (device + 11)) | reg;
223 bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1,
224 IFPGA_PCI_APP1_CONF_T0_MAP | ((address >> 16) & 0xff00));
225
226 /* Read the value from the bus... */
227 data = bus_space_read_4(sc->sc_iot, sc->sc_conf_ioh,
228 address & 0x00ffffff);
229
230 } else {
231 bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1,
232 IFPGA_PCI_APP1_CONF_T1_MAP);
233
234 /* Read the value from the bus... */
235 data = bus_space_read_4(sc->sc_iot, sc->sc_conf_ioh,
236 tag | reg);
237 }
238 /* ... and put the memory spaces back again. */
239
240 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1,
241 IFPGA_PCI_APP1_256MB_BASE);
242 bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1,
243 IFPGA_PCI_APP1_256MB_MAP);
244 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0,
245 IFPGA_PCI_APP0_256MB_BASE);
246 #ifdef PCI_DEBUG
247 printf("ifpga_pci_conf_read(pcv=%p tag=0x%08lx reg=0x%02x)=0x%08x\n",
248 pcv, tag, reg, data);
249 #endif
250 return data;
251 }
252
253 void
ifpga_pci_conf_write(void * pcv,pcitag_t tag,int reg,pcireg_t data)254 ifpga_pci_conf_write(void *pcv, pcitag_t tag, int reg, pcireg_t data)
255 {
256 struct ifpga_pci_softc *sc = (struct ifpga_pci_softc *)pcv;
257 int bus, device, function;
258 u_int address;
259
260 #ifdef PCI_DEBUG
261 printf("ifpga_pci_conf_write(pcv=%p tag=0x%08lx reg=0x%02x, 0x%08x)\n",
262 pcv, tag, reg, data);
263 #endif
264
265 if ((unsigned int)reg >= PCI_CONF_SIZE)
266 return;
267
268 ifpga_pci_decompose_tag(pcv, tag, &bus, &device, &function);
269
270 /* Reset the appertures so that we can talk to the register space. */
271 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0,
272 IFPGA_PCI_APP0_512MB_BASE);
273 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1,
274 IFPGA_PCI_APP1_CONF_BASE);
275
276 if (bus == 0) {
277 address = (1 << (device + 11)) | reg;
278 bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1,
279 IFPGA_PCI_APP1_CONF_T0_MAP | ((address >> 16) & 0xff00));
280
281 /* Write the value to the bus... */
282 bus_space_write_4(sc->sc_iot, sc->sc_conf_ioh,
283 address & 0x00ffffff, data);
284
285 } else {
286 bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1,
287 IFPGA_PCI_APP1_CONF_T1_MAP);
288
289 /* Write the value to the bus... */
290 bus_space_write_4(sc->sc_iot, sc->sc_conf_ioh, tag | reg,
291 data);
292 }
293 /* ... and put the memory spaces back again. */
294
295 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1,
296 IFPGA_PCI_APP1_256MB_BASE);
297 bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1,
298 IFPGA_PCI_APP1_256MB_MAP);
299 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0,
300 IFPGA_PCI_APP0_256MB_BASE);
301 }
302
303 int
ifpga_pci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)304 ifpga_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
305 {
306 int line = pa->pa_intrline;
307
308 #ifdef PCI_DEBUG
309 int pin = pa->pa_intrpin;
310 void *pcv = pa->pa_pc;
311 pcitag_t intrtag = pa->pa_intrtag;
312 int bus, device, function;
313
314 ifpga_pci_decompose_tag(pcv, intrtag, &bus, &device, &function);
315 printf("ifpga_pci_intr_map: pcv=%p, tag=%08lx pin=%d line=%d "
316 "dev=%d\n", pcv, intrtag, pin, line, device);
317 #endif
318
319
320 #ifdef PCI_DEBUG
321 printf("pin %d, line %d mapped to int %d\n", pin, line, line);
322 #endif
323
324 *ihp = line;
325 return 0;
326 }
327
328 const char *
ifpga_pci_intr_string(void * pcv,pci_intr_handle_t ih,char * buf,size_t len)329 ifpga_pci_intr_string(void *pcv, pci_intr_handle_t ih, char *buf, size_t len)
330 {
331 #ifdef PCI_DEBUG
332 printf("ifpga_pci_intr_string(pcv=%p, ih=0x%" PRIu64 ")\n", pcv, ih);
333 #endif
334 if (ih == 0)
335 panic("ifpga_pci_intr_string: bogus handle 0x%" PRIu64, ih);
336
337 snprintf(buf, len, "pciint%" PRIu64, ih - IFPGA_INTRNUM_PCIINT0);
338 return buf;
339 }
340
341 const struct evcnt *
ifpga_pci_intr_evcnt(void * pcv,pci_intr_handle_t ih)342 ifpga_pci_intr_evcnt(void *pcv, pci_intr_handle_t ih)
343 {
344
345 /* XXX for now, no evcnt parent reported */
346 return NULL;
347 }
348
349 void *
ifpga_pci_intr_establish(void * pcv,pci_intr_handle_t ih,int level,int (* func)(void *),void * arg,const char * xname)350 ifpga_pci_intr_establish(void *pcv, pci_intr_handle_t ih, int level,
351 int (*func) (void *), void *arg, const char *xname)
352 {
353 void *intr;
354
355 #ifdef PCI_DEBUG
356 printf("ifpga_pci_intr_establish(pcv=%p, ih=0x%" PRIu64 ", level=%d, "
357 "func=%p, arg=%p, xname=%s)\n", pcv, ih, level, func, arg, xname);
358 #endif
359
360 intr = ifpga_intr_establish(ih, level, func, arg);
361
362 return intr;
363 }
364
365 void
ifpga_pci_intr_disestablish(void * pcv,void * cookie)366 ifpga_pci_intr_disestablish(void *pcv, void *cookie)
367 {
368 #ifdef PCI_DEBUG
369 printf("ifpga_pci_intr_disestablish(pcv=%p, cookie=%p)\n",
370 pcv, cookie);
371 #endif
372 ifpga_intr_disestablish(cookie);
373 }
374