1 /* -----------------------------------------------------------------------------
2 The copyright in this software is being made available under the BSD
3 License, included below. No patent rights, trademark rights and/or
4 other Intellectual Property Rights other than the copyrights concerning
5 the Software are granted under this license.
6
7 For any license concerning other Intellectual Property rights than the software,
8 especially patent licenses, a separate Agreement needs to be closed.
9 For more information please contact:
10
11 Fraunhofer Heinrich Hertz Institute
12 Einsteinufer 37
13 10587 Berlin, Germany
14 www.hhi.fraunhofer.de/vvc
15 vvc@hhi.fraunhofer.de
16
17 Copyright (c) 2018-2021, Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
18 All rights reserved.
19
20 Redistribution and use in source and binary forms, with or without
21 modification, are permitted provided that the following conditions are met:
22
23 * Redistributions of source code must retain the above copyright notice,
24 this list of conditions and the following disclaimer.
25 * Redistributions in binary form must reproduce the above copyright notice,
26 this list of conditions and the following disclaimer in the documentation
27 and/or other materials provided with the distribution.
28 * Neither the name of Fraunhofer nor the names of its contributors may
29 be used to endorse or promote products derived from this software without
30 specific prior written permission.
31
32 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
36 BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
37 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
38 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
39 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
40 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
41 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
42 THE POSSIBILITY OF SUCH DAMAGE.
43
44
45 ------------------------------------------------------------------------------------------- */
46
47 /*
48 * \ingroup CommonLib
49 * \file InitX86.cpp
50 * \brief Initialize encoder SIMD functions.
51 */
52
53
54 #include "CommonLib/CommonDef.h"
55 #include "CommonLib/InterpolationFilter.h"
56 #include "CommonLib/TrQuant.h"
57 #include "CommonLib/RdCost.h"
58 #include "CommonLib/Buffer.h"
59 #include "CommonLib/TrQuant_EMT.h"
60 #include "CommonLib/IntraPrediction.h"
61 #include "CommonLib/LoopFilter.h"
62 #include "CommonLib/Picture.h"
63
64 #include "CommonLib/AdaptiveLoopFilter.h"
65 #include "CommonLib/SampleAdaptiveOffset.h"
66
67 namespace vvdec
68 {
69
70 #ifdef TARGET_SIMD_X86
71
72
73 #if ENABLE_SIMD_OPT_MCIF
initInterpolationFilterX86()74 void InterpolationFilter::initInterpolationFilterX86( /*int iBitDepthY, int iBitDepthC*/ )
75 {
76 auto vext = read_x86_extension_flags();
77 switch (vext){
78 case AVX512:
79 case AVX2:
80 _initInterpolationFilterX86<AVX2>(/*iBitDepthY, iBitDepthC*/);
81 break;
82 case AVX:
83 _initInterpolationFilterX86<AVX>(/*iBitDepthY, iBitDepthC*/);
84 break;
85 case SSE42:
86 case SSE41:
87 _initInterpolationFilterX86<SSE41>(/*iBitDepthY, iBitDepthC*/);
88 break;
89 default:
90 break;
91 }
92 }
93 #endif
94
95 #if ENABLE_SIMD_OPT_BUFFER
initPelBufOpsX86()96 void PelBufferOps::initPelBufOpsX86()
97 {
98 auto vext = read_x86_extension_flags();
99 switch (vext){
100 case AVX512:
101 case AVX2:
102 _initPelBufOpsX86<AVX2>();
103 break;
104 case AVX:
105 _initPelBufOpsX86<AVX>();
106 break;
107 case SSE42:
108 case SSE41:
109 _initPelBufOpsX86<SSE41>();
110 break;
111 default:
112 break;
113 }
114 }
115 #endif
116
117
118
119
120 #if ENABLE_SIMD_OPT_DIST
initRdCostX86()121 void RdCost::initRdCostX86()
122 {
123 auto vext = read_x86_extension_flags();
124 switch (vext){
125 case AVX512:
126 case AVX2:
127 _initRdCostX86<AVX2>();
128 break;
129 case AVX:
130 _initRdCostX86<AVX>();
131 break;
132 case SSE42:
133 case SSE41:
134 _initRdCostX86<SSE41>();
135 break;
136 default:
137 break;
138 }
139 }
140 #endif
141
142 #if ENABLE_SIMD_OPT_ALF
initAdaptiveLoopFilterX86()143 void AdaptiveLoopFilter::initAdaptiveLoopFilterX86()
144 {
145 auto vext = read_x86_extension_flags();
146 switch ( vext )
147 {
148 case AVX512:
149 case AVX2:
150 _initAdaptiveLoopFilterX86<AVX2>();
151 break;
152 case AVX:
153 _initAdaptiveLoopFilterX86<AVX>();
154 break;
155 case SSE42:
156 case SSE41:
157 _initAdaptiveLoopFilterX86<SSE41>();
158 break;
159 default:
160 break;
161 }
162 }
163 #endif
164
165 #if ENABLE_SIMD_DBLF
initLoopFilterX86()166 void LoopFilter::initLoopFilterX86()
167 {
168 auto vext = read_x86_extension_flags();
169 switch ( vext )
170 {
171 case AVX512:
172 case AVX2:
173 _initLoopFilterX86<AVX2>();
174 break;
175 case AVX:
176 _initLoopFilterX86<AVX>();
177 break;
178 case SSE42:
179 case SSE41:
180 _initLoopFilterX86<SSE41>();
181 break;
182 default:
183 break;
184 }
185 }
186 #endif
187
188 #if ENABLE_SIMD_TCOEFF_OPS
initTCoeffOpsX86()189 void TCoeffOps::initTCoeffOpsX86()
190 {
191 auto vext = read_x86_extension_flags();
192
193 switch( vext )
194 {
195 case AVX512:
196 case AVX2:
197 _initTCoeffOpsX86<AVX2>();
198 break;
199 case AVX:
200 _initTCoeffOpsX86<AVX>();
201 break;
202 case SSE42:
203 case SSE41:
204 _initTCoeffOpsX86<SSE41>();
205 break;
206 default:
207 break;
208 }
209 }
210 #endif
211
212 #if ENABLE_SIMD_OPT_INTRAPRED
initIntraPredictionX86()213 void IntraPrediction::initIntraPredictionX86()
214 {
215 auto vext = read_x86_extension_flags();
216 switch (vext){
217 case AVX512:
218 case AVX2:
219 _initIntraPredictionX86<AVX2>();
220 break;
221 case AVX:
222 _initIntraPredictionX86<AVX>();
223 break;
224 case SSE42:
225 case SSE41:
226 _initIntraPredictionX86<SSE41>();
227 break;
228 default:
229 break;
230 }
231
232 }
233
234 #endif
235 #if ENABLE_SIMD_OPT_SAO
initSampleAdaptiveOffsetX86()236 void SampleAdaptiveOffset::initSampleAdaptiveOffsetX86()
237 {
238 auto vext = read_x86_extension_flags();
239 switch (vext){
240 case AVX512:
241 case AVX2:
242 _initSampleAdaptiveOffsetX86<AVX2>();
243 break;
244 case AVX:
245 _initSampleAdaptiveOffsetX86<AVX>();
246 break;
247 case SSE42:
248 case SSE41:
249 _initSampleAdaptiveOffsetX86<SSE41>();
250 break;
251 default:
252 break;
253 }
254
255 }
256
257 #endif
258
259 #if ENABLE_SIMD_OPT_BIO
initInterPredictionX86()260 void InterPrediction::initInterPredictionX86()
261 {
262 auto vext = read_x86_extension_flags();
263 switch (vext){
264 case AVX512:
265 case AVX2:
266 _initInterPredictionX86<AVX2>();
267 break;
268 case AVX:
269 _initInterPredictionX86<AVX>();
270 break;
271 case SSE42:
272 case SSE41:
273 _initInterPredictionX86<SSE41>();
274 break;
275 default:
276 break;
277 }
278
279 }
280 #endif
281
282 #if ENABLE_SIMD_OPT_PICTURE
initPictureX86()283 void Picture::initPictureX86()
284 {
285 auto vext = read_x86_extension_flags();
286 switch (vext){
287 case AVX512:
288 case AVX2:
289 _initPictureX86<AVX2>();
290 break;
291 case AVX:
292 _initPictureX86<AVX>();
293 break;
294 case SSE42:
295 case SSE41:
296 _initPictureX86<SSE41>();
297 break;
298 default:
299 break;
300 }
301
302 }
303 #endif
304
305 #if ENABLE_SIMD_OPT_QUANT
initQuantX86()306 void Quant::initQuantX86()
307 {
308 auto vext = read_x86_extension_flags();
309 switch (vext){
310 case AVX512:
311 case AVX2:
312 _initQuantX86<AVX2>();
313 break;
314 case AVX:
315 _initQuantX86<AVX>();
316 break;
317 case SSE42:
318 case SSE41:
319 _initQuantX86<SSE41>();
320 break;
321 default:
322 break;
323 }
324
325 }
326
327 #endif
328
329
330
331 #endif
332
333 }
334