1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #include <type_support.h> 17 18 //CSI reveiver has 3 ports. 19 #define N_CSI_PORTS (3) 20 //AM: Use previous define for this. 21 22 //MIPI allows up to 4 channels. 23 #define N_CHANNELS (4) 24 // 12KB = 256bit x 384 words 25 #define IB_CAPACITY_IN_WORDS (384) 26 27 typedef enum { 28 MIPI_0LANE_CFG = 0, 29 MIPI_1LANE_CFG = 1, 30 MIPI_2LANE_CFG = 2, 31 MIPI_3LANE_CFG = 3, 32 MIPI_4LANE_CFG = 4 33 } mipi_lane_cfg_t; 34 35 typedef enum { 36 INPUT_SYSTEM_SOURCE_SENSOR = 0, 37 INPUT_SYSTEM_SOURCE_FIFO, 38 INPUT_SYSTEM_SOURCE_PRBS, 39 INPUT_SYSTEM_SOURCE_MEMORY, 40 N_INPUT_SYSTEM_SOURCE 41 } input_system_source_t; 42 43 /* internal routing configuration */ 44 typedef enum { 45 INPUT_SYSTEM_DISCARD_ALL = 0, 46 INPUT_SYSTEM_CSI_BACKEND = 1, 47 INPUT_SYSTEM_INPUT_BUFFER = 2, 48 INPUT_SYSTEM_MULTICAST = 3, 49 N_INPUT_SYSTEM_CONNECTION 50 } input_system_connection_t; 51 52 typedef enum { 53 INPUT_SYSTEM_MIPI_PORT0, 54 INPUT_SYSTEM_MIPI_PORT1, 55 INPUT_SYSTEM_MIPI_PORT2, 56 INPUT_SYSTEM_ACQUISITION_UNIT, 57 N_INPUT_SYSTEM_MULTIPLEX 58 } input_system_multiplex_t; 59 60 typedef enum { 61 INPUT_SYSTEM_SINK_MEMORY = 0, 62 INPUT_SYSTEM_SINK_ISP, 63 INPUT_SYSTEM_SINK_SP, 64 N_INPUT_SYSTEM_SINK 65 } input_system_sink_t; 66 67 typedef enum { 68 INPUT_SYSTEM_FIFO_CAPTURE = 0, 69 INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING, 70 INPUT_SYSTEM_SRAM_BUFFERING, 71 INPUT_SYSTEM_XMEM_BUFFERING, 72 INPUT_SYSTEM_XMEM_CAPTURE, 73 INPUT_SYSTEM_XMEM_ACQUIRE, 74 N_INPUT_SYSTEM_BUFFERING_MODE 75 } buffering_mode_t; 76 77 typedef struct isp2400_input_system_cfg_s input_system_cfg_t; 78 typedef struct sync_generator_cfg_s sync_generator_cfg_t; 79 typedef struct tpg_cfg_s tpg_cfg_t; 80 typedef struct prbs_cfg_s prbs_cfg_t; 81 82 /* MW: uint16_t should be sufficient */ 83 struct isp2400_input_system_cfg_s { 84 u32 no_side_band; 85 u32 fmt_type; 86 u32 ch_id; 87 u32 input_mode; 88 }; 89 90 struct sync_generator_cfg_s { 91 u32 width; 92 u32 height; 93 u32 hblank_cycles; 94 u32 vblank_cycles; 95 }; 96 97 /* MW: tpg & prbs are exclusive */ 98 struct tpg_cfg_s { 99 u32 x_mask; 100 u32 y_mask; 101 u32 x_delta; 102 u32 y_delta; 103 u32 xy_mask; 104 sync_generator_cfg_t sync_gen_cfg; 105 }; 106 107 struct prbs_cfg_s { 108 u32 seed; 109 sync_generator_cfg_t sync_gen_cfg; 110 }; 111 112 struct gpfifo_cfg_s { 113 // TBD. 114 sync_generator_cfg_t sync_gen_cfg; 115 }; 116 117 typedef struct gpfifo_cfg_s gpfifo_cfg_t; 118 119 //ALX:Commented out to pass the compilation. 120 //typedef struct isp2400_input_system_cfg_s input_system_cfg_t; 121 122 struct ib_buffer_s { 123 u32 mem_reg_size; 124 u32 nof_mem_regs; 125 u32 mem_reg_addr; 126 }; 127 128 typedef struct ib_buffer_s isp2400_ib_buffer_t; 129 130 struct csi_cfg_s { 131 u32 csi_port; 132 buffering_mode_t buffering_mode; 133 isp2400_ib_buffer_t csi_buffer; 134 isp2400_ib_buffer_t acquisition_buffer; 135 u32 nof_xmem_buffers; 136 }; 137 138 typedef struct csi_cfg_s csi_cfg_t; 139 140 typedef enum { 141 INPUT_SYSTEM_CFG_FLAG_RESET = 0, 142 INPUT_SYSTEM_CFG_FLAG_SET = 1U << 0, 143 INPUT_SYSTEM_CFG_FLAG_BLOCKED = 1U << 1, 144 INPUT_SYSTEM_CFG_FLAG_REQUIRED = 1U << 2, 145 INPUT_SYSTEM_CFG_FLAG_CONFLICT = 1U << 3 // To mark a conflicting configuration. 146 } isp2400_input_system_cfg_flag_t; 147 148 typedef u32 input_system_config_flags_t; 149