1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_CONTEXT_TYPES__ 7 #define __INTEL_CONTEXT_TYPES__ 8 9 #include <linux/average.h> 10 #include <linux/kref.h> 11 #include <linux/list.h> 12 #include <linux/mutex.h> 13 #include <linux/types.h> 14 15 #include "i915_active_types.h" 16 #include "i915_sw_fence.h" 17 #include "i915_utils.h" 18 #include "intel_engine_types.h" 19 #include "intel_sseu.h" 20 #include "intel_wakeref.h" 21 22 #include "uc/intel_guc_fwif.h" 23 24 #define CONTEXT_REDZONE POISON_INUSE 25 DECLARE_EWMA(runtime, 3, 8); 26 27 struct i915_gem_context; 28 struct i915_gem_ww_ctx; 29 struct i915_vma; 30 struct intel_breadcrumbs; 31 struct intel_context; 32 struct intel_ring; 33 34 struct intel_context_ops { 35 unsigned long flags; 36 #define COPS_HAS_INFLIGHT_BIT 0 37 #define COPS_HAS_INFLIGHT BIT(COPS_HAS_INFLIGHT_BIT) 38 39 #define COPS_RUNTIME_CYCLES_BIT 1 40 #define COPS_RUNTIME_CYCLES BIT(COPS_RUNTIME_CYCLES_BIT) 41 42 int (*alloc)(struct intel_context *ce); 43 44 void (*revoke)(struct intel_context *ce, struct i915_request *rq, 45 unsigned int preempt_timeout_ms); 46 47 void (*close)(struct intel_context *ce); 48 49 int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void **vaddr); 50 int (*pin)(struct intel_context *ce, void *vaddr); 51 void (*unpin)(struct intel_context *ce); 52 void (*post_unpin)(struct intel_context *ce); 53 54 void (*cancel_request)(struct intel_context *ce, 55 struct i915_request *rq); 56 57 void (*enter)(struct intel_context *ce); 58 void (*exit)(struct intel_context *ce); 59 60 void (*sched_disable)(struct intel_context *ce); 61 62 void (*update_stats)(struct intel_context *ce); 63 64 void (*reset)(struct intel_context *ce); 65 void (*destroy)(struct kref *kref); 66 67 /* virtual/parallel engine/context interface */ 68 struct intel_context *(*create_virtual)(struct intel_engine_cs **engine, 69 unsigned int count, 70 unsigned long flags); 71 struct intel_context *(*create_parallel)(struct intel_engine_cs **engines, 72 unsigned int num_siblings, 73 unsigned int width); 74 struct intel_engine_cs *(*get_sibling)(struct intel_engine_cs *engine, 75 unsigned int sibling); 76 }; 77 78 struct intel_context { 79 /* 80 * Note: Some fields may be accessed under RCU. 81 * 82 * Unless otherwise noted a field can safely be assumed to be protected 83 * by strong reference counting. 84 */ 85 union { 86 struct kref ref; /* no kref_get_unless_zero()! */ 87 struct rcu_head rcu; 88 }; 89 90 struct intel_engine_cs *engine; 91 struct intel_engine_cs *inflight; 92 #define __intel_context_inflight(engine) ptr_mask_bits(engine, 3) 93 #define __intel_context_inflight_count(engine) ptr_unmask_bits(engine, 3) 94 #define intel_context_inflight(ce) \ 95 __intel_context_inflight(READ_ONCE((ce)->inflight)) 96 #define intel_context_inflight_count(ce) \ 97 __intel_context_inflight_count(READ_ONCE((ce)->inflight)) 98 99 struct i915_address_space *vm; 100 struct i915_gem_context __rcu *gem_context; 101 102 /* 103 * @signal_lock protects the list of requests that need signaling, 104 * @signals. While there are any requests that need signaling, 105 * we add the context to the breadcrumbs worker, and remove it 106 * upon completion/cancellation of the last request. 107 */ 108 struct list_head signal_link; /* Accessed under RCU */ 109 struct list_head signals; /* Guarded by signal_lock */ 110 spinlock_t signal_lock; /* protects signals, the list of requests */ 111 112 struct i915_vma *state; 113 u32 ring_size; 114 struct intel_ring *ring; 115 struct intel_timeline *timeline; 116 intel_wakeref_t wakeref; 117 118 unsigned long flags; 119 #define CONTEXT_BARRIER_BIT 0 120 #define CONTEXT_ALLOC_BIT 1 121 #define CONTEXT_INIT_BIT 2 122 #define CONTEXT_VALID_BIT 3 123 #define CONTEXT_CLOSED_BIT 4 124 #define CONTEXT_USE_SEMAPHORES 5 125 #define CONTEXT_BANNED 6 126 #define CONTEXT_FORCE_SINGLE_SUBMISSION 7 127 #define CONTEXT_NOPREEMPT 8 128 #define CONTEXT_LRCA_DIRTY 9 129 #define CONTEXT_GUC_INIT 10 130 #define CONTEXT_PERMA_PIN 11 131 #define CONTEXT_IS_PARKING 12 132 #define CONTEXT_EXITING 13 133 #define CONTEXT_LOW_LATENCY 14 134 135 struct { 136 u64 timeout_us; 137 } watchdog; 138 139 u32 *lrc_reg_state; 140 union { 141 struct { 142 u32 lrca; 143 u32 ccid; 144 }; 145 u64 desc; 146 } lrc; 147 u32 tag; /* cookie passed to HW to track this context on submission */ 148 149 /** stats: Context GPU engine busyness tracking. */ 150 struct intel_context_stats { 151 u64 active; 152 153 /* Time on GPU as tracked by the hw. */ 154 struct { 155 struct ewma_runtime avg; 156 u64 total; 157 u32 last; 158 I915_SELFTEST_DECLARE(u32 num_underflow); 159 I915_SELFTEST_DECLARE(u32 max_underflow); 160 } runtime; 161 } stats; 162 163 unsigned int active_count; /* protected by timeline->mutex */ 164 165 atomic_t pin_count; 166 struct mutex pin_mutex; /* guards pinning and associated on-gpuing */ 167 168 /** 169 * active: Active tracker for the rq activity (inc. external) on this 170 * intel_context object. 171 */ 172 struct i915_active active; 173 174 const struct intel_context_ops *ops; 175 176 /** sseu: Control eu/slice partitioning */ 177 struct intel_sseu sseu; 178 179 /** 180 * pinned_contexts_link: List link for the engine's pinned contexts. 181 * This is only used if this is a perma-pinned kernel context and 182 * the list is assumed to only be manipulated during driver load 183 * or unload time so no mutex protection currently. 184 */ 185 struct list_head pinned_contexts_link; 186 187 u8 wa_bb_page; /* if set, page num reserved for context workarounds */ 188 189 struct { 190 /** @lock: protects everything in guc_state */ 191 spinlock_t lock; 192 /** 193 * @sched_state: scheduling state of this context using GuC 194 * submission 195 */ 196 u32 sched_state; 197 /* 198 * @fences: maintains a list of requests that are currently 199 * being fenced until a GuC operation completes 200 */ 201 struct list_head fences; 202 /** 203 * @blocked: fence used to signal when the blocking of a 204 * context's submissions is complete. 205 */ 206 struct i915_sw_fence blocked; 207 /** @requests: list of active requests on this context */ 208 struct list_head requests; 209 /** @prio: the context's current guc priority */ 210 u8 prio; 211 /** 212 * @prio_count: a counter of the number requests in flight in 213 * each priority bucket 214 */ 215 u32 prio_count[GUC_CLIENT_PRIORITY_NUM]; 216 /** 217 * @sched_disable_delay_work: worker to disable scheduling on this 218 * context 219 */ 220 struct delayed_work sched_disable_delay_work; 221 } guc_state; 222 223 struct { 224 /** 225 * @id: handle which is used to uniquely identify this context 226 * with the GuC, protected by guc->submission_state.lock 227 */ 228 u16 id; 229 /** 230 * @ref: the number of references to the guc_id, when 231 * transitioning in and out of zero protected by 232 * guc->submission_state.lock 233 */ 234 atomic_t ref; 235 /** 236 * @link: in guc->guc_id_list when the guc_id has no refs but is 237 * still valid, protected by guc->submission_state.lock 238 */ 239 struct list_head link; 240 } guc_id; 241 242 /** 243 * @destroyed_link: link in guc->submission_state.destroyed_contexts, in 244 * list when context is pending to be destroyed (deregistered with the 245 * GuC), protected by guc->submission_state.lock 246 */ 247 struct list_head destroyed_link; 248 249 /** @parallel: sub-structure for parallel submission members */ 250 struct { 251 union { 252 /** 253 * @child_list: parent's list of children 254 * contexts, no protection as immutable after context 255 * creation 256 */ 257 struct list_head child_list; 258 /** 259 * @child_link: child's link into parent's list of 260 * children 261 */ 262 struct list_head child_link; 263 }; 264 /** @parent: pointer to parent if child */ 265 struct intel_context *parent; 266 /** 267 * @last_rq: last request submitted on a parallel context, used 268 * to insert submit fences between requests in the parallel 269 * context 270 */ 271 struct i915_request *last_rq; 272 /** 273 * @fence_context: fence context composite fence when doing 274 * parallel submission 275 */ 276 u64 fence_context; 277 /** 278 * @seqno: seqno for composite fence when doing parallel 279 * submission 280 */ 281 u32 seqno; 282 /** @number_children: number of children if parent */ 283 u8 number_children; 284 /** @child_index: index into child_list if child */ 285 u8 child_index; 286 /** @guc: GuC specific members for parallel submission */ 287 struct { 288 /** @wqi_head: cached head pointer in work queue */ 289 u16 wqi_head; 290 /** @wqi_tail: cached tail pointer in work queue */ 291 u16 wqi_tail; 292 /** @wq_head: pointer to the actual head in work queue */ 293 u32 *wq_head; 294 /** @wq_tail: pointer to the actual head in work queue */ 295 u32 *wq_tail; 296 /** @wq_status: pointer to the status in work queue */ 297 u32 *wq_status; 298 299 /** 300 * @parent_page: page in context state (ce->state) used 301 * by parent for work queue, process descriptor 302 */ 303 u8 parent_page; 304 } guc; 305 } parallel; 306 307 #ifdef CONFIG_DRM_I915_SELFTEST 308 /** 309 * @drop_schedule_enable: Force drop of schedule enable G2H for selftest 310 */ 311 bool drop_schedule_enable; 312 313 /** 314 * @drop_schedule_disable: Force drop of schedule disable G2H for 315 * selftest 316 */ 317 bool drop_schedule_disable; 318 319 /** 320 * @drop_deregister: Force drop of deregister G2H for selftest 321 */ 322 bool drop_deregister; 323 #endif 324 }; 325 326 #endif /* __INTEL_CONTEXT_TYPES__ */ 327