1 /*
2 * Copyright � 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Ben Widawsky <ben@bwidawsk.net>
25 *
26 */
27
28 #include <stdio.h>
29 #include <stdarg.h>
30 #include <stdlib.h>
31 #include <sys/types.h>
32 #include "intel_gpu_tools.h"
33
34 static struct intel_register_range gen_bwcl_register_map[] = {
35 {0x00000000, 0x00000fff, INTEL_RANGE_RW},
36 {0x00001000, 0x00000fff, INTEL_RANGE_RSVD},
37 {0x00002000, 0x00000fff, INTEL_RANGE_RW},
38 {0x00003000, 0x000001ff, INTEL_RANGE_RW},
39 {0x00003200, 0x00000dff, INTEL_RANGE_RW},
40 {0x00004000, 0x000003ff, INTEL_RANGE_RSVD},
41 {0x00004400, 0x00000bff, INTEL_RANGE_RSVD},
42 {0x00005000, 0x00000fff, INTEL_RANGE_RW},
43 {0x00006000, 0x00000fff, INTEL_RANGE_RW},
44 {0x00007000, 0x000003ff, INTEL_RANGE_RW},
45 {0x00007400, 0x000014ff, INTEL_RANGE_RW},
46 {0x00008900, 0x000006ff, INTEL_RANGE_RSVD},
47 {0x00009000, 0x00000fff, INTEL_RANGE_RSVD},
48 {0x0000a000, 0x00000fff, INTEL_RANGE_RW},
49 {0x0000b000, 0x00004fff, INTEL_RANGE_RSVD},
50 {0x00010000, 0x00003fff, INTEL_RANGE_RW},
51 {0x00014000, 0x0001bfff, INTEL_RANGE_RSVD},
52 {0x00030000, 0x0000ffff, INTEL_RANGE_RW},
53 {0x00040000, 0x0001ffff, INTEL_RANGE_RSVD},
54 {0x00060000, 0x0000ffff, INTEL_RANGE_RW},
55 {0x00070000, 0x00002fff, INTEL_RANGE_RW},
56 {0x00073000, 0x00000fff, INTEL_RANGE_RW},
57 {0x00074000, 0x0000bfff, INTEL_RANGE_RSVD},
58 {0x00000000, 0x00000000, INTEL_RANGE_END}
59 };
60
61 static struct intel_register_range gen4_register_map[] = {
62 {0x00000000, 0x00000fff, INTEL_RANGE_RW},
63 {0x00001000, 0x00000fff, INTEL_RANGE_RSVD},
64 {0x00002000, 0x00000fff, INTEL_RANGE_RW},
65 {0x00003000, 0x000001ff, INTEL_RANGE_RW},
66 {0x00003200, 0x00000dff, INTEL_RANGE_RW},
67 {0x00004000, 0x000003ff, INTEL_RANGE_RW},
68 {0x00004400, 0x00000bff, INTEL_RANGE_RW},
69 {0x00005000, 0x00000fff, INTEL_RANGE_RW},
70 {0x00006000, 0x00000fff, INTEL_RANGE_RW},
71 {0x00007000, 0x000003ff, INTEL_RANGE_RW},
72 {0x00007400, 0x000014ff, INTEL_RANGE_RW},
73 {0x00008900, 0x000006ff, INTEL_RANGE_RSVD},
74 {0x00009000, 0x00000fff, INTEL_RANGE_RSVD},
75 {0x0000a000, 0x00000fff, INTEL_RANGE_RW},
76 {0x0000b000, 0x00004fff, INTEL_RANGE_RSVD},
77 {0x00010000, 0x00003fff, INTEL_RANGE_RW},
78 {0x00014000, 0x0001bfff, INTEL_RANGE_RSVD},
79 {0x00030000, 0x0000ffff, INTEL_RANGE_RW},
80 {0x00040000, 0x0001ffff, INTEL_RANGE_RSVD},
81 {0x00060000, 0x0000ffff, INTEL_RANGE_RW},
82 {0x00070000, 0x00002fff, INTEL_RANGE_RW},
83 {0x00073000, 0x00000fff, INTEL_RANGE_RW},
84 {0x00074000, 0x0000bfff, INTEL_RANGE_RSVD},
85 {0x00000000, 0x00000000, INTEL_RANGE_END}
86 };
87
88 /* The documentation is a little sketchy on these register ranges. */
89 static struct intel_register_range gen6_gt_register_map[] = {
90 {0x00000000, 0x00000fff, INTEL_RANGE_RW},
91 {0x00001000, 0x00000fff, INTEL_RANGE_RSVD},
92 {0x00002000, 0x00000fff, INTEL_RANGE_RW},
93 {0x00003000, 0x000001ff, INTEL_RANGE_RW},
94 {0x00003200, 0x00000dff, INTEL_RANGE_RW},
95 {0x00004000, 0x00000fff, INTEL_RANGE_RW},
96 {0x00005000, 0x0000017f, INTEL_RANGE_RW},
97 {0x00005180, 0x00000e7f, INTEL_RANGE_RW},
98 {0x00006000, 0x00001fff, INTEL_RANGE_RW},
99 {0x00008000, 0x000007ff, INTEL_RANGE_RW},
100 {0x00008800, 0x000000ff, INTEL_RANGE_RSVD},
101 {0x00008900, 0x000006ff, INTEL_RANGE_RW},
102 {0x00009000, 0x00000fff, INTEL_RANGE_RSVD},
103 {0x0000a000, 0x00000fff, INTEL_RANGE_RW},
104 {0x0000b000, 0x00004fff, INTEL_RANGE_RSVD},
105 {0x00010000, 0x00001fff, INTEL_RANGE_RW},
106 {0x00012000, 0x000003ff, INTEL_RANGE_RW},
107 {0x00012400, 0x00000bff, INTEL_RANGE_RW},
108 {0x00013000, 0x00000fff, INTEL_RANGE_RW},
109 {0x00014000, 0x00000fff, INTEL_RANGE_RW},
110 {0x00015000, 0x0000cfff, INTEL_RANGE_RW},
111 {0x00022000, 0x00000fff, INTEL_RANGE_RW},
112 {0x00023000, 0x00000fff, INTEL_RANGE_RSVD},
113 {0x00024000, 0x00000fff, INTEL_RANGE_RW},
114 {0x00025000, 0x0000afff, INTEL_RANGE_RSVD},
115 {0x00030000, 0x0000ffff, INTEL_RANGE_RW},
116 {0x00040000, 0x0000ffff, INTEL_RANGE_RW},
117 {0x00050000, 0x0000ffff, INTEL_RANGE_RW},
118 {0x00060000, 0x0000ffff, INTEL_RANGE_RW},
119 {0x00070000, 0x00003fff, INTEL_RANGE_RW},
120 {0x00074000, 0x0008bfff, INTEL_RANGE_RSVD},
121 {0x00100000, 0x00007fff, INTEL_RANGE_RW},
122 {0x00108000, 0x00037fff, INTEL_RANGE_RSVD},
123 {0x00140000, 0x0003ffff, INTEL_RANGE_RW},
124 {0x00000000, 0x00000000, INTEL_RANGE_END}
125 };
126
127 struct intel_register_map
intel_get_register_map(uint32_t devid)128 intel_get_register_map(uint32_t devid)
129 {
130 struct intel_register_map map;
131 const int gen = intel_gen(devid);
132
133 if (gen >= 6) {
134 map.map = gen6_gt_register_map;
135 map.top = 0x180000;
136 } else if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
137 map.map = gen_bwcl_register_map;
138 map.top = 0x80000;
139 } else if (gen >= 4) {
140 map.map = gen4_register_map;
141 map.top = 0x80000;
142 } else {
143 fprintf(stderr, "Gen2/3 Ranges are not supported. Please use "
144 "unsafe access.");
145 abort();
146 }
147
148 map.alignment_mask = 0x3;
149
150 return map;
151 }
152
153 struct intel_register_range *
intel_get_register_range(struct intel_register_map map,uint32_t offset,int mode)154 intel_get_register_range(struct intel_register_map map, uint32_t offset, int mode)
155 {
156 struct intel_register_range *range = map.map;
157 uint32_t align = map.alignment_mask;
158
159 if (offset & map.alignment_mask)
160 return NULL;
161
162 if (offset >= map.top)
163 return NULL;
164
165 while (!(range->flags & INTEL_RANGE_END)) {
166 /* list is assumed to be in order */
167 if (offset < range->base)
168 break;
169
170 if ( (offset >= range->base) &&
171 (offset + align) <= (range->base + range->size)) {
172 if ((mode & range->flags) == mode)
173 return range;
174 }
175 range++;
176 }
177
178 return NULL;
179 }
180