1 /* $NetBSD: edid.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $ */
2
3 /*
4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Ke Yu
27 * Zhiyuan Lv <zhiyuan.lv@intel.com>
28 *
29 * Contributors:
30 * Terrence Xu <terrence.xu@intel.com>
31 * Changbin Du <changbin.du@intel.com>
32 * Bing Niu <bing.niu@intel.com>
33 * Zhi Wang <zhi.a.wang@intel.com>
34 *
35 */
36
37 #include <sys/cdefs.h>
38 __KERNEL_RCSID(0, "$NetBSD: edid.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $");
39
40 #include "i915_drv.h"
41 #include "gvt.h"
42
43 #define GMBUS1_TOTAL_BYTES_SHIFT 16
44 #define GMBUS1_TOTAL_BYTES_MASK 0x1ff
45 #define gmbus1_total_byte_count(v) (((v) >> \
46 GMBUS1_TOTAL_BYTES_SHIFT) & GMBUS1_TOTAL_BYTES_MASK)
47 #define gmbus1_slave_addr(v) (((v) & 0xff) >> 1)
48 #define gmbus1_slave_index(v) (((v) >> 8) & 0xff)
49 #define gmbus1_bus_cycle(v) (((v) >> 25) & 0x7)
50
51 /* GMBUS0 bits definitions */
52 #define _GMBUS_PIN_SEL_MASK (0x7)
53
edid_get_byte(struct intel_vgpu * vgpu)54 static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
55 {
56 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
57 unsigned char chr = 0;
58
59 if (edid->state == I2C_NOT_SPECIFIED || !edid->slave_selected) {
60 gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n");
61 return 0;
62 }
63 if (edid->current_edid_read >= EDID_SIZE) {
64 gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n");
65 return 0;
66 }
67
68 if (!edid->edid_available) {
69 gvt_vgpu_err("Reading EDID but EDID is not available!\n");
70 return 0;
71 }
72
73 if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) {
74 struct intel_vgpu_edid_data *edid_data =
75 intel_vgpu_port(vgpu, edid->port)->edid;
76
77 chr = edid_data->edid_block[edid->current_edid_read];
78 edid->current_edid_read++;
79 } else {
80 gvt_vgpu_err("No EDID available during the reading?\n");
81 }
82 return chr;
83 }
84
cnp_get_port_from_gmbus0(u32 gmbus0)85 static inline int cnp_get_port_from_gmbus0(u32 gmbus0)
86 {
87 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
88 int port = -EINVAL;
89
90 if (port_select == GMBUS_PIN_1_BXT)
91 port = PORT_B;
92 else if (port_select == GMBUS_PIN_2_BXT)
93 port = PORT_C;
94 else if (port_select == GMBUS_PIN_3_BXT)
95 port = PORT_D;
96 else if (port_select == GMBUS_PIN_4_CNP)
97 port = PORT_E;
98 return port;
99 }
100
bxt_get_port_from_gmbus0(u32 gmbus0)101 static inline int bxt_get_port_from_gmbus0(u32 gmbus0)
102 {
103 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
104 int port = -EINVAL;
105
106 if (port_select == GMBUS_PIN_1_BXT)
107 port = PORT_B;
108 else if (port_select == GMBUS_PIN_2_BXT)
109 port = PORT_C;
110 else if (port_select == GMBUS_PIN_3_BXT)
111 port = PORT_D;
112 return port;
113 }
114
get_port_from_gmbus0(u32 gmbus0)115 static inline int get_port_from_gmbus0(u32 gmbus0)
116 {
117 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
118 int port = -EINVAL;
119
120 if (port_select == GMBUS_PIN_VGADDC)
121 port = PORT_E;
122 else if (port_select == GMBUS_PIN_DPC)
123 port = PORT_C;
124 else if (port_select == GMBUS_PIN_DPB)
125 port = PORT_B;
126 else if (port_select == GMBUS_PIN_DPD)
127 port = PORT_D;
128 return port;
129 }
130
reset_gmbus_controller(struct intel_vgpu * vgpu)131 static void reset_gmbus_controller(struct intel_vgpu *vgpu)
132 {
133 vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
134 if (!vgpu->display.i2c_edid.edid_available)
135 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
136 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
137 }
138
139 /* GMBUS0 */
gmbus0_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)140 static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
141 unsigned int offset, void *p_data, unsigned int bytes)
142 {
143 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
144 int port, pin_select;
145
146 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
147
148 pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;
149
150 intel_vgpu_init_i2c_edid(vgpu);
151
152 if (pin_select == 0)
153 return 0;
154
155 if (IS_BROXTON(dev_priv))
156 port = bxt_get_port_from_gmbus0(pin_select);
157 else if (IS_COFFEELAKE(dev_priv))
158 port = cnp_get_port_from_gmbus0(pin_select);
159 else
160 port = get_port_from_gmbus0(pin_select);
161 if (WARN_ON(port < 0))
162 return 0;
163
164 vgpu->display.i2c_edid.state = I2C_GMBUS;
165 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
166
167 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
168 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
169
170 if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
171 !intel_vgpu_port_is_dp(vgpu, port)) {
172 vgpu->display.i2c_edid.port = port;
173 vgpu->display.i2c_edid.edid_available = true;
174 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
175 } else
176 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
177 return 0;
178 }
179
gmbus1_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)180 static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
181 void *p_data, unsigned int bytes)
182 {
183 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
184 u32 slave_addr;
185 u32 wvalue = *(u32 *)p_data;
186
187 if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
188 if (!(wvalue & GMBUS_SW_CLR_INT)) {
189 vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;
190 reset_gmbus_controller(vgpu);
191 }
192 /*
193 * TODO: "This bit is cleared to zero when an event
194 * causes the HW_RDY bit transition to occur "
195 */
196 } else {
197 /*
198 * per bspec setting this bit can cause:
199 * 1) INT status bit cleared
200 * 2) HW_RDY bit asserted
201 */
202 if (wvalue & GMBUS_SW_CLR_INT) {
203 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
204 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
205 }
206
207 /* For virtualization, we suppose that HW is always ready,
208 * so GMBUS_SW_RDY should always be cleared
209 */
210 if (wvalue & GMBUS_SW_RDY)
211 wvalue &= ~GMBUS_SW_RDY;
212
213 i2c_edid->gmbus.total_byte_count =
214 gmbus1_total_byte_count(wvalue);
215 slave_addr = gmbus1_slave_addr(wvalue);
216
217 /* vgpu gmbus only support EDID */
218 if (slave_addr == EDID_ADDR) {
219 i2c_edid->slave_selected = true;
220 } else if (slave_addr != 0) {
221 gvt_dbg_dpy(
222 "vgpu%d: unsupported gmbus slave addr(0x%x)\n"
223 " gmbus operations will be ignored.\n",
224 vgpu->id, slave_addr);
225 }
226
227 if (wvalue & GMBUS_CYCLE_INDEX)
228 i2c_edid->current_edid_read =
229 gmbus1_slave_index(wvalue);
230
231 i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue);
232 switch (gmbus1_bus_cycle(wvalue)) {
233 case GMBUS_NOCYCLE:
234 break;
235 case GMBUS_STOP:
236 /* From spec:
237 * This can only cause a STOP to be generated
238 * if a GMBUS cycle is generated, the GMBUS is
239 * currently in a data/wait/idle phase, or it is in a
240 * WAIT phase
241 */
242 if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))
243 != GMBUS_NOCYCLE) {
244 intel_vgpu_init_i2c_edid(vgpu);
245 /* After the 'stop' cycle, hw state would become
246 * 'stop phase' and then 'idle phase' after a
247 * few milliseconds. In emulation, we just set
248 * it as 'idle phase' ('stop phase' is not
249 * visible in gmbus interface)
250 */
251 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
252 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
253 }
254 break;
255 case NIDX_NS_W:
256 case IDX_NS_W:
257 case NIDX_STOP:
258 case IDX_STOP:
259 /* From hw spec the GMBUS phase
260 * transition like this:
261 * START (-->INDEX) -->DATA
262 */
263 i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;
264 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
265 break;
266 default:
267 gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
268 break;
269 }
270 /*
271 * From hw spec the WAIT state will be
272 * cleared:
273 * (1) in a new GMBUS cycle
274 * (2) by generating a stop
275 */
276 vgpu_vreg(vgpu, offset) = wvalue;
277 }
278 return 0;
279 }
280
gmbus3_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)281 static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
282 void *p_data, unsigned int bytes)
283 {
284 WARN_ON(1);
285 return 0;
286 }
287
gmbus3_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)288 static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
289 void *p_data, unsigned int bytes)
290 {
291 int i;
292 unsigned char byte_data;
293 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
294 int byte_left = i2c_edid->gmbus.total_byte_count -
295 i2c_edid->current_edid_read;
296 int byte_count = byte_left;
297 u32 reg_data = 0;
298
299 /* Data can only be recevied if previous settings correct */
300 if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
301 if (byte_left <= 0) {
302 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
303 return 0;
304 }
305
306 if (byte_count > 4)
307 byte_count = 4;
308 for (i = 0; i < byte_count; i++) {
309 byte_data = edid_get_byte(vgpu);
310 reg_data |= (byte_data << (i << 3));
311 }
312
313 memcpy(&vgpu_vreg(vgpu, offset), ®_data, byte_count);
314 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
315
316 if (byte_left <= 4) {
317 switch (i2c_edid->gmbus.cycle_type) {
318 case NIDX_STOP:
319 case IDX_STOP:
320 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
321 break;
322 case NIDX_NS_W:
323 case IDX_NS_W:
324 default:
325 i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE;
326 break;
327 }
328 intel_vgpu_init_i2c_edid(vgpu);
329 }
330 /*
331 * Read GMBUS3 during send operation,
332 * return the latest written value
333 */
334 } else {
335 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
336 gvt_vgpu_err("warning: gmbus3 read with nothing returned\n");
337 }
338 return 0;
339 }
340
gmbus2_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)341 static int gmbus2_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
342 void *p_data, unsigned int bytes)
343 {
344 u32 value = vgpu_vreg(vgpu, offset);
345
346 if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))
347 vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;
348 memcpy(p_data, (void *)&value, bytes);
349 return 0;
350 }
351
gmbus2_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)352 static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
353 void *p_data, unsigned int bytes)
354 {
355 u32 wvalue = *(u32 *)p_data;
356
357 if (wvalue & GMBUS_INUSE)
358 vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;
359 /* All other bits are read-only */
360 return 0;
361 }
362
363 /**
364 * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
365 * @vgpu: a vGPU
366 * @offset: reg offset
367 * @p_data: data return buffer
368 * @bytes: access data length
369 *
370 * This function is used to emulate gmbus register mmio read
371 *
372 * Returns:
373 * Zero on success, negative error code if failed.
374 *
375 */
intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)376 int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
377 unsigned int offset, void *p_data, unsigned int bytes)
378 {
379 if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
380 return -EINVAL;
381
382 if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
383 return gmbus2_mmio_read(vgpu, offset, p_data, bytes);
384 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
385 return gmbus3_mmio_read(vgpu, offset, p_data, bytes);
386
387 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
388 return 0;
389 }
390
391 /**
392 * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
393 * @vgpu: a vGPU
394 * @offset: reg offset
395 * @p_data: data return buffer
396 * @bytes: access data length
397 *
398 * This function is used to emulate gmbus register mmio write
399 *
400 * Returns:
401 * Zero on success, negative error code if failed.
402 *
403 */
intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)404 int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
405 unsigned int offset, void *p_data, unsigned int bytes)
406 {
407 if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
408 return -EINVAL;
409
410 if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
411 return gmbus0_mmio_write(vgpu, offset, p_data, bytes);
412 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1))
413 return gmbus1_mmio_write(vgpu, offset, p_data, bytes);
414 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
415 return gmbus2_mmio_write(vgpu, offset, p_data, bytes);
416 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
417 return gmbus3_mmio_write(vgpu, offset, p_data, bytes);
418
419 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
420 return 0;
421 }
422
423 enum {
424 AUX_CH_CTL = 0,
425 AUX_CH_DATA1,
426 AUX_CH_DATA2,
427 AUX_CH_DATA3,
428 AUX_CH_DATA4,
429 AUX_CH_DATA5
430 };
431
get_aux_ch_reg(unsigned int offset)432 static inline int get_aux_ch_reg(unsigned int offset)
433 {
434 int reg;
435
436 switch (offset & 0xff) {
437 case 0x10:
438 reg = AUX_CH_CTL;
439 break;
440 case 0x14:
441 reg = AUX_CH_DATA1;
442 break;
443 case 0x18:
444 reg = AUX_CH_DATA2;
445 break;
446 case 0x1c:
447 reg = AUX_CH_DATA3;
448 break;
449 case 0x20:
450 reg = AUX_CH_DATA4;
451 break;
452 case 0x24:
453 reg = AUX_CH_DATA5;
454 break;
455 default:
456 reg = -1;
457 break;
458 }
459 return reg;
460 }
461
462 #define AUX_CTL_MSG_LENGTH(reg) \
463 ((reg & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> \
464 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT)
465
466 /**
467 * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
468 * @vgpu: a vGPU
469 * @port_idx: port index
470 * @offset: reg offset
471 * @p_data: write ptr
472 *
473 * This function is used to emulate AUX channel register write
474 *
475 */
intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu * vgpu,int port_idx,unsigned int offset,void * p_data)476 void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
477 int port_idx,
478 unsigned int offset,
479 void *p_data)
480 {
481 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
482 int msg_length, ret_msg_size;
483 int msg, addr, ctrl, op;
484 u32 value = *(u32 *)p_data;
485 int aux_data_for_write = 0;
486 int reg = get_aux_ch_reg(offset);
487
488 if (reg != AUX_CH_CTL) {
489 vgpu_vreg(vgpu, offset) = value;
490 return;
491 }
492
493 msg_length = AUX_CTL_MSG_LENGTH(value);
494 // check the msg in DATA register.
495 msg = vgpu_vreg(vgpu, offset + 4);
496 addr = (msg >> 8) & 0xffff;
497 ctrl = (msg >> 24) & 0xff;
498 op = ctrl >> 4;
499 if (!(value & DP_AUX_CH_CTL_SEND_BUSY)) {
500 /* The ctl write to clear some states */
501 return;
502 }
503
504 /* Always set the wanted value for vms. */
505 ret_msg_size = (((op & 0x1) == GVT_AUX_I2C_READ) ? 2 : 1);
506 vgpu_vreg(vgpu, offset) =
507 DP_AUX_CH_CTL_DONE |
508 ((ret_msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) &
509 DP_AUX_CH_CTL_MESSAGE_SIZE_MASK);
510
511 if (msg_length == 3) {
512 if (!(op & GVT_AUX_I2C_MOT)) {
513 /* stop */
514 intel_vgpu_init_i2c_edid(vgpu);
515 } else {
516 /* start or restart */
517 i2c_edid->aux_ch.i2c_over_aux_ch = true;
518 i2c_edid->aux_ch.aux_ch_mot = true;
519 if (addr == 0) {
520 /* reset the address */
521 intel_vgpu_init_i2c_edid(vgpu);
522 } else if (addr == EDID_ADDR) {
523 i2c_edid->state = I2C_AUX_CH;
524 i2c_edid->port = port_idx;
525 i2c_edid->slave_selected = true;
526 if (intel_vgpu_has_monitor_on_port(vgpu,
527 port_idx) &&
528 intel_vgpu_port_is_dp(vgpu, port_idx))
529 i2c_edid->edid_available = true;
530 }
531 }
532 } else if ((op & 0x1) == GVT_AUX_I2C_WRITE) {
533 /* TODO
534 * We only support EDID reading from I2C_over_AUX. And
535 * we do not expect the index mode to be used. Right now
536 * the WRITE operation is ignored. It is good enough to
537 * support the gfx driver to do EDID access.
538 */
539 } else {
540 if (WARN_ON((op & 0x1) != GVT_AUX_I2C_READ))
541 return;
542 if (WARN_ON(msg_length != 4))
543 return;
544 if (i2c_edid->edid_available && i2c_edid->slave_selected) {
545 unsigned char val = edid_get_byte(vgpu);
546
547 aux_data_for_write = (val << 16);
548 } else
549 aux_data_for_write = (0xff << 16);
550 }
551 /* write the return value in AUX_CH_DATA reg which includes:
552 * ACK of I2C_WRITE
553 * returned byte if it is READ
554 */
555 aux_data_for_write |= GVT_AUX_I2C_REPLY_ACK << 24;
556 vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;
557 }
558
559 /**
560 * intel_vgpu_init_i2c_edid - initialize vGPU i2c edid emulation
561 * @vgpu: a vGPU
562 *
563 * This function is used to initialize vGPU i2c edid emulation stuffs
564 *
565 */
intel_vgpu_init_i2c_edid(struct intel_vgpu * vgpu)566 void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu)
567 {
568 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
569
570 edid->state = I2C_NOT_SPECIFIED;
571
572 edid->port = -1;
573 edid->slave_selected = false;
574 edid->edid_available = false;
575 edid->current_edid_read = 0;
576
577 memset(&edid->gmbus, 0, sizeof(struct intel_vgpu_i2c_gmbus));
578
579 edid->aux_ch.i2c_over_aux_ch = false;
580 edid->aux_ch.aux_ch_mot = false;
581 }
582