1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include "i915_drv.h"
7 #include "i915_irq.h"
8 #include "i915_reg.h"
9 #include "intel_backlight_regs.h"
10 #include "intel_combo_phy.h"
11 #include "intel_combo_phy_regs.h"
12 #include "intel_crt.h"
13 #include "intel_de.h"
14 #include "intel_display_irq.h"
15 #include "intel_display_power_well.h"
16 #include "intel_display_types.h"
17 #include "intel_dkl_phy.h"
18 #include "intel_dkl_phy_regs.h"
19 #include "intel_dmc.h"
20 #include "intel_dmc_wl.h"
21 #include "intel_dp_aux_regs.h"
22 #include "intel_dpio_phy.h"
23 #include "intel_dpll.h"
24 #include "intel_hotplug.h"
25 #include "intel_pcode.h"
26 #include "intel_pps.h"
27 #include "intel_tc.h"
28 #include "intel_vga.h"
29 #include "skl_watermark.h"
30 #include "vlv_dpio_phy_regs.h"
31 #include "vlv_sideband.h"
32 #include "vlv_sideband_reg.h"
33
34 struct i915_power_well_regs {
35 i915_reg_t bios;
36 i915_reg_t driver;
37 i915_reg_t kvmr;
38 i915_reg_t debug;
39 };
40
41 struct i915_power_well_ops {
42 const struct i915_power_well_regs *regs;
43 /*
44 * Synchronize the well's hw state to match the current sw state, for
45 * example enable/disable it based on the current refcount. Called
46 * during driver init and resume time, possibly after first calling
47 * the enable/disable handlers.
48 */
49 void (*sync_hw)(struct drm_i915_private *i915,
50 struct i915_power_well *power_well);
51 /*
52 * Enable the well and resources that depend on it (for example
53 * interrupts located on the well). Called after the 0->1 refcount
54 * transition.
55 */
56 void (*enable)(struct drm_i915_private *i915,
57 struct i915_power_well *power_well);
58 /*
59 * Disable the well and resources that depend on it. Called after
60 * the 1->0 refcount transition.
61 */
62 void (*disable)(struct drm_i915_private *i915,
63 struct i915_power_well *power_well);
64 /* Returns the hw enabled state. */
65 bool (*is_enabled)(struct drm_i915_private *i915,
66 struct i915_power_well *power_well);
67 };
68
69 static const struct i915_power_well_instance *
i915_power_well_instance(const struct i915_power_well * power_well)70 i915_power_well_instance(const struct i915_power_well *power_well)
71 {
72 return &power_well->desc->instances->list[power_well->instance_idx];
73 }
74
75 struct i915_power_well *
lookup_power_well(struct drm_i915_private * i915,enum i915_power_well_id power_well_id)76 lookup_power_well(struct drm_i915_private *i915,
77 enum i915_power_well_id power_well_id)
78 {
79 struct i915_power_well *power_well;
80
81 for_each_power_well(i915, power_well)
82 if (i915_power_well_instance(power_well)->id == power_well_id)
83 return power_well;
84
85 /*
86 * It's not feasible to add error checking code to the callers since
87 * this condition really shouldn't happen and it doesn't even make sense
88 * to abort things like display initialization sequences. Just return
89 * the first power well and hope the WARN gets reported so we can fix
90 * our driver.
91 */
92 drm_WARN(&i915->drm, 1,
93 "Power well %d not defined for this platform\n",
94 power_well_id);
95 return &i915->display.power.domains.power_wells[0];
96 }
97
intel_power_well_enable(struct drm_i915_private * i915,struct i915_power_well * power_well)98 void intel_power_well_enable(struct drm_i915_private *i915,
99 struct i915_power_well *power_well)
100 {
101 drm_dbg_kms(&i915->drm, "enabling %s\n", intel_power_well_name(power_well));
102 power_well->desc->ops->enable(i915, power_well);
103 power_well->hw_enabled = true;
104 }
105
intel_power_well_disable(struct drm_i915_private * i915,struct i915_power_well * power_well)106 void intel_power_well_disable(struct drm_i915_private *i915,
107 struct i915_power_well *power_well)
108 {
109 drm_dbg_kms(&i915->drm, "disabling %s\n", intel_power_well_name(power_well));
110 power_well->hw_enabled = false;
111 power_well->desc->ops->disable(i915, power_well);
112 }
113
intel_power_well_sync_hw(struct drm_i915_private * i915,struct i915_power_well * power_well)114 void intel_power_well_sync_hw(struct drm_i915_private *i915,
115 struct i915_power_well *power_well)
116 {
117 power_well->desc->ops->sync_hw(i915, power_well);
118 power_well->hw_enabled =
119 power_well->desc->ops->is_enabled(i915, power_well);
120 }
121
intel_power_well_get(struct drm_i915_private * i915,struct i915_power_well * power_well)122 void intel_power_well_get(struct drm_i915_private *i915,
123 struct i915_power_well *power_well)
124 {
125 if (!power_well->count++)
126 intel_power_well_enable(i915, power_well);
127 }
128
intel_power_well_put(struct drm_i915_private * i915,struct i915_power_well * power_well)129 void intel_power_well_put(struct drm_i915_private *i915,
130 struct i915_power_well *power_well)
131 {
132 drm_WARN(&i915->drm, !power_well->count,
133 "Use count on power well %s is already zero",
134 i915_power_well_instance(power_well)->name);
135
136 if (!--power_well->count)
137 intel_power_well_disable(i915, power_well);
138 }
139
intel_power_well_is_enabled(struct drm_i915_private * i915,struct i915_power_well * power_well)140 bool intel_power_well_is_enabled(struct drm_i915_private *i915,
141 struct i915_power_well *power_well)
142 {
143 return power_well->desc->ops->is_enabled(i915, power_well);
144 }
145
intel_power_well_is_enabled_cached(struct i915_power_well * power_well)146 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well)
147 {
148 return power_well->hw_enabled;
149 }
150
intel_display_power_well_is_enabled(struct drm_i915_private * dev_priv,enum i915_power_well_id power_well_id)151 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
152 enum i915_power_well_id power_well_id)
153 {
154 struct i915_power_well *power_well;
155
156 power_well = lookup_power_well(dev_priv, power_well_id);
157
158 return intel_power_well_is_enabled(dev_priv, power_well);
159 }
160
intel_power_well_is_always_on(struct i915_power_well * power_well)161 bool intel_power_well_is_always_on(struct i915_power_well *power_well)
162 {
163 return power_well->desc->always_on;
164 }
165
intel_power_well_name(struct i915_power_well * power_well)166 const char *intel_power_well_name(struct i915_power_well *power_well)
167 {
168 return i915_power_well_instance(power_well)->name;
169 }
170
intel_power_well_domains(struct i915_power_well * power_well)171 struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well)
172 {
173 return &power_well->domains;
174 }
175
intel_power_well_refcount(struct i915_power_well * power_well)176 int intel_power_well_refcount(struct i915_power_well *power_well)
177 {
178 return power_well->count;
179 }
180
181 /*
182 * Starting with Haswell, we have a "Power Down Well" that can be turned off
183 * when not needed anymore. We have 4 registers that can request the power well
184 * to be enabled, and it will only be disabled if none of the registers is
185 * requesting it to be enabled.
186 */
hsw_power_well_post_enable(struct drm_i915_private * dev_priv,u8 irq_pipe_mask,bool has_vga)187 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
188 u8 irq_pipe_mask, bool has_vga)
189 {
190 if (has_vga)
191 intel_vga_reset_io_mem(dev_priv);
192
193 if (irq_pipe_mask)
194 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
195 }
196
hsw_power_well_pre_disable(struct drm_i915_private * dev_priv,u8 irq_pipe_mask)197 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
198 u8 irq_pipe_mask)
199 {
200 if (irq_pipe_mask)
201 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
202 }
203
204 #define ICL_AUX_PW_TO_PHY(pw_idx) \
205 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + PHY_A)
206
207 #define ICL_AUX_PW_TO_CH(pw_idx) \
208 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
209
210 #define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
211 ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
212
icl_aux_pw_to_ch(const struct i915_power_well * power_well)213 static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well)
214 {
215 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
216
217 return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
218 ICL_AUX_PW_TO_CH(pw_idx);
219 }
220
221 static struct intel_digital_port *
aux_ch_to_digital_port(struct drm_i915_private * dev_priv,enum aux_ch aux_ch)222 aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
223 enum aux_ch aux_ch)
224 {
225 struct intel_encoder *encoder;
226
227 for_each_intel_encoder(&dev_priv->drm, encoder) {
228 struct intel_digital_port *dig_port;
229
230 /* We'll check the MST primary port */
231 if (encoder->type == INTEL_OUTPUT_DP_MST)
232 continue;
233
234 dig_port = enc_to_dig_port(encoder);
235
236 if (dig_port && dig_port->aux_ch == aux_ch)
237 return dig_port;
238 }
239
240 return NULL;
241 }
242
icl_aux_pw_to_phy(struct drm_i915_private * i915,const struct i915_power_well * power_well)243 static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915,
244 const struct i915_power_well *power_well)
245 {
246 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
247 struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch);
248
249 /*
250 * FIXME should we care about the (VBT defined) dig_port->aux_ch
251 * relationship or should this be purely defined by the hardware layout?
252 * Currently if the port doesn't appear in the VBT, or if it's declared
253 * as HDMI-only and routed to a combo PHY, the encoder either won't be
254 * present at all or it will not have an aux_ch assigned.
255 */
256 return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE;
257 }
258
hsw_wait_for_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well,bool timeout_expected)259 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
260 struct i915_power_well *power_well,
261 bool timeout_expected)
262 {
263 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
264 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
265 int timeout = power_well->desc->enable_timeout ? : 1;
266
267 /*
268 * For some power wells we're not supposed to watch the status bit for
269 * an ack, but rather just wait a fixed amount of time and then
270 * proceed. This is only used on DG2.
271 */
272 if (IS_DG2(dev_priv) && power_well->desc->fixed_enable_delay) {
273 usleep_range(600, 1200);
274 return;
275 }
276
277 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
278 if (intel_de_wait_for_set(dev_priv, regs->driver,
279 HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) {
280 drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n",
281 intel_power_well_name(power_well));
282
283 drm_WARN_ON(&dev_priv->drm, !timeout_expected);
284
285 }
286 }
287
hsw_power_well_requesters(struct drm_i915_private * dev_priv,const struct i915_power_well_regs * regs,int pw_idx)288 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
289 const struct i915_power_well_regs *regs,
290 int pw_idx)
291 {
292 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
293 u32 ret;
294
295 ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0;
296 ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0;
297 if (regs->kvmr.reg)
298 ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0;
299 ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0;
300
301 return ret;
302 }
303
hsw_wait_for_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)304 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
305 struct i915_power_well *power_well)
306 {
307 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
308 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
309 bool disabled;
310 u32 reqs;
311
312 /*
313 * Bspec doesn't require waiting for PWs to get disabled, but still do
314 * this for paranoia. The known cases where a PW will be forced on:
315 * - a KVMR request on any power well via the KVMR request register
316 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and
317 * DEBUG request registers
318 * Skip the wait in case any of the request bits are set and print a
319 * diagnostic message.
320 */
321 wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) &
322 HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
323 (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1);
324 if (disabled)
325 return;
326
327 drm_dbg_kms(&dev_priv->drm,
328 "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
329 intel_power_well_name(power_well),
330 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
331 }
332
gen9_wait_for_power_well_fuses(struct drm_i915_private * dev_priv,enum skl_power_gate pg)333 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
334 enum skl_power_gate pg)
335 {
336 /* Timeout 5us for PG#0, for other PGs 1us */
337 drm_WARN_ON(&dev_priv->drm,
338 intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS,
339 SKL_FUSE_PG_DIST_STATUS(pg), 1));
340 }
341
hsw_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)342 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
343 struct i915_power_well *power_well)
344 {
345 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
346 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
347
348 if (power_well->desc->has_fuses) {
349 enum skl_power_gate pg;
350
351 pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
352 SKL_PW_CTL_IDX_TO_PG(pw_idx);
353
354 /* Wa_16013190616:adlp */
355 if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1)
356 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC);
357
358 /*
359 * For PW1 we have to wait both for the PW0/PG0 fuse state
360 * before enabling the power well and PW1/PG1's own fuse
361 * state after the enabling. For all other power wells with
362 * fuses we only have to wait for that PW/PG's fuse state
363 * after the enabling.
364 */
365 if (pg == SKL_PG1)
366 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
367 }
368
369 intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx));
370
371 hsw_wait_for_power_well_enable(dev_priv, power_well, false);
372
373 if (power_well->desc->has_fuses) {
374 enum skl_power_gate pg;
375
376 pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
377 SKL_PW_CTL_IDX_TO_PG(pw_idx);
378 gen9_wait_for_power_well_fuses(dev_priv, pg);
379 }
380
381 hsw_power_well_post_enable(dev_priv,
382 power_well->desc->irq_pipe_mask,
383 power_well->desc->has_vga);
384 }
385
hsw_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)386 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
387 struct i915_power_well *power_well)
388 {
389 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
390 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
391
392 hsw_power_well_pre_disable(dev_priv,
393 power_well->desc->irq_pipe_mask);
394
395 intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0);
396 hsw_wait_for_power_well_disable(dev_priv, power_well);
397 }
398
intel_aux_ch_is_edp(struct drm_i915_private * i915,enum aux_ch aux_ch)399 static bool intel_aux_ch_is_edp(struct drm_i915_private *i915, enum aux_ch aux_ch)
400 {
401 struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch);
402
403 return dig_port && dig_port->base.type == INTEL_OUTPUT_EDP;
404 }
405
406 static void
icl_combo_phy_aux_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)407 icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
408 struct i915_power_well *power_well)
409 {
410 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
411 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
412
413 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
414
415 intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx));
416
417 /*
418 * FIXME not sure if we should derive the PHY from the pw_idx, or
419 * from the VBT defined AUX_CH->DDI->PHY mapping.
420 */
421 intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)),
422 0, ICL_LANE_ENABLE_AUX);
423
424 hsw_wait_for_power_well_enable(dev_priv, power_well, false);
425
426 /* Display WA #1178: icl */
427 if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
428 !intel_aux_ch_is_edp(dev_priv, ICL_AUX_PW_TO_CH(pw_idx)))
429 intel_de_rmw(dev_priv, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)),
430 0, O_FUNC_OVRD_EN | O_LDO_BYPASS_CRI);
431 }
432
433 static void
icl_combo_phy_aux_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)434 icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
435 struct i915_power_well *power_well)
436 {
437 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
438 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
439
440 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
441
442 /*
443 * FIXME not sure if we should derive the PHY from the pw_idx, or
444 * from the VBT defined AUX_CH->DDI->PHY mapping.
445 */
446 intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)),
447 ICL_LANE_ENABLE_AUX, 0);
448
449 intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0);
450
451 hsw_wait_for_power_well_disable(dev_priv, power_well);
452 }
453
454 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
455
icl_tc_port_assert_ref_held(struct drm_i915_private * dev_priv,struct i915_power_well * power_well,struct intel_digital_port * dig_port)456 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
457 struct i915_power_well *power_well,
458 struct intel_digital_port *dig_port)
459 {
460 if (drm_WARN_ON(&dev_priv->drm, !dig_port))
461 return;
462
463 if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
464 return;
465
466 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
467 }
468
469 #else
470
icl_tc_port_assert_ref_held(struct drm_i915_private * dev_priv,struct i915_power_well * power_well,struct intel_digital_port * dig_port)471 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
472 struct i915_power_well *power_well,
473 struct intel_digital_port *dig_port)
474 {
475 }
476
477 #endif
478
479 #define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1)
480
icl_tc_cold_exit(struct drm_i915_private * i915)481 static void icl_tc_cold_exit(struct drm_i915_private *i915)
482 {
483 int ret, tries = 0;
484
485 while (1) {
486 ret = snb_pcode_write_timeout(&i915->uncore, ICL_PCODE_EXIT_TCCOLD, 0,
487 250, 1);
488 if (ret != -EAGAIN || ++tries == 3)
489 break;
490 msleep(1);
491 }
492
493 /* Spec states that TC cold exit can take up to 1ms to complete */
494 if (!ret)
495 msleep(1);
496
497 /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */
498 drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" :
499 "succeeded");
500 }
501
502 static void
icl_tc_phy_aux_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)503 icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
504 struct i915_power_well *power_well)
505 {
506 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
507 struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
508 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
509 bool is_tbt = power_well->desc->is_tc_tbt;
510 bool timeout_expected;
511
512 icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
513
514 intel_de_rmw(dev_priv, DP_AUX_CH_CTL(aux_ch),
515 DP_AUX_CH_CTL_TBT_IO, is_tbt ? DP_AUX_CH_CTL_TBT_IO : 0);
516
517 intel_de_rmw(dev_priv, regs->driver,
518 0,
519 HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx));
520
521 /*
522 * An AUX timeout is expected if the TBT DP tunnel is down,
523 * or need to enable AUX on a legacy TypeC port as part of the TC-cold
524 * exit sequence.
525 */
526 timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port);
527 if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
528 icl_tc_cold_exit(dev_priv);
529
530 hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected);
531
532 if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) {
533 enum tc_port tc_port;
534
535 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx);
536
537 if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) &
538 DKL_CMN_UC_DW27_UC_HEALTH, 1))
539 drm_warn(&dev_priv->drm,
540 "Timeout waiting TC uC health\n");
541 }
542 }
543
544 static void
icl_aux_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)545 icl_aux_power_well_enable(struct drm_i915_private *dev_priv,
546 struct i915_power_well *power_well)
547 {
548 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
549
550 if (intel_phy_is_tc(dev_priv, phy))
551 return icl_tc_phy_aux_power_well_enable(dev_priv, power_well);
552 else if (IS_ICELAKE(dev_priv))
553 return icl_combo_phy_aux_power_well_enable(dev_priv,
554 power_well);
555 else
556 return hsw_power_well_enable(dev_priv, power_well);
557 }
558
559 static void
icl_aux_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)560 icl_aux_power_well_disable(struct drm_i915_private *dev_priv,
561 struct i915_power_well *power_well)
562 {
563 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
564
565 if (intel_phy_is_tc(dev_priv, phy))
566 return hsw_power_well_disable(dev_priv, power_well);
567 else if (IS_ICELAKE(dev_priv))
568 return icl_combo_phy_aux_power_well_disable(dev_priv,
569 power_well);
570 else
571 return hsw_power_well_disable(dev_priv, power_well);
572 }
573
574 /*
575 * We should only use the power well if we explicitly asked the hardware to
576 * enable it, so check if it's enabled and also check if we've requested it to
577 * be enabled.
578 */
hsw_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)579 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
580 struct i915_power_well *power_well)
581 {
582 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
583 enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
584 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
585 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
586 HSW_PWR_WELL_CTL_STATE(pw_idx);
587 u32 val;
588
589 val = intel_de_read(dev_priv, regs->driver);
590
591 /*
592 * On GEN9 big core due to a DMC bug the driver's request bits for PW1
593 * and the MISC_IO PW will be not restored, so check instead for the
594 * BIOS's own request bits, which are forced-on for these power wells
595 * when exiting DC5/6.
596 */
597 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
598 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
599 val |= intel_de_read(dev_priv, regs->bios);
600
601 return (val & mask) == mask;
602 }
603
assert_can_enable_dc9(struct drm_i915_private * dev_priv)604 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
605 {
606 drm_WARN_ONCE(&dev_priv->drm,
607 (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9),
608 "DC9 already programmed to be enabled.\n");
609 drm_WARN_ONCE(&dev_priv->drm,
610 intel_de_read(dev_priv, DC_STATE_EN) &
611 DC_STATE_EN_UPTO_DC5,
612 "DC5 still not disabled to enable DC9.\n");
613 drm_WARN_ONCE(&dev_priv->drm,
614 intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) &
615 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
616 "Power well 2 on.\n");
617 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
618 "Interrupts not disabled yet.\n");
619
620 /*
621 * TODO: check for the following to verify the conditions to enter DC9
622 * state are satisfied:
623 * 1] Check relevant display engine registers to verify if mode set
624 * disable sequence was followed.
625 * 2] Check if display uninitialize sequence is initialized.
626 */
627 }
628
assert_can_disable_dc9(struct drm_i915_private * dev_priv)629 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
630 {
631 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
632 "Interrupts not disabled yet.\n");
633 drm_WARN_ONCE(&dev_priv->drm,
634 intel_de_read(dev_priv, DC_STATE_EN) &
635 DC_STATE_EN_UPTO_DC5,
636 "DC5 still not disabled.\n");
637
638 /*
639 * TODO: check for the following to verify DC9 state was indeed
640 * entered before programming to disable it:
641 * 1] Check relevant display engine registers to verify if mode
642 * set disable sequence was followed.
643 * 2] Check if display uninitialize sequence is initialized.
644 */
645 }
646
gen9_write_dc_state(struct drm_i915_private * dev_priv,u32 state)647 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
648 u32 state)
649 {
650 int rewrites = 0;
651 int rereads = 0;
652 u32 v;
653
654 intel_de_write(dev_priv, DC_STATE_EN, state);
655
656 /* It has been observed that disabling the dc6 state sometimes
657 * doesn't stick and dmc keeps returning old value. Make sure
658 * the write really sticks enough times and also force rewrite until
659 * we are confident that state is exactly what we want.
660 */
661 do {
662 v = intel_de_read(dev_priv, DC_STATE_EN);
663
664 if (v != state) {
665 intel_de_write(dev_priv, DC_STATE_EN, state);
666 rewrites++;
667 rereads = 0;
668 } else if (rereads++ > 5) {
669 break;
670 }
671
672 } while (rewrites < 100);
673
674 if (v != state)
675 drm_err(&dev_priv->drm,
676 "Writing dc state to 0x%x failed, now 0x%x\n",
677 state, v);
678
679 /* Most of the times we need one retry, avoid spam */
680 if (rewrites > 1)
681 drm_dbg_kms(&dev_priv->drm,
682 "Rewrote dc state to 0x%x %d times\n",
683 state, rewrites);
684 }
685
gen9_dc_mask(struct drm_i915_private * dev_priv)686 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
687 {
688 u32 mask;
689
690 mask = DC_STATE_EN_UPTO_DC5;
691
692 if (DISPLAY_VER(dev_priv) >= 12)
693 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
694 | DC_STATE_EN_DC9;
695 else if (DISPLAY_VER(dev_priv) == 11)
696 mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
697 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
698 mask |= DC_STATE_EN_DC9;
699 else
700 mask |= DC_STATE_EN_UPTO_DC6;
701
702 return mask;
703 }
704
gen9_sanitize_dc_state(struct drm_i915_private * i915)705 void gen9_sanitize_dc_state(struct drm_i915_private *i915)
706 {
707 struct i915_power_domains *power_domains = &i915->display.power.domains;
708 u32 val;
709
710 if (!HAS_DISPLAY(i915))
711 return;
712
713 val = intel_de_read(i915, DC_STATE_EN) & gen9_dc_mask(i915);
714
715 drm_dbg_kms(&i915->drm,
716 "Resetting DC state tracking from %02x to %02x\n",
717 power_domains->dc_state, val);
718 power_domains->dc_state = val;
719 }
720
721 /**
722 * gen9_set_dc_state - set target display C power state
723 * @dev_priv: i915 device instance
724 * @state: target DC power state
725 * - DC_STATE_DISABLE
726 * - DC_STATE_EN_UPTO_DC5
727 * - DC_STATE_EN_UPTO_DC6
728 * - DC_STATE_EN_DC9
729 *
730 * Signal to DMC firmware/HW the target DC power state passed in @state.
731 * DMC/HW can turn off individual display clocks and power rails when entering
732 * a deeper DC power state (higher in number) and turns these back when exiting
733 * that state to a shallower power state (lower in number). The HW will decide
734 * when to actually enter a given state on an on-demand basis, for instance
735 * depending on the active state of display pipes. The state of display
736 * registers backed by affected power rails are saved/restored as needed.
737 *
738 * Based on the above enabling a deeper DC power state is asynchronous wrt.
739 * enabling it. Disabling a deeper power state is synchronous: for instance
740 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned
741 * back on and register state is restored. This is guaranteed by the MMIO write
742 * to DC_STATE_EN blocking until the state is restored.
743 */
gen9_set_dc_state(struct drm_i915_private * dev_priv,u32 state)744 void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
745 {
746 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
747 u32 val;
748 u32 mask;
749
750 if (!HAS_DISPLAY(dev_priv))
751 return;
752
753 if (drm_WARN_ON_ONCE(&dev_priv->drm,
754 state & ~power_domains->allowed_dc_mask))
755 state &= power_domains->allowed_dc_mask;
756
757 val = intel_de_read(dev_priv, DC_STATE_EN);
758 mask = gen9_dc_mask(dev_priv);
759 drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to %02x\n",
760 val & mask, state);
761
762 /* Check if DMC is ignoring our DC state requests */
763 if ((val & mask) != power_domains->dc_state)
764 drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
765 power_domains->dc_state, val & mask);
766
767 val &= ~mask;
768 val |= state;
769
770 gen9_write_dc_state(dev_priv, val);
771
772 power_domains->dc_state = val & mask;
773 }
774
tgl_enable_dc3co(struct drm_i915_private * dev_priv)775 static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
776 {
777 drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n");
778 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
779 }
780
tgl_disable_dc3co(struct drm_i915_private * dev_priv)781 static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
782 {
783 drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n");
784 intel_de_rmw(dev_priv, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0);
785 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
786 /*
787 * Delay of 200us DC3CO Exit time B.Spec 49196
788 */
789 usleep_range(200, 210);
790 }
791
assert_can_enable_dc5(struct drm_i915_private * dev_priv)792 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
793 {
794 enum i915_power_well_id high_pg;
795
796 /* Power wells at this level and above must be disabled for DC5 entry */
797 if (DISPLAY_VER(dev_priv) == 12)
798 high_pg = ICL_DISP_PW_3;
799 else
800 high_pg = SKL_DISP_PW_2;
801
802 drm_WARN_ONCE(&dev_priv->drm,
803 intel_display_power_well_is_enabled(dev_priv, high_pg),
804 "Power wells above platform's DC5 limit still enabled.\n");
805
806 drm_WARN_ONCE(&dev_priv->drm,
807 (intel_de_read(dev_priv, DC_STATE_EN) &
808 DC_STATE_EN_UPTO_DC5),
809 "DC5 already programmed to be enabled.\n");
810 assert_rpm_wakelock_held(&dev_priv->runtime_pm);
811
812 assert_dmc_loaded(dev_priv);
813 }
814
gen9_enable_dc5(struct drm_i915_private * dev_priv)815 void gen9_enable_dc5(struct drm_i915_private *dev_priv)
816 {
817 assert_can_enable_dc5(dev_priv);
818
819 drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n");
820
821 /* Wa Display #1183: skl,kbl,cfl */
822 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
823 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
824 0, SKL_SELECT_ALTERNATE_DC_EXIT);
825
826 intel_dmc_wl_enable(&dev_priv->display);
827
828 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
829 }
830
assert_can_enable_dc6(struct drm_i915_private * dev_priv)831 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
832 {
833 drm_WARN_ONCE(&dev_priv->drm,
834 (intel_de_read(dev_priv, UTIL_PIN_CTL) &
835 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) ==
836 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),
837 "Utility pin enabled in PWM mode\n");
838 drm_WARN_ONCE(&dev_priv->drm,
839 (intel_de_read(dev_priv, DC_STATE_EN) &
840 DC_STATE_EN_UPTO_DC6),
841 "DC6 already programmed to be enabled.\n");
842
843 assert_dmc_loaded(dev_priv);
844 }
845
skl_enable_dc6(struct drm_i915_private * dev_priv)846 void skl_enable_dc6(struct drm_i915_private *dev_priv)
847 {
848 assert_can_enable_dc6(dev_priv);
849
850 drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n");
851
852 /* Wa Display #1183: skl,kbl,cfl */
853 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
854 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
855 0, SKL_SELECT_ALTERNATE_DC_EXIT);
856
857 intel_dmc_wl_enable(&dev_priv->display);
858
859 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
860 }
861
bxt_enable_dc9(struct drm_i915_private * dev_priv)862 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
863 {
864 assert_can_enable_dc9(dev_priv);
865
866 drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n");
867 /*
868 * Power sequencer reset is not needed on
869 * platforms with South Display Engine on PCH,
870 * because PPS registers are always on.
871 */
872 if (!HAS_PCH_SPLIT(dev_priv))
873 intel_pps_reset_all(dev_priv);
874 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
875 }
876
bxt_disable_dc9(struct drm_i915_private * dev_priv)877 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
878 {
879 assert_can_disable_dc9(dev_priv);
880
881 drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n");
882
883 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
884
885 intel_pps_unlock_regs_wa(dev_priv);
886 }
887
hsw_power_well_sync_hw(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)888 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
889 struct i915_power_well *power_well)
890 {
891 const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
892 int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
893 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
894 u32 bios_req = intel_de_read(dev_priv, regs->bios);
895
896 /* Take over the request bit if set by BIOS. */
897 if (bios_req & mask) {
898 u32 drv_req = intel_de_read(dev_priv, regs->driver);
899
900 if (!(drv_req & mask))
901 intel_de_write(dev_priv, regs->driver, drv_req | mask);
902 intel_de_write(dev_priv, regs->bios, bios_req & ~mask);
903 }
904 }
905
bxt_dpio_cmn_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)906 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
907 struct i915_power_well *power_well)
908 {
909 bxt_dpio_phy_init(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
910 }
911
bxt_dpio_cmn_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)912 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
913 struct i915_power_well *power_well)
914 {
915 bxt_dpio_phy_uninit(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
916 }
917
bxt_dpio_cmn_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)918 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
919 struct i915_power_well *power_well)
920 {
921 return bxt_dpio_phy_is_enabled(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
922 }
923
bxt_verify_dpio_phy_power_wells(struct drm_i915_private * dev_priv)924 static void bxt_verify_dpio_phy_power_wells(struct drm_i915_private *dev_priv)
925 {
926 struct i915_power_well *power_well;
927
928 power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
929 if (intel_power_well_refcount(power_well) > 0)
930 bxt_dpio_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
931
932 power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
933 if (intel_power_well_refcount(power_well) > 0)
934 bxt_dpio_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
935
936 if (IS_GEMINILAKE(dev_priv)) {
937 power_well = lookup_power_well(dev_priv,
938 GLK_DISP_PW_DPIO_CMN_C);
939 if (intel_power_well_refcount(power_well) > 0)
940 bxt_dpio_phy_verify_state(dev_priv,
941 i915_power_well_instance(power_well)->bxt.phy);
942 }
943 }
944
gen9_dc_off_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)945 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
946 struct i915_power_well *power_well)
947 {
948 return ((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
949 (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
950 }
951
gen9_assert_dbuf_enabled(struct drm_i915_private * dev_priv)952 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
953 {
954 u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv);
955 u8 enabled_dbuf_slices = dev_priv->display.dbuf.enabled_slices;
956
957 drm_WARN(&dev_priv->drm,
958 hw_enabled_dbuf_slices != enabled_dbuf_slices,
959 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n",
960 hw_enabled_dbuf_slices,
961 enabled_dbuf_slices);
962 }
963
gen9_disable_dc_states(struct drm_i915_private * dev_priv)964 void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
965 {
966 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
967 struct intel_cdclk_config cdclk_config = {};
968
969 if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) {
970 tgl_disable_dc3co(dev_priv);
971 return;
972 }
973
974 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
975
976 if (!HAS_DISPLAY(dev_priv))
977 return;
978
979 intel_dmc_wl_disable(&dev_priv->display);
980
981 intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
982 /* Can't read out voltage_level so can't use intel_cdclk_changed() */
983 drm_WARN_ON(&dev_priv->drm,
984 intel_cdclk_clock_changed(&dev_priv->display.cdclk.hw,
985 &cdclk_config));
986
987 gen9_assert_dbuf_enabled(dev_priv);
988
989 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
990 bxt_verify_dpio_phy_power_wells(dev_priv);
991
992 if (DISPLAY_VER(dev_priv) >= 11)
993 /*
994 * DMC retains HW context only for port A, the other combo
995 * PHY's HW context for port B is lost after DC transitions,
996 * so we need to restore it manually.
997 */
998 intel_combo_phy_init(dev_priv);
999 }
1000
gen9_dc_off_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1001 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
1002 struct i915_power_well *power_well)
1003 {
1004 gen9_disable_dc_states(dev_priv);
1005 }
1006
gen9_dc_off_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1007 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
1008 struct i915_power_well *power_well)
1009 {
1010 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1011
1012 if (!intel_dmc_has_payload(dev_priv))
1013 return;
1014
1015 switch (power_domains->target_dc_state) {
1016 case DC_STATE_EN_DC3CO:
1017 tgl_enable_dc3co(dev_priv);
1018 break;
1019 case DC_STATE_EN_UPTO_DC6:
1020 skl_enable_dc6(dev_priv);
1021 break;
1022 case DC_STATE_EN_UPTO_DC5:
1023 gen9_enable_dc5(dev_priv);
1024 break;
1025 }
1026 }
1027
i9xx_power_well_sync_hw_noop(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1028 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
1029 struct i915_power_well *power_well)
1030 {
1031 }
1032
i9xx_always_on_power_well_noop(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1033 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
1034 struct i915_power_well *power_well)
1035 {
1036 }
1037
i9xx_always_on_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1038 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
1039 struct i915_power_well *power_well)
1040 {
1041 return true;
1042 }
1043
i830_pipes_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1044 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
1045 struct i915_power_well *power_well)
1046 {
1047 if ((intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE) == 0)
1048 i830_enable_pipe(dev_priv, PIPE_A);
1049 if ((intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE) == 0)
1050 i830_enable_pipe(dev_priv, PIPE_B);
1051 }
1052
i830_pipes_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1053 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
1054 struct i915_power_well *power_well)
1055 {
1056 i830_disable_pipe(dev_priv, PIPE_B);
1057 i830_disable_pipe(dev_priv, PIPE_A);
1058 }
1059
i830_pipes_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1060 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
1061 struct i915_power_well *power_well)
1062 {
1063 return intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE &&
1064 intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
1065 }
1066
i830_pipes_power_well_sync_hw(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1067 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
1068 struct i915_power_well *power_well)
1069 {
1070 if (intel_power_well_refcount(power_well) > 0)
1071 i830_pipes_power_well_enable(dev_priv, power_well);
1072 else
1073 i830_pipes_power_well_disable(dev_priv, power_well);
1074 }
1075
vlv_set_power_well(struct drm_i915_private * dev_priv,struct i915_power_well * power_well,bool enable)1076 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
1077 struct i915_power_well *power_well, bool enable)
1078 {
1079 int pw_idx = i915_power_well_instance(power_well)->vlv.idx;
1080 u32 mask;
1081 u32 state;
1082 u32 ctrl;
1083
1084 mask = PUNIT_PWRGT_MASK(pw_idx);
1085 state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
1086 PUNIT_PWRGT_PWR_GATE(pw_idx);
1087
1088 vlv_punit_get(dev_priv);
1089
1090 #define COND \
1091 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
1092
1093 if (COND)
1094 goto out;
1095
1096 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
1097 ctrl &= ~mask;
1098 ctrl |= state;
1099 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
1100
1101 if (wait_for(COND, 100))
1102 drm_err(&dev_priv->drm,
1103 "timeout setting power well state %08x (%08x)\n",
1104 state,
1105 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
1106
1107 #undef COND
1108
1109 out:
1110 vlv_punit_put(dev_priv);
1111 }
1112
vlv_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1113 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
1114 struct i915_power_well *power_well)
1115 {
1116 vlv_set_power_well(dev_priv, power_well, true);
1117 }
1118
vlv_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1119 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
1120 struct i915_power_well *power_well)
1121 {
1122 vlv_set_power_well(dev_priv, power_well, false);
1123 }
1124
vlv_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1125 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
1126 struct i915_power_well *power_well)
1127 {
1128 int pw_idx = i915_power_well_instance(power_well)->vlv.idx;
1129 bool enabled = false;
1130 u32 mask;
1131 u32 state;
1132 u32 ctrl;
1133
1134 mask = PUNIT_PWRGT_MASK(pw_idx);
1135 ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
1136
1137 vlv_punit_get(dev_priv);
1138
1139 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
1140 /*
1141 * We only ever set the power-on and power-gate states, anything
1142 * else is unexpected.
1143 */
1144 drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) &&
1145 state != PUNIT_PWRGT_PWR_GATE(pw_idx));
1146 if (state == ctrl)
1147 enabled = true;
1148
1149 /*
1150 * A transient state at this point would mean some unexpected party
1151 * is poking at the power controls too.
1152 */
1153 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
1154 drm_WARN_ON(&dev_priv->drm, ctrl != state);
1155
1156 vlv_punit_put(dev_priv);
1157
1158 return enabled;
1159 }
1160
vlv_init_display_clock_gating(struct drm_i915_private * dev_priv)1161 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
1162 {
1163 /*
1164 * On driver load, a pipe may be active and driving a DSI display.
1165 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
1166 * (and never recovering) in this case. intel_dsi_post_disable() will
1167 * clear it when we turn off the display.
1168 */
1169 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv),
1170 ~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE);
1171
1172 /*
1173 * Disable trickle feed and enable pnd deadline calculation
1174 */
1175 intel_de_write(dev_priv, MI_ARB_VLV,
1176 MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
1177 intel_de_write(dev_priv, CBR1_VLV, 0);
1178
1179 drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
1180 intel_de_write(dev_priv, RAWCLK_FREQ_VLV,
1181 DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq,
1182 1000));
1183 }
1184
vlv_display_power_well_init(struct drm_i915_private * dev_priv)1185 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
1186 {
1187 struct intel_encoder *encoder;
1188 enum pipe pipe;
1189
1190 /*
1191 * Enable the CRI clock source so we can get at the
1192 * display and the reference clock for VGA
1193 * hotplug / manual detection. Supposedly DSI also
1194 * needs the ref clock up and running.
1195 *
1196 * CHV DPLL B/C have some issues if VGA mode is enabled.
1197 */
1198 for_each_pipe(dev_priv, pipe) {
1199 u32 val = intel_de_read(dev_priv, DPLL(pipe));
1200
1201 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1202 if (pipe != PIPE_A)
1203 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1204
1205 intel_de_write(dev_priv, DPLL(pipe), val);
1206 }
1207
1208 vlv_init_display_clock_gating(dev_priv);
1209
1210 spin_lock_irq(&dev_priv->irq_lock);
1211 valleyview_enable_display_irqs(dev_priv);
1212 spin_unlock_irq(&dev_priv->irq_lock);
1213
1214 /*
1215 * During driver initialization/resume we can avoid restoring the
1216 * part of the HW/SW state that will be inited anyway explicitly.
1217 */
1218 if (dev_priv->display.power.domains.initializing)
1219 return;
1220
1221 intel_hpd_init(dev_priv);
1222 intel_hpd_poll_disable(dev_priv);
1223
1224 /* Re-enable the ADPA, if we have one */
1225 for_each_intel_encoder(&dev_priv->drm, encoder) {
1226 if (encoder->type == INTEL_OUTPUT_ANALOG)
1227 intel_crt_reset(&encoder->base);
1228 }
1229
1230 intel_vga_redisable_power_on(dev_priv);
1231
1232 intel_pps_unlock_regs_wa(dev_priv);
1233 }
1234
vlv_display_power_well_deinit(struct drm_i915_private * dev_priv)1235 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1236 {
1237 spin_lock_irq(&dev_priv->irq_lock);
1238 valleyview_disable_display_irqs(dev_priv);
1239 spin_unlock_irq(&dev_priv->irq_lock);
1240
1241 /* make sure we're done processing display irqs */
1242 intel_synchronize_irq(dev_priv);
1243
1244 intel_pps_reset_all(dev_priv);
1245
1246 /* Prevent us from re-enabling polling on accident in late suspend */
1247 if (!dev_priv->drm.dev->power.is_suspended)
1248 intel_hpd_poll_enable(dev_priv);
1249 }
1250
vlv_display_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1251 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1252 struct i915_power_well *power_well)
1253 {
1254 vlv_set_power_well(dev_priv, power_well, true);
1255
1256 vlv_display_power_well_init(dev_priv);
1257 }
1258
vlv_display_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1259 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1260 struct i915_power_well *power_well)
1261 {
1262 vlv_display_power_well_deinit(dev_priv);
1263
1264 vlv_set_power_well(dev_priv, power_well, false);
1265 }
1266
vlv_dpio_cmn_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1267 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1268 struct i915_power_well *power_well)
1269 {
1270 /* since ref/cri clock was enabled */
1271 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1272
1273 vlv_set_power_well(dev_priv, power_well, true);
1274
1275 /*
1276 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1277 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1278 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1279 * b. The other bits such as sfr settings / modesel may all
1280 * be set to 0.
1281 *
1282 * This should only be done on init and resume from S3 with
1283 * both PLLs disabled, or we risk losing DPIO and PLL
1284 * synchronization.
1285 */
1286 intel_de_rmw(dev_priv, DPIO_CTL, 0, DPIO_CMNRST);
1287 }
1288
vlv_dpio_cmn_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1289 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1290 struct i915_power_well *power_well)
1291 {
1292 enum pipe pipe;
1293
1294 for_each_pipe(dev_priv, pipe)
1295 assert_pll_disabled(dev_priv, pipe);
1296
1297 /* Assert common reset */
1298 intel_de_rmw(dev_priv, DPIO_CTL, DPIO_CMNRST, 0);
1299
1300 vlv_set_power_well(dev_priv, power_well, false);
1301 }
1302
1303 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1304
assert_chv_phy_status(struct drm_i915_private * dev_priv)1305 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1306 {
1307 struct i915_power_well *cmn_bc =
1308 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1309 struct i915_power_well *cmn_d =
1310 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
1311 u32 phy_control = dev_priv->display.power.chv_phy_control;
1312 u32 phy_status = 0;
1313 u32 phy_status_mask = 0xffffffff;
1314
1315 /*
1316 * The BIOS can leave the PHY is some weird state
1317 * where it doesn't fully power down some parts.
1318 * Disable the asserts until the PHY has been fully
1319 * reset (ie. the power well has been disabled at
1320 * least once).
1321 */
1322 if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0])
1323 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1324 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1325 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1326 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1327 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1328 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1329
1330 if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1])
1331 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1332 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1333 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1334
1335 if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
1336 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1337
1338 /* this assumes override is only used to enable lanes */
1339 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1340 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1341
1342 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1343 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1344
1345 /* CL1 is on whenever anything is on in either channel */
1346 if (BITS_SET(phy_control,
1347 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1348 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1349 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1350
1351 /*
1352 * The DPLLB check accounts for the pipe B + port A usage
1353 * with CL2 powered up but all the lanes in the second channel
1354 * powered down.
1355 */
1356 if (BITS_SET(phy_control,
1357 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1358 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1359 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1360
1361 if (BITS_SET(phy_control,
1362 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1363 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1364 if (BITS_SET(phy_control,
1365 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1366 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1367
1368 if (BITS_SET(phy_control,
1369 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1370 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1371 if (BITS_SET(phy_control,
1372 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1373 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1374 }
1375
1376 if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
1377 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1378
1379 /* this assumes override is only used to enable lanes */
1380 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1381 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1382
1383 if (BITS_SET(phy_control,
1384 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1385 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1386
1387 if (BITS_SET(phy_control,
1388 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1389 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1390 if (BITS_SET(phy_control,
1391 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1392 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1393 }
1394
1395 phy_status &= phy_status_mask;
1396
1397 /*
1398 * The PHY may be busy with some initial calibration and whatnot,
1399 * so the power state can take a while to actually change.
1400 */
1401 if (intel_de_wait(dev_priv, DISPLAY_PHY_STATUS,
1402 phy_status_mask, phy_status, 10))
1403 drm_err(&dev_priv->drm,
1404 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1405 intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,
1406 phy_status, dev_priv->display.power.chv_phy_control);
1407 }
1408
1409 #undef BITS_SET
1410
chv_dpio_cmn_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1411 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1412 struct i915_power_well *power_well)
1413 {
1414 enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
1415 enum dpio_phy phy;
1416 u32 tmp;
1417
1418 drm_WARN_ON_ONCE(&dev_priv->drm,
1419 id != VLV_DISP_PW_DPIO_CMN_BC &&
1420 id != CHV_DISP_PW_DPIO_CMN_D);
1421
1422 if (id == VLV_DISP_PW_DPIO_CMN_BC)
1423 phy = DPIO_PHY0;
1424 else
1425 phy = DPIO_PHY1;
1426
1427 /* since ref/cri clock was enabled */
1428 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1429 vlv_set_power_well(dev_priv, power_well, true);
1430
1431 /* Poll for phypwrgood signal */
1432 if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS,
1433 PHY_POWERGOOD(phy), 1))
1434 drm_err(&dev_priv->drm, "Display PHY %d is not power up\n",
1435 phy);
1436
1437 vlv_dpio_get(dev_priv);
1438
1439 /* Enable dynamic power down */
1440 tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW28);
1441 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1442 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1443 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW28, tmp);
1444
1445 if (id == VLV_DISP_PW_DPIO_CMN_BC) {
1446 tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW6_CH1);
1447 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1448 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW6_CH1, tmp);
1449 } else {
1450 /*
1451 * Force the non-existing CL2 off. BXT does this
1452 * too, so maybe it saves some power even though
1453 * CL2 doesn't exist?
1454 */
1455 tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW30);
1456 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1457 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW30, tmp);
1458 }
1459
1460 vlv_dpio_put(dev_priv);
1461
1462 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1463 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1464 dev_priv->display.power.chv_phy_control);
1465
1466 drm_dbg_kms(&dev_priv->drm,
1467 "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1468 phy, dev_priv->display.power.chv_phy_control);
1469
1470 assert_chv_phy_status(dev_priv);
1471 }
1472
chv_dpio_cmn_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1473 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1474 struct i915_power_well *power_well)
1475 {
1476 enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
1477 enum dpio_phy phy;
1478
1479 drm_WARN_ON_ONCE(&dev_priv->drm,
1480 id != VLV_DISP_PW_DPIO_CMN_BC &&
1481 id != CHV_DISP_PW_DPIO_CMN_D);
1482
1483 if (id == VLV_DISP_PW_DPIO_CMN_BC) {
1484 phy = DPIO_PHY0;
1485 assert_pll_disabled(dev_priv, PIPE_A);
1486 assert_pll_disabled(dev_priv, PIPE_B);
1487 } else {
1488 phy = DPIO_PHY1;
1489 assert_pll_disabled(dev_priv, PIPE_C);
1490 }
1491
1492 dev_priv->display.power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1493 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1494 dev_priv->display.power.chv_phy_control);
1495
1496 vlv_set_power_well(dev_priv, power_well, false);
1497
1498 drm_dbg_kms(&dev_priv->drm,
1499 "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1500 phy, dev_priv->display.power.chv_phy_control);
1501
1502 /* PHY is fully reset now, so we can enable the PHY state asserts */
1503 dev_priv->display.power.chv_phy_assert[phy] = true;
1504
1505 assert_chv_phy_status(dev_priv);
1506 }
1507
assert_chv_phy_powergate(struct drm_i915_private * dev_priv,enum dpio_phy phy,enum dpio_channel ch,bool override,unsigned int mask)1508 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1509 enum dpio_channel ch, bool override, unsigned int mask)
1510 {
1511 u32 reg, val, expected, actual;
1512
1513 /*
1514 * The BIOS can leave the PHY is some weird state
1515 * where it doesn't fully power down some parts.
1516 * Disable the asserts until the PHY has been fully
1517 * reset (ie. the power well has been disabled at
1518 * least once).
1519 */
1520 if (!dev_priv->display.power.chv_phy_assert[phy])
1521 return;
1522
1523 if (ch == DPIO_CH0)
1524 reg = CHV_CMN_DW0_CH0;
1525 else
1526 reg = CHV_CMN_DW6_CH1;
1527
1528 vlv_dpio_get(dev_priv);
1529 val = vlv_dpio_read(dev_priv, phy, reg);
1530 vlv_dpio_put(dev_priv);
1531
1532 /*
1533 * This assumes !override is only used when the port is disabled.
1534 * All lanes should power down even without the override when
1535 * the port is disabled.
1536 */
1537 if (!override || mask == 0xf) {
1538 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1539 /*
1540 * If CH1 common lane is not active anymore
1541 * (eg. for pipe B DPLL) the entire channel will
1542 * shut down, which causes the common lane registers
1543 * to read as 0. That means we can't actually check
1544 * the lane power down status bits, but as the entire
1545 * register reads as 0 it's a good indication that the
1546 * channel is indeed entirely powered down.
1547 */
1548 if (ch == DPIO_CH1 && val == 0)
1549 expected = 0;
1550 } else if (mask != 0x0) {
1551 expected = DPIO_ANYDL_POWERDOWN;
1552 } else {
1553 expected = 0;
1554 }
1555
1556 if (ch == DPIO_CH0)
1557 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 |
1558 DPIO_ALLDL_POWERDOWN_CH0, val);
1559 else
1560 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 |
1561 DPIO_ALLDL_POWERDOWN_CH1, val);
1562
1563 drm_WARN(&dev_priv->drm, actual != expected,
1564 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1565 !!(actual & DPIO_ALLDL_POWERDOWN),
1566 !!(actual & DPIO_ANYDL_POWERDOWN),
1567 !!(expected & DPIO_ALLDL_POWERDOWN),
1568 !!(expected & DPIO_ANYDL_POWERDOWN),
1569 reg, val);
1570 }
1571
chv_phy_powergate_ch(struct drm_i915_private * dev_priv,enum dpio_phy phy,enum dpio_channel ch,bool override)1572 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1573 enum dpio_channel ch, bool override)
1574 {
1575 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1576 bool was_override;
1577
1578 mutex_lock(&power_domains->lock);
1579
1580 was_override = dev_priv->display.power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1581
1582 if (override == was_override)
1583 goto out;
1584
1585 if (override)
1586 dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1587 else
1588 dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1589
1590 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1591 dev_priv->display.power.chv_phy_control);
1592
1593 drm_dbg_kms(&dev_priv->drm,
1594 "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1595 phy, ch, dev_priv->display.power.chv_phy_control);
1596
1597 assert_chv_phy_status(dev_priv);
1598
1599 out:
1600 mutex_unlock(&power_domains->lock);
1601
1602 return was_override;
1603 }
1604
chv_phy_powergate_lanes(struct intel_encoder * encoder,bool override,unsigned int mask)1605 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1606 bool override, unsigned int mask)
1607 {
1608 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1609 struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1610 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
1611 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
1612
1613 mutex_lock(&power_domains->lock);
1614
1615 dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1616 dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1617
1618 if (override)
1619 dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1620 else
1621 dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1622
1623 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1624 dev_priv->display.power.chv_phy_control);
1625
1626 drm_dbg_kms(&dev_priv->drm,
1627 "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1628 phy, ch, mask, dev_priv->display.power.chv_phy_control);
1629
1630 assert_chv_phy_status(dev_priv);
1631
1632 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1633
1634 mutex_unlock(&power_domains->lock);
1635 }
1636
chv_pipe_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1637 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1638 struct i915_power_well *power_well)
1639 {
1640 enum pipe pipe = PIPE_A;
1641 bool enabled;
1642 u32 state, ctrl;
1643
1644 vlv_punit_get(dev_priv);
1645
1646 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);
1647 /*
1648 * We only ever set the power-on and power-gate states, anything
1649 * else is unexpected.
1650 */
1651 drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) &&
1652 state != DP_SSS_PWR_GATE(pipe));
1653 enabled = state == DP_SSS_PWR_ON(pipe);
1654
1655 /*
1656 * A transient state at this point would mean some unexpected party
1657 * is poking at the power controls too.
1658 */
1659 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);
1660 drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state);
1661
1662 vlv_punit_put(dev_priv);
1663
1664 return enabled;
1665 }
1666
chv_set_pipe_power_well(struct drm_i915_private * dev_priv,struct i915_power_well * power_well,bool enable)1667 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1668 struct i915_power_well *power_well,
1669 bool enable)
1670 {
1671 enum pipe pipe = PIPE_A;
1672 u32 state;
1673 u32 ctrl;
1674
1675 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1676
1677 vlv_punit_get(dev_priv);
1678
1679 #define COND \
1680 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state)
1681
1682 if (COND)
1683 goto out;
1684
1685 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
1686 ctrl &= ~DP_SSC_MASK(pipe);
1687 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1688 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl);
1689
1690 if (wait_for(COND, 100))
1691 drm_err(&dev_priv->drm,
1692 "timeout setting power well state %08x (%08x)\n",
1693 state,
1694 vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM));
1695
1696 #undef COND
1697
1698 out:
1699 vlv_punit_put(dev_priv);
1700 }
1701
chv_pipe_power_well_sync_hw(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1702 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1703 struct i915_power_well *power_well)
1704 {
1705 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1706 dev_priv->display.power.chv_phy_control);
1707 }
1708
chv_pipe_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1709 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1710 struct i915_power_well *power_well)
1711 {
1712 chv_set_pipe_power_well(dev_priv, power_well, true);
1713
1714 vlv_display_power_well_init(dev_priv);
1715 }
1716
chv_pipe_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1717 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1718 struct i915_power_well *power_well)
1719 {
1720 vlv_display_power_well_deinit(dev_priv);
1721
1722 chv_set_pipe_power_well(dev_priv, power_well, false);
1723 }
1724
1725 static void
tgl_tc_cold_request(struct drm_i915_private * i915,bool block)1726 tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
1727 {
1728 u8 tries = 0;
1729 int ret;
1730
1731 while (1) {
1732 u32 low_val;
1733 u32 high_val = 0;
1734
1735 if (block)
1736 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ;
1737 else
1738 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ;
1739
1740 /*
1741 * Spec states that we should timeout the request after 200us
1742 * but the function below will timeout after 500us
1743 */
1744 ret = snb_pcode_read(&i915->uncore, TGL_PCODE_TCCOLD, &low_val, &high_val);
1745 if (ret == 0) {
1746 if (block &&
1747 (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
1748 ret = -EIO;
1749 else
1750 break;
1751 }
1752
1753 if (++tries == 3)
1754 break;
1755
1756 msleep(1);
1757 }
1758
1759 if (ret)
1760 drm_err(&i915->drm, "TC cold %sblock failed\n",
1761 block ? "" : "un");
1762 else
1763 drm_dbg_kms(&i915->drm, "TC cold %sblock succeeded\n",
1764 block ? "" : "un");
1765 }
1766
1767 static void
tgl_tc_cold_off_power_well_enable(struct drm_i915_private * i915,struct i915_power_well * power_well)1768 tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915,
1769 struct i915_power_well *power_well)
1770 {
1771 tgl_tc_cold_request(i915, true);
1772 }
1773
1774 static void
tgl_tc_cold_off_power_well_disable(struct drm_i915_private * i915,struct i915_power_well * power_well)1775 tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915,
1776 struct i915_power_well *power_well)
1777 {
1778 tgl_tc_cold_request(i915, false);
1779 }
1780
1781 static void
tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private * i915,struct i915_power_well * power_well)1782 tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915,
1783 struct i915_power_well *power_well)
1784 {
1785 if (intel_power_well_refcount(power_well) > 0)
1786 tgl_tc_cold_off_power_well_enable(i915, power_well);
1787 else
1788 tgl_tc_cold_off_power_well_disable(i915, power_well);
1789 }
1790
1791 static bool
tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1792 tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
1793 struct i915_power_well *power_well)
1794 {
1795 /*
1796 * Not the correctly implementation but there is no way to just read it
1797 * from PCODE, so returning count to avoid state mismatch errors
1798 */
1799 return intel_power_well_refcount(power_well);
1800 }
1801
xelpdp_aux_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1802 static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
1803 struct i915_power_well *power_well)
1804 {
1805 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
1806 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
1807
1808 if (intel_phy_is_tc(dev_priv, phy))
1809 icl_tc_port_assert_ref_held(dev_priv, power_well,
1810 aux_ch_to_digital_port(dev_priv, aux_ch));
1811
1812 intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch),
1813 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
1814 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
1815
1816 /*
1817 * The power status flag cannot be used to determine whether aux
1818 * power wells have finished powering up. Instead we're
1819 * expected to just wait a fixed 600us after raising the request
1820 * bit.
1821 */
1822 usleep_range(600, 1200);
1823 }
1824
xelpdp_aux_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1825 static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
1826 struct i915_power_well *power_well)
1827 {
1828 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
1829
1830 intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch),
1831 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
1832 0);
1833 usleep_range(10, 30);
1834 }
1835
xelpdp_aux_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1836 static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
1837 struct i915_power_well *power_well)
1838 {
1839 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
1840
1841 return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch)) &
1842 XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
1843 }
1844
xe2lpd_pica_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1845 static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
1846 struct i915_power_well *power_well)
1847 {
1848 intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL,
1849 XE2LPD_PICA_CTL_POWER_REQUEST);
1850
1851 if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
1852 XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
1853 drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
1854
1855 drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
1856 }
1857 }
1858
xe2lpd_pica_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1859 static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
1860 struct i915_power_well *power_well)
1861 {
1862 intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL, 0);
1863
1864 if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
1865 XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
1866 drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
1867
1868 drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
1869 }
1870 }
1871
xe2lpd_pica_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1872 static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
1873 struct i915_power_well *power_well)
1874 {
1875 return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
1876 XE2LPD_PICA_CTL_POWER_STATUS;
1877 }
1878
1879 const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1880 .sync_hw = i9xx_power_well_sync_hw_noop,
1881 .enable = i9xx_always_on_power_well_noop,
1882 .disable = i9xx_always_on_power_well_noop,
1883 .is_enabled = i9xx_always_on_power_well_enabled,
1884 };
1885
1886 const struct i915_power_well_ops chv_pipe_power_well_ops = {
1887 .sync_hw = chv_pipe_power_well_sync_hw,
1888 .enable = chv_pipe_power_well_enable,
1889 .disable = chv_pipe_power_well_disable,
1890 .is_enabled = chv_pipe_power_well_enabled,
1891 };
1892
1893 const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1894 .sync_hw = i9xx_power_well_sync_hw_noop,
1895 .enable = chv_dpio_cmn_power_well_enable,
1896 .disable = chv_dpio_cmn_power_well_disable,
1897 .is_enabled = vlv_power_well_enabled,
1898 };
1899
1900 const struct i915_power_well_ops i830_pipes_power_well_ops = {
1901 .sync_hw = i830_pipes_power_well_sync_hw,
1902 .enable = i830_pipes_power_well_enable,
1903 .disable = i830_pipes_power_well_disable,
1904 .is_enabled = i830_pipes_power_well_enabled,
1905 };
1906
1907 static const struct i915_power_well_regs hsw_power_well_regs = {
1908 .bios = HSW_PWR_WELL_CTL1,
1909 .driver = HSW_PWR_WELL_CTL2,
1910 .kvmr = HSW_PWR_WELL_CTL3,
1911 .debug = HSW_PWR_WELL_CTL4,
1912 };
1913
1914 const struct i915_power_well_ops hsw_power_well_ops = {
1915 .regs = &hsw_power_well_regs,
1916 .sync_hw = hsw_power_well_sync_hw,
1917 .enable = hsw_power_well_enable,
1918 .disable = hsw_power_well_disable,
1919 .is_enabled = hsw_power_well_enabled,
1920 };
1921
1922 const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1923 .sync_hw = i9xx_power_well_sync_hw_noop,
1924 .enable = gen9_dc_off_power_well_enable,
1925 .disable = gen9_dc_off_power_well_disable,
1926 .is_enabled = gen9_dc_off_power_well_enabled,
1927 };
1928
1929 const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
1930 .sync_hw = i9xx_power_well_sync_hw_noop,
1931 .enable = bxt_dpio_cmn_power_well_enable,
1932 .disable = bxt_dpio_cmn_power_well_disable,
1933 .is_enabled = bxt_dpio_cmn_power_well_enabled,
1934 };
1935
1936 const struct i915_power_well_ops vlv_display_power_well_ops = {
1937 .sync_hw = i9xx_power_well_sync_hw_noop,
1938 .enable = vlv_display_power_well_enable,
1939 .disable = vlv_display_power_well_disable,
1940 .is_enabled = vlv_power_well_enabled,
1941 };
1942
1943 const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1944 .sync_hw = i9xx_power_well_sync_hw_noop,
1945 .enable = vlv_dpio_cmn_power_well_enable,
1946 .disable = vlv_dpio_cmn_power_well_disable,
1947 .is_enabled = vlv_power_well_enabled,
1948 };
1949
1950 const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1951 .sync_hw = i9xx_power_well_sync_hw_noop,
1952 .enable = vlv_power_well_enable,
1953 .disable = vlv_power_well_disable,
1954 .is_enabled = vlv_power_well_enabled,
1955 };
1956
1957 static const struct i915_power_well_regs icl_aux_power_well_regs = {
1958 .bios = ICL_PWR_WELL_CTL_AUX1,
1959 .driver = ICL_PWR_WELL_CTL_AUX2,
1960 .debug = ICL_PWR_WELL_CTL_AUX4,
1961 };
1962
1963 const struct i915_power_well_ops icl_aux_power_well_ops = {
1964 .regs = &icl_aux_power_well_regs,
1965 .sync_hw = hsw_power_well_sync_hw,
1966 .enable = icl_aux_power_well_enable,
1967 .disable = icl_aux_power_well_disable,
1968 .is_enabled = hsw_power_well_enabled,
1969 };
1970
1971 static const struct i915_power_well_regs icl_ddi_power_well_regs = {
1972 .bios = ICL_PWR_WELL_CTL_DDI1,
1973 .driver = ICL_PWR_WELL_CTL_DDI2,
1974 .debug = ICL_PWR_WELL_CTL_DDI4,
1975 };
1976
1977 const struct i915_power_well_ops icl_ddi_power_well_ops = {
1978 .regs = &icl_ddi_power_well_regs,
1979 .sync_hw = hsw_power_well_sync_hw,
1980 .enable = hsw_power_well_enable,
1981 .disable = hsw_power_well_disable,
1982 .is_enabled = hsw_power_well_enabled,
1983 };
1984
1985 const struct i915_power_well_ops tgl_tc_cold_off_ops = {
1986 .sync_hw = tgl_tc_cold_off_power_well_sync_hw,
1987 .enable = tgl_tc_cold_off_power_well_enable,
1988 .disable = tgl_tc_cold_off_power_well_disable,
1989 .is_enabled = tgl_tc_cold_off_power_well_is_enabled,
1990 };
1991
1992 const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
1993 .sync_hw = i9xx_power_well_sync_hw_noop,
1994 .enable = xelpdp_aux_power_well_enable,
1995 .disable = xelpdp_aux_power_well_disable,
1996 .is_enabled = xelpdp_aux_power_well_enabled,
1997 };
1998
1999 const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
2000 .sync_hw = i9xx_power_well_sync_hw_noop,
2001 .enable = xe2lpd_pica_power_well_enable,
2002 .disable = xe2lpd_pica_power_well_disable,
2003 .is_enabled = xe2lpd_pica_power_well_enabled,
2004 };
2005