1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 */
5
6 #include "g4x_dp.h"
7 #include "i915_drv.h"
8 #include "i915_reg.h"
9 #include "intel_de.h"
10 #include "intel_display_power_well.h"
11 #include "intel_display_types.h"
12 #include "intel_dp.h"
13 #include "intel_dpio_phy.h"
14 #include "intel_dpll.h"
15 #include "intel_lvds.h"
16 #include "intel_lvds_regs.h"
17 #include "intel_pps.h"
18 #include "intel_pps_regs.h"
19 #include "intel_quirks.h"
20
21 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
22 enum pipe pipe);
23
24 static void pps_init_delays(struct intel_dp *intel_dp);
25 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
26
pps_name(struct drm_i915_private * i915,struct intel_pps * pps)27 static const char *pps_name(struct drm_i915_private *i915,
28 struct intel_pps *pps)
29 {
30 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
31 switch (pps->pps_pipe) {
32 case INVALID_PIPE:
33 /*
34 * FIXME would be nice if we can guarantee
35 * to always have a valid PPS when calling this.
36 */
37 return "PPS <none>";
38 case PIPE_A:
39 return "PPS A";
40 case PIPE_B:
41 return "PPS B";
42 default:
43 MISSING_CASE(pps->pps_pipe);
44 break;
45 }
46 } else {
47 switch (pps->pps_idx) {
48 case 0:
49 return "PPS 0";
50 case 1:
51 return "PPS 1";
52 default:
53 MISSING_CASE(pps->pps_idx);
54 break;
55 }
56 }
57
58 return "PPS <invalid>";
59 }
60
intel_pps_lock(struct intel_dp * intel_dp)61 intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
62 {
63 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
64 intel_wakeref_t wakeref;
65
66 /*
67 * See intel_pps_reset_all() why we need a power domain reference here.
68 */
69 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
70 mutex_lock(&dev_priv->display.pps.mutex);
71
72 return wakeref;
73 }
74
intel_pps_unlock(struct intel_dp * intel_dp,intel_wakeref_t wakeref)75 intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
76 intel_wakeref_t wakeref)
77 {
78 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
79
80 mutex_unlock(&dev_priv->display.pps.mutex);
81 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
82
83 return 0;
84 }
85
86 static void
vlv_power_sequencer_kick(struct intel_dp * intel_dp)87 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
88 {
89 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
90 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
91 enum pipe pipe = intel_dp->pps.pps_pipe;
92 bool pll_enabled, release_cl_override = false;
93 enum dpio_phy phy = vlv_pipe_to_phy(pipe);
94 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
95 u32 DP;
96
97 if (drm_WARN(&dev_priv->drm,
98 intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
99 "skipping %s kick due to [ENCODER:%d:%s] being active\n",
100 pps_name(dev_priv, &intel_dp->pps),
101 dig_port->base.base.base.id, dig_port->base.base.name))
102 return;
103
104 drm_dbg_kms(&dev_priv->drm,
105 "kicking %s for [ENCODER:%d:%s]\n",
106 pps_name(dev_priv, &intel_dp->pps),
107 dig_port->base.base.base.id, dig_port->base.base.name);
108
109 /* Preserve the BIOS-computed detected bit. This is
110 * supposed to be read-only.
111 */
112 DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
113 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
114 DP |= DP_PORT_WIDTH(1);
115 DP |= DP_LINK_TRAIN_PAT_1;
116
117 if (IS_CHERRYVIEW(dev_priv))
118 DP |= DP_PIPE_SEL_CHV(pipe);
119 else
120 DP |= DP_PIPE_SEL(pipe);
121
122 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
123
124 /*
125 * The DPLL for the pipe must be enabled for this to work.
126 * So enable temporarily it if it's not already enabled.
127 */
128 if (!pll_enabled) {
129 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
130 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
131
132 if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
133 drm_err(&dev_priv->drm,
134 "Failed to force on PLL for pipe %c!\n",
135 pipe_name(pipe));
136 return;
137 }
138 }
139
140 /*
141 * Similar magic as in intel_dp_enable_port().
142 * We _must_ do this port enable + disable trick
143 * to make this power sequencer lock onto the port.
144 * Otherwise even VDD force bit won't work.
145 */
146 intel_de_write(dev_priv, intel_dp->output_reg, DP);
147 intel_de_posting_read(dev_priv, intel_dp->output_reg);
148
149 intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
150 intel_de_posting_read(dev_priv, intel_dp->output_reg);
151
152 intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
153 intel_de_posting_read(dev_priv, intel_dp->output_reg);
154
155 if (!pll_enabled) {
156 vlv_force_pll_off(dev_priv, pipe);
157
158 if (release_cl_override)
159 chv_phy_powergate_ch(dev_priv, phy, ch, false);
160 }
161 }
162
vlv_find_free_pps(struct drm_i915_private * dev_priv)163 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
164 {
165 struct intel_encoder *encoder;
166 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
167
168 /*
169 * We don't have power sequencer currently.
170 * Pick one that's not used by other ports.
171 */
172 for_each_intel_dp(&dev_priv->drm, encoder) {
173 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
174
175 if (encoder->type == INTEL_OUTPUT_EDP) {
176 drm_WARN_ON(&dev_priv->drm,
177 intel_dp->pps.active_pipe != INVALID_PIPE &&
178 intel_dp->pps.active_pipe !=
179 intel_dp->pps.pps_pipe);
180
181 if (intel_dp->pps.pps_pipe != INVALID_PIPE)
182 pipes &= ~(1 << intel_dp->pps.pps_pipe);
183 } else {
184 drm_WARN_ON(&dev_priv->drm,
185 intel_dp->pps.pps_pipe != INVALID_PIPE);
186
187 if (intel_dp->pps.active_pipe != INVALID_PIPE)
188 pipes &= ~(1 << intel_dp->pps.active_pipe);
189 }
190 }
191
192 if (pipes == 0)
193 return INVALID_PIPE;
194
195 return ffs(pipes) - 1;
196 }
197
198 static enum pipe
vlv_power_sequencer_pipe(struct intel_dp * intel_dp)199 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
200 {
201 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
202 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
203 enum pipe pipe;
204
205 lockdep_assert_held(&dev_priv->display.pps.mutex);
206
207 /* We should never land here with regular DP ports */
208 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
209
210 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE &&
211 intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe);
212
213 if (intel_dp->pps.pps_pipe != INVALID_PIPE)
214 return intel_dp->pps.pps_pipe;
215
216 pipe = vlv_find_free_pps(dev_priv);
217
218 /*
219 * Didn't find one. This should not happen since there
220 * are two power sequencers and up to two eDP ports.
221 */
222 if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
223 pipe = PIPE_A;
224
225 vlv_steal_power_sequencer(dev_priv, pipe);
226 intel_dp->pps.pps_pipe = pipe;
227
228 drm_dbg_kms(&dev_priv->drm,
229 "picked %s for [ENCODER:%d:%s]\n",
230 pps_name(dev_priv, &intel_dp->pps),
231 dig_port->base.base.base.id, dig_port->base.base.name);
232
233 /* init power sequencer on this pipe and port */
234 pps_init_delays(intel_dp);
235 pps_init_registers(intel_dp, true);
236
237 /*
238 * Even vdd force doesn't work until we've made
239 * the power sequencer lock in on the port.
240 */
241 vlv_power_sequencer_kick(intel_dp);
242
243 return intel_dp->pps.pps_pipe;
244 }
245
246 static int
bxt_power_sequencer_idx(struct intel_dp * intel_dp)247 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
248 {
249 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
250 int pps_idx = intel_dp->pps.pps_idx;
251
252 lockdep_assert_held(&dev_priv->display.pps.mutex);
253
254 /* We should never land here with regular DP ports */
255 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
256
257 if (!intel_dp->pps.pps_reset)
258 return pps_idx;
259
260 intel_dp->pps.pps_reset = false;
261
262 /*
263 * Only the HW needs to be reprogrammed, the SW state is fixed and
264 * has been setup during connector init.
265 */
266 pps_init_registers(intel_dp, false);
267
268 return pps_idx;
269 }
270
271 typedef bool (*pps_check)(struct drm_i915_private *dev_priv, int pps_idx);
272
pps_has_pp_on(struct drm_i915_private * dev_priv,int pps_idx)273 static bool pps_has_pp_on(struct drm_i915_private *dev_priv, int pps_idx)
274 {
275 return intel_de_read(dev_priv, PP_STATUS(pps_idx)) & PP_ON;
276 }
277
pps_has_vdd_on(struct drm_i915_private * dev_priv,int pps_idx)278 static bool pps_has_vdd_on(struct drm_i915_private *dev_priv, int pps_idx)
279 {
280 return intel_de_read(dev_priv, PP_CONTROL(pps_idx)) & EDP_FORCE_VDD;
281 }
282
pps_any(struct drm_i915_private * dev_priv,int pps_idx)283 static bool pps_any(struct drm_i915_private *dev_priv, int pps_idx)
284 {
285 return true;
286 }
287
288 static enum pipe
vlv_initial_pps_pipe(struct drm_i915_private * dev_priv,enum port port,pps_check check)289 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
290 enum port port, pps_check check)
291 {
292 enum pipe pipe;
293
294 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
295 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
296 PANEL_PORT_SELECT_MASK;
297
298 if (port_sel != PANEL_PORT_SELECT_VLV(port))
299 continue;
300
301 if (!check(dev_priv, pipe))
302 continue;
303
304 return pipe;
305 }
306
307 return INVALID_PIPE;
308 }
309
310 static void
vlv_initial_power_sequencer_setup(struct intel_dp * intel_dp)311 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
312 {
313 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
314 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
315 enum port port = dig_port->base.port;
316
317 lockdep_assert_held(&dev_priv->display.pps.mutex);
318
319 /* try to find a pipe with this port selected */
320 /* first pick one where the panel is on */
321 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
322 pps_has_pp_on);
323 /* didn't find one? pick one where vdd is on */
324 if (intel_dp->pps.pps_pipe == INVALID_PIPE)
325 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
326 pps_has_vdd_on);
327 /* didn't find one? pick one with just the correct port */
328 if (intel_dp->pps.pps_pipe == INVALID_PIPE)
329 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
330 pps_any);
331
332 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
333 if (intel_dp->pps.pps_pipe == INVALID_PIPE) {
334 drm_dbg_kms(&dev_priv->drm,
335 "[ENCODER:%d:%s] no initial power sequencer\n",
336 dig_port->base.base.base.id, dig_port->base.base.name);
337 return;
338 }
339
340 drm_dbg_kms(&dev_priv->drm,
341 "[ENCODER:%d:%s] initial power sequencer: %s\n",
342 dig_port->base.base.base.id, dig_port->base.base.name,
343 pps_name(dev_priv, &intel_dp->pps));
344 }
345
intel_num_pps(struct drm_i915_private * i915)346 static int intel_num_pps(struct drm_i915_private *i915)
347 {
348 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
349 return 2;
350
351 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
352 return 2;
353
354 if (INTEL_PCH_TYPE(i915) >= PCH_DG1)
355 return 1;
356
357 if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
358 return 2;
359
360 return 1;
361 }
362
intel_pps_is_valid(struct intel_dp * intel_dp)363 static bool intel_pps_is_valid(struct intel_dp *intel_dp)
364 {
365 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
366
367 if (intel_dp->pps.pps_idx == 1 &&
368 INTEL_PCH_TYPE(i915) >= PCH_ICP &&
369 INTEL_PCH_TYPE(i915) <= PCH_ADP)
370 return intel_de_read(i915, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;
371
372 return true;
373 }
374
375 static int
bxt_initial_pps_idx(struct drm_i915_private * i915,pps_check check)376 bxt_initial_pps_idx(struct drm_i915_private *i915, pps_check check)
377 {
378 int pps_idx, pps_num = intel_num_pps(i915);
379
380 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
381 if (check(i915, pps_idx))
382 return pps_idx;
383 }
384
385 return -1;
386 }
387
388 static bool
pps_initial_setup(struct intel_dp * intel_dp)389 pps_initial_setup(struct intel_dp *intel_dp)
390 {
391 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
392 struct intel_connector *connector = intel_dp->attached_connector;
393 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
394
395 lockdep_assert_held(&i915->display.pps.mutex);
396
397 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
398 vlv_initial_power_sequencer_setup(intel_dp);
399 return true;
400 }
401
402 /* first ask the VBT */
403 if (intel_num_pps(i915) > 1)
404 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;
405 else
406 intel_dp->pps.pps_idx = 0;
407
408 if (drm_WARN_ON(&i915->drm, intel_dp->pps.pps_idx >= intel_num_pps(i915)))
409 intel_dp->pps.pps_idx = -1;
410
411 /* VBT wasn't parsed yet? pick one where the panel is on */
412 if (intel_dp->pps.pps_idx < 0)
413 intel_dp->pps.pps_idx = bxt_initial_pps_idx(i915, pps_has_pp_on);
414 /* didn't find one? pick one where vdd is on */
415 if (intel_dp->pps.pps_idx < 0)
416 intel_dp->pps.pps_idx = bxt_initial_pps_idx(i915, pps_has_vdd_on);
417 /* didn't find one? pick any */
418 if (intel_dp->pps.pps_idx < 0) {
419 intel_dp->pps.pps_idx = bxt_initial_pps_idx(i915, pps_any);
420
421 drm_dbg_kms(&i915->drm,
422 "[ENCODER:%d:%s] no initial power sequencer, assuming %s\n",
423 encoder->base.base.id, encoder->base.name,
424 pps_name(i915, &intel_dp->pps));
425 } else {
426 drm_dbg_kms(&i915->drm,
427 "[ENCODER:%d:%s] initial power sequencer: %s\n",
428 encoder->base.base.id, encoder->base.name,
429 pps_name(i915, &intel_dp->pps));
430 }
431
432 return intel_pps_is_valid(intel_dp);
433 }
434
intel_pps_reset_all(struct drm_i915_private * dev_priv)435 void intel_pps_reset_all(struct drm_i915_private *dev_priv)
436 {
437 struct intel_encoder *encoder;
438
439 if (drm_WARN_ON(&dev_priv->drm, !IS_LP(dev_priv)))
440 return;
441
442 if (!HAS_DISPLAY(dev_priv))
443 return;
444
445 /*
446 * We can't grab pps_mutex here due to deadlock with power_domain
447 * mutex when power_domain functions are called while holding pps_mutex.
448 * That also means that in order to use pps_pipe the code needs to
449 * hold both a power domain reference and pps_mutex, and the power domain
450 * reference get/put must be done while _not_ holding pps_mutex.
451 * pps_{lock,unlock}() do these steps in the correct order, so one
452 * should use them always.
453 */
454
455 for_each_intel_dp(&dev_priv->drm, encoder) {
456 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
457
458 drm_WARN_ON(&dev_priv->drm,
459 intel_dp->pps.active_pipe != INVALID_PIPE);
460
461 if (encoder->type != INTEL_OUTPUT_EDP)
462 continue;
463
464 if (DISPLAY_VER(dev_priv) >= 9)
465 intel_dp->pps.pps_reset = true;
466 else
467 intel_dp->pps.pps_pipe = INVALID_PIPE;
468 }
469 }
470
471 struct pps_registers {
472 i915_reg_t pp_ctrl;
473 i915_reg_t pp_stat;
474 i915_reg_t pp_on;
475 i915_reg_t pp_off;
476 i915_reg_t pp_div;
477 };
478
intel_pps_get_registers(struct intel_dp * intel_dp,struct pps_registers * regs)479 static void intel_pps_get_registers(struct intel_dp *intel_dp,
480 struct pps_registers *regs)
481 {
482 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
483 int pps_idx;
484
485 memset(regs, 0, sizeof(*regs));
486
487 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
488 pps_idx = vlv_power_sequencer_pipe(intel_dp);
489 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
490 pps_idx = bxt_power_sequencer_idx(intel_dp);
491 else
492 pps_idx = intel_dp->pps.pps_idx;
493
494 regs->pp_ctrl = PP_CONTROL(pps_idx);
495 regs->pp_stat = PP_STATUS(pps_idx);
496 regs->pp_on = PP_ON_DELAYS(pps_idx);
497 regs->pp_off = PP_OFF_DELAYS(pps_idx);
498
499 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
500 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
501 INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
502 regs->pp_div = INVALID_MMIO_REG;
503 else
504 regs->pp_div = PP_DIVISOR(pps_idx);
505 }
506
507 static i915_reg_t
_pp_ctrl_reg(struct intel_dp * intel_dp)508 _pp_ctrl_reg(struct intel_dp *intel_dp)
509 {
510 struct pps_registers regs;
511
512 intel_pps_get_registers(intel_dp, ®s);
513
514 return regs.pp_ctrl;
515 }
516
517 static i915_reg_t
_pp_stat_reg(struct intel_dp * intel_dp)518 _pp_stat_reg(struct intel_dp *intel_dp)
519 {
520 struct pps_registers regs;
521
522 intel_pps_get_registers(intel_dp, ®s);
523
524 return regs.pp_stat;
525 }
526
edp_have_panel_power(struct intel_dp * intel_dp)527 static bool edp_have_panel_power(struct intel_dp *intel_dp)
528 {
529 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
530
531 lockdep_assert_held(&dev_priv->display.pps.mutex);
532
533 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
534 intel_dp->pps.pps_pipe == INVALID_PIPE)
535 return false;
536
537 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
538 }
539
edp_have_panel_vdd(struct intel_dp * intel_dp)540 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
541 {
542 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
543
544 lockdep_assert_held(&dev_priv->display.pps.mutex);
545
546 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
547 intel_dp->pps.pps_pipe == INVALID_PIPE)
548 return false;
549
550 return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
551 }
552
intel_pps_check_power_unlocked(struct intel_dp * intel_dp)553 void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
554 {
555 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
556 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
557
558 if (!intel_dp_is_edp(intel_dp))
559 return;
560
561 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
562 drm_WARN(&dev_priv->drm, 1,
563 "[ENCODER:%d:%s] %s powered off while attempting AUX CH communication.\n",
564 dig_port->base.base.base.id, dig_port->base.base.name,
565 pps_name(dev_priv, &intel_dp->pps));
566 drm_dbg_kms(&dev_priv->drm,
567 "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
568 dig_port->base.base.base.id, dig_port->base.base.name,
569 pps_name(dev_priv, &intel_dp->pps),
570 intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
571 intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
572 }
573 }
574
575 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
576 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
577
578 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
579 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
580
581 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
582 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
583
584 static void intel_pps_verify_state(struct intel_dp *intel_dp);
585
wait_panel_status(struct intel_dp * intel_dp,u32 mask,u32 value)586 static void wait_panel_status(struct intel_dp *intel_dp,
587 u32 mask, u32 value)
588 {
589 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
590 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
591 i915_reg_t pp_stat_reg, pp_ctrl_reg;
592
593 lockdep_assert_held(&dev_priv->display.pps.mutex);
594
595 intel_pps_verify_state(intel_dp);
596
597 pp_stat_reg = _pp_stat_reg(intel_dp);
598 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
599
600 drm_dbg_kms(&dev_priv->drm,
601 "[ENCODER:%d:%s] %s mask: 0x%08x value: 0x%08x PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
602 dig_port->base.base.base.id, dig_port->base.base.name,
603 pps_name(dev_priv, &intel_dp->pps),
604 mask, value,
605 intel_de_read(dev_priv, pp_stat_reg),
606 intel_de_read(dev_priv, pp_ctrl_reg));
607
608 if (intel_de_wait(dev_priv, pp_stat_reg, mask, value, 5000))
609 drm_err(&dev_priv->drm,
610 "[ENCODER:%d:%s] %s panel status timeout: PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
611 dig_port->base.base.base.id, dig_port->base.base.name,
612 pps_name(dev_priv, &intel_dp->pps),
613 intel_de_read(dev_priv, pp_stat_reg),
614 intel_de_read(dev_priv, pp_ctrl_reg));
615
616 drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
617 }
618
wait_panel_on(struct intel_dp * intel_dp)619 static void wait_panel_on(struct intel_dp *intel_dp)
620 {
621 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
622 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
623
624 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] %s wait for panel power on\n",
625 dig_port->base.base.base.id, dig_port->base.base.name,
626 pps_name(i915, &intel_dp->pps));
627 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
628 }
629
wait_panel_off(struct intel_dp * intel_dp)630 static void wait_panel_off(struct intel_dp *intel_dp)
631 {
632 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
633 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
634
635 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] %s wait for panel power off time\n",
636 dig_port->base.base.base.id, dig_port->base.base.name,
637 pps_name(i915, &intel_dp->pps));
638 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
639 }
640
wait_panel_power_cycle(struct intel_dp * intel_dp)641 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
642 {
643 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
644 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
645 ktime_t panel_power_on_time;
646 s64 panel_power_off_duration;
647
648 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] %s wait for panel power cycle\n",
649 dig_port->base.base.base.id, dig_port->base.base.name,
650 pps_name(i915, &intel_dp->pps));
651
652 /* take the difference of current time and panel power off time
653 * and then make panel wait for t11_t12 if needed. */
654 panel_power_on_time = ktime_get_boottime();
655 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);
656
657 /* When we disable the VDD override bit last we have to do the manual
658 * wait. */
659 if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay)
660 wait_remaining_ms_from_jiffies(jiffies,
661 intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);
662
663 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
664 }
665
intel_pps_wait_power_cycle(struct intel_dp * intel_dp)666 void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
667 {
668 intel_wakeref_t wakeref;
669
670 if (!intel_dp_is_edp(intel_dp))
671 return;
672
673 with_intel_pps_lock(intel_dp, wakeref)
674 wait_panel_power_cycle(intel_dp);
675 }
676
wait_backlight_on(struct intel_dp * intel_dp)677 static void wait_backlight_on(struct intel_dp *intel_dp)
678 {
679 wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,
680 intel_dp->pps.backlight_on_delay);
681 }
682
edp_wait_backlight_off(struct intel_dp * intel_dp)683 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
684 {
685 wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,
686 intel_dp->pps.backlight_off_delay);
687 }
688
689 /* Read the current pp_control value, unlocking the register if it
690 * is locked
691 */
692
ilk_get_pp_control(struct intel_dp * intel_dp)693 static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
694 {
695 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
696 u32 control;
697
698 lockdep_assert_held(&dev_priv->display.pps.mutex);
699
700 control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
701 if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
702 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
703 control &= ~PANEL_UNLOCK_MASK;
704 control |= PANEL_UNLOCK_REGS;
705 }
706 return control;
707 }
708
709 /*
710 * Must be paired with intel_pps_vdd_off_unlocked().
711 * Must hold pps_mutex around the whole on/off sequence.
712 * Can be nested with intel_pps_vdd_{on,off}() calls.
713 */
intel_pps_vdd_on_unlocked(struct intel_dp * intel_dp)714 bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
715 {
716 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
717 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
718 u32 pp;
719 i915_reg_t pp_stat_reg, pp_ctrl_reg;
720 bool need_to_disable = !intel_dp->pps.want_panel_vdd;
721
722 lockdep_assert_held(&dev_priv->display.pps.mutex);
723
724 if (!intel_dp_is_edp(intel_dp))
725 return false;
726
727 cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
728 intel_dp->pps.want_panel_vdd = true;
729
730 if (edp_have_panel_vdd(intel_dp))
731 return need_to_disable;
732
733 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
734 intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
735 intel_aux_power_domain(dig_port));
736
737 pp_stat_reg = _pp_stat_reg(intel_dp);
738 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
739
740 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turning VDD on\n",
741 dig_port->base.base.base.id, dig_port->base.base.name,
742 pps_name(dev_priv, &intel_dp->pps));
743
744 if (!edp_have_panel_power(intel_dp))
745 wait_panel_power_cycle(intel_dp);
746
747 pp = ilk_get_pp_control(intel_dp);
748 pp |= EDP_FORCE_VDD;
749
750 intel_de_write(dev_priv, pp_ctrl_reg, pp);
751 intel_de_posting_read(dev_priv, pp_ctrl_reg);
752 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
753 dig_port->base.base.base.id, dig_port->base.base.name,
754 pps_name(dev_priv, &intel_dp->pps),
755 intel_de_read(dev_priv, pp_stat_reg),
756 intel_de_read(dev_priv, pp_ctrl_reg));
757 /*
758 * If the panel wasn't on, delay before accessing aux channel
759 */
760 if (!edp_have_panel_power(intel_dp)) {
761 drm_dbg_kms(&dev_priv->drm,
762 "[ENCODER:%d:%s] %s panel power wasn't enabled\n",
763 dig_port->base.base.base.id, dig_port->base.base.name,
764 pps_name(dev_priv, &intel_dp->pps));
765 msleep(intel_dp->pps.panel_power_up_delay);
766 }
767
768 return need_to_disable;
769 }
770
771 /*
772 * Must be paired with intel_pps_off().
773 * Nested calls to these functions are not allowed since
774 * we drop the lock. Caller must use some higher level
775 * locking to prevent nested calls from other threads.
776 */
intel_pps_vdd_on(struct intel_dp * intel_dp)777 void intel_pps_vdd_on(struct intel_dp *intel_dp)
778 {
779 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
780 intel_wakeref_t wakeref;
781 bool vdd;
782
783 if (!intel_dp_is_edp(intel_dp))
784 return;
785
786 vdd = false;
787 with_intel_pps_lock(intel_dp, wakeref)
788 vdd = intel_pps_vdd_on_unlocked(intel_dp);
789 I915_STATE_WARN(i915, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n",
790 dp_to_dig_port(intel_dp)->base.base.base.id,
791 dp_to_dig_port(intel_dp)->base.base.name,
792 pps_name(i915, &intel_dp->pps));
793 }
794
intel_pps_vdd_off_sync_unlocked(struct intel_dp * intel_dp)795 static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
796 {
797 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
798 struct intel_digital_port *dig_port =
799 dp_to_dig_port(intel_dp);
800 u32 pp;
801 i915_reg_t pp_stat_reg, pp_ctrl_reg;
802
803 lockdep_assert_held(&dev_priv->display.pps.mutex);
804
805 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd);
806
807 if (!edp_have_panel_vdd(intel_dp))
808 return;
809
810 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turning VDD off\n",
811 dig_port->base.base.base.id, dig_port->base.base.name,
812 pps_name(dev_priv, &intel_dp->pps));
813
814 pp = ilk_get_pp_control(intel_dp);
815 pp &= ~EDP_FORCE_VDD;
816
817 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
818 pp_stat_reg = _pp_stat_reg(intel_dp);
819
820 intel_de_write(dev_priv, pp_ctrl_reg, pp);
821 intel_de_posting_read(dev_priv, pp_ctrl_reg);
822
823 /* Make sure sequencer is idle before allowing subsequent activity */
824 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
825 dig_port->base.base.base.id, dig_port->base.base.name,
826 pps_name(dev_priv, &intel_dp->pps),
827 intel_de_read(dev_priv, pp_stat_reg),
828 intel_de_read(dev_priv, pp_ctrl_reg));
829
830 if ((pp & PANEL_POWER_ON) == 0)
831 intel_dp->pps.panel_power_off_time = ktime_get_boottime();
832
833 intel_display_power_put(dev_priv,
834 intel_aux_power_domain(dig_port),
835 fetch_and_zero(&intel_dp->pps.vdd_wakeref));
836 }
837
intel_pps_vdd_off_sync(struct intel_dp * intel_dp)838 void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
839 {
840 intel_wakeref_t wakeref;
841
842 if (!intel_dp_is_edp(intel_dp))
843 return;
844
845 cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);
846 /*
847 * vdd might still be enabled due to the delayed vdd off.
848 * Make sure vdd is actually turned off here.
849 */
850 with_intel_pps_lock(intel_dp, wakeref)
851 intel_pps_vdd_off_sync_unlocked(intel_dp);
852 }
853
edp_panel_vdd_work(struct work_struct * __work)854 static void edp_panel_vdd_work(struct work_struct *__work)
855 {
856 struct intel_pps *pps = container_of(to_delayed_work(__work),
857 struct intel_pps, panel_vdd_work);
858 struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);
859 intel_wakeref_t wakeref;
860
861 with_intel_pps_lock(intel_dp, wakeref) {
862 if (!intel_dp->pps.want_panel_vdd)
863 intel_pps_vdd_off_sync_unlocked(intel_dp);
864 }
865 }
866
edp_panel_vdd_schedule_off(struct intel_dp * intel_dp)867 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
868 {
869 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
870 unsigned long delay;
871
872 /*
873 * We may not yet know the real power sequencing delays,
874 * so keep VDD enabled until we're done with init.
875 */
876 if (intel_dp->pps.initializing)
877 return;
878
879 /*
880 * Queue the timer to fire a long time from now (relative to the power
881 * down delay) to keep the panel power up across a sequence of
882 * operations.
883 */
884 delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);
885 queue_delayed_work(i915->unordered_wq,
886 &intel_dp->pps.panel_vdd_work, delay);
887 }
888
889 /*
890 * Must be paired with edp_panel_vdd_on().
891 * Must hold pps_mutex around the whole on/off sequence.
892 * Can be nested with intel_pps_vdd_{on,off}() calls.
893 */
intel_pps_vdd_off_unlocked(struct intel_dp * intel_dp,bool sync)894 void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
895 {
896 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
897
898 lockdep_assert_held(&dev_priv->display.pps.mutex);
899
900 if (!intel_dp_is_edp(intel_dp))
901 return;
902
903 I915_STATE_WARN(dev_priv, !intel_dp->pps.want_panel_vdd,
904 "[ENCODER:%d:%s] %s VDD not forced on",
905 dp_to_dig_port(intel_dp)->base.base.base.id,
906 dp_to_dig_port(intel_dp)->base.base.name,
907 pps_name(dev_priv, &intel_dp->pps));
908
909 intel_dp->pps.want_panel_vdd = false;
910
911 if (sync)
912 intel_pps_vdd_off_sync_unlocked(intel_dp);
913 else
914 edp_panel_vdd_schedule_off(intel_dp);
915 }
916
intel_pps_on_unlocked(struct intel_dp * intel_dp)917 void intel_pps_on_unlocked(struct intel_dp *intel_dp)
918 {
919 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
920 u32 pp;
921 i915_reg_t pp_ctrl_reg;
922
923 lockdep_assert_held(&dev_priv->display.pps.mutex);
924
925 if (!intel_dp_is_edp(intel_dp))
926 return;
927
928 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turn panel power on\n",
929 dp_to_dig_port(intel_dp)->base.base.base.id,
930 dp_to_dig_port(intel_dp)->base.base.name,
931 pps_name(dev_priv, &intel_dp->pps));
932
933 if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
934 "[ENCODER:%d:%s] %s panel power already on\n",
935 dp_to_dig_port(intel_dp)->base.base.base.id,
936 dp_to_dig_port(intel_dp)->base.base.name,
937 pps_name(dev_priv, &intel_dp->pps)))
938 return;
939
940 wait_panel_power_cycle(intel_dp);
941
942 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
943 pp = ilk_get_pp_control(intel_dp);
944 if (IS_IRONLAKE(dev_priv)) {
945 /* ILK workaround: disable reset around power sequence */
946 pp &= ~PANEL_POWER_RESET;
947 intel_de_write(dev_priv, pp_ctrl_reg, pp);
948 intel_de_posting_read(dev_priv, pp_ctrl_reg);
949 }
950
951 pp |= PANEL_POWER_ON;
952 if (!IS_IRONLAKE(dev_priv))
953 pp |= PANEL_POWER_RESET;
954
955 intel_de_write(dev_priv, pp_ctrl_reg, pp);
956 intel_de_posting_read(dev_priv, pp_ctrl_reg);
957
958 wait_panel_on(intel_dp);
959 intel_dp->pps.last_power_on = jiffies;
960
961 if (IS_IRONLAKE(dev_priv)) {
962 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
963 intel_de_write(dev_priv, pp_ctrl_reg, pp);
964 intel_de_posting_read(dev_priv, pp_ctrl_reg);
965 }
966 }
967
intel_pps_on(struct intel_dp * intel_dp)968 void intel_pps_on(struct intel_dp *intel_dp)
969 {
970 intel_wakeref_t wakeref;
971
972 if (!intel_dp_is_edp(intel_dp))
973 return;
974
975 with_intel_pps_lock(intel_dp, wakeref)
976 intel_pps_on_unlocked(intel_dp);
977 }
978
intel_pps_off_unlocked(struct intel_dp * intel_dp)979 void intel_pps_off_unlocked(struct intel_dp *intel_dp)
980 {
981 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
982 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
983 u32 pp;
984 i915_reg_t pp_ctrl_reg;
985
986 lockdep_assert_held(&dev_priv->display.pps.mutex);
987
988 if (!intel_dp_is_edp(intel_dp))
989 return;
990
991 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turn panel power off\n",
992 dig_port->base.base.base.id, dig_port->base.base.name,
993 pps_name(dev_priv, &intel_dp->pps));
994
995 drm_WARN(&dev_priv->drm, !intel_dp->pps.want_panel_vdd,
996 "[ENCODER:%d:%s] %s need VDD to turn off panel\n",
997 dig_port->base.base.base.id, dig_port->base.base.name,
998 pps_name(dev_priv, &intel_dp->pps));
999
1000 pp = ilk_get_pp_control(intel_dp);
1001 /* We need to switch off panel power _and_ force vdd, for otherwise some
1002 * panels get very unhappy and cease to work. */
1003 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1004 EDP_BLC_ENABLE);
1005
1006 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1007
1008 intel_dp->pps.want_panel_vdd = false;
1009
1010 intel_de_write(dev_priv, pp_ctrl_reg, pp);
1011 intel_de_posting_read(dev_priv, pp_ctrl_reg);
1012
1013 wait_panel_off(intel_dp);
1014 intel_dp->pps.panel_power_off_time = ktime_get_boottime();
1015
1016 /* We got a reference when we enabled the VDD. */
1017 intel_display_power_put(dev_priv,
1018 intel_aux_power_domain(dig_port),
1019 fetch_and_zero(&intel_dp->pps.vdd_wakeref));
1020 }
1021
intel_pps_off(struct intel_dp * intel_dp)1022 void intel_pps_off(struct intel_dp *intel_dp)
1023 {
1024 intel_wakeref_t wakeref;
1025
1026 if (!intel_dp_is_edp(intel_dp))
1027 return;
1028
1029 with_intel_pps_lock(intel_dp, wakeref)
1030 intel_pps_off_unlocked(intel_dp);
1031 }
1032
1033 /* Enable backlight in the panel power control. */
intel_pps_backlight_on(struct intel_dp * intel_dp)1034 void intel_pps_backlight_on(struct intel_dp *intel_dp)
1035 {
1036 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1037 intel_wakeref_t wakeref;
1038
1039 /*
1040 * If we enable the backlight right away following a panel power
1041 * on, we may see slight flicker as the panel syncs with the eDP
1042 * link. So delay a bit to make sure the image is solid before
1043 * allowing it to appear.
1044 */
1045 wait_backlight_on(intel_dp);
1046
1047 with_intel_pps_lock(intel_dp, wakeref) {
1048 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1049 u32 pp;
1050
1051 pp = ilk_get_pp_control(intel_dp);
1052 pp |= EDP_BLC_ENABLE;
1053
1054 intel_de_write(dev_priv, pp_ctrl_reg, pp);
1055 intel_de_posting_read(dev_priv, pp_ctrl_reg);
1056 }
1057 }
1058
1059 /* Disable backlight in the panel power control. */
intel_pps_backlight_off(struct intel_dp * intel_dp)1060 void intel_pps_backlight_off(struct intel_dp *intel_dp)
1061 {
1062 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1063 intel_wakeref_t wakeref;
1064
1065 if (!intel_dp_is_edp(intel_dp))
1066 return;
1067
1068 with_intel_pps_lock(intel_dp, wakeref) {
1069 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1070 u32 pp;
1071
1072 pp = ilk_get_pp_control(intel_dp);
1073 pp &= ~EDP_BLC_ENABLE;
1074
1075 intel_de_write(dev_priv, pp_ctrl_reg, pp);
1076 intel_de_posting_read(dev_priv, pp_ctrl_reg);
1077 }
1078
1079 intel_dp->pps.last_backlight_off = jiffies;
1080 edp_wait_backlight_off(intel_dp);
1081 }
1082
1083 /*
1084 * Hook for controlling the panel power control backlight through the bl_power
1085 * sysfs attribute. Take care to handle multiple calls.
1086 */
intel_pps_backlight_power(struct intel_connector * connector,bool enable)1087 void intel_pps_backlight_power(struct intel_connector *connector, bool enable)
1088 {
1089 struct drm_i915_private *i915 = to_i915(connector->base.dev);
1090 struct intel_dp *intel_dp = intel_attached_dp(connector);
1091 intel_wakeref_t wakeref;
1092 bool is_enabled;
1093
1094 is_enabled = false;
1095 with_intel_pps_lock(intel_dp, wakeref)
1096 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1097 if (is_enabled == enable)
1098 return;
1099
1100 drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
1101 enable ? "enable" : "disable");
1102
1103 if (enable)
1104 intel_pps_backlight_on(intel_dp);
1105 else
1106 intel_pps_backlight_off(intel_dp);
1107 }
1108
vlv_detach_power_sequencer(struct intel_dp * intel_dp)1109 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
1110 {
1111 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1112 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1113 enum pipe pipe = intel_dp->pps.pps_pipe;
1114 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
1115
1116 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
1117
1118 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
1119 return;
1120
1121 intel_pps_vdd_off_sync_unlocked(intel_dp);
1122
1123 /*
1124 * VLV seems to get confused when multiple power sequencers
1125 * have the same port selected (even if only one has power/vdd
1126 * enabled). The failure manifests as vlv_wait_port_ready() failing
1127 * CHV on the other hand doesn't seem to mind having the same port
1128 * selected in multiple power sequencers, but let's clear the
1129 * port select always when logically disconnecting a power sequencer
1130 * from a port.
1131 */
1132 drm_dbg_kms(&dev_priv->drm,
1133 "detaching %s from [ENCODER:%d:%s]\n",
1134 pps_name(dev_priv, &intel_dp->pps),
1135 dig_port->base.base.base.id, dig_port->base.base.name);
1136 intel_de_write(dev_priv, pp_on_reg, 0);
1137 intel_de_posting_read(dev_priv, pp_on_reg);
1138
1139 intel_dp->pps.pps_pipe = INVALID_PIPE;
1140 }
1141
vlv_steal_power_sequencer(struct drm_i915_private * dev_priv,enum pipe pipe)1142 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
1143 enum pipe pipe)
1144 {
1145 struct intel_encoder *encoder;
1146
1147 lockdep_assert_held(&dev_priv->display.pps.mutex);
1148
1149 for_each_intel_dp(&dev_priv->drm, encoder) {
1150 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1151
1152 drm_WARN(&dev_priv->drm, intel_dp->pps.active_pipe == pipe,
1153 "stealing PPS %c from active [ENCODER:%d:%s]\n",
1154 pipe_name(pipe), encoder->base.base.id,
1155 encoder->base.name);
1156
1157 if (intel_dp->pps.pps_pipe != pipe)
1158 continue;
1159
1160 drm_dbg_kms(&dev_priv->drm,
1161 "stealing PPS %c from [ENCODER:%d:%s]\n",
1162 pipe_name(pipe), encoder->base.base.id,
1163 encoder->base.name);
1164
1165 /* make sure vdd is off before we steal it */
1166 vlv_detach_power_sequencer(intel_dp);
1167 }
1168 }
1169
vlv_pps_init(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1170 void vlv_pps_init(struct intel_encoder *encoder,
1171 const struct intel_crtc_state *crtc_state)
1172 {
1173 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1174 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1175 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1176
1177 lockdep_assert_held(&dev_priv->display.pps.mutex);
1178
1179 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
1180
1181 if (intel_dp->pps.pps_pipe != INVALID_PIPE &&
1182 intel_dp->pps.pps_pipe != crtc->pipe) {
1183 /*
1184 * If another power sequencer was being used on this
1185 * port previously make sure to turn off vdd there while
1186 * we still have control of it.
1187 */
1188 vlv_detach_power_sequencer(intel_dp);
1189 }
1190
1191 /*
1192 * We may be stealing the power
1193 * sequencer from another port.
1194 */
1195 vlv_steal_power_sequencer(dev_priv, crtc->pipe);
1196
1197 intel_dp->pps.active_pipe = crtc->pipe;
1198
1199 if (!intel_dp_is_edp(intel_dp))
1200 return;
1201
1202 /* now it's all ours */
1203 intel_dp->pps.pps_pipe = crtc->pipe;
1204
1205 drm_dbg_kms(&dev_priv->drm,
1206 "initializing %s for [ENCODER:%d:%s]\n",
1207 pps_name(dev_priv, &intel_dp->pps),
1208 encoder->base.base.id, encoder->base.name);
1209
1210 /* init power sequencer on this pipe and port */
1211 pps_init_delays(intel_dp);
1212 pps_init_registers(intel_dp, true);
1213 }
1214
pps_vdd_init(struct intel_dp * intel_dp)1215 static void pps_vdd_init(struct intel_dp *intel_dp)
1216 {
1217 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1218 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1219
1220 lockdep_assert_held(&dev_priv->display.pps.mutex);
1221
1222 if (!edp_have_panel_vdd(intel_dp))
1223 return;
1224
1225 /*
1226 * The VDD bit needs a power domain reference, so if the bit is
1227 * already enabled when we boot or resume, grab this reference and
1228 * schedule a vdd off, so we don't hold on to the reference
1229 * indefinitely.
1230 */
1231 drm_dbg_kms(&dev_priv->drm,
1232 "[ENCODER:%d:%s] %s VDD left on by BIOS, adjusting state tracking\n",
1233 dig_port->base.base.base.id, dig_port->base.base.name,
1234 pps_name(dev_priv, &intel_dp->pps));
1235 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
1236 intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
1237 intel_aux_power_domain(dig_port));
1238 }
1239
intel_pps_have_panel_power_or_vdd(struct intel_dp * intel_dp)1240 bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp)
1241 {
1242 intel_wakeref_t wakeref;
1243 bool have_power = false;
1244
1245 with_intel_pps_lock(intel_dp, wakeref) {
1246 have_power = edp_have_panel_power(intel_dp) ||
1247 edp_have_panel_vdd(intel_dp);
1248 }
1249
1250 return have_power;
1251 }
1252
pps_init_timestamps(struct intel_dp * intel_dp)1253 static void pps_init_timestamps(struct intel_dp *intel_dp)
1254 {
1255 /*
1256 * Initialize panel power off time to 0, assuming panel power could have
1257 * been toggled between kernel boot and now only by a previously loaded
1258 * and removed i915, which has already ensured sufficient power off
1259 * delay at module remove.
1260 */
1261 intel_dp->pps.panel_power_off_time = 0;
1262 intel_dp->pps.last_power_on = jiffies;
1263 intel_dp->pps.last_backlight_off = jiffies;
1264 }
1265
1266 static void
intel_pps_readout_hw_state(struct intel_dp * intel_dp,struct edp_power_seq * seq)1267 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
1268 {
1269 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1270 u32 pp_on, pp_off, pp_ctl;
1271 struct pps_registers regs;
1272
1273 intel_pps_get_registers(intel_dp, ®s);
1274
1275 pp_ctl = ilk_get_pp_control(intel_dp);
1276
1277 /* Ensure PPS is unlocked */
1278 if (!HAS_DDI(dev_priv))
1279 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
1280
1281 pp_on = intel_de_read(dev_priv, regs.pp_on);
1282 pp_off = intel_de_read(dev_priv, regs.pp_off);
1283
1284 /* Pull timing values out of registers */
1285 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
1286 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
1287 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
1288 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
1289
1290 if (i915_mmio_reg_valid(regs.pp_div)) {
1291 u32 pp_div;
1292
1293 pp_div = intel_de_read(dev_priv, regs.pp_div);
1294
1295 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
1296 } else {
1297 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
1298 }
1299 }
1300
1301 static void
intel_pps_dump_state(struct intel_dp * intel_dp,const char * state_name,const struct edp_power_seq * seq)1302 intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name,
1303 const struct edp_power_seq *seq)
1304 {
1305 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1306
1307 drm_dbg_kms(&i915->drm, "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
1308 state_name,
1309 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
1310 }
1311
1312 static void
intel_pps_verify_state(struct intel_dp * intel_dp)1313 intel_pps_verify_state(struct intel_dp *intel_dp)
1314 {
1315 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1316 struct edp_power_seq hw;
1317 struct edp_power_seq *sw = &intel_dp->pps.pps_delays;
1318
1319 intel_pps_readout_hw_state(intel_dp, &hw);
1320
1321 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
1322 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
1323 drm_err(&i915->drm, "PPS state mismatch\n");
1324 intel_pps_dump_state(intel_dp, "sw", sw);
1325 intel_pps_dump_state(intel_dp, "hw", &hw);
1326 }
1327 }
1328
pps_delays_valid(struct edp_power_seq * delays)1329 static bool pps_delays_valid(struct edp_power_seq *delays)
1330 {
1331 return delays->t1_t3 || delays->t8 || delays->t9 ||
1332 delays->t10 || delays->t11_t12;
1333 }
1334
pps_init_delays_bios(struct intel_dp * intel_dp,struct edp_power_seq * bios)1335 static void pps_init_delays_bios(struct intel_dp *intel_dp,
1336 struct edp_power_seq *bios)
1337 {
1338 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1339
1340 lockdep_assert_held(&dev_priv->display.pps.mutex);
1341
1342 if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))
1343 intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);
1344
1345 *bios = intel_dp->pps.bios_pps_delays;
1346
1347 intel_pps_dump_state(intel_dp, "bios", bios);
1348 }
1349
pps_init_delays_vbt(struct intel_dp * intel_dp,struct edp_power_seq * vbt)1350 static void pps_init_delays_vbt(struct intel_dp *intel_dp,
1351 struct edp_power_seq *vbt)
1352 {
1353 struct intel_display *display = to_intel_display(intel_dp);
1354 struct intel_connector *connector = intel_dp->attached_connector;
1355
1356 *vbt = connector->panel.vbt.edp.pps;
1357
1358 if (!pps_delays_valid(vbt))
1359 return;
1360
1361 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
1362 * of 500ms appears to be too short. Ocassionally the panel
1363 * just fails to power back on. Increasing the delay to 800ms
1364 * seems sufficient to avoid this problem.
1365 */
1366 if (intel_has_quirk(display, QUIRK_INCREASE_T12_DELAY)) {
1367 vbt->t11_t12 = max_t(u16, vbt->t11_t12, 1300 * 10);
1368 drm_dbg_kms(display->drm,
1369 "Increasing T12 panel delay as per the quirk to %d\n",
1370 vbt->t11_t12);
1371 }
1372
1373 /* T11_T12 delay is special and actually in units of 100ms, but zero
1374 * based in the hw (so we need to add 100 ms). But the sw vbt
1375 * table multiplies it with 1000 to make it in units of 100usec,
1376 * too. */
1377 vbt->t11_t12 += 100 * 10;
1378
1379 intel_pps_dump_state(intel_dp, "vbt", vbt);
1380 }
1381
pps_init_delays_spec(struct intel_dp * intel_dp,struct edp_power_seq * spec)1382 static void pps_init_delays_spec(struct intel_dp *intel_dp,
1383 struct edp_power_seq *spec)
1384 {
1385 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1386
1387 lockdep_assert_held(&dev_priv->display.pps.mutex);
1388
1389 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
1390 * our hw here, which are all in 100usec. */
1391 spec->t1_t3 = 210 * 10;
1392 spec->t8 = 50 * 10; /* no limit for t8, use t7 instead */
1393 spec->t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
1394 spec->t10 = 500 * 10;
1395 /* This one is special and actually in units of 100ms, but zero
1396 * based in the hw (so we need to add 100 ms). But the sw vbt
1397 * table multiplies it with 1000 to make it in units of 100usec,
1398 * too. */
1399 spec->t11_t12 = (510 + 100) * 10;
1400
1401 intel_pps_dump_state(intel_dp, "spec", spec);
1402 }
1403
pps_init_delays(struct intel_dp * intel_dp)1404 static void pps_init_delays(struct intel_dp *intel_dp)
1405 {
1406 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1407 struct edp_power_seq cur, vbt, spec,
1408 *final = &intel_dp->pps.pps_delays;
1409
1410 lockdep_assert_held(&dev_priv->display.pps.mutex);
1411
1412 /* already initialized? */
1413 if (pps_delays_valid(final))
1414 return;
1415
1416 pps_init_delays_bios(intel_dp, &cur);
1417 pps_init_delays_vbt(intel_dp, &vbt);
1418 pps_init_delays_spec(intel_dp, &spec);
1419
1420 /* Use the max of the register settings and vbt. If both are
1421 * unset, fall back to the spec limits. */
1422 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
1423 spec.field : \
1424 max(cur.field, vbt.field))
1425 assign_final(t1_t3);
1426 assign_final(t8);
1427 assign_final(t9);
1428 assign_final(t10);
1429 assign_final(t11_t12);
1430 #undef assign_final
1431
1432 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
1433 intel_dp->pps.panel_power_up_delay = get_delay(t1_t3);
1434 intel_dp->pps.backlight_on_delay = get_delay(t8);
1435 intel_dp->pps.backlight_off_delay = get_delay(t9);
1436 intel_dp->pps.panel_power_down_delay = get_delay(t10);
1437 intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12);
1438 #undef get_delay
1439
1440 drm_dbg_kms(&dev_priv->drm,
1441 "panel power up delay %d, power down delay %d, power cycle delay %d\n",
1442 intel_dp->pps.panel_power_up_delay,
1443 intel_dp->pps.panel_power_down_delay,
1444 intel_dp->pps.panel_power_cycle_delay);
1445
1446 drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
1447 intel_dp->pps.backlight_on_delay,
1448 intel_dp->pps.backlight_off_delay);
1449
1450 /*
1451 * We override the HW backlight delays to 1 because we do manual waits
1452 * on them. For T8, even BSpec recommends doing it. For T9, if we
1453 * don't do this, we'll end up waiting for the backlight off delay
1454 * twice: once when we do the manual sleep, and once when we disable
1455 * the panel and wait for the PP_STATUS bit to become zero.
1456 */
1457 final->t8 = 1;
1458 final->t9 = 1;
1459
1460 /*
1461 * HW has only a 100msec granularity for t11_t12 so round it up
1462 * accordingly.
1463 */
1464 final->t11_t12 = roundup(final->t11_t12, 100 * 10);
1465 }
1466
pps_init_registers(struct intel_dp * intel_dp,bool force_disable_vdd)1467 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd)
1468 {
1469 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1470 u32 pp_on, pp_off, port_sel = 0;
1471 int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
1472 struct pps_registers regs;
1473 enum port port = dp_to_dig_port(intel_dp)->base.port;
1474 const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
1475
1476 lockdep_assert_held(&dev_priv->display.pps.mutex);
1477
1478 intel_pps_get_registers(intel_dp, ®s);
1479
1480 /*
1481 * On some VLV machines the BIOS can leave the VDD
1482 * enabled even on power sequencers which aren't
1483 * hooked up to any port. This would mess up the
1484 * power domain tracking the first time we pick
1485 * one of these power sequencers for use since
1486 * intel_pps_vdd_on_unlocked() would notice that the VDD was
1487 * already on and therefore wouldn't grab the power
1488 * domain reference. Disable VDD first to avoid this.
1489 * This also avoids spuriously turning the VDD on as
1490 * soon as the new power sequencer gets initialized.
1491 */
1492 if (force_disable_vdd) {
1493 u32 pp = ilk_get_pp_control(intel_dp);
1494
1495 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
1496 "Panel power already on\n");
1497
1498 if (pp & EDP_FORCE_VDD)
1499 drm_dbg_kms(&dev_priv->drm,
1500 "VDD already on, disabling first\n");
1501
1502 pp &= ~EDP_FORCE_VDD;
1503
1504 intel_de_write(dev_priv, regs.pp_ctrl, pp);
1505 }
1506
1507 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
1508 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
1509 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
1510 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
1511
1512 /* Haswell doesn't have any port selection bits for the panel
1513 * power sequencer any more. */
1514 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1515 port_sel = PANEL_PORT_SELECT_VLV(port);
1516 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
1517 switch (port) {
1518 case PORT_A:
1519 port_sel = PANEL_PORT_SELECT_DPA;
1520 break;
1521 case PORT_C:
1522 port_sel = PANEL_PORT_SELECT_DPC;
1523 break;
1524 case PORT_D:
1525 port_sel = PANEL_PORT_SELECT_DPD;
1526 break;
1527 default:
1528 MISSING_CASE(port);
1529 break;
1530 }
1531 }
1532
1533 pp_on |= port_sel;
1534
1535 intel_de_write(dev_priv, regs.pp_on, pp_on);
1536 intel_de_write(dev_priv, regs.pp_off, pp_off);
1537
1538 /*
1539 * Compute the divisor for the pp clock, simply match the Bspec formula.
1540 */
1541 if (i915_mmio_reg_valid(regs.pp_div))
1542 intel_de_write(dev_priv, regs.pp_div,
1543 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
1544 else
1545 intel_de_rmw(dev_priv, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK,
1546 REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK,
1547 DIV_ROUND_UP(seq->t11_t12, 1000)));
1548
1549 drm_dbg_kms(&dev_priv->drm,
1550 "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
1551 intel_de_read(dev_priv, regs.pp_on),
1552 intel_de_read(dev_priv, regs.pp_off),
1553 i915_mmio_reg_valid(regs.pp_div) ?
1554 intel_de_read(dev_priv, regs.pp_div) :
1555 (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
1556 }
1557
intel_pps_encoder_reset(struct intel_dp * intel_dp)1558 void intel_pps_encoder_reset(struct intel_dp *intel_dp)
1559 {
1560 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1561 intel_wakeref_t wakeref;
1562
1563 if (!intel_dp_is_edp(intel_dp))
1564 return;
1565
1566 with_intel_pps_lock(intel_dp, wakeref) {
1567 /*
1568 * Reinit the power sequencer also on the resume path, in case
1569 * BIOS did something nasty with it.
1570 */
1571 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1572 vlv_initial_power_sequencer_setup(intel_dp);
1573
1574 pps_init_delays(intel_dp);
1575 pps_init_registers(intel_dp, false);
1576 pps_vdd_init(intel_dp);
1577
1578 if (edp_have_panel_vdd(intel_dp))
1579 edp_panel_vdd_schedule_off(intel_dp);
1580 }
1581 }
1582
intel_pps_init(struct intel_dp * intel_dp)1583 bool intel_pps_init(struct intel_dp *intel_dp)
1584 {
1585 intel_wakeref_t wakeref;
1586 bool ret;
1587
1588 intel_dp->pps.initializing = true;
1589 INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
1590
1591 pps_init_timestamps(intel_dp);
1592
1593 with_intel_pps_lock(intel_dp, wakeref) {
1594 ret = pps_initial_setup(intel_dp);
1595
1596 pps_init_delays(intel_dp);
1597 pps_init_registers(intel_dp, false);
1598 pps_vdd_init(intel_dp);
1599 }
1600
1601 return ret;
1602 }
1603
pps_init_late(struct intel_dp * intel_dp)1604 static void pps_init_late(struct intel_dp *intel_dp)
1605 {
1606 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1607 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1608 struct intel_connector *connector = intel_dp->attached_connector;
1609
1610 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1611 return;
1612
1613 if (intel_num_pps(i915) < 2)
1614 return;
1615
1616 drm_WARN(&i915->drm, connector->panel.vbt.backlight.controller >= 0 &&
1617 intel_dp->pps.pps_idx != connector->panel.vbt.backlight.controller,
1618 "[ENCODER:%d:%s] power sequencer mismatch: %d (initial) vs. %d (VBT)\n",
1619 encoder->base.base.id, encoder->base.name,
1620 intel_dp->pps.pps_idx, connector->panel.vbt.backlight.controller);
1621
1622 if (connector->panel.vbt.backlight.controller >= 0)
1623 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;
1624 }
1625
intel_pps_init_late(struct intel_dp * intel_dp)1626 void intel_pps_init_late(struct intel_dp *intel_dp)
1627 {
1628 intel_wakeref_t wakeref;
1629
1630 with_intel_pps_lock(intel_dp, wakeref) {
1631 /* Reinit delays after per-panel info has been parsed from VBT */
1632 pps_init_late(intel_dp);
1633
1634 memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays));
1635 pps_init_delays(intel_dp);
1636 pps_init_registers(intel_dp, false);
1637
1638 intel_dp->pps.initializing = false;
1639
1640 if (edp_have_panel_vdd(intel_dp))
1641 edp_panel_vdd_schedule_off(intel_dp);
1642 }
1643 }
1644
intel_pps_unlock_regs_wa(struct drm_i915_private * dev_priv)1645 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
1646 {
1647 int pps_num;
1648 int pps_idx;
1649
1650 if (!HAS_DISPLAY(dev_priv) || HAS_DDI(dev_priv))
1651 return;
1652 /*
1653 * This w/a is needed at least on CPT/PPT, but to be sure apply it
1654 * everywhere where registers can be write protected.
1655 */
1656 pps_num = intel_num_pps(dev_priv);
1657
1658 for (pps_idx = 0; pps_idx < pps_num; pps_idx++)
1659 intel_de_rmw(dev_priv, PP_CONTROL(pps_idx),
1660 PANEL_UNLOCK_MASK, PANEL_UNLOCK_REGS);
1661 }
1662
intel_pps_setup(struct drm_i915_private * i915)1663 void intel_pps_setup(struct drm_i915_private *i915)
1664 {
1665 if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915))
1666 i915->display.pps.mmio_base = PCH_PPS_BASE;
1667 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1668 i915->display.pps.mmio_base = VLV_PPS_BASE;
1669 else
1670 i915->display.pps.mmio_base = PPS_BASE;
1671 }
1672
intel_pps_show(struct seq_file * m,void * data)1673 static int intel_pps_show(struct seq_file *m, void *data)
1674 {
1675 struct intel_connector *connector = m->private;
1676 struct intel_dp *intel_dp = intel_attached_dp(connector);
1677
1678 if (connector->base.status != connector_status_connected)
1679 return -ENODEV;
1680
1681 seq_printf(m, "Panel power up delay: %d\n",
1682 intel_dp->pps.panel_power_up_delay);
1683 seq_printf(m, "Panel power down delay: %d\n",
1684 intel_dp->pps.panel_power_down_delay);
1685 seq_printf(m, "Backlight on delay: %d\n",
1686 intel_dp->pps.backlight_on_delay);
1687 seq_printf(m, "Backlight off delay: %d\n",
1688 intel_dp->pps.backlight_off_delay);
1689
1690 return 0;
1691 }
1692 DEFINE_SHOW_ATTRIBUTE(intel_pps);
1693
intel_pps_connector_debugfs_add(struct intel_connector * connector)1694 void intel_pps_connector_debugfs_add(struct intel_connector *connector)
1695 {
1696 struct dentry *root = connector->base.debugfs_entry;
1697 int connector_type = connector->base.connector_type;
1698
1699 if (connector_type == DRM_MODE_CONNECTOR_eDP)
1700 debugfs_create_file("i915_panel_timings", 0444, root,
1701 connector, &intel_pps_fops);
1702 }
1703
assert_pps_unlocked(struct drm_i915_private * dev_priv,enum pipe pipe)1704 void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1705 {
1706 i915_reg_t pp_reg;
1707 u32 val;
1708 enum pipe panel_pipe = INVALID_PIPE;
1709 bool locked = true;
1710
1711 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
1712 return;
1713
1714 if (HAS_PCH_SPLIT(dev_priv)) {
1715 u32 port_sel;
1716
1717 pp_reg = PP_CONTROL(0);
1718 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1719
1720 switch (port_sel) {
1721 case PANEL_PORT_SELECT_LVDS:
1722 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1723 break;
1724 case PANEL_PORT_SELECT_DPA:
1725 g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1726 break;
1727 case PANEL_PORT_SELECT_DPC:
1728 g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1729 break;
1730 case PANEL_PORT_SELECT_DPD:
1731 g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1732 break;
1733 default:
1734 MISSING_CASE(port_sel);
1735 break;
1736 }
1737 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1738 /* presumably write lock depends on pipe, not port select */
1739 pp_reg = PP_CONTROL(pipe);
1740 panel_pipe = pipe;
1741 } else {
1742 u32 port_sel;
1743
1744 pp_reg = PP_CONTROL(0);
1745 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1746
1747 drm_WARN_ON(&dev_priv->drm,
1748 port_sel != PANEL_PORT_SELECT_LVDS);
1749 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1750 }
1751
1752 val = intel_de_read(dev_priv, pp_reg);
1753 if (!(val & PANEL_POWER_ON) ||
1754 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1755 locked = false;
1756
1757 I915_STATE_WARN(dev_priv, panel_pipe == pipe && locked,
1758 "panel assertion failure, pipe %c regs locked\n",
1759 pipe_name(pipe));
1760 }
1761