1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: src/sys/i386/isa/intr_machdep.h,v 1.19.2.2 2001/10/14 20:05:50 luigi Exp $ 31 */ 32 33 #ifndef _ARCH_INTR_MACHDEP_H_ 34 #define _ARCH_INTR_MACHDEP_H_ 35 36 #ifndef LOCORE 37 #ifndef _SYS_TYPES_H_ 38 #include <sys/types.h> 39 #endif 40 #endif 41 42 /* 43 * Low level interrupt code. 44 */ 45 46 #ifdef _KERNEL 47 48 #define IDT_OFFSET 0x20 49 #define IDT_OFFSET_SYSCALL 0x80 50 #define IDT_OFFSET_IPI 0xe0 51 52 #define IDT_HWI_VECTORS (IDT_OFFSET_IPI - IDT_OFFSET) 53 54 /* 55 * Local APIC TPR priority vector levels: 56 * 57 * 0xff (255) +-------------+ 58 * | | 15 (IPIs: Xcpustop, Xspuriousint) 59 * 0xf0 (240) +-------------+ 60 * | | 14 (IPIs: Xinvltlb, Xipiq, Xtimer, Xsniff) 61 * 0xe0 (224) +-------------+ 62 * | | 13 63 * 0xd0 (208) +-------------+ 64 * | | 12 65 * 0xc0 (192) +-------------+ 66 * | | 11 67 * 0xb0 (176) +-------------+ 68 * | | 10 69 * 0xa0 (160) +-------------+ 70 * | | 9 71 * 0x90 (144) +-------------+ 72 * | | 8 (syscall at 0x80) 73 * 0x80 (128) +-------------+ 74 * | | 7 75 * 0x70 (112) +-------------+ 76 * | | 6 77 * 0x60 (96) +-------------+ 78 * | | 5 79 * 0x50 (80) +-------------+ 80 * | | 4 81 * 0x40 (64) +-------------+ 82 * | | 3 83 * 0x30 (48) +-------------+ 84 * | | 2 (hardware INTs) 85 * 0x20 (32) +-------------+ 86 * | | 1 (exceptions, traps, etc.) 87 * 0x10 (16) +-------------+ 88 * | | 0 (exceptions, traps, etc.) 89 * 0x00 (0) +-------------+ 90 */ 91 #define TPR_STEP 0x10 92 93 /* Local APIC Task Priority Register */ 94 #define TPR_IPI (IDT_OFFSET_IPI - 1) 95 96 97 /* 98 * IPI group1 99 */ 100 #define IDT_OFFSET_IPIG1 IDT_OFFSET_IPI 101 102 /* TLB shootdowns */ 103 #define XINVLTLB_OFFSET (IDT_OFFSET_IPIG1 + 0) 104 105 /* IPI group1 1: unused (was inter-cpu clock handling) */ 106 /* IPI group1 2: unused (was inter-cpu rendezvous) */ 107 108 /* IPIQ rendezvous */ 109 #define XIPIQ_OFFSET (IDT_OFFSET_IPIG1 + 3) 110 111 /* TIMER rendezvous */ 112 #define XTIMER_OFFSET (IDT_OFFSET_IPIG1 + 4) 113 114 /* SNIFF rendezvous */ 115 #define XSNIFF_OFFSET (IDT_OFFSET_IPIG1 + 5) 116 117 /* IPI group1 6 ~ 15: unused */ 118 119 120 /* 121 * IPI group2 122 */ 123 #define IDT_OFFSET_IPIG2 (IDT_OFFSET_IPIG1 + TPR_STEP) 124 125 /* IPI to signal CPUs to stop and wait for another CPU to restart them */ 126 #define XCPUSTOP_OFFSET (IDT_OFFSET_IPIG2 + 0) 127 128 /* IPI group2 1 ~ 14: unused */ 129 130 /* NOTE: this vector MUST be xxxx1111 */ 131 #define XSPURIOUSINT_OFFSET (IDT_OFFSET_IPIG2 + 15) 132 133 #ifndef LOCORE 134 135 /* 136 * Type of the first (asm) part of an interrupt handler. 137 */ 138 typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss); 139 140 #define IDTVEC(name) __CONCAT(X,name) 141 142 inthand_t 143 Xspuriousint, /* handle APIC "spurious INTs" */ 144 Xtimer; /* handle per-cpu timer INT */ 145 146 inthand_t 147 Xinvltlb, /* TLB shootdowns */ 148 Xcpustop, /* CPU stops & waits for another CPU to restart it */ 149 Xipiq, /* handle lwkt_send_ipiq() requests */ 150 Xsniff; /* sniff CPU */ 151 152 #endif /* LOCORE */ 153 154 #endif /* _KERNEL */ 155 156 #endif /* !_ARCH_INTR_MACHDEP_H_ */ 157