1 //===-- RISCVRegisterInfo.cpp - RISC-V Register Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISC-V implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "RISCVRegisterInfo.h"
14 #include "RISCV.h"
15 #include "RISCVMachineFunctionInfo.h"
16 #include "RISCVSubtarget.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/BinaryFormat/Dwarf.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/CodeGen/TargetFrameLowering.h"
24 #include "llvm/CodeGen/TargetInstrInfo.h"
25 #include "llvm/IR/DebugInfoMetadata.h"
26 #include "llvm/Support/ErrorHandling.h"
27
28 #define GET_REGINFO_TARGET_DESC
29 #include "RISCVGenRegisterInfo.inc"
30
31 using namespace llvm;
32
33 static cl::opt<bool>
34 DisableRegAllocHints("riscv-disable-regalloc-hints", cl::Hidden,
35 cl::init(false),
36 cl::desc("Disable two address hints for register "
37 "allocation"));
38
39 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
40 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
41 static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
42 static_assert(RISCV::F31_H == RISCV::F0_H + 31,
43 "Register list not consecutive");
44 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
45 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
46 "Register list not consecutive");
47 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
48 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
49 "Register list not consecutive");
50 static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
51 static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
52
RISCVRegisterInfo(unsigned HwMode)53 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
54 : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
55 /*PC*/0, HwMode) {}
56
57 const MCPhysReg *
getCalleeSavedRegs(const MachineFunction * MF) const58 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
59 auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
60 if (MF->getFunction().getCallingConv() == CallingConv::GHC)
61 return CSR_NoRegs_SaveList;
62 if (MF->getFunction().hasFnAttribute("interrupt")) {
63 if (Subtarget.hasStdExtD())
64 return CSR_XLEN_F64_Interrupt_SaveList;
65 if (Subtarget.hasStdExtF())
66 return Subtarget.isRVE() ? CSR_XLEN_F32_Interrupt_RVE_SaveList
67 : CSR_XLEN_F32_Interrupt_SaveList;
68 return Subtarget.isRVE() ? CSR_Interrupt_RVE_SaveList
69 : CSR_Interrupt_SaveList;
70 }
71
72 switch (Subtarget.getTargetABI()) {
73 default:
74 llvm_unreachable("Unrecognized ABI");
75 case RISCVABI::ABI_ILP32E:
76 case RISCVABI::ABI_LP64E:
77 return CSR_ILP32E_LP64E_SaveList;
78 case RISCVABI::ABI_ILP32:
79 case RISCVABI::ABI_LP64:
80 return CSR_ILP32_LP64_SaveList;
81 case RISCVABI::ABI_ILP32F:
82 case RISCVABI::ABI_LP64F:
83 return CSR_ILP32F_LP64F_SaveList;
84 case RISCVABI::ABI_ILP32D:
85 case RISCVABI::ABI_LP64D:
86 return CSR_ILP32D_LP64D_SaveList;
87 }
88 }
89
getReservedRegs(const MachineFunction & MF) const90 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
91 const RISCVFrameLowering *TFI = getFrameLowering(MF);
92 BitVector Reserved(getNumRegs());
93 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
94
95 // Mark any registers requested to be reserved as such
96 for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
97 if (Subtarget.isRegisterReservedByUser(Reg))
98 markSuperRegs(Reserved, Reg);
99 }
100
101 // Use markSuperRegs to ensure any register aliases are also reserved
102 markSuperRegs(Reserved, RISCV::X0); // zero
103 markSuperRegs(Reserved, RISCV::X2); // sp
104 markSuperRegs(Reserved, RISCV::X3); // gp
105 markSuperRegs(Reserved, RISCV::X4); // tp
106 if (TFI->hasFP(MF))
107 markSuperRegs(Reserved, RISCV::X8); // fp
108 // Reserve the base register if we need to realign the stack and allocate
109 // variable-sized objects at runtime.
110 if (TFI->hasBP(MF))
111 markSuperRegs(Reserved, RISCVABI::getBPReg()); // bp
112
113 // Additionally reserve dummy register used to form the register pair
114 // beginning with 'x0' for instructions that take register pairs.
115 markSuperRegs(Reserved, RISCV::DUMMY_REG_PAIR_WITH_X0);
116
117 // There are only 16 GPRs for RVE.
118 if (Subtarget.isRVE())
119 for (MCPhysReg Reg = RISCV::X16; Reg <= RISCV::X31; Reg++)
120 markSuperRegs(Reserved, Reg);
121
122 // V registers for code generation. We handle them manually.
123 markSuperRegs(Reserved, RISCV::VL);
124 markSuperRegs(Reserved, RISCV::VTYPE);
125 markSuperRegs(Reserved, RISCV::VXSAT);
126 markSuperRegs(Reserved, RISCV::VXRM);
127 markSuperRegs(Reserved, RISCV::VLENB); // vlenb (constant)
128
129 // Floating point environment registers.
130 markSuperRegs(Reserved, RISCV::FRM);
131 markSuperRegs(Reserved, RISCV::FFLAGS);
132
133 if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
134 if (Subtarget.isRVE())
135 report_fatal_error("Graal reserved registers do not exist in RVE");
136 markSuperRegs(Reserved, RISCV::X23);
137 markSuperRegs(Reserved, RISCV::X27);
138 }
139
140 // Shadow stack pointer.
141 markSuperRegs(Reserved, RISCV::SSP);
142
143 assert(checkAllSuperRegsMarked(Reserved));
144 return Reserved;
145 }
146
isAsmClobberable(const MachineFunction & MF,MCRegister PhysReg) const147 bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
148 MCRegister PhysReg) const {
149 return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
150 }
151
getNoPreservedMask() const152 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
153 return CSR_NoRegs_RegMask;
154 }
155
156 // Frame indexes representing locations of CSRs which are given a fixed location
157 // by save/restore libcalls or Zcmp Push/Pop.
158 static const std::pair<unsigned, int> FixedCSRFIMap[] = {
159 {/*ra*/ RISCV::X1, -1},
160 {/*s0*/ RISCV::X8, -2},
161 {/*s1*/ RISCV::X9, -3},
162 {/*s2*/ RISCV::X18, -4},
163 {/*s3*/ RISCV::X19, -5},
164 {/*s4*/ RISCV::X20, -6},
165 {/*s5*/ RISCV::X21, -7},
166 {/*s6*/ RISCV::X22, -8},
167 {/*s7*/ RISCV::X23, -9},
168 {/*s8*/ RISCV::X24, -10},
169 {/*s9*/ RISCV::X25, -11},
170 {/*s10*/ RISCV::X26, -12},
171 {/*s11*/ RISCV::X27, -13}
172 };
173
hasReservedSpillSlot(const MachineFunction & MF,Register Reg,int & FrameIdx) const174 bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
175 Register Reg,
176 int &FrameIdx) const {
177 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
178 if (!RVFI->useSaveRestoreLibCalls(MF) && !RVFI->isPushable(MF))
179 return false;
180
181 const auto *FII =
182 llvm::find_if(FixedCSRFIMap, [&](auto P) { return P.first == Reg; });
183 if (FII == std::end(FixedCSRFIMap))
184 return false;
185
186 FrameIdx = FII->second;
187 return true;
188 }
189
adjustReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator II,const DebugLoc & DL,Register DestReg,Register SrcReg,StackOffset Offset,MachineInstr::MIFlag Flag,MaybeAlign RequiredAlign) const190 void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
191 MachineBasicBlock::iterator II,
192 const DebugLoc &DL, Register DestReg,
193 Register SrcReg, StackOffset Offset,
194 MachineInstr::MIFlag Flag,
195 MaybeAlign RequiredAlign) const {
196
197 if (DestReg == SrcReg && !Offset.getFixed() && !Offset.getScalable())
198 return;
199
200 MachineFunction &MF = *MBB.getParent();
201 MachineRegisterInfo &MRI = MF.getRegInfo();
202 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
203 const RISCVInstrInfo *TII = ST.getInstrInfo();
204
205 bool KillSrcReg = false;
206
207 if (Offset.getScalable()) {
208 unsigned ScalableAdjOpc = RISCV::ADD;
209 int64_t ScalableValue = Offset.getScalable();
210 if (ScalableValue < 0) {
211 ScalableValue = -ScalableValue;
212 ScalableAdjOpc = RISCV::SUB;
213 }
214 // Get vlenb and multiply vlen with the number of vector registers.
215 Register ScratchReg = DestReg;
216 if (DestReg == SrcReg)
217 ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
218 TII->getVLENFactoredAmount(MF, MBB, II, DL, ScratchReg, ScalableValue, Flag);
219 BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), DestReg)
220 .addReg(SrcReg).addReg(ScratchReg, RegState::Kill)
221 .setMIFlag(Flag);
222 SrcReg = DestReg;
223 KillSrcReg = true;
224 }
225
226 int64_t Val = Offset.getFixed();
227 if (DestReg == SrcReg && Val == 0)
228 return;
229
230 const uint64_t Align = RequiredAlign.valueOrOne().value();
231
232 if (isInt<12>(Val)) {
233 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg)
234 .addReg(SrcReg, getKillRegState(KillSrcReg))
235 .addImm(Val)
236 .setMIFlag(Flag);
237 return;
238 }
239
240 // Try to split the offset across two ADDIs. We need to keep the intermediate
241 // result aligned after each ADDI. We need to determine the maximum value we
242 // can put in each ADDI. In the negative direction, we can use -2048 which is
243 // always sufficiently aligned. In the positive direction, we need to find the
244 // largest 12-bit immediate that is aligned. Exclude -4096 since it can be
245 // created with LUI.
246 assert(Align < 2048 && "Required alignment too large");
247 int64_t MaxPosAdjStep = 2048 - Align;
248 if (Val > -4096 && Val <= (2 * MaxPosAdjStep)) {
249 int64_t FirstAdj = Val < 0 ? -2048 : MaxPosAdjStep;
250 Val -= FirstAdj;
251 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg)
252 .addReg(SrcReg, getKillRegState(KillSrcReg))
253 .addImm(FirstAdj)
254 .setMIFlag(Flag);
255 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg)
256 .addReg(DestReg, RegState::Kill)
257 .addImm(Val)
258 .setMIFlag(Flag);
259 return;
260 }
261
262 unsigned Opc = RISCV::ADD;
263 if (Val < 0) {
264 Val = -Val;
265 Opc = RISCV::SUB;
266 }
267
268 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
269 TII->movImm(MBB, II, DL, ScratchReg, Val, Flag);
270 BuildMI(MBB, II, DL, TII->get(Opc), DestReg)
271 .addReg(SrcReg, getKillRegState(KillSrcReg))
272 .addReg(ScratchReg, RegState::Kill)
273 .setMIFlag(Flag);
274 }
275
276 // Split a VSPILLx_Mx pseudo into multiple whole register stores separated by
277 // LMUL*VLENB bytes.
lowerVSPILL(MachineBasicBlock::iterator II) const278 void RISCVRegisterInfo::lowerVSPILL(MachineBasicBlock::iterator II) const {
279 DebugLoc DL = II->getDebugLoc();
280 MachineBasicBlock &MBB = *II->getParent();
281 MachineFunction &MF = *MBB.getParent();
282 MachineRegisterInfo &MRI = MF.getRegInfo();
283 const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
284 const TargetInstrInfo *TII = STI.getInstrInfo();
285 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
286
287 auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(II->getOpcode());
288 unsigned NF = ZvlssegInfo->first;
289 unsigned LMUL = ZvlssegInfo->second;
290 assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations.");
291 unsigned Opcode, SubRegIdx;
292 switch (LMUL) {
293 default:
294 llvm_unreachable("LMUL must be 1, 2, or 4.");
295 case 1:
296 Opcode = RISCV::VS1R_V;
297 SubRegIdx = RISCV::sub_vrm1_0;
298 break;
299 case 2:
300 Opcode = RISCV::VS2R_V;
301 SubRegIdx = RISCV::sub_vrm2_0;
302 break;
303 case 4:
304 Opcode = RISCV::VS4R_V;
305 SubRegIdx = RISCV::sub_vrm4_0;
306 break;
307 }
308 static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7,
309 "Unexpected subreg numbering");
310 static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3,
311 "Unexpected subreg numbering");
312 static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1,
313 "Unexpected subreg numbering");
314
315 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
316 // Optimize for constant VLEN.
317 if (STI.getRealMinVLen() == STI.getRealMaxVLen()) {
318 const int64_t VLENB = STI.getRealMinVLen() / 8;
319 int64_t Offset = VLENB * LMUL;
320 STI.getInstrInfo()->movImm(MBB, II, DL, VL, Offset);
321 } else {
322 BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
323 uint32_t ShiftAmount = Log2_32(LMUL);
324 if (ShiftAmount != 0)
325 BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
326 .addReg(VL)
327 .addImm(ShiftAmount);
328 }
329
330 Register SrcReg = II->getOperand(0).getReg();
331 Register Base = II->getOperand(1).getReg();
332 bool IsBaseKill = II->getOperand(1).isKill();
333 Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass);
334 for (unsigned I = 0; I < NF; ++I) {
335 // Adding implicit-use of super register to describe we are using part of
336 // super register, that prevents machine verifier complaining when part of
337 // subreg is undef, see comment in MachineVerifier::checkLiveness for more
338 // detail.
339 BuildMI(MBB, II, DL, TII->get(Opcode))
340 .addReg(TRI->getSubReg(SrcReg, SubRegIdx + I))
341 .addReg(Base, getKillRegState(I == NF - 1))
342 .addMemOperand(*(II->memoperands_begin()))
343 .addReg(SrcReg, RegState::Implicit);
344 if (I != NF - 1)
345 BuildMI(MBB, II, DL, TII->get(RISCV::ADD), NewBase)
346 .addReg(Base, getKillRegState(I != 0 || IsBaseKill))
347 .addReg(VL, getKillRegState(I == NF - 2));
348 Base = NewBase;
349 }
350 II->eraseFromParent();
351 }
352
353 // Split a VSPILLx_Mx pseudo into multiple whole register loads separated by
354 // LMUL*VLENB bytes.
lowerVRELOAD(MachineBasicBlock::iterator II) const355 void RISCVRegisterInfo::lowerVRELOAD(MachineBasicBlock::iterator II) const {
356 DebugLoc DL = II->getDebugLoc();
357 MachineBasicBlock &MBB = *II->getParent();
358 MachineFunction &MF = *MBB.getParent();
359 MachineRegisterInfo &MRI = MF.getRegInfo();
360 const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
361 const TargetInstrInfo *TII = STI.getInstrInfo();
362 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
363
364 auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(II->getOpcode());
365 unsigned NF = ZvlssegInfo->first;
366 unsigned LMUL = ZvlssegInfo->second;
367 assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations.");
368 unsigned Opcode, SubRegIdx;
369 switch (LMUL) {
370 default:
371 llvm_unreachable("LMUL must be 1, 2, or 4.");
372 case 1:
373 Opcode = RISCV::VL1RE8_V;
374 SubRegIdx = RISCV::sub_vrm1_0;
375 break;
376 case 2:
377 Opcode = RISCV::VL2RE8_V;
378 SubRegIdx = RISCV::sub_vrm2_0;
379 break;
380 case 4:
381 Opcode = RISCV::VL4RE8_V;
382 SubRegIdx = RISCV::sub_vrm4_0;
383 break;
384 }
385 static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7,
386 "Unexpected subreg numbering");
387 static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3,
388 "Unexpected subreg numbering");
389 static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1,
390 "Unexpected subreg numbering");
391
392 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
393 // Optimize for constant VLEN.
394 if (STI.getRealMinVLen() == STI.getRealMaxVLen()) {
395 const int64_t VLENB = STI.getRealMinVLen() / 8;
396 int64_t Offset = VLENB * LMUL;
397 STI.getInstrInfo()->movImm(MBB, II, DL, VL, Offset);
398 } else {
399 BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
400 uint32_t ShiftAmount = Log2_32(LMUL);
401 if (ShiftAmount != 0)
402 BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
403 .addReg(VL)
404 .addImm(ShiftAmount);
405 }
406
407 Register DestReg = II->getOperand(0).getReg();
408 Register Base = II->getOperand(1).getReg();
409 bool IsBaseKill = II->getOperand(1).isKill();
410 Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass);
411 for (unsigned I = 0; I < NF; ++I) {
412 BuildMI(MBB, II, DL, TII->get(Opcode),
413 TRI->getSubReg(DestReg, SubRegIdx + I))
414 .addReg(Base, getKillRegState(I == NF - 1))
415 .addMemOperand(*(II->memoperands_begin()));
416 if (I != NF - 1)
417 BuildMI(MBB, II, DL, TII->get(RISCV::ADD), NewBase)
418 .addReg(Base, getKillRegState(I != 0 || IsBaseKill))
419 .addReg(VL, getKillRegState(I == NF - 2));
420 Base = NewBase;
421 }
422 II->eraseFromParent();
423 }
424
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const425 bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
426 int SPAdj, unsigned FIOperandNum,
427 RegScavenger *RS) const {
428 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
429
430 MachineInstr &MI = *II;
431 MachineFunction &MF = *MI.getParent()->getParent();
432 MachineRegisterInfo &MRI = MF.getRegInfo();
433 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
434 DebugLoc DL = MI.getDebugLoc();
435
436 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
437 Register FrameReg;
438 StackOffset Offset =
439 getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg);
440 bool IsRVVSpill = RISCV::isRVVSpill(MI);
441 if (!IsRVVSpill)
442 Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
443
444 if (Offset.getScalable() &&
445 ST.getRealMinVLen() == ST.getRealMaxVLen()) {
446 // For an exact VLEN value, scalable offsets become constant and thus
447 // can be converted entirely into fixed offsets.
448 int64_t FixedValue = Offset.getFixed();
449 int64_t ScalableValue = Offset.getScalable();
450 assert(ScalableValue % 8 == 0 &&
451 "Scalable offset is not a multiple of a single vector size.");
452 int64_t NumOfVReg = ScalableValue / 8;
453 int64_t VLENB = ST.getRealMinVLen() / 8;
454 Offset = StackOffset::getFixed(FixedValue + NumOfVReg * VLENB);
455 }
456
457 if (!isInt<32>(Offset.getFixed())) {
458 report_fatal_error(
459 "Frame offsets outside of the signed 32-bit range not supported");
460 }
461
462 if (!IsRVVSpill) {
463 if (MI.getOpcode() == RISCV::ADDI && !isInt<12>(Offset.getFixed())) {
464 // We chose to emit the canonical immediate sequence rather than folding
465 // the offset into the using add under the theory that doing so doesn't
466 // save dynamic instruction count and some target may fuse the canonical
467 // 32 bit immediate sequence. We still need to clear the portion of the
468 // offset encoded in the immediate.
469 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
470 } else {
471 // We can encode an add with 12 bit signed immediate in the immediate
472 // operand of our user instruction. As a result, the remaining
473 // offset can by construction, at worst, a LUI and a ADD.
474 int64_t Val = Offset.getFixed();
475 int64_t Lo12 = SignExtend64<12>(Val);
476 if ((MI.getOpcode() == RISCV::PREFETCH_I ||
477 MI.getOpcode() == RISCV::PREFETCH_R ||
478 MI.getOpcode() == RISCV::PREFETCH_W) &&
479 (Lo12 & 0b11111) != 0)
480 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
481 else {
482 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Lo12);
483 Offset = StackOffset::get((uint64_t)Val - (uint64_t)Lo12,
484 Offset.getScalable());
485 }
486 }
487 }
488
489 if (Offset.getScalable() || Offset.getFixed()) {
490 Register DestReg;
491 if (MI.getOpcode() == RISCV::ADDI)
492 DestReg = MI.getOperand(0).getReg();
493 else
494 DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
495 adjustReg(*II->getParent(), II, DL, DestReg, FrameReg, Offset,
496 MachineInstr::NoFlags, std::nullopt);
497 MI.getOperand(FIOperandNum).ChangeToRegister(DestReg, /*IsDef*/false,
498 /*IsImp*/false,
499 /*IsKill*/true);
500 } else {
501 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*IsDef*/false,
502 /*IsImp*/false,
503 /*IsKill*/false);
504 }
505
506 // If after materializing the adjustment, we have a pointless ADDI, remove it
507 if (MI.getOpcode() == RISCV::ADDI &&
508 MI.getOperand(0).getReg() == MI.getOperand(1).getReg() &&
509 MI.getOperand(2).getImm() == 0) {
510 MI.eraseFromParent();
511 return true;
512 }
513
514 // Handle spill/fill of synthetic register classes for segment operations to
515 // ensure correctness in the edge case one gets spilled. There are many
516 // possible optimizations here, but given the extreme rarity of such spills,
517 // we prefer simplicity of implementation for now.
518 switch (MI.getOpcode()) {
519 case RISCV::PseudoVSPILL2_M1:
520 case RISCV::PseudoVSPILL2_M2:
521 case RISCV::PseudoVSPILL2_M4:
522 case RISCV::PseudoVSPILL3_M1:
523 case RISCV::PseudoVSPILL3_M2:
524 case RISCV::PseudoVSPILL4_M1:
525 case RISCV::PseudoVSPILL4_M2:
526 case RISCV::PseudoVSPILL5_M1:
527 case RISCV::PseudoVSPILL6_M1:
528 case RISCV::PseudoVSPILL7_M1:
529 case RISCV::PseudoVSPILL8_M1:
530 lowerVSPILL(II);
531 return true;
532 case RISCV::PseudoVRELOAD2_M1:
533 case RISCV::PseudoVRELOAD2_M2:
534 case RISCV::PseudoVRELOAD2_M4:
535 case RISCV::PseudoVRELOAD3_M1:
536 case RISCV::PseudoVRELOAD3_M2:
537 case RISCV::PseudoVRELOAD4_M1:
538 case RISCV::PseudoVRELOAD4_M2:
539 case RISCV::PseudoVRELOAD5_M1:
540 case RISCV::PseudoVRELOAD6_M1:
541 case RISCV::PseudoVRELOAD7_M1:
542 case RISCV::PseudoVRELOAD8_M1:
543 lowerVRELOAD(II);
544 return true;
545 }
546
547 return false;
548 }
549
requiresVirtualBaseRegisters(const MachineFunction & MF) const550 bool RISCVRegisterInfo::requiresVirtualBaseRegisters(
551 const MachineFunction &MF) const {
552 return true;
553 }
554
555 // Returns true if the instruction's frame index reference would be better
556 // served by a base register other than FP or SP.
557 // Used by LocalStackSlotAllocation pass to determine which frame index
558 // references it should create new base registers for.
needsFrameBaseReg(MachineInstr * MI,int64_t Offset) const559 bool RISCVRegisterInfo::needsFrameBaseReg(MachineInstr *MI,
560 int64_t Offset) const {
561 unsigned FIOperandNum = 0;
562 for (; !MI->getOperand(FIOperandNum).isFI(); FIOperandNum++)
563 assert(FIOperandNum < MI->getNumOperands() &&
564 "Instr doesn't have FrameIndex operand");
565
566 // For RISC-V, The machine instructions that include a FrameIndex operand
567 // are load/store, ADDI instructions.
568 unsigned MIFrm = RISCVII::getFormat(MI->getDesc().TSFlags);
569 if (MIFrm != RISCVII::InstFormatI && MIFrm != RISCVII::InstFormatS)
570 return false;
571 // We only generate virtual base registers for loads and stores, so
572 // return false for everything else.
573 if (!MI->mayLoad() && !MI->mayStore())
574 return false;
575
576 const MachineFunction &MF = *MI->getMF();
577 const MachineFrameInfo &MFI = MF.getFrameInfo();
578 const RISCVFrameLowering *TFI = getFrameLowering(MF);
579 const MachineRegisterInfo &MRI = MF.getRegInfo();
580 unsigned CalleeSavedSize = 0;
581 Offset += getFrameIndexInstrOffset(MI, FIOperandNum);
582
583 // Estimate the stack size used to store callee saved registers(
584 // excludes reserved registers).
585 BitVector ReservedRegs = getReservedRegs(MF);
586 for (const MCPhysReg *R = MRI.getCalleeSavedRegs(); MCPhysReg Reg = *R; ++R) {
587 if (!ReservedRegs.test(Reg))
588 CalleeSavedSize += getSpillSize(*getMinimalPhysRegClass(Reg));
589 }
590
591 int64_t MaxFPOffset = Offset - CalleeSavedSize;
592 if (TFI->hasFP(MF) && !shouldRealignStack(MF))
593 return !isFrameOffsetLegal(MI, RISCV::X8, MaxFPOffset);
594
595 // Assume 128 bytes spill slots size to estimate the maximum possible
596 // offset relative to the stack pointer.
597 // FIXME: The 128 is copied from ARM. We should run some statistics and pick a
598 // real one for RISC-V.
599 int64_t MaxSPOffset = Offset + 128;
600 MaxSPOffset += MFI.getLocalFrameSize();
601 return !isFrameOffsetLegal(MI, RISCV::X2, MaxSPOffset);
602 }
603
604 // Determine whether a given base register plus offset immediate is
605 // encodable to resolve a frame index.
isFrameOffsetLegal(const MachineInstr * MI,Register BaseReg,int64_t Offset) const606 bool RISCVRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
607 Register BaseReg,
608 int64_t Offset) const {
609 unsigned FIOperandNum = 0;
610 while (!MI->getOperand(FIOperandNum).isFI()) {
611 FIOperandNum++;
612 assert(FIOperandNum < MI->getNumOperands() &&
613 "Instr does not have a FrameIndex operand!");
614 }
615
616 Offset += getFrameIndexInstrOffset(MI, FIOperandNum);
617 return isInt<12>(Offset);
618 }
619
620 // Insert defining instruction(s) for a pointer to FrameIdx before
621 // insertion point I.
622 // Return materialized frame pointer.
materializeFrameBaseRegister(MachineBasicBlock * MBB,int FrameIdx,int64_t Offset) const623 Register RISCVRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
624 int FrameIdx,
625 int64_t Offset) const {
626 MachineBasicBlock::iterator MBBI = MBB->begin();
627 DebugLoc DL;
628 if (MBBI != MBB->end())
629 DL = MBBI->getDebugLoc();
630 MachineFunction *MF = MBB->getParent();
631 MachineRegisterInfo &MFI = MF->getRegInfo();
632 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
633
634 Register BaseReg = MFI.createVirtualRegister(&RISCV::GPRRegClass);
635 BuildMI(*MBB, MBBI, DL, TII->get(RISCV::ADDI), BaseReg)
636 .addFrameIndex(FrameIdx)
637 .addImm(Offset);
638 return BaseReg;
639 }
640
641 // Resolve a frame index operand of an instruction to reference the
642 // indicated base register plus offset instead.
resolveFrameIndex(MachineInstr & MI,Register BaseReg,int64_t Offset) const643 void RISCVRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
644 int64_t Offset) const {
645 unsigned FIOperandNum = 0;
646 while (!MI.getOperand(FIOperandNum).isFI()) {
647 FIOperandNum++;
648 assert(FIOperandNum < MI.getNumOperands() &&
649 "Instr does not have a FrameIndex operand!");
650 }
651
652 Offset += getFrameIndexInstrOffset(&MI, FIOperandNum);
653 // FrameIndex Operands are always represented as a
654 // register followed by an immediate.
655 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
656 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
657 }
658
659 // Get the offset from the referenced frame index in the instruction,
660 // if there is one.
getFrameIndexInstrOffset(const MachineInstr * MI,int Idx) const661 int64_t RISCVRegisterInfo::getFrameIndexInstrOffset(const MachineInstr *MI,
662 int Idx) const {
663 assert((RISCVII::getFormat(MI->getDesc().TSFlags) == RISCVII::InstFormatI ||
664 RISCVII::getFormat(MI->getDesc().TSFlags) == RISCVII::InstFormatS) &&
665 "The MI must be I or S format.");
666 assert(MI->getOperand(Idx).isFI() && "The Idx'th operand of MI is not a "
667 "FrameIndex operand");
668 return MI->getOperand(Idx + 1).getImm();
669 }
670
getFrameRegister(const MachineFunction & MF) const671 Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
672 const TargetFrameLowering *TFI = getFrameLowering(MF);
673 return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
674 }
675
676 const uint32_t *
getCallPreservedMask(const MachineFunction & MF,CallingConv::ID CC) const677 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
678 CallingConv::ID CC) const {
679 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
680
681 if (CC == CallingConv::GHC)
682 return CSR_NoRegs_RegMask;
683 switch (Subtarget.getTargetABI()) {
684 default:
685 llvm_unreachable("Unrecognized ABI");
686 case RISCVABI::ABI_ILP32E:
687 case RISCVABI::ABI_LP64E:
688 return CSR_ILP32E_LP64E_RegMask;
689 case RISCVABI::ABI_ILP32:
690 case RISCVABI::ABI_LP64:
691 return CSR_ILP32_LP64_RegMask;
692 case RISCVABI::ABI_ILP32F:
693 case RISCVABI::ABI_LP64F:
694 return CSR_ILP32F_LP64F_RegMask;
695 case RISCVABI::ABI_ILP32D:
696 case RISCVABI::ABI_LP64D:
697 return CSR_ILP32D_LP64D_RegMask;
698 }
699 }
700
701 const TargetRegisterClass *
getLargestLegalSuperClass(const TargetRegisterClass * RC,const MachineFunction &) const702 RISCVRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
703 const MachineFunction &) const {
704 if (RC == &RISCV::VMV0RegClass)
705 return &RISCV::VRRegClass;
706 if (RC == &RISCV::VRNoV0RegClass)
707 return &RISCV::VRRegClass;
708 if (RC == &RISCV::VRM2NoV0RegClass)
709 return &RISCV::VRM2RegClass;
710 if (RC == &RISCV::VRM4NoV0RegClass)
711 return &RISCV::VRM4RegClass;
712 if (RC == &RISCV::VRM8NoV0RegClass)
713 return &RISCV::VRM8RegClass;
714 return RC;
715 }
716
getOffsetOpcodes(const StackOffset & Offset,SmallVectorImpl<uint64_t> & Ops) const717 void RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset,
718 SmallVectorImpl<uint64_t> &Ops) const {
719 // VLENB is the length of a vector register in bytes. We use <vscale x 8 x i8>
720 // to represent one vector register. The dwarf offset is
721 // VLENB * scalable_offset / 8.
722 assert(Offset.getScalable() % 8 == 0 && "Invalid frame offset");
723
724 // Add fixed-sized offset using existing DIExpression interface.
725 DIExpression::appendOffset(Ops, Offset.getFixed());
726
727 unsigned VLENB = getDwarfRegNum(RISCV::VLENB, true);
728 int64_t VLENBSized = Offset.getScalable() / 8;
729 if (VLENBSized > 0) {
730 Ops.push_back(dwarf::DW_OP_constu);
731 Ops.push_back(VLENBSized);
732 Ops.append({dwarf::DW_OP_bregx, VLENB, 0ULL});
733 Ops.push_back(dwarf::DW_OP_mul);
734 Ops.push_back(dwarf::DW_OP_plus);
735 } else if (VLENBSized < 0) {
736 Ops.push_back(dwarf::DW_OP_constu);
737 Ops.push_back(-VLENBSized);
738 Ops.append({dwarf::DW_OP_bregx, VLENB, 0ULL});
739 Ops.push_back(dwarf::DW_OP_mul);
740 Ops.push_back(dwarf::DW_OP_minus);
741 }
742 }
743
744 unsigned
getRegisterCostTableIndex(const MachineFunction & MF) const745 RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const {
746 return MF.getSubtarget<RISCVSubtarget>().hasStdExtCOrZca() ? 1 : 0;
747 }
748
749 // Add two address hints to improve chances of being able to use a compressed
750 // instruction.
getRegAllocationHints(Register VirtReg,ArrayRef<MCPhysReg> Order,SmallVectorImpl<MCPhysReg> & Hints,const MachineFunction & MF,const VirtRegMap * VRM,const LiveRegMatrix * Matrix) const751 bool RISCVRegisterInfo::getRegAllocationHints(
752 Register VirtReg, ArrayRef<MCPhysReg> Order,
753 SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
754 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
755 const MachineRegisterInfo *MRI = &MF.getRegInfo();
756 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
757
758 bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
759 VirtReg, Order, Hints, MF, VRM, Matrix);
760
761 if (!VRM || DisableRegAllocHints)
762 return BaseImplRetVal;
763
764 // Add any two address hints after any copy hints.
765 SmallSet<Register, 4> TwoAddrHints;
766
767 auto tryAddHint = [&](const MachineOperand &VRRegMO, const MachineOperand &MO,
768 bool NeedGPRC) -> void {
769 Register Reg = MO.getReg();
770 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(Reg));
771 if (PhysReg && (!NeedGPRC || RISCV::GPRCRegClass.contains(PhysReg))) {
772 assert(!MO.getSubReg() && !VRRegMO.getSubReg() && "Unexpected subreg!");
773 if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
774 TwoAddrHints.insert(PhysReg);
775 }
776 };
777
778 // This is all of the compressible binary instructions. If an instruction
779 // needs GPRC register class operands \p NeedGPRC will be set to true.
780 auto isCompressible = [&Subtarget](const MachineInstr &MI, bool &NeedGPRC) {
781 NeedGPRC = false;
782 switch (MI.getOpcode()) {
783 default:
784 return false;
785 case RISCV::AND:
786 case RISCV::OR:
787 case RISCV::XOR:
788 case RISCV::SUB:
789 case RISCV::ADDW:
790 case RISCV::SUBW:
791 NeedGPRC = true;
792 return true;
793 case RISCV::ANDI: {
794 NeedGPRC = true;
795 if (!MI.getOperand(2).isImm())
796 return false;
797 int64_t Imm = MI.getOperand(2).getImm();
798 if (isInt<6>(Imm))
799 return true;
800 // c.zext.b
801 return Subtarget.hasStdExtZcb() && Imm == 255;
802 }
803 case RISCV::SRAI:
804 case RISCV::SRLI:
805 NeedGPRC = true;
806 return true;
807 case RISCV::ADD:
808 case RISCV::SLLI:
809 return true;
810 case RISCV::ADDI:
811 case RISCV::ADDIW:
812 return MI.getOperand(2).isImm() && isInt<6>(MI.getOperand(2).getImm());
813 case RISCV::MUL:
814 case RISCV::SEXT_B:
815 case RISCV::SEXT_H:
816 case RISCV::ZEXT_H_RV32:
817 case RISCV::ZEXT_H_RV64:
818 // c.mul, c.sext.b, c.sext.h, c.zext.h
819 NeedGPRC = true;
820 return Subtarget.hasStdExtZcb();
821 case RISCV::ADD_UW:
822 // c.zext.w
823 NeedGPRC = true;
824 return Subtarget.hasStdExtZcb() && MI.getOperand(2).isReg() &&
825 MI.getOperand(2).getReg() == RISCV::X0;
826 case RISCV::XORI:
827 // c.not
828 NeedGPRC = true;
829 return Subtarget.hasStdExtZcb() && MI.getOperand(2).isImm() &&
830 MI.getOperand(2).getImm() == -1;
831 }
832 };
833
834 // Returns true if this operand is compressible. For non-registers it always
835 // returns true. Immediate range was already checked in isCompressible.
836 // For registers, it checks if the register is a GPRC register. reg-reg
837 // instructions that require GPRC need all register operands to be GPRC.
838 auto isCompressibleOpnd = [&](const MachineOperand &MO) {
839 if (!MO.isReg())
840 return true;
841 Register Reg = MO.getReg();
842 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(Reg));
843 return PhysReg && RISCV::GPRCRegClass.contains(PhysReg);
844 };
845
846 for (auto &MO : MRI->reg_nodbg_operands(VirtReg)) {
847 const MachineInstr &MI = *MO.getParent();
848 unsigned OpIdx = MO.getOperandNo();
849 bool NeedGPRC;
850 if (isCompressible(MI, NeedGPRC)) {
851 if (OpIdx == 0 && MI.getOperand(1).isReg()) {
852 if (!NeedGPRC || MI.getNumExplicitOperands() < 3 ||
853 MI.getOpcode() == RISCV::ADD_UW ||
854 isCompressibleOpnd(MI.getOperand(2)))
855 tryAddHint(MO, MI.getOperand(1), NeedGPRC);
856 if (MI.isCommutable() && MI.getOperand(2).isReg() &&
857 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(1))))
858 tryAddHint(MO, MI.getOperand(2), NeedGPRC);
859 } else if (OpIdx == 1 && (!NeedGPRC || MI.getNumExplicitOperands() < 3 ||
860 isCompressibleOpnd(MI.getOperand(2)))) {
861 tryAddHint(MO, MI.getOperand(0), NeedGPRC);
862 } else if (MI.isCommutable() && OpIdx == 2 &&
863 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(1)))) {
864 tryAddHint(MO, MI.getOperand(0), NeedGPRC);
865 }
866 }
867 }
868
869 for (MCPhysReg OrderReg : Order)
870 if (TwoAddrHints.count(OrderReg))
871 Hints.push_back(OrderReg);
872
873 return BaseImplRetVal;
874 }
875