1 /*========================== begin_copyright_notice ============================ 2 3 Copyright (C) 2017-2021 Intel Corporation 4 5 SPDX-License-Identifier: MIT 6 7 ============================= end_copyright_notice ===========================*/ 8 9 #ifndef _VISA_IGC_COMMON_HEADER_H_ 10 #define _VISA_IGC_COMMON_HEADER_H_ 11 12 13 typedef enum 14 { 15 vISA_DEFAULT, // default mode: input is in-memory IR or vISA binary 16 vISA_ASM_WRITER, // mode for inline asm: input is in-memory IR + inline vISA assembly, output is vISA text 17 vISA_ASM_READER // mode for visa text input 18 } vISABuilderMode; 19 20 typedef enum 21 { 22 PREDEFINED_NULL = 0, 23 PREDEFINED_X = 1, 24 PREDEFINED_Y = 2, 25 PREDEFINED_GROUP_ID_X = 3, 26 PREDEFINED_GROUP_ID_Y = 4, 27 PREDEFINED_GROUP_ID_Z = 5, 28 PREDEFINED_TSC = 6, 29 PREDEFINED_R0 = 7, 30 PREDEFINED_ARG = 8, 31 PREDEFINED_RET = 9, 32 PREDEFINED_FE_SP = 10, 33 PREDEFINED_FE_FP = 11, 34 PREDEFINED_HW_TID = 12, 35 PREDEFINED_SR0 = 13, 36 PREDEFINED_CR0 = 14, 37 PREDEFINED_CE0 = 15, 38 PREDEFINED_DBG = 16, 39 PREDEFINED_COLOR = 17, 40 PREDEFINED_IMPL_ARG_BUF_PTR = 18, 41 PREDEFINED_LOCAL_ID_BUF_PTR = 19, 42 PREDEFINED_VAR_LAST = PREDEFINED_LOCAL_ID_BUF_PTR 43 } PreDefined_Vars; 44 45 typedef enum 46 { 47 // FIXME: why not expose PREDEF_SURF_0 etc. directly? 48 PREDEFINED_SURFACE_SLM = 0, 49 PREDEFINED_SURFACE_STACK = 1, 50 PREDEFINED_SURFACE_SCRATCH = 3, 51 PREDEFINED_SURFACE_T252 = 4, 52 PREDEFINED_SURFACE_T255 = 5, 53 PREDEFINED_SURFACE_LAST = PREDEFINED_SURFACE_T255 54 } PreDefined_Surface; 55 56 typedef enum { 57 ATOMIC_ADD = 0x0, 58 ATOMIC_SUB = 0x1, 59 ATOMIC_INC = 0x2, 60 ATOMIC_DEC = 0x3, 61 ATOMIC_MIN = 0x4, 62 ATOMIC_MAX = 0x5, 63 ATOMIC_XCHG = 0x6, 64 ATOMIC_CMPXCHG = 0x7, 65 ATOMIC_AND = 0x8, 66 ATOMIC_OR = 0x9, 67 ATOMIC_XOR = 0xa, 68 ATOMIC_IMIN = 0xb, 69 ATOMIC_IMAX = 0xc, 70 ATOMIC_PREDEC = 0xd, 71 ATOMIC_FMAX = 0x10, 72 ATOMIC_FMIN = 0x11, 73 ATOMIC_FCMPWR = 0x12, 74 ATOMIC_FADD = 0x13, 75 ATOMIC_FSUB = 0x14, 76 ATOMIC_UNDEF 77 } VISAAtomicOps; 78 79 /* 80 * Various enumerations representing the binary encoding definitions for the common ISA 81 * 82 */ 83 typedef enum : unsigned char { 84 ISA_TYPE_UD = 0x0, 85 ISA_TYPE_D = 0x1, 86 ISA_TYPE_UW = 0x2, 87 ISA_TYPE_W = 0x3, 88 ISA_TYPE_UB = 0x4, 89 ISA_TYPE_B = 0x5, 90 ISA_TYPE_DF = 0x6, 91 ISA_TYPE_F = 0x7, 92 ISA_TYPE_V = 0x8, 93 ISA_TYPE_VF = 0x9, 94 ISA_TYPE_BOOL = 0xA, 95 ISA_TYPE_UQ = 0xB, 96 ISA_TYPE_UV = 0xC, 97 ISA_TYPE_Q = 0xD, 98 ISA_TYPE_HF = 0xE, 99 ISA_TYPE_BF = 0xF, 100 ISA_TYPE_NUM 101 } VISA_Type ; 102 103 typedef struct { 104 VISA_Type CISAType; 105 const char* typeName; 106 int typeSize; 107 } CISATypeInfo; 108 109 extern CISATypeInfo CISATypeTable[ISA_TYPE_NUM]; 110 111 typedef enum { 112 ALIGN_UNDEF = 0x0, 113 ALIGN_BYTE = 0x0, 114 ALIGN_WORD = 0x1, 115 ALIGN_DWORD = 0x2, 116 ALIGN_QWORD = 0x3, 117 ALIGN_OWORD = 0x4, 118 ALIGN_GRF = 0x5, 119 ALIGN_2_GRF = 0x6, 120 ALIGN_HWORD = 0x7, 121 ALIGN_32WORD = 0x8, 122 ALIGN_64WORD = 0x9, 123 124 ALIGN_TOTAL_NUM = 0xA 125 } VISA_Align; 126 127 typedef enum { 128 LABEL_BLOCK = 0x0, 129 LABEL_SUBROUTINE = 0x1, 130 LABEL_FC = 0x2, 131 LABEL_FUNCTION = 0x3 132 } VISA_Label_Kind; 133 134 typedef enum { 135 ISA_CMP_E = 0, /* Zero or Equal */ 136 ISA_CMP_NE, /* Not Zero or Not Equal */ 137 ISA_CMP_G, /* Greater-than */ 138 ISA_CMP_GE, /* Greater-than-or-equal */ 139 ISA_CMP_L, /* Less-than */ 140 ISA_CMP_LE, /* Less-than-or-equal */ 141 ISA_CMP_UNDEF 142 } VISA_Cond_Mod; 143 144 typedef enum { 145 MODIFIER_NONE = 0x0, 146 MODIFIER_ABS = 0x1, 147 MODIFIER_NEG = 0x2, 148 MODIFIER_NEG_ABS = 0x3, 149 MODIFIER_SAT = 0x4, 150 MODIFIER_NOT = 0x5 //BDW only 151 } VISA_Modifier; 152 153 typedef enum { 154 PredState_NO_INVERSE = 0, 155 PredState_INVERSE = 1 156 } VISA_PREDICATE_STATE; 157 158 typedef enum { 159 EXEC_SIZE_1 = 0x0, 160 EXEC_SIZE_2 = 0x1, 161 EXEC_SIZE_4 = 0x2, 162 EXEC_SIZE_8 = 0x3, 163 EXEC_SIZE_16 = 0x4, 164 EXEC_SIZE_32 = 0x5, 165 EXEC_SIZE_ILLEGAL = 0x6 166 } VISA_Exec_Size; 167 168 // predicate control 169 // Currently only support Any and all 170 typedef enum { 171 PRED_CTRL_NON = 0x0, 172 PRED_CTRL_ANY = 0x1, 173 PRED_CTRL_ALL = 0x2, 174 PRED_CTRL_UNDEF 175 } VISA_PREDICATE_CONTROL; 176 177 typedef enum { 178 vISA_EMASK_M1 = 0, 179 vISA_EMASK_M2 = 1, 180 vISA_EMASK_M3 = 2, 181 vISA_EMASK_M4 = 3, 182 vISA_EMASK_M5 = 4, 183 vISA_EMASK_M6 = 5, 184 vISA_EMASK_M7 = 6, 185 vISA_EMASK_M8 = 7, 186 vISA_EMASK_M1_NM = 8, 187 vISA_EMASK_M2_NM = 9, 188 vISA_EMASK_M3_NM = 10, 189 vISA_EMASK_M4_NM = 11, 190 vISA_EMASK_M5_NM = 12, 191 vISA_EMASK_M6_NM = 13, 192 vISA_EMASK_M7_NM = 14, 193 vISA_EMASK_M8_NM = 15, 194 vISA_NUM_EMASK = 16 195 } VISA_EMask_Ctrl; 196 197 typedef enum { 198 OWORD_NUM_1 = 0x0, 199 OWORD_NUM_2 = 0x1, 200 OWORD_NUM_4 = 0x2, 201 OWORD_NUM_8 = 0x3, 202 OWORD_NUM_16 = 0x4, 203 OWORD_NUM_ILLEGAL = 0x5 204 } VISA_Oword_Num; 205 206 // media load inst modifiers 207 typedef enum { 208 MEDIA_LD_nomod = 0x0, 209 MEDIA_LD_modified = 0x1, 210 MEDIA_LD_top = 0x2, 211 MEDIA_LD_bottom = 0x3, 212 MEDIA_LD_top_mod = 0x4, 213 MEDIA_LD_bottom_mod = 0x5, 214 MEDIA_LD_Mod_NUM 215 } MEDIA_LD_mod; 216 217 typedef enum { 218 VME_OP_MODE_INTER = 0x0, 219 VME_OP_MODE_INTRA = 0x1, 220 VME_OP_MODE_ALL = 0x2, 221 VME_OP_MODE_NUM = 0x3 222 } COMMON_ISA_VME_OP_MODE; 223 224 typedef enum { 225 VME_STREAM_DISABLE = 0, 226 VME_STREAM_OUT = 1, 227 VME_STREAM_IN = 2, 228 VME_STREAM_IN_OUT = 3 229 } COMMON_ISA_VME_STREAM_MODE; 230 231 typedef enum { 232 VME_SEARCH_SINGLE_REF_SINGLE_REC_SINGLE_START = 0, 233 VME_SEARCH_SINGLE_REF_SINGLE_REC_DUAL_START = 1, 234 VME_SEARCH_SINGLE_REF_DUAL_REC = 3, 235 VME_SEARCH_DUAL_REF_DUAL_REC = 7 236 } COMMON_ISA_VME_SEARCH_CTRL; 237 238 typedef enum 239 { 240 CISA_DM_FMIN = 0, 241 CISA_DM_FMAX = 1 242 } CISA_MIN_MAX_SUB_OPCODE; 243 244 typedef enum 245 { 246 CISA_PLANE_Y = 0, 247 CISA_PLANE_UV = 1, 248 CISA_PLANE_V = 2 249 } CISA_PLANE_ID; 250 251 typedef enum { 252 /* 0x0 reserved -- used for illegal/nop op? */ 253 ISA_RESERVED_0 = 0x0 , 254 ISA_ADD = 0x1 , 255 ISA_AVG = 0x2 , 256 ISA_DIV = 0x3 , 257 ISA_DP2 = 0x4 , 258 ISA_DP3 = 0x5 , 259 ISA_DP4 = 0x6 , 260 ISA_DPH = 0x7 , 261 ISA_EXP = 0x8 , 262 ISA_FRC = 0x9 , 263 ISA_LINE = 0xA , 264 ISA_LOG = 0xB , 265 ISA_MAD = 0xC , 266 ISA_MULH = 0xD , 267 ISA_LRP = 0xE , 268 ISA_MOD = 0xF , 269 ISA_MUL = 0x10, 270 ISA_POW = 0x11, 271 ISA_RNDD = 0x12, 272 ISA_RNDU = 0x13, 273 ISA_RNDE = 0x14, 274 ISA_RNDZ = 0x15, 275 ISA_SAD2 = 0x16, 276 ISA_SIN = 0x17, 277 ISA_COS = 0x18, 278 ISA_SQRT = 0x19, 279 ISA_RSQRT = 0x1A, 280 ISA_INV = 0x1B, 281 ISA_DPASW = 0x1C, 282 ISA_FCVT = 0x1D, 283 ISA_QF_CVT = ISA_FCVT, // temp for cmc 284 ISA_SRND = 0x1E, 285 ISA_LZD = 0x1F, 286 ISA_AND = 0x20, 287 ISA_OR = 0x21, 288 ISA_XOR = 0x22, 289 ISA_NOT = 0x23, 290 ISA_SHL = 0x24, 291 ISA_SHR = 0x25, 292 ISA_ASR = 0x26, 293 ISA_CBIT = 0x27, 294 ISA_ADDR_ADD = 0x28, 295 ISA_MOV = 0x29, 296 ISA_SEL = 0x2A, 297 ISA_SETP = 0x2B, 298 ISA_CMP = 0x2C, 299 ISA_MOVS = 0x2D, 300 ISA_FBL = 0x2E, 301 ISA_FBH = 0x2F, 302 ISA_SUBROUTINE = 0x30, 303 ISA_LABEL = 0x31, 304 ISA_JMP = 0x32, 305 ISA_CALL = 0x33, 306 ISA_RET = 0x34, 307 ISA_OWORD_LD = 0x35, 308 ISA_OWORD_ST = 0x36, 309 ISA_MEDIA_LD = 0x37, 310 ISA_MEDIA_ST = 0x38, 311 ISA_GATHER = 0x39, 312 ISA_SCATTER = 0x3A, 313 ISA_RESERVED_3B = 0x3B, 314 ISA_OWORD_LD_UNALIGNED = 0x3C, 315 ISA_RESERVED_3D = 0x3D, 316 ISA_RESERVED_3E = 0x3E, 317 ISA_RESERVED_3F = 0x3F, 318 ISA_SAMPLE = 0x40, 319 ISA_SAMPLE_UNORM = 0x41, 320 ISA_LOAD = 0x42, 321 ISA_AVS = 0x43, 322 ISA_VA = 0x44, 323 ISA_FMINMAX = 0x45, 324 ISA_BFE = 0x46, 325 ISA_BFI = 0x47, 326 ISA_BFREV = 0x48, 327 ISA_ADDC = 0x49, 328 ISA_SUBB = 0x4A, 329 ISA_GATHER4_TYPED = 0x4B, 330 ISA_SCATTER4_TYPED = 0x4C, 331 ISA_VA_SKL_PLUS = 0x4D, 332 ISA_SVM = 0x4E, 333 ISA_IFCALL = 0x4F, 334 ISA_FADDR = 0x50, 335 ISA_FILE = 0x51, 336 ISA_LOC = 0x52, 337 ISA_RESERVED_53 = 0x53, 338 ISA_VME_IME = 0x54, 339 ISA_VME_SIC = 0x55, 340 ISA_VME_FBR = 0x56, 341 ISA_VME_IDM = 0x57, 342 ISA_RESERVED_58 = 0x58, 343 ISA_BARRIER = 0x59, 344 ISA_SAMPLR_CACHE_FLUSH = 0x5A, 345 ISA_WAIT = 0x5B, 346 ISA_FENCE = 0x5C, 347 ISA_RAW_SEND = 0x5D, 348 ISA_RESERVED_5E = 0x5E, 349 ISA_YIELD = 0x5F, 350 ISA_NBARRIER = 0x60, 351 ISA_RESERVED_61 = 0x61, 352 ISA_RESERVED_62 = 0x62, 353 ISA_RESERVED_63 = 0x63, 354 ISA_RESERVED_64 = 0x64, 355 ISA_RESERVED_65 = 0x65, 356 ISA_RESERVED_66 = 0x66, 357 ISA_FCALL = 0x67, 358 ISA_FRET = 0x68, 359 ISA_SWITCHJMP = 0x69, 360 ISA_SAD2ADD = 0x6A, 361 ISA_PLANE = 0x6B, 362 ISA_GOTO = 0x6C, 363 ISA_3D_SAMPLE = 0x6D, 364 ISA_3D_LOAD = 0x6E, 365 ISA_3D_GATHER4 = 0x6F, 366 ISA_3D_INFO = 0x70, 367 ISA_3D_RT_WRITE = 0x71, 368 ISA_3D_URB_WRITE = 0x72, 369 ISA_3D_TYPED_ATOMIC = 0x73, 370 ISA_GATHER4_SCALED = 0x74, 371 ISA_SCATTER4_SCALED = 0x75, 372 ISA_RESERVED_76 = 0x76, 373 ISA_RESERVED_77 = 0x77, 374 ISA_GATHER_SCALED = 0x78, 375 ISA_SCATTER_SCALED = 0x79, 376 ISA_RAW_SENDS = 0x7A, 377 ISA_LIFETIME = 0x7B, 378 ISA_SBARRIER = 0x7C, 379 ISA_DWORD_ATOMIC = 0x7D, 380 ISA_SQRTM = 0x7E, 381 ISA_DIVM = 0x7F, 382 ISA_ROL = 0x80, 383 ISA_ROR = 0x81, 384 ISA_DP4A = 0x82, 385 ISA_DPAS = 0x83, 386 ISA_ADD3 = 0x84, 387 ISA_BFN = 0x85, 388 ISA_QW_GATHER = 0x86, 389 ISA_QW_SCATTER = 0x87, 390 ISA_BF_CVT = 0x88, 391 ISA_LSC_UNTYPED = 0x89, 392 ISA_LSC_TYPED = 0x8A, 393 ISA_LSC_FENCE = 0x8B, 394 ISA_RESERVED_8C = 0x8C, 395 ISA_RESERVED_8D = 0x8D, 396 ISA_RESERVED_8E = 0x8E, 397 ISA_RESERVED_8F = 0x8F, 398 ISA_RESERVED_90 = 0x90, 399 ISA_MADW = 0x91, 400 ISA_ADD3O = 0x92, 401 ISA_NUM_OPCODE, 402 ISA_OPCODE_ENUM_SIZE = 0xFF 403 } ISA_Opcode; 404 405 typedef enum 406 { 407 VISA_3D_SAMPLE = 0, 408 VISA_3D_SAMPLE_B = 1, 409 VISA_3D_SAMPLE_L = 2, 410 VISA_3D_SAMPLE_C = 3, 411 VISA_3D_SAMPLE_D = 4, 412 VISA_3D_SAMPLE_B_C = 5, 413 VISA_3D_SAMPLE_L_C = 6, 414 VISA_3D_LD = 7, 415 VISA_3D_GATHER4 = 8, 416 VISA_3D_LOD = 9, 417 VISA_3D_RESINFO = 10, 418 VISA_3D_SAMPLEINFO = 11, 419 VISA_3D_SAMPLE_KILLPIX = 12, 420 VISA_3D_GATHER4_C = 16, 421 VISA_3D_GATHER4_PO = 17, 422 VISA_3D_GATHER4_PO_C = 18, 423 VISA_3D_SAMPLE_D_C = 20, 424 VISA_3D_SAMPLE_LZ = 24, 425 VISA_3D_SAMPLE_C_LZ = 25, 426 VISA_3D_LD_LZ = 26, 427 VISA_3D_LD2DMS_W = 28, 428 VISA_3D_LD_MCS = 29, 429 VISA_3D_TOTAL_NUM_OPS = 30 430 } VISASampler3DSubOpCode; 431 432 typedef enum { 433 CHANNEL_MASK_NOMASK = 0x0, 434 CHANNEL_MASK_R = 0x1, 435 CHANNEL_MASK_G = 0x2, 436 CHANNEL_MASK_RG = 0x3, 437 CHANNEL_MASK_B = 0x4, 438 CHANNEL_MASK_RB = 0x5, 439 CHANNEL_MASK_GB = 0x6, 440 CHANNEL_MASK_RGB = 0x7, 441 CHANNEL_MASK_A = 0x8, 442 CHANNEL_MASK_RA = 0x9, 443 CHANNEL_MASK_GA = 0xa, 444 CHANNEL_MASK_RGA = 0xb, 445 CHANNEL_MASK_BA = 0xc, 446 CHANNEL_MASK_RBA = 0xd, 447 CHANNEL_MASK_GBA = 0xe, 448 CHANNEL_MASK_RGBA = 0xf, 449 CHANNEL_MASK_NUM 450 } VISAChannelMask; 451 452 typedef enum { 453 CHANNEL_16_BIT_FULL = 0, 454 CHANNEL_16_BIT_DOWNSAMPLED = 1, 455 CHANNEL_8_BIT_FULL = 2, 456 CHANNEL_8_BIT_DOWNSAMPLED = 3, 457 CHANNEL_OUTPUT_NUM = 4 458 } CHANNEL_OUTPUT_FORMAT ; 459 460 typedef enum 461 { 462 VISA_3D_GATHER4_CHANNEL_R = 0, 463 VISA_3D_GATHER4_CHANNEL_G = 1, 464 VISA_3D_GATHER4_CHANNEL_B = 2, 465 VISA_3D_GATHER4_CHANNEL_A = 3 466 } VISASourceSingleChannel; 467 468 typedef enum { 469 GENX_NONE = -1, 470 GENX_BDW, 471 GENX_CHV, 472 GENX_SKL, 473 GENX_BXT, 474 GENX_CNL, 475 GENX_ICLLP, 476 GENX_TGLLP, 477 XeHP_SDV, 478 GENX_DG2, 479 GENX_PVC, 480 GENX_PVCXT, 481 ALL 482 } TARGET_PLATFORM; 483 484 // gather/scatter element size 485 typedef enum { 486 GATHER_SCATTER_BYTE = 0x0, 487 GATHER_SCATTER_WORD = 0x1, 488 GATHER_SCATTER_DWORD = 0x2, 489 GATHER_SCATTER_BYTE_UNDEF 490 } GATHER_SCATTER_ELEMENT_SIZE; 491 492 /// Sampler8x8 DevBDW+ Functionality Opcodes 493 typedef enum VA_fopcode 494 { 495 AVS_FOPCODE = 0x00, 496 Convolve_FOPCODE = 0x01, 497 MINMAX_FOPCODE = 0x02, 498 MINMAXFILTER_FOPCODE = 0x03, 499 ERODE_FOPCODE = 0x04, 500 Dilate_FOPCODE = 0x05, 501 BoolCentroid_FOPCODE = 0x06, 502 Centroid_FOPCODE = 0x07, 503 VA_OP_CODE_1D_CONVOLVE_VERTICAL = 0x08, 504 VA_OP_CODE_1D_CONVOLVE_HORIZONTAL = 0x09, 505 VA_OP_CODE_1PIXEL_CONVOLVE = 0x0A, 506 VA_OP_CODE_FLOOD_FILL = 0x0B, 507 VA_OP_CODE_LBP_CREATION = 0x0C, 508 VA_OP_CODE_LBP_CORRELATION = 0x0D, 509 VA_OP_CODE_NONE = 0x0E, 510 VA_OP_CODE_CORRELATION_SEARCH = 0x0F, 511 ISA_HDC_CONV = 0x10, 512 ISA_HDC_MMF = 0x11, 513 ISA_HDC_ERODE = 0x12, 514 ISA_HDC_DILATE = 0x13, 515 ISA_HDC_LBPCORRELATION = 0x14, 516 ISA_HDC_LBPCREATION = 0x15, 517 ISA_HDC_1DCONV_H = 0x16, 518 ISA_HDC_1DCONV_V = 0x17, 519 ISA_HDC_1PIXELCONV = 0x18, 520 VA_OP_CODE_UNDEFINED = 0x19 521 } ISA_VA_Sub_Opcode; 522 523 typedef enum _OutputFormatControl_ 524 { AVS_16_FULL = 0, 525 AVS_16_DOWN_SAMPLE = 1, 526 AVS_8_FULL = 2, 527 AVS_8_DOWN_SAMPLE = 3 528 } OutputFormatControl; 529 530 typedef enum _AVSExecMode_ 531 { AVS_16x4 = 0, 532 AVS_8x4 = 1, 533 AVS_16x8 = 2, 534 AVS_4x4 = 3 535 } AVSExecMode; 536 537 typedef enum _MMFExecMode_ 538 { VA_MMF_16x4 = 0, 539 VA_MMF_16x1 = 2, 540 VA_MMF_1x1 = 3 541 } MMFExecMode; 542 543 typedef enum _MMFEnableMode_ 544 { VA_MINMAX_ENABLE = 0, 545 VA_MAX_ENABLE = 1, 546 VA_MIN_ENABLE = 2 547 } MMFEnableMode; 548 549 typedef enum _CONVExecMode_ 550 { VA_CONV_16x4 = 0, 551 VA_CONV_16x1 = 2 552 } CONVExecMode; 553 554 typedef enum _EDExecMode_ 555 { VA_ED_64x4 = 0, 556 VA_ED_32x4 = 1, 557 VA_ED_64x1 = 2, 558 VA_ED_32x1 = 3 559 } EDExecMode; 560 561 typedef enum _EDMode_ 562 { VA_ERODE = 4, 563 VA_DILATE = 5 564 } EDMode; 565 566 typedef enum _LBPCreationMode_ 567 { 568 VA_3x3_AND_5x5 = 0, 569 VA_3x3 = 1, 570 VA_5x5 = 2 571 } LBPCreationMode; 572 573 typedef enum _Convolve1DDirection_ 574 { 575 VA_H_DIRECTION = 0, 576 VA_V_DIRECTION = 1 577 } Convolve1DDirection; 578 579 typedef enum _CONV1PixelExecMode_ 580 { VA_CONV1P_16x4 = 0, 581 VA_CONV1P_16x1 = 2, 582 VA_CONV1P_1x1 = 3 583 } CONV1PixelExecMode; 584 585 typedef enum _HDCReturnFormat_ 586 { 587 VA_HDC_CONVOVLE_Y16 = 0, 588 VA_HDC_CONVOLVE_Y8 = 1 589 } HDCReturnFormat; 590 591 typedef enum _CONVHDCRegionSize_ 592 { 593 VA_HDC_CONVOLVE_15x15 = 0, 594 VA_HDC_CONVOLVE_31x31 = 1 595 } CONVHDCRegionSize; 596 597 typedef enum 598 { 599 SVM_BLOCK_NUM_1 = 0x0, 600 SVM_BLOCK_NUM_2 = 0x1, 601 SVM_BLOCK_NUM_4 = 0x2, 602 SVM_BLOCK_NUM_8 = 0x3 603 } VISA_SVM_Block_Num; 604 605 typedef enum 606 { 607 SVM_BLOCK_TYPE_BYTE = 0x0, 608 SVM_BLOCK_TYPE_DWORD = 0x1, 609 SVM_BLOCK_TYPE_QWORD = 0x2 610 } VISA_SVM_Block_Type; 611 612 613 typedef struct _vISA_RT_CONTROLS 614 { 615 unsigned s0aPresent:1; //src0 Alpha 616 unsigned oMPresent:1; //oMask 617 unsigned zPresent:1; //depth 618 unsigned RTIndexPresent : 1; // Whether need to set RTIndex in header 619 unsigned isLastWrite:1; //is last RT Write, sets Last Render Target Select bit 620 unsigned isPerSample:1; //Enables Per Sample Render Target Write 621 unsigned isStencil:1; 622 unsigned isCoarseMode:1; //controls coasrse mode bit inmsg descriptor 623 unsigned isSampleIndex : 1; //controls whether sampleIndex is used. 624 unsigned isHeaderMaskfromCe0 : 1; 625 unsigned isNullRT : 1; // null render target 626 } vISA_RT_CONTROLS; 627 628 typedef enum 629 { 630 LIFETIME_START = 0, 631 LIFETIME_END = 1 632 } VISAVarLifetime; 633 634 enum class GenPrecision : unsigned char 635 { 636 INVALID = 0, 637 638 U1 = 1, 639 S1 = 2, 640 U2 = 3, 641 S2 = 4, 642 U4 = 5, 643 S4 = 6, 644 U8 = 7, 645 S8 = 8, 646 BF16 = 9, // bfloat16 (1, 8, 7) 647 FP16 = 10, // half (1, 5, 10) 648 BF8 = 11, // bfloat8 (1, 5, 2) 649 TF32 = 12, // TensorFloat (1, 8, 10), 19 bits 650 TOTAL_NUM 651 }; 652 653 /////////////////////////////////////////////////////////////////////////////// 654 // Data types to support LSC load/store messages. 655 // 656 657 // The size of each data element 658 enum LSC_DATA_SIZE { 659 LSC_DATA_SIZE_INVALID, 660 LSC_DATA_SIZE_8b, // DATA:u8... 661 LSC_DATA_SIZE_16b, // DATA:u16... 662 LSC_DATA_SIZE_32b, // DATA:u32... 663 LSC_DATA_SIZE_64b, // DATA:u64... 664 // data types supporting conversion on load 665 // 8c32b reads load (8) bits, (c)onvert to (32) bits (zero extending) 666 // store truncates 667 LSC_DATA_SIZE_8c32b, // DATA:u8c32... (zero-extend / truncate) 668 LSC_DATA_SIZE_16c32b, // DATA:u16c32.. (zero-extend / truncate) 669 LSC_DATA_SIZE_16c32bH, // DATA:u16c32h.. h means load to (h)igh 16 670 // data stored in upper 16; zero-fills bottom 16 671 // (bfloat raw conversion to 32b float) 672 }; 673 674 // The number of elements per address ("vector" size) 675 enum LSC_DATA_ELEMS { 676 LSC_DATA_ELEMS_INVALID, 677 LSC_DATA_ELEMS_1, // DATA:..x1 678 LSC_DATA_ELEMS_2, // DATA:..x2 679 LSC_DATA_ELEMS_3, // DATA:..x3 680 LSC_DATA_ELEMS_4, // DATA:..x4 681 LSC_DATA_ELEMS_8, // DATA:..x8 682 LSC_DATA_ELEMS_16, // DATA:..x16 683 LSC_DATA_ELEMS_32, // DATA:..x32 684 LSC_DATA_ELEMS_64, // DATA:..x64 685 }; 686 687 enum LSC_DATA_ORDER { 688 LSC_DATA_ORDER_INVALID, 689 LSC_DATA_ORDER_NONTRANSPOSE, 690 LSC_DATA_ORDER_TRANSPOSE, // DATA:...t 691 }; 692 693 enum LSC_DATA_CHMASK { 694 LSC_DATA_CHMASK_INVALID, 695 LSC_DATA_CHMASK_X = 1 << 0, 696 LSC_DATA_CHMASK_Y = 1 << 1, 697 LSC_DATA_CHMASK_Z = 1 << 2, 698 LSC_DATA_CHMASK_W = 1 << 3, 699 }; 700 701 struct LSC_DATA_SHAPE { 702 LSC_DATA_SIZE size; 703 LSC_DATA_ORDER order; 704 union { 705 LSC_DATA_ELEMS elems; // all other operations use the regular vector 706 int chmask; // for LSC_*_QUAD; bitmask of LSC_DATA_CHMASK 707 }; 708 }; 709 710 struct LSC_DATA_SHAPE_BLOCK2D { 711 LSC_DATA_SIZE size; 712 LSC_DATA_ORDER order; 713 int blocks; // the count of 2d blocks to load (array len) 714 int width; // the width (in elems) of the 2d region 715 int height; // the height (in elems) of the 2d region 716 bool vnni; // perform a vnni transform on load 717 }; 718 static const unsigned LSC_BLOCK2D_ADDR_PARAMS = 6; 719 720 enum LSC_ADDR_SIZE { 721 LSC_ADDR_SIZE_INVALID, 722 LSC_ADDR_SIZE_16b, // [ADDR]:a16 723 LSC_ADDR_SIZE_32b, // [ADDR]:a32 724 LSC_ADDR_SIZE_64b, // [ADDR]:a64 725 }; 726 enum LSC_ADDR_TYPE { 727 LSC_ADDR_TYPE_INVALID, 728 LSC_ADDR_TYPE_FLAT, // aka "stateless" 729 LSC_ADDR_TYPE_BSS, // bindless surface state offset 730 LSC_ADDR_TYPE_SS, // surface state offset 731 LSC_ADDR_TYPE_BTI, // binding table interface (legacy) 732 }; 733 734 // 735 // Caching override behavior 736 // 737 // We support all combinations in IR, though not all are supported in hardware 738 // https://gfxspecs.intel.com/Predator/Home/Index/53560 739 typedef enum { 740 LSC_CACHING_DEFAULT, // .df 741 LSC_CACHING_UNCACHED, // .uc 742 LSC_CACHING_CACHED, // .ca 743 LSC_CACHING_WRITEBACK, // .wb 744 LSC_CACHING_WRITETHROUGH, // .wt 745 LSC_CACHING_STREAMING, // .st 746 LSC_CACHING_READINVALIDATE, // .ri last use / invalidate after read 747 748 } LSC_CACHE_OPT; 749 // Only some combinations are legal (per platform) 750 struct LSC_CACHE_OPTS { 751 LSC_CACHE_OPT l1; 752 LSC_CACHE_OPT l3; 753 }; 754 755 // L1,L3 available cache policies combinations 756 // Auxiliary enums for cache options translation from intrinsics into 757 // vISA representation. 758 typedef enum { 759 LSC_L1DEF_L3DEF = 0, 760 LSC_L1UC_L3UC, // Load: L1 uncached L3 uncached # Store: L1 uncached L3 uncached 761 LSC_L1UC_L3C_WB, // Load: L1 uncached L3 cached # Store: L1 uncached L3 write-back 762 LSC_L1C_WT_L3UC, // Load: L1 cached L3 uncached # Store: L1 write-through L3 uncached 763 LSC_L1C_WT_L3C_WB, // Load: L1 cached L3 cached # Store: L1 write-through L3 write-back 764 LSC_L1S_L3UC, // Load: L1 streaming L3 uncached # Store: L1 streaming L3 uncached 765 LSC_L1S_L3C_WB, // Load: L1 streaming L3 cached # Store: L1 streaming L3 write-back 766 767 LSC_L1IAR_WB_L3C_WB, // Load: L1 invalidate after read L3 cached # Store: L1 write-back L3 write-back 768 LSC_CC_INVALID, 769 } LSC_L1_L3_CC; 770 771 // Groups all the necessary address into a product type 772 struct LSC_ADDR { 773 // The address model being used (e.g. flat, bti, bss, ss) 774 LSC_ADDR_TYPE type; 775 776 // An optional uniform immediate scale. Default this to 1 if 777 // scaling is not desired (or supported). 0 is an illegal value here. 778 int immScale; 779 780 // An optional uniform immediate offset; for the given address model, 781 // if hardware supports this and the value is small enough to fit in the 782 // descriptor, then it can be fused into the operation. Conversely, if the 783 // immediate value is too big or immediate offsets are not supported for 784 // the given address type or device, codegen will generate separate adds 785 // to the address. 786 // 787 // This value is intended to be pre-scaled and 'immScale' 788 // doesn't impact it. I.e. the effective address is 789 // EA = immScale * ADDR + immOffset (result in bytes) 790 int immOffset; // [...+0x100] (can be 0) 791 792 // The number of bits per address; not all address models support all sizes 793 LSC_ADDR_SIZE size; // e.g. :a64, :a32, ... 794 }; 795 796 // The specific fence op 797 enum LSC_FENCE_OP { 798 LSC_FENCE_OP_NONE, // .none 799 LSC_FENCE_OP_EVICT, // .evict (dirty lines evicted and invalided; 800 // clean lines are invalidated) 801 LSC_FENCE_OP_INVALIDATE, // .invalidate (inv. all clean lines; don't evict) 802 LSC_FENCE_OP_DISCARD, // .discard (dirty and clean lines written, 803 // but stay in cache) 804 LSC_FENCE_OP_CLEAN, // .clean 805 LSC_FENCE_OP_FLUSHL3, // .flushl3 (flush L3 only, but not L1) 806 LSC_FENCE_OP_TYPE6 // .flushtype6 807 }; 808 809 // The scope of a given IO operation (typically fence) 810 enum LSC_SCOPE { 811 LSC_SCOPE_GROUP, // .group (thread group) 812 LSC_SCOPE_LOCAL, // .local (dss?) 813 LSC_SCOPE_TILE, // .tile 814 LSC_SCOPE_GPU, // .gpu 815 LSC_SCOPE_GPUS, // .gpus 816 LSC_SCOPE_SYSREL, // .sysrel 817 LSC_SCOPE_SYSACQ, // .sysacq 818 }; 819 820 // The subset of SFIDs that are permitted for LSC messages 821 enum LSC_SFID { 822 LSC_UGM, // .ugm 823 LSC_UGML, // .ugml 824 LSC_TGM, // .tgm 825 LSC_SLM, // .slm 826 }; 827 828 enum LSC_OP { 829 LSC_LOAD = 0x00, 830 LSC_LOAD_STRIDED = 0x01, // aka "load_block" 831 LSC_LOAD_QUAD = 0x02, // aka "load_cmask" 832 LSC_LOAD_BLOCK2D = 0x03, 833 LSC_STORE = 0x04, 834 LSC_STORE_STRIDED = 0x05, // aka "load_block" 835 LSC_STORE_QUAD = 0x06, // aka "store_cmask" 836 LSC_STORE_BLOCK2D = 0x07, 837 // 838 LSC_ATOMIC_IINC = 0x08, 839 LSC_ATOMIC_IDEC = 0x09, 840 LSC_ATOMIC_LOAD = 0x0A, 841 LSC_ATOMIC_STORE = 0x0B, 842 LSC_ATOMIC_IADD = 0x0C, 843 LSC_ATOMIC_ISUB = 0x0D, 844 LSC_ATOMIC_SMIN = 0x0E, 845 LSC_ATOMIC_SMAX = 0x0F, 846 LSC_ATOMIC_UMIN = 0x10, 847 LSC_ATOMIC_UMAX = 0x11, 848 LSC_ATOMIC_ICAS = 0x12, 849 LSC_ATOMIC_FADD = 0x13, 850 LSC_ATOMIC_FSUB = 0x14, 851 LSC_ATOMIC_FMIN = 0x15, 852 LSC_ATOMIC_FMAX = 0x16, 853 LSC_ATOMIC_FCAS = 0x17, 854 LSC_ATOMIC_AND = 0x18, 855 LSC_ATOMIC_OR = 0x19, 856 LSC_ATOMIC_XOR = 0x1A, 857 // 858 LSC_LOAD_STATUS = 0x1B, 859 LSC_STORE_UNCOMPRESSED = 0x1C, 860 LSC_CCS_UPDATE = 0x1D, 861 LSC_READ_STATE_INFO = 0x1E, 862 LSC_FENCE = 0x1F, 863 // 864 865 LSC_INVALID = 0xFFFFFFFF, 866 }; 867 static_assert(LSC_LOAD == 0x0, 868 "vISA binary encoding depends on enum ordinal value"); 869 static_assert(LSC_FENCE == 0x1F, 870 "vISA binary encoding depends on enum ordinal value"); 871 872 ///////////////////////////////////////////////////////////////////// 873 // The vISA spec depends on the enum values assigned. If you really 874 // need to change then, fix any consumers encoders dependent on the 875 // encoding (e.g. CM binary encoder) as well as the vISA spec. 876 // 877 static_assert(LSC_DATA_ELEMS_8 == 5, 878 "vISA binary encoding depends on enum ordinal value"); 879 static_assert(LSC_ADDR_SIZE_16b == 1, 880 "vISA binary encoding depends on enum ordinal value"); 881 static_assert(LSC_DATA_SIZE_8b == 1, 882 "vISA binary encoding depends on enum ordinal value"); 883 static_assert(LSC_DATA_SIZE_16b == 2, 884 "vISA binary encoding depends on enum ordinal value"); 885 static_assert(LSC_DATA_SIZE_32b == 3, 886 "vISA binary encoding depends on enum ordinal value"); 887 static_assert(LSC_DATA_SIZE_64b == 4, 888 "vISA binary encoding depends on enum ordinal value"); 889 static_assert(LSC_DATA_SIZE_16c32bH == 7, 890 "vISA binary encoding depends on enum ordinal value"); 891 static_assert(LSC_DATA_ORDER_NONTRANSPOSE == 1, 892 "vISA binary encoding depends on enum ordinal value"); 893 static_assert(LSC_DATA_ORDER_TRANSPOSE == 2, 894 "vISA binary encoding depends on enum ordinal value"); 895 static_assert(LSC_ADDR_TYPE_FLAT == 1, 896 "vISA binary encoding depends on enum ordinal value"); 897 static_assert(LSC_ADDR_TYPE_BTI == 4, 898 "vISA binary encoding depends on enum ordinal value"); 899 static_assert(LSC_CACHING_DEFAULT == 0, 900 "vISA binary encoding depends on enum ordinal value"); 901 static_assert(LSC_CACHING_READINVALIDATE == 6, 902 "vISA binary encoding depends on enum ordinal value"); 903 static_assert(LSC_FENCE_OP_NONE == 0, 904 "vISA binary encoding depends on enum ordinal value"); 905 static_assert(LSC_FENCE_OP_FLUSHL3 == 5, 906 "vISA binary encoding depends on enum ordinal value"); 907 908 // FixedFunctionID: these are hardware FFID values 909 enum FFID 910 { 911 FFID_NULL = 0x0, 912 FFID_VSR = 0x3, 913 FFID_HS = 0x4, 914 FFID_DS = 0x5, 915 FFID_TS = 0x6, 916 FFID_GP = 0x7, 917 FFID_GP1 = 0x8, 918 FFID_VS = 0x9, 919 FFID_GS = 0xC, 920 FFID_PS = 0xF, 921 922 FFID_INVALID = 0xFF 923 }; 924 925 #endif 926