1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class wraps target description classes used by the various code
10 // generation TableGen backends. This makes it easier to access the data and
11 // provides a single place that needs to check it for validity. All of these
12 // classes abort on error conditions.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "CodeGenTarget.h"
17 #include "CodeGenInstruction.h"
18 #include "CodeGenIntrinsics.h"
19 #include "CodeGenSchedule.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/TableGen/Error.h"
23 #include "llvm/TableGen/Record.h"
24 #include <algorithm>
25 using namespace llvm;
26
27 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser");
28 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer");
29
30 static cl::opt<unsigned>
31 AsmParserNum("asmparsernum", cl::init(0),
32 cl::desc("Make -gen-asm-parser emit assembly parser #N"),
33 cl::cat(AsmParserCat));
34
35 static cl::opt<unsigned>
36 AsmWriterNum("asmwriternum", cl::init(0),
37 cl::desc("Make -gen-asm-writer emit assembly writer #N"),
38 cl::cat(AsmWriterCat));
39
40 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
41 /// record corresponds to.
getValueType(Record * Rec)42 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
43 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
44 }
45
getName(MVT::SimpleValueType T)46 StringRef llvm::getName(MVT::SimpleValueType T) {
47 switch (T) {
48 case MVT::Other: return "UNKNOWN";
49 case MVT::iPTR: return "TLI.getPointerTy()";
50 case MVT::iPTRAny: return "TLI.getPointerTy()";
51 default: return getEnumName(T);
52 }
53 }
54
getEnumName(MVT::SimpleValueType T)55 StringRef llvm::getEnumName(MVT::SimpleValueType T) {
56 // clang-format off
57 switch (T) {
58 case MVT::Other: return "MVT::Other";
59 case MVT::i1: return "MVT::i1";
60 case MVT::i2: return "MVT::i2";
61 case MVT::i4: return "MVT::i4";
62 case MVT::i8: return "MVT::i8";
63 case MVT::i16: return "MVT::i16";
64 case MVT::i32: return "MVT::i32";
65 case MVT::i64: return "MVT::i64";
66 case MVT::i128: return "MVT::i128";
67 case MVT::Any: return "MVT::Any";
68 case MVT::iAny: return "MVT::iAny";
69 case MVT::fAny: return "MVT::fAny";
70 case MVT::vAny: return "MVT::vAny";
71 case MVT::f16: return "MVT::f16";
72 case MVT::bf16: return "MVT::bf16";
73 case MVT::f32: return "MVT::f32";
74 case MVT::f64: return "MVT::f64";
75 case MVT::f80: return "MVT::f80";
76 case MVT::f128: return "MVT::f128";
77 case MVT::ppcf128: return "MVT::ppcf128";
78 case MVT::x86mmx: return "MVT::x86mmx";
79 case MVT::x86amx: return "MVT::x86amx";
80 case MVT::i64x8: return "MVT::i64x8";
81 case MVT::Glue: return "MVT::Glue";
82 case MVT::isVoid: return "MVT::isVoid";
83 case MVT::v1i1: return "MVT::v1i1";
84 case MVT::v2i1: return "MVT::v2i1";
85 case MVT::v4i1: return "MVT::v4i1";
86 case MVT::v8i1: return "MVT::v8i1";
87 case MVT::v16i1: return "MVT::v16i1";
88 case MVT::v32i1: return "MVT::v32i1";
89 case MVT::v64i1: return "MVT::v64i1";
90 case MVT::v128i1: return "MVT::v128i1";
91 case MVT::v256i1: return "MVT::v256i1";
92 case MVT::v512i1: return "MVT::v512i1";
93 case MVT::v1024i1: return "MVT::v1024i1";
94 case MVT::v2048i1: return "MVT::v2048i1";
95 case MVT::v128i2: return "MVT::v128i2";
96 case MVT::v256i2: return "MVT::v256i2";
97 case MVT::v64i4: return "MVT::v64i4";
98 case MVT::v128i4: return "MVT::v128i4";
99 case MVT::v1i8: return "MVT::v1i8";
100 case MVT::v2i8: return "MVT::v2i8";
101 case MVT::v4i8: return "MVT::v4i8";
102 case MVT::v8i8: return "MVT::v8i8";
103 case MVT::v16i8: return "MVT::v16i8";
104 case MVT::v32i8: return "MVT::v32i8";
105 case MVT::v64i8: return "MVT::v64i8";
106 case MVT::v128i8: return "MVT::v128i8";
107 case MVT::v256i8: return "MVT::v256i8";
108 case MVT::v512i8: return "MVT::v512i8";
109 case MVT::v1024i8: return "MVT::v1024i8";
110 case MVT::v1i16: return "MVT::v1i16";
111 case MVT::v2i16: return "MVT::v2i16";
112 case MVT::v3i16: return "MVT::v3i16";
113 case MVT::v4i16: return "MVT::v4i16";
114 case MVT::v8i16: return "MVT::v8i16";
115 case MVT::v16i16: return "MVT::v16i16";
116 case MVT::v32i16: return "MVT::v32i16";
117 case MVT::v64i16: return "MVT::v64i16";
118 case MVT::v128i16: return "MVT::v128i16";
119 case MVT::v256i16: return "MVT::v256i16";
120 case MVT::v512i16: return "MVT::v512i16";
121 case MVT::v1i32: return "MVT::v1i32";
122 case MVT::v2i32: return "MVT::v2i32";
123 case MVT::v3i32: return "MVT::v3i32";
124 case MVT::v4i32: return "MVT::v4i32";
125 case MVT::v5i32: return "MVT::v5i32";
126 case MVT::v6i32: return "MVT::v6i32";
127 case MVT::v7i32: return "MVT::v7i32";
128 case MVT::v8i32: return "MVT::v8i32";
129 case MVT::v9i32: return "MVT::v9i32";
130 case MVT::v10i32: return "MVT::v10i32";
131 case MVT::v11i32: return "MVT::v11i32";
132 case MVT::v12i32: return "MVT::v12i32";
133 case MVT::v16i32: return "MVT::v16i32";
134 case MVT::v32i32: return "MVT::v32i32";
135 case MVT::v64i32: return "MVT::v64i32";
136 case MVT::v128i32: return "MVT::v128i32";
137 case MVT::v256i32: return "MVT::v256i32";
138 case MVT::v512i32: return "MVT::v512i32";
139 case MVT::v1024i32: return "MVT::v1024i32";
140 case MVT::v2048i32: return "MVT::v2048i32";
141 case MVT::v1i64: return "MVT::v1i64";
142 case MVT::v2i64: return "MVT::v2i64";
143 case MVT::v3i64: return "MVT::v3i64";
144 case MVT::v4i64: return "MVT::v4i64";
145 case MVT::v8i64: return "MVT::v8i64";
146 case MVT::v16i64: return "MVT::v16i64";
147 case MVT::v32i64: return "MVT::v32i64";
148 case MVT::v64i64: return "MVT::v64i64";
149 case MVT::v128i64: return "MVT::v128i64";
150 case MVT::v256i64: return "MVT::v256i64";
151 case MVT::v1i128: return "MVT::v1i128";
152 case MVT::v1f16: return "MVT::v1f16";
153 case MVT::v2f16: return "MVT::v2f16";
154 case MVT::v3f16: return "MVT::v3f16";
155 case MVT::v4f16: return "MVT::v4f16";
156 case MVT::v8f16: return "MVT::v8f16";
157 case MVT::v16f16: return "MVT::v16f16";
158 case MVT::v32f16: return "MVT::v32f16";
159 case MVT::v64f16: return "MVT::v64f16";
160 case MVT::v128f16: return "MVT::v128f16";
161 case MVT::v256f16: return "MVT::v256f16";
162 case MVT::v512f16: return "MVT::v512f16";
163 case MVT::v2bf16: return "MVT::v2bf16";
164 case MVT::v3bf16: return "MVT::v3bf16";
165 case MVT::v4bf16: return "MVT::v4bf16";
166 case MVT::v8bf16: return "MVT::v8bf16";
167 case MVT::v16bf16: return "MVT::v16bf16";
168 case MVT::v32bf16: return "MVT::v32bf16";
169 case MVT::v64bf16: return "MVT::v64bf16";
170 case MVT::v128bf16: return "MVT::v128bf16";
171 case MVT::v1f32: return "MVT::v1f32";
172 case MVT::v2f32: return "MVT::v2f32";
173 case MVT::v3f32: return "MVT::v3f32";
174 case MVT::v4f32: return "MVT::v4f32";
175 case MVT::v5f32: return "MVT::v5f32";
176 case MVT::v6f32: return "MVT::v6f32";
177 case MVT::v7f32: return "MVT::v7f32";
178 case MVT::v8f32: return "MVT::v8f32";
179 case MVT::v9f32: return "MVT::v9f32";
180 case MVT::v10f32: return "MVT::v10f32";
181 case MVT::v11f32: return "MVT::v11f32";
182 case MVT::v12f32: return "MVT::v12f32";
183 case MVT::v16f32: return "MVT::v16f32";
184 case MVT::v32f32: return "MVT::v32f32";
185 case MVT::v64f32: return "MVT::v64f32";
186 case MVT::v128f32: return "MVT::v128f32";
187 case MVT::v256f32: return "MVT::v256f32";
188 case MVT::v512f32: return "MVT::v512f32";
189 case MVT::v1024f32: return "MVT::v1024f32";
190 case MVT::v2048f32: return "MVT::v2048f32";
191 case MVT::v1f64: return "MVT::v1f64";
192 case MVT::v2f64: return "MVT::v2f64";
193 case MVT::v3f64: return "MVT::v3f64";
194 case MVT::v4f64: return "MVT::v4f64";
195 case MVT::v8f64: return "MVT::v8f64";
196 case MVT::v16f64: return "MVT::v16f64";
197 case MVT::v32f64: return "MVT::v32f64";
198 case MVT::v64f64: return "MVT::v64f64";
199 case MVT::v128f64: return "MVT::v128f64";
200 case MVT::v256f64: return "MVT::v256f64";
201 case MVT::nxv1i1: return "MVT::nxv1i1";
202 case MVT::nxv2i1: return "MVT::nxv2i1";
203 case MVT::nxv4i1: return "MVT::nxv4i1";
204 case MVT::nxv8i1: return "MVT::nxv8i1";
205 case MVT::nxv16i1: return "MVT::nxv16i1";
206 case MVT::nxv32i1: return "MVT::nxv32i1";
207 case MVT::nxv64i1: return "MVT::nxv64i1";
208 case MVT::nxv1i8: return "MVT::nxv1i8";
209 case MVT::nxv2i8: return "MVT::nxv2i8";
210 case MVT::nxv4i8: return "MVT::nxv4i8";
211 case MVT::nxv8i8: return "MVT::nxv8i8";
212 case MVT::nxv16i8: return "MVT::nxv16i8";
213 case MVT::nxv32i8: return "MVT::nxv32i8";
214 case MVT::nxv64i8: return "MVT::nxv64i8";
215 case MVT::nxv1i16: return "MVT::nxv1i16";
216 case MVT::nxv2i16: return "MVT::nxv2i16";
217 case MVT::nxv4i16: return "MVT::nxv4i16";
218 case MVT::nxv8i16: return "MVT::nxv8i16";
219 case MVT::nxv16i16: return "MVT::nxv16i16";
220 case MVT::nxv32i16: return "MVT::nxv32i16";
221 case MVT::nxv1i32: return "MVT::nxv1i32";
222 case MVT::nxv2i32: return "MVT::nxv2i32";
223 case MVT::nxv4i32: return "MVT::nxv4i32";
224 case MVT::nxv8i32: return "MVT::nxv8i32";
225 case MVT::nxv16i32: return "MVT::nxv16i32";
226 case MVT::nxv32i32: return "MVT::nxv32i32";
227 case MVT::nxv1i64: return "MVT::nxv1i64";
228 case MVT::nxv2i64: return "MVT::nxv2i64";
229 case MVT::nxv4i64: return "MVT::nxv4i64";
230 case MVT::nxv8i64: return "MVT::nxv8i64";
231 case MVT::nxv16i64: return "MVT::nxv16i64";
232 case MVT::nxv32i64: return "MVT::nxv32i64";
233 case MVT::nxv1f16: return "MVT::nxv1f16";
234 case MVT::nxv2f16: return "MVT::nxv2f16";
235 case MVT::nxv4f16: return "MVT::nxv4f16";
236 case MVT::nxv8f16: return "MVT::nxv8f16";
237 case MVT::nxv16f16: return "MVT::nxv16f16";
238 case MVT::nxv32f16: return "MVT::nxv32f16";
239 case MVT::nxv1bf16: return "MVT::nxv1bf16";
240 case MVT::nxv2bf16: return "MVT::nxv2bf16";
241 case MVT::nxv4bf16: return "MVT::nxv4bf16";
242 case MVT::nxv8bf16: return "MVT::nxv8bf16";
243 case MVT::nxv16bf16: return "MVT::nxv16bf16";
244 case MVT::nxv32bf16: return "MVT::nxv32bf16";
245 case MVT::nxv1f32: return "MVT::nxv1f32";
246 case MVT::nxv2f32: return "MVT::nxv2f32";
247 case MVT::nxv4f32: return "MVT::nxv4f32";
248 case MVT::nxv8f32: return "MVT::nxv8f32";
249 case MVT::nxv16f32: return "MVT::nxv16f32";
250 case MVT::nxv1f64: return "MVT::nxv1f64";
251 case MVT::nxv2f64: return "MVT::nxv2f64";
252 case MVT::nxv4f64: return "MVT::nxv4f64";
253 case MVT::nxv8f64: return "MVT::nxv8f64";
254 case MVT::token: return "MVT::token";
255 case MVT::Metadata: return "MVT::Metadata";
256 case MVT::iPTR: return "MVT::iPTR";
257 case MVT::iPTRAny: return "MVT::iPTRAny";
258 case MVT::Untyped: return "MVT::Untyped";
259 case MVT::funcref: return "MVT::funcref";
260 case MVT::externref: return "MVT::externref";
261 default: llvm_unreachable("ILLEGAL VALUE TYPE!");
262 }
263 // clang-format on
264 }
265
266 /// getQualifiedName - Return the name of the specified record, with a
267 /// namespace qualifier if the record contains one.
268 ///
getQualifiedName(const Record * R)269 std::string llvm::getQualifiedName(const Record *R) {
270 std::string Namespace;
271 if (R->getValue("Namespace"))
272 Namespace = std::string(R->getValueAsString("Namespace"));
273 if (Namespace.empty())
274 return std::string(R->getName());
275 return Namespace + "::" + R->getName().str();
276 }
277
278
279 /// getTarget - Return the current instance of the Target class.
280 ///
CodeGenTarget(RecordKeeper & records)281 CodeGenTarget::CodeGenTarget(RecordKeeper &records)
282 : Records(records), CGH(records) {
283 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
284 if (Targets.size() == 0)
285 PrintFatalError("No 'Target' subclasses defined!");
286 if (Targets.size() != 1)
287 PrintFatalError("Multiple subclasses of Target defined!");
288 TargetRec = Targets[0];
289 }
290
~CodeGenTarget()291 CodeGenTarget::~CodeGenTarget() {
292 }
293
getName() const294 StringRef CodeGenTarget::getName() const { return TargetRec->getName(); }
295
296 /// getInstNamespace - Find and return the target machine's instruction
297 /// namespace. The namespace is cached because it is requested multiple times.
getInstNamespace() const298 StringRef CodeGenTarget::getInstNamespace() const {
299 if (InstNamespace.empty()) {
300 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) {
301 // We are not interested in the "TargetOpcode" namespace.
302 if (Inst->Namespace != "TargetOpcode") {
303 InstNamespace = Inst->Namespace;
304 break;
305 }
306 }
307 }
308
309 return InstNamespace;
310 }
311
getRegNamespace() const312 StringRef CodeGenTarget::getRegNamespace() const {
313 auto &RegClasses = RegBank->getRegClasses();
314 return RegClasses.size() > 0 ? RegClasses.front().Namespace : "";
315 }
316
getInstructionSet() const317 Record *CodeGenTarget::getInstructionSet() const {
318 return TargetRec->getValueAsDef("InstructionSet");
319 }
320
getAllowRegisterRenaming() const321 bool CodeGenTarget::getAllowRegisterRenaming() const {
322 return TargetRec->getValueAsInt("AllowRegisterRenaming");
323 }
324
325 /// getAsmParser - Return the AssemblyParser definition for this target.
326 ///
getAsmParser() const327 Record *CodeGenTarget::getAsmParser() const {
328 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
329 if (AsmParserNum >= LI.size())
330 PrintFatalError("Target does not have an AsmParser #" +
331 Twine(AsmParserNum) + "!");
332 return LI[AsmParserNum];
333 }
334
335 /// getAsmParserVariant - Return the AssemblyParserVariant definition for
336 /// this target.
337 ///
getAsmParserVariant(unsigned i) const338 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
339 std::vector<Record*> LI =
340 TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
341 if (i >= LI.size())
342 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) +
343 "!");
344 return LI[i];
345 }
346
347 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition
348 /// available for this target.
349 ///
getAsmParserVariantCount() const350 unsigned CodeGenTarget::getAsmParserVariantCount() const {
351 std::vector<Record*> LI =
352 TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
353 return LI.size();
354 }
355
356 /// getAsmWriter - Return the AssemblyWriter definition for this target.
357 ///
getAsmWriter() const358 Record *CodeGenTarget::getAsmWriter() const {
359 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
360 if (AsmWriterNum >= LI.size())
361 PrintFatalError("Target does not have an AsmWriter #" +
362 Twine(AsmWriterNum) + "!");
363 return LI[AsmWriterNum];
364 }
365
getRegBank() const366 CodeGenRegBank &CodeGenTarget::getRegBank() const {
367 if (!RegBank)
368 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes());
369 return *RegBank;
370 }
371
getSuperRegForSubReg(const ValueTypeByHwMode & ValueTy,CodeGenRegBank & RegBank,const CodeGenSubRegIndex * SubIdx,bool MustBeAllocatable) const372 std::optional<CodeGenRegisterClass *> CodeGenTarget::getSuperRegForSubReg(
373 const ValueTypeByHwMode &ValueTy, CodeGenRegBank &RegBank,
374 const CodeGenSubRegIndex *SubIdx, bool MustBeAllocatable) const {
375 std::vector<CodeGenRegisterClass *> Candidates;
376 auto &RegClasses = RegBank.getRegClasses();
377
378 // Try to find a register class which supports ValueTy, and also contains
379 // SubIdx.
380 for (CodeGenRegisterClass &RC : RegClasses) {
381 // Is there a subclass of this class which contains this subregister index?
382 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx);
383 if (!SubClassWithSubReg)
384 continue;
385
386 // We have a class. Check if it supports this value type.
387 if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy))
388 continue;
389
390 // If necessary, check that it is allocatable.
391 if (MustBeAllocatable && !SubClassWithSubReg->Allocatable)
392 continue;
393
394 // We have a register class which supports both the value type and
395 // subregister index. Remember it.
396 Candidates.push_back(SubClassWithSubReg);
397 }
398
399 // If we didn't find anything, we're done.
400 if (Candidates.empty())
401 return std::nullopt;
402
403 // Find and return the largest of our candidate classes.
404 llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A,
405 const CodeGenRegisterClass *B) {
406 if (A->getMembers().size() > B->getMembers().size())
407 return true;
408
409 if (A->getMembers().size() < B->getMembers().size())
410 return false;
411
412 // Order by name as a tie-breaker.
413 return StringRef(A->getName()) < B->getName();
414 });
415
416 return Candidates[0];
417 }
418
ReadRegAltNameIndices() const419 void CodeGenTarget::ReadRegAltNameIndices() const {
420 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
421 llvm::sort(RegAltNameIndices, LessRecord());
422 }
423
424 /// getRegisterByName - If there is a register with the specific AsmName,
425 /// return it.
getRegisterByName(StringRef Name) const426 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
427 return getRegBank().getRegistersByName().lookup(Name);
428 }
429
getRegisterVTs(Record * R) const430 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
431 const {
432 const CodeGenRegister *Reg = getRegBank().getReg(R);
433 std::vector<ValueTypeByHwMode> Result;
434 for (const auto &RC : getRegBank().getRegClasses()) {
435 if (RC.contains(Reg)) {
436 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes();
437 llvm::append_range(Result, InVTs);
438 }
439 }
440
441 // Remove duplicates.
442 llvm::sort(Result);
443 Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
444 return Result;
445 }
446
447
ReadLegalValueTypes() const448 void CodeGenTarget::ReadLegalValueTypes() const {
449 for (const auto &RC : getRegBank().getRegClasses())
450 llvm::append_range(LegalValueTypes, RC.VTs);
451
452 // Remove duplicates.
453 llvm::sort(LegalValueTypes);
454 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
455 LegalValueTypes.end()),
456 LegalValueTypes.end());
457 }
458
getSchedModels() const459 CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
460 if (!SchedModels)
461 SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this);
462 return *SchedModels;
463 }
464
ReadInstructions() const465 void CodeGenTarget::ReadInstructions() const {
466 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
467 if (Insts.size() <= 2)
468 PrintFatalError("No 'Instruction' subclasses defined!");
469
470 // Parse the instructions defined in the .td file.
471 for (unsigned i = 0, e = Insts.size(); i != e; ++i)
472 Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]);
473 }
474
475 static const CodeGenInstruction *
GetInstByName(const char * Name,const DenseMap<const Record *,std::unique_ptr<CodeGenInstruction>> & Insts,RecordKeeper & Records)476 GetInstByName(const char *Name,
477 const DenseMap<const Record*,
478 std::unique_ptr<CodeGenInstruction>> &Insts,
479 RecordKeeper &Records) {
480 const Record *Rec = Records.getDef(Name);
481
482 const auto I = Insts.find(Rec);
483 if (!Rec || I == Insts.end())
484 PrintFatalError(Twine("Could not find '") + Name + "' instruction!");
485 return I->second.get();
486 }
487
488 static const char *FixedInstrs[] = {
489 #define HANDLE_TARGET_OPCODE(OPC) #OPC,
490 #include "llvm/Support/TargetOpcodes.def"
491 nullptr};
492
getNumFixedInstructions()493 unsigned CodeGenTarget::getNumFixedInstructions() {
494 return std::size(FixedInstrs) - 1;
495 }
496
497 /// Return all of the instructions defined by the target, ordered by
498 /// their enum value.
ComputeInstrsByEnum() const499 void CodeGenTarget::ComputeInstrsByEnum() const {
500 const auto &Insts = getInstructions();
501 for (const char *const *p = FixedInstrs; *p; ++p) {
502 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
503 assert(Instr && "Missing target independent instruction");
504 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
505 InstrsByEnum.push_back(Instr);
506 }
507 unsigned EndOfPredefines = InstrsByEnum.size();
508 assert(EndOfPredefines == getNumFixedInstructions() &&
509 "Missing generic opcode");
510
511 for (const auto &I : Insts) {
512 const CodeGenInstruction *CGI = I.second.get();
513 if (CGI->Namespace != "TargetOpcode") {
514 InstrsByEnum.push_back(CGI);
515 if (CGI->TheDef->getValueAsBit("isPseudo"))
516 ++NumPseudoInstructions;
517 }
518 }
519
520 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
521
522 // All of the instructions are now in random order based on the map iteration.
523 llvm::sort(
524 InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(),
525 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) {
526 const auto &D1 = *Rec1->TheDef;
527 const auto &D2 = *Rec2->TheDef;
528 return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) <
529 std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName());
530 });
531 }
532
533
534 /// isLittleEndianEncoding - Return whether this target encodes its instruction
535 /// in little-endian format, i.e. bits laid out in the order [0..n]
536 ///
isLittleEndianEncoding() const537 bool CodeGenTarget::isLittleEndianEncoding() const {
538 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
539 }
540
541 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
542 /// encodings, reverse the bit order of all instructions.
reverseBitsForLittleEndianEncoding()543 void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
544 if (!isLittleEndianEncoding())
545 return;
546
547 std::vector<Record *> Insts =
548 Records.getAllDerivedDefinitions("InstructionEncoding");
549 for (Record *R : Insts) {
550 if (R->getValueAsString("Namespace") == "TargetOpcode" ||
551 R->getValueAsBit("isPseudo"))
552 continue;
553
554 BitsInit *BI = R->getValueAsBitsInit("Inst");
555
556 unsigned numBits = BI->getNumBits();
557
558 SmallVector<Init *, 16> NewBits(numBits);
559
560 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
561 unsigned bitSwapIdx = numBits - bit - 1;
562 Init *OrigBit = BI->getBit(bit);
563 Init *BitSwap = BI->getBit(bitSwapIdx);
564 NewBits[bit] = BitSwap;
565 NewBits[bitSwapIdx] = OrigBit;
566 }
567 if (numBits % 2) {
568 unsigned middle = (numBits + 1) / 2;
569 NewBits[middle] = BI->getBit(middle);
570 }
571
572 BitsInit *NewBI = BitsInit::get(Records, NewBits);
573
574 // Update the bits in reversed order so that emitInstrOpBits will get the
575 // correct endianness.
576 R->getValue("Inst")->setValue(NewBI);
577 }
578 }
579
580 /// guessInstructionProperties - Return true if it's OK to guess instruction
581 /// properties instead of raising an error.
582 ///
583 /// This is configurable as a temporary migration aid. It will eventually be
584 /// permanently false.
guessInstructionProperties() const585 bool CodeGenTarget::guessInstructionProperties() const {
586 return getInstructionSet()->getValueAsBit("guessInstructionProperties");
587 }
588
589 //===----------------------------------------------------------------------===//
590 // ComplexPattern implementation
591 //
ComplexPattern(Record * R)592 ComplexPattern::ComplexPattern(Record *R) {
593 Ty = R->getValueAsDef("Ty");
594 NumOperands = R->getValueAsInt("NumOperands");
595 SelectFunc = std::string(R->getValueAsString("SelectFunc"));
596 RootNodes = R->getValueAsListOfDefs("RootNodes");
597
598 // FIXME: This is a hack to statically increase the priority of patterns which
599 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best
600 // possible pattern match we'll need to dynamically calculate the complexity
601 // of all patterns a dag can potentially map to.
602 int64_t RawComplexity = R->getValueAsInt("Complexity");
603 if (RawComplexity == -1)
604 Complexity = NumOperands * 3;
605 else
606 Complexity = RawComplexity;
607
608 // FIXME: Why is this different from parseSDPatternOperatorProperties?
609 // Parse the properties.
610 Properties = 0;
611 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
612 for (unsigned i = 0, e = PropList.size(); i != e; ++i)
613 if (PropList[i]->getName() == "SDNPHasChain") {
614 Properties |= 1 << SDNPHasChain;
615 } else if (PropList[i]->getName() == "SDNPOptInGlue") {
616 Properties |= 1 << SDNPOptInGlue;
617 } else if (PropList[i]->getName() == "SDNPMayStore") {
618 Properties |= 1 << SDNPMayStore;
619 } else if (PropList[i]->getName() == "SDNPMayLoad") {
620 Properties |= 1 << SDNPMayLoad;
621 } else if (PropList[i]->getName() == "SDNPSideEffect") {
622 Properties |= 1 << SDNPSideEffect;
623 } else if (PropList[i]->getName() == "SDNPMemOperand") {
624 Properties |= 1 << SDNPMemOperand;
625 } else if (PropList[i]->getName() == "SDNPVariadic") {
626 Properties |= 1 << SDNPVariadic;
627 } else if (PropList[i]->getName() == "SDNPWantRoot") {
628 Properties |= 1 << SDNPWantRoot;
629 } else if (PropList[i]->getName() == "SDNPWantParent") {
630 Properties |= 1 << SDNPWantParent;
631 } else {
632 PrintFatalError(R->getLoc(), "Unsupported SD Node property '" +
633 PropList[i]->getName() +
634 "' on ComplexPattern '" + R->getName() +
635 "'!");
636 }
637 }
638
639 //===----------------------------------------------------------------------===//
640 // CodeGenIntrinsic Implementation
641 //===----------------------------------------------------------------------===//
642
CodeGenIntrinsicTable(const RecordKeeper & RC)643 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) {
644 std::vector<Record *> IntrProperties =
645 RC.getAllDerivedDefinitions("IntrinsicProperty");
646
647 std::vector<Record *> DefaultProperties;
648 for (Record *Rec : IntrProperties)
649 if (Rec->getValueAsBit("IsDefault"))
650 DefaultProperties.push_back(Rec);
651
652 std::vector<Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic");
653 Intrinsics.reserve(Defs.size());
654
655 for (unsigned I = 0, e = Defs.size(); I != e; ++I)
656 Intrinsics.push_back(CodeGenIntrinsic(Defs[I], DefaultProperties));
657
658 llvm::sort(Intrinsics,
659 [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) {
660 return std::tie(LHS.TargetPrefix, LHS.Name) <
661 std::tie(RHS.TargetPrefix, RHS.Name);
662 });
663 Targets.push_back({"", 0, 0});
664 for (size_t I = 0, E = Intrinsics.size(); I < E; ++I)
665 if (Intrinsics[I].TargetPrefix != Targets.back().Name) {
666 Targets.back().Count = I - Targets.back().Offset;
667 Targets.push_back({Intrinsics[I].TargetPrefix, I, 0});
668 }
669 Targets.back().Count = Intrinsics.size() - Targets.back().Offset;
670 }
671
CodeGenIntrinsic(Record * R,std::vector<Record * > DefaultProperties)672 CodeGenIntrinsic::CodeGenIntrinsic(Record *R,
673 std::vector<Record *> DefaultProperties) {
674 TheDef = R;
675 std::string DefName = std::string(R->getName());
676 ArrayRef<SMLoc> DefLoc = R->getLoc();
677 Properties = 0;
678 isOverloaded = false;
679 isCommutative = false;
680 canThrow = false;
681 isNoReturn = false;
682 isNoCallback = false;
683 isNoSync = false;
684 isNoFree = false;
685 isWillReturn = false;
686 isCold = false;
687 isNoDuplicate = false;
688 isNoMerge = false;
689 isConvergent = false;
690 isSpeculatable = false;
691 hasSideEffects = false;
692
693 if (DefName.size() <= 4 || DefName.substr(0, 4) != "int_")
694 PrintFatalError(DefLoc,
695 "Intrinsic '" + DefName + "' does not start with 'int_'!");
696
697 EnumName = DefName.substr(4);
698
699 if (R->getValue("ClangBuiltinName")) // Ignore a missing ClangBuiltinName field.
700 ClangBuiltinName = std::string(R->getValueAsString("ClangBuiltinName"));
701 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field.
702 MSBuiltinName = std::string(R->getValueAsString("MSBuiltinName"));
703
704 TargetPrefix = std::string(R->getValueAsString("TargetPrefix"));
705 Name = std::string(R->getValueAsString("LLVMName"));
706
707 if (Name == "") {
708 // If an explicit name isn't specified, derive one from the DefName.
709 Name = "llvm.";
710
711 for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
712 Name += (EnumName[i] == '_') ? '.' : EnumName[i];
713 } else {
714 // Verify it starts with "llvm.".
715 if (Name.size() <= 5 || Name.substr(0, 5) != "llvm.")
716 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
717 "'s name does not start with 'llvm.'!");
718 }
719
720 // If TargetPrefix is specified, make sure that Name starts with
721 // "llvm.<targetprefix>.".
722 if (!TargetPrefix.empty()) {
723 if (Name.size() < 6+TargetPrefix.size() ||
724 Name.substr(5, 1 + TargetPrefix.size()) != (TargetPrefix + "."))
725 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
726 "' does not start with 'llvm." +
727 TargetPrefix + ".'!");
728 }
729
730 ListInit *RetTypes = R->getValueAsListInit("RetTypes");
731 ListInit *ParamTypes = R->getValueAsListInit("ParamTypes");
732
733 // First collate a list of overloaded types.
734 std::vector<MVT::SimpleValueType> OverloadedVTs;
735 for (ListInit *TypeList : {RetTypes, ParamTypes}) {
736 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
737 Record *TyEl = TypeList->getElementAsRecord(i);
738 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
739
740 if (TyEl->isSubClassOf("LLVMMatchType"))
741 continue;
742
743 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT"));
744 if (MVT(VT).isOverloaded()) {
745 OverloadedVTs.push_back(VT);
746 isOverloaded = true;
747 }
748 }
749 }
750
751 // Parse the list of return types.
752 ListInit *TypeList = RetTypes;
753 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
754 Record *TyEl = TypeList->getElementAsRecord(i);
755 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
756 MVT::SimpleValueType VT;
757 if (TyEl->isSubClassOf("LLVMMatchType")) {
758 unsigned MatchTy = TyEl->getValueAsInt("Number");
759 assert(MatchTy < OverloadedVTs.size() &&
760 "Invalid matching number!");
761 VT = OverloadedVTs[MatchTy];
762 // It only makes sense to use the extended and truncated vector element
763 // variants with iAny types; otherwise, if the intrinsic is not
764 // overloaded, all the types can be specified directly.
765 assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
766 !TyEl->isSubClassOf("LLVMTruncatedType")) ||
767 VT == MVT::iAny || VT == MVT::vAny) &&
768 "Expected iAny or vAny type");
769 } else {
770 VT = getValueType(TyEl->getValueAsDef("VT"));
771 }
772
773 // Reject invalid types.
774 if (VT == MVT::isVoid)
775 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
776 " has void in result type list!");
777
778 IS.RetVTs.push_back(VT);
779 IS.RetTypeDefs.push_back(TyEl);
780 }
781
782 // Parse the list of parameter types.
783 TypeList = ParamTypes;
784 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
785 Record *TyEl = TypeList->getElementAsRecord(i);
786 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
787 MVT::SimpleValueType VT;
788 if (TyEl->isSubClassOf("LLVMMatchType")) {
789 unsigned MatchTy = TyEl->getValueAsInt("Number");
790 if (MatchTy >= OverloadedVTs.size()) {
791 PrintError(R->getLoc(),
792 "Parameter #" + Twine(i) + " has out of bounds matching "
793 "number " + Twine(MatchTy));
794 PrintFatalError(DefLoc,
795 Twine("ParamTypes is ") + TypeList->getAsString());
796 }
797 VT = OverloadedVTs[MatchTy];
798 // It only makes sense to use the extended and truncated vector element
799 // variants with iAny types; otherwise, if the intrinsic is not
800 // overloaded, all the types can be specified directly.
801 assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
802 !TyEl->isSubClassOf("LLVMTruncatedType")) ||
803 VT == MVT::iAny || VT == MVT::vAny) &&
804 "Expected iAny or vAny type");
805 } else
806 VT = getValueType(TyEl->getValueAsDef("VT"));
807
808 // Reject invalid types.
809 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/)
810 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
811 " has void in result type list!");
812
813 IS.ParamVTs.push_back(VT);
814 IS.ParamTypeDefs.push_back(TyEl);
815 }
816
817 // Parse the intrinsic properties.
818 ListInit *PropList = R->getValueAsListInit("IntrProperties");
819 for (unsigned i = 0, e = PropList->size(); i != e; ++i) {
820 Record *Property = PropList->getElementAsRecord(i);
821 assert(Property->isSubClassOf("IntrinsicProperty") &&
822 "Expected a property!");
823
824 setProperty(Property);
825 }
826
827 // Set default properties to true.
828 setDefaultProperties(R, DefaultProperties);
829
830 // Also record the SDPatternOperator Properties.
831 Properties = parseSDPatternOperatorProperties(R);
832
833 // Sort the argument attributes for later benefit.
834 for (auto &Attrs : ArgumentAttributes)
835 llvm::sort(Attrs);
836 }
837
setDefaultProperties(Record * R,std::vector<Record * > DefaultProperties)838 void CodeGenIntrinsic::setDefaultProperties(
839 Record *R, std::vector<Record *> DefaultProperties) {
840 // opt-out of using default attributes.
841 if (R->getValueAsBit("DisableDefaultAttributes"))
842 return;
843
844 for (Record *Rec : DefaultProperties)
845 setProperty(Rec);
846 }
847
setProperty(Record * R)848 void CodeGenIntrinsic::setProperty(Record *R) {
849 if (R->getName() == "IntrNoMem")
850 ME = MemoryEffects::none();
851 else if (R->getName() == "IntrReadMem") {
852 if (ME.onlyWritesMemory())
853 PrintFatalError(TheDef->getLoc(),
854 Twine("IntrReadMem cannot be used after IntrNoMem or "
855 "IntrWriteMem. Default is ReadWrite"));
856 ME &= MemoryEffects::readOnly();
857 } else if (R->getName() == "IntrWriteMem") {
858 if (ME.onlyReadsMemory())
859 PrintFatalError(TheDef->getLoc(),
860 Twine("IntrWriteMem cannot be used after IntrNoMem or "
861 "IntrReadMem. Default is ReadWrite"));
862 ME &= MemoryEffects::writeOnly();
863 } else if (R->getName() == "IntrArgMemOnly")
864 ME &= MemoryEffects::argMemOnly();
865 else if (R->getName() == "IntrInaccessibleMemOnly")
866 ME &= MemoryEffects::inaccessibleMemOnly();
867 else if (R->getName() == "IntrInaccessibleMemOrArgMemOnly")
868 ME &= MemoryEffects::inaccessibleOrArgMemOnly();
869 else if (R->getName() == "Commutative")
870 isCommutative = true;
871 else if (R->getName() == "Throws")
872 canThrow = true;
873 else if (R->getName() == "IntrNoDuplicate")
874 isNoDuplicate = true;
875 else if (R->getName() == "IntrNoMerge")
876 isNoMerge = true;
877 else if (R->getName() == "IntrConvergent")
878 isConvergent = true;
879 else if (R->getName() == "IntrNoReturn")
880 isNoReturn = true;
881 else if (R->getName() == "IntrNoCallback")
882 isNoCallback = true;
883 else if (R->getName() == "IntrNoSync")
884 isNoSync = true;
885 else if (R->getName() == "IntrNoFree")
886 isNoFree = true;
887 else if (R->getName() == "IntrWillReturn")
888 isWillReturn = !isNoReturn;
889 else if (R->getName() == "IntrCold")
890 isCold = true;
891 else if (R->getName() == "IntrSpeculatable")
892 isSpeculatable = true;
893 else if (R->getName() == "IntrHasSideEffects")
894 hasSideEffects = true;
895 else if (R->isSubClassOf("NoCapture")) {
896 unsigned ArgNo = R->getValueAsInt("ArgNo");
897 addArgAttribute(ArgNo, NoCapture);
898 } else if (R->isSubClassOf("NoAlias")) {
899 unsigned ArgNo = R->getValueAsInt("ArgNo");
900 addArgAttribute(ArgNo, NoAlias);
901 } else if (R->isSubClassOf("NoUndef")) {
902 unsigned ArgNo = R->getValueAsInt("ArgNo");
903 addArgAttribute(ArgNo, NoUndef);
904 } else if (R->isSubClassOf("NonNull")) {
905 unsigned ArgNo = R->getValueAsInt("ArgNo");
906 addArgAttribute(ArgNo, NonNull);
907 } else if (R->isSubClassOf("Returned")) {
908 unsigned ArgNo = R->getValueAsInt("ArgNo");
909 addArgAttribute(ArgNo, Returned);
910 } else if (R->isSubClassOf("ReadOnly")) {
911 unsigned ArgNo = R->getValueAsInt("ArgNo");
912 addArgAttribute(ArgNo, ReadOnly);
913 } else if (R->isSubClassOf("WriteOnly")) {
914 unsigned ArgNo = R->getValueAsInt("ArgNo");
915 addArgAttribute(ArgNo, WriteOnly);
916 } else if (R->isSubClassOf("ReadNone")) {
917 unsigned ArgNo = R->getValueAsInt("ArgNo");
918 addArgAttribute(ArgNo, ReadNone);
919 } else if (R->isSubClassOf("ImmArg")) {
920 unsigned ArgNo = R->getValueAsInt("ArgNo");
921 addArgAttribute(ArgNo, ImmArg);
922 } else if (R->isSubClassOf("Align")) {
923 unsigned ArgNo = R->getValueAsInt("ArgNo");
924 uint64_t Align = R->getValueAsInt("Align");
925 addArgAttribute(ArgNo, Alignment, Align);
926 } else
927 llvm_unreachable("Unknown property!");
928 }
929
isParamAPointer(unsigned ParamIdx) const930 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const {
931 if (ParamIdx >= IS.ParamVTs.size())
932 return false;
933 MVT ParamType = MVT(IS.ParamVTs[ParamIdx]);
934 return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny;
935 }
936
isParamImmArg(unsigned ParamIdx) const937 bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const {
938 // Convert argument index to attribute index starting from `FirstArgIndex`.
939 ++ParamIdx;
940 if (ParamIdx >= ArgumentAttributes.size())
941 return false;
942 ArgAttribute Val{ImmArg, 0};
943 return std::binary_search(ArgumentAttributes[ParamIdx].begin(),
944 ArgumentAttributes[ParamIdx].end(), Val);
945 }
946
addArgAttribute(unsigned Idx,ArgAttrKind AK,uint64_t V)947 void CodeGenIntrinsic::addArgAttribute(unsigned Idx, ArgAttrKind AK,
948 uint64_t V) {
949 if (Idx >= ArgumentAttributes.size())
950 ArgumentAttributes.resize(Idx + 1);
951 ArgumentAttributes[Idx].emplace_back(AK, V);
952 }
953