1 //===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineOperand class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_MACHINEOPERAND_H
14 #define LLVM_CODEGEN_MACHINEOPERAND_H
15 
16 #include "llvm/ADT/DenseMapInfo.h"
17 #include "llvm/CodeGen/Register.h"
18 #include "llvm/IR/Intrinsics.h"
19 #include <cassert>
20 
21 namespace llvm {
22 
23 class LLT;
24 class BlockAddress;
25 class Constant;
26 class ConstantFP;
27 class ConstantInt;
28 class GlobalValue;
29 class MachineBasicBlock;
30 class MachineInstr;
31 class MachineRegisterInfo;
32 class MCCFIInstruction;
33 class MDNode;
34 class ModuleSlotTracker;
35 class TargetIntrinsicInfo;
36 class TargetRegisterInfo;
37 class hash_code;
38 class raw_ostream;
39 class MCSymbol;
40 
41 /// MachineOperand class - Representation of each machine instruction operand.
42 ///
43 /// This class isn't a POD type because it has a private constructor, but its
44 /// destructor must be trivial. Functions like MachineInstr::addOperand(),
45 /// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
46 /// not having to call the MachineOperand destructor.
47 ///
48 class MachineOperand {
49 public:
50   enum MachineOperandType : unsigned char {
51     MO_Register,          ///< Register operand.
52     MO_Immediate,         ///< Immediate operand
53     MO_CImmediate,        ///< Immediate >64bit operand
54     MO_FPImmediate,       ///< Floating-point immediate operand
55     MO_MachineBasicBlock, ///< MachineBasicBlock reference
56     MO_FrameIndex,        ///< Abstract Stack Frame Index
57     MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
58     MO_TargetIndex,       ///< Target-dependent index+offset operand.
59     MO_JumpTableIndex,    ///< Address of indexed Jump Table for switch
60     MO_ExternalSymbol,    ///< Name of external global symbol
61     MO_GlobalAddress,     ///< Address of a global value
62     MO_BlockAddress,      ///< Address of a basic block
63     MO_RegisterMask,      ///< Mask of preserved registers.
64     MO_RegisterLiveOut,   ///< Mask of live-out registers.
65     MO_Metadata,          ///< Metadata reference (for debug info)
66     MO_MCSymbol,          ///< MCSymbol reference (for debug/eh info)
67     MO_CFIIndex,          ///< MCCFIInstruction index.
68     MO_IntrinsicID,       ///< Intrinsic ID for ISel
69     MO_Predicate,         ///< Generic predicate for ISel
70     MO_ShuffleMask,       ///< Other IR Constant for ISel (shuffle masks)
71     MO_DbgInstrRef, ///< Integer indices referring to an instruction+operand
72     MO_Last = MO_DbgInstrRef
73   };
74 
75 private:
76   /// OpKind - Specify what kind of operand this is.  This discriminates the
77   /// union.
78   unsigned OpKind : 8;
79 
80   /// Subregister number for MO_Register.  A value of 0 indicates the
81   /// MO_Register has no subReg.
82   ///
83   /// For all other kinds of operands, this field holds target-specific flags.
84   unsigned SubReg_TargetFlags : 12;
85 
86   /// TiedTo - Non-zero when this register operand is tied to another register
87   /// operand. The encoding of this field is described in the block comment
88   /// before MachineInstr::tieOperands().
89   unsigned TiedTo : 4;
90 
91   /// IsDef - True if this is a def, false if this is a use of the register.
92   /// This is only valid on register operands.
93   ///
94   unsigned IsDef : 1;
95 
96   /// IsImp - True if this is an implicit def or use, false if it is explicit.
97   /// This is only valid on register opderands.
98   ///
99   unsigned IsImp : 1;
100 
101   /// IsDeadOrKill
102   /// For uses: IsKill - Conservatively indicates the last use of a register
103   /// on this path through the function. A register operand with true value of
104   /// this flag must be the last use of the register, a register operand with
105   /// false value may or may not be the last use of the register. After regalloc
106   /// we can use recomputeLivenessFlags to get precise kill flags.
107   /// For defs: IsDead - True if this register is never used by a subsequent
108   /// instruction.
109   /// This is only valid on register operands.
110   unsigned IsDeadOrKill : 1;
111 
112   /// See isRenamable().
113   unsigned IsRenamable : 1;
114 
115   /// IsUndef - True if this register operand reads an "undef" value, i.e. the
116   /// read value doesn't matter.  This flag can be set on both use and def
117   /// operands.  On a sub-register def operand, it refers to the part of the
118   /// register that isn't written.  On a full-register def operand, it is a
119   /// noop.  See readsReg().
120   ///
121   /// This is only valid on registers.
122   ///
123   /// Note that an instruction may have multiple <undef> operands referring to
124   /// the same register.  In that case, the instruction may depend on those
125   /// operands reading the same dont-care value.  For example:
126   ///
127   ///   %1 = XOR undef %2, undef %2
128   ///
129   /// Any register can be used for %2, and its value doesn't matter, but
130   /// the two operands must be the same register.
131   ///
132   unsigned IsUndef : 1;
133 
134   /// IsInternalRead - True if this operand reads a value that was defined
135   /// inside the same instruction or bundle.  This flag can be set on both use
136   /// and def operands.  On a sub-register def operand, it refers to the part
137   /// of the register that isn't written.  On a full-register def operand, it
138   /// is a noop.
139   ///
140   /// When this flag is set, the instruction bundle must contain at least one
141   /// other def of the register.  If multiple instructions in the bundle define
142   /// the register, the meaning is target-defined.
143   unsigned IsInternalRead : 1;
144 
145   /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
146   /// by the MachineInstr before all input registers are read.  This is used to
147   /// model the GCC inline asm '&' constraint modifier.
148   unsigned IsEarlyClobber : 1;
149 
150   /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
151   /// not a real instruction.  Such uses should be ignored during codegen.
152   unsigned IsDebug : 1;
153 
154   /// SmallContents - This really should be part of the Contents union, but
155   /// lives out here so we can get a better packed struct.
156   /// MO_Register: Register number.
157   /// OffsetedInfo: Low bits of offset.
158   union {
159     unsigned RegNo;           // For MO_Register.
160     unsigned OffsetLo;        // Matches Contents.OffsetedInfo.OffsetHi.
161   } SmallContents;
162 
163   /// ParentMI - This is the instruction that this operand is embedded into.
164   /// This is valid for all operand types, when the operand is in an instr.
165   MachineInstr *ParentMI = nullptr;
166 
167   /// Contents union - This contains the payload for the various operand types.
168   union ContentsUnion {
ContentsUnion()169     ContentsUnion() {}
170     MachineBasicBlock *MBB;  // For MO_MachineBasicBlock.
171     const ConstantFP *CFP;   // For MO_FPImmediate.
172     const ConstantInt *CI;   // For MO_CImmediate. Integers > 64bit.
173     int64_t ImmVal;          // For MO_Immediate.
174     const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
175     const MDNode *MD;        // For MO_Metadata.
176     MCSymbol *Sym;           // For MO_MCSymbol.
177     unsigned CFIIndex;       // For MO_CFI.
178     Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
179     unsigned Pred;           // For MO_Predicate
180     ArrayRef<int> ShuffleMask; // For MO_ShuffleMask
181 
182     struct {                  // For MO_Register.
183       // Register number is in SmallContents.RegNo.
184       MachineOperand *Prev;   // Access list for register. See MRI.
185       MachineOperand *Next;
186     } Reg;
187 
188     struct { // For MO_DbgInstrRef.
189       unsigned InstrIdx;
190       unsigned OpIdx;
191     } InstrRef;
192 
193     /// OffsetedInfo - This struct contains the offset and an object identifier.
194     /// this represent the object as with an optional offset from it.
195     struct {
196       union {
197         int Index;                // For MO_*Index - The index itself.
198         const char *SymbolName;   // For MO_ExternalSymbol.
199         const GlobalValue *GV;    // For MO_GlobalAddress.
200         const BlockAddress *BA;   // For MO_BlockAddress.
201       } Val;
202       // Low bits of offset are in SmallContents.OffsetLo.
203       int OffsetHi;               // An offset from the object, high 32 bits.
204     } OffsetedInfo;
205   } Contents;
206 
MachineOperand(MachineOperandType K)207   explicit MachineOperand(MachineOperandType K)
208       : OpKind(K), SubReg_TargetFlags(0) {
209     // Assert that the layout is what we expect. It's easy to grow this object.
210     static_assert(alignof(MachineOperand) <= alignof(int64_t),
211                   "MachineOperand shouldn't be more than 8 byte aligned");
212     static_assert(sizeof(Contents) <= 2 * sizeof(void *),
213                   "Contents should be at most two pointers");
214     static_assert(sizeof(MachineOperand) <=
215                       alignTo<alignof(int64_t)>(2 * sizeof(unsigned) +
216                                                 3 * sizeof(void *)),
217                   "MachineOperand too big. Should be Kind, SmallContents, "
218                   "ParentMI, and Contents");
219   }
220 
221 public:
222   /// getType - Returns the MachineOperandType for this operand.
223   ///
getType()224   MachineOperandType getType() const { return (MachineOperandType)OpKind; }
225 
getTargetFlags()226   unsigned getTargetFlags() const {
227     return isReg() ? 0 : SubReg_TargetFlags;
228   }
setTargetFlags(unsigned F)229   void setTargetFlags(unsigned F) {
230     assert(!isReg() && "Register operands can't have target flags");
231     SubReg_TargetFlags = F;
232     assert(SubReg_TargetFlags == F && "Target flags out of range");
233   }
addTargetFlag(unsigned F)234   void addTargetFlag(unsigned F) {
235     assert(!isReg() && "Register operands can't have target flags");
236     SubReg_TargetFlags |= F;
237     assert((SubReg_TargetFlags & F) && "Target flags out of range");
238   }
239 
240 
241   /// getParent - Return the instruction that this operand belongs to.
242   ///
getParent()243   MachineInstr *getParent() { return ParentMI; }
getParent()244   const MachineInstr *getParent() const { return ParentMI; }
245 
246   /// clearParent - Reset the parent pointer.
247   ///
248   /// The MachineOperand copy constructor also copies ParentMI, expecting the
249   /// original to be deleted. If a MachineOperand is ever stored outside a
250   /// MachineInstr, the parent pointer must be cleared.
251   ///
252   /// Never call clearParent() on an operand in a MachineInstr.
253   ///
clearParent()254   void clearParent() { ParentMI = nullptr; }
255 
256   /// Print a subreg index operand.
257   /// MO_Immediate operands can also be subreg idices. If it's the case, the
258   /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
259   /// called to check this.
260   static void printSubRegIdx(raw_ostream &OS, uint64_t Index,
261                              const TargetRegisterInfo *TRI);
262 
263   /// Print operand target flags.
264   static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
265 
266   /// Print a MCSymbol as an operand.
267   static void printSymbol(raw_ostream &OS, MCSymbol &Sym);
268 
269   /// Print a stack object reference.
270   static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex,
271                                         bool IsFixed, StringRef Name);
272 
273   /// Print the offset with explicit +/- signs.
274   static void printOperandOffset(raw_ostream &OS, int64_t Offset);
275 
276   /// Print an IRSlotNumber.
277   static void printIRSlotNumber(raw_ostream &OS, int Slot);
278 
279   /// Print the MachineOperand to \p os.
280   /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
281   /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
282   /// function will try to pick it up from the parent.
283   void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
284              const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
285 
286   /// More complex way of printing a MachineOperand.
287   /// \param TypeToPrint specifies the generic type to be printed on uses and
288   /// defs. It can be determined using MachineInstr::getTypeToPrint.
289   /// \param OpIdx - specifies the index of the operand in machine instruction.
290   /// This will be used by target dependent MIR formatter. Could be std::nullopt
291   /// if the index is unknown, e.g. called by dump().
292   /// \param PrintDef - whether we want to print `def` on an operand which
293   /// isDef. Sometimes, if the operand is printed before '=', we don't print
294   /// `def`.
295   /// \param IsStandalone - whether we want a verbose output of the MO. This
296   /// prints extra information that can be easily inferred when printing the
297   /// whole function, but not when printing only a fragment of it.
298   /// \param ShouldPrintRegisterTies - whether we want to print register ties.
299   /// Sometimes they are easily determined by the instruction's descriptor
300   /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
301   /// \param TiedOperandIdx - if we need to print register ties this needs to
302   /// provide the index of the tied register. If not, it will be ignored.
303   /// \param TRI - provide more target-specific information to the printer.
304   /// Unlike the previous function, this one will not try and get the
305   /// information from it's parent.
306   /// \param IntrinsicInfo - same as \p TRI.
307   void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
308              std::optional<unsigned> OpIdx, bool PrintDef, bool IsStandalone,
309              bool ShouldPrintRegisterTies, unsigned TiedOperandIdx,
310              const TargetRegisterInfo *TRI,
311              const TargetIntrinsicInfo *IntrinsicInfo) const;
312 
313   /// Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level
314   /// type to be printed the same way the full version of print(...) does it.
315   void print(raw_ostream &os, LLT TypeToPrint,
316              const TargetRegisterInfo *TRI = nullptr,
317              const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
318 
319   void dump() const;
320 
321   //===--------------------------------------------------------------------===//
322   // Accessors that tell you what kind of MachineOperand you're looking at.
323   //===--------------------------------------------------------------------===//
324 
325   /// isReg - Tests if this is a MO_Register operand.
isReg()326   bool isReg() const { return OpKind == MO_Register; }
327   /// isImm - Tests if this is a MO_Immediate operand.
isImm()328   bool isImm() const { return OpKind == MO_Immediate; }
329   /// isCImm - Test if this is a MO_CImmediate operand.
isCImm()330   bool isCImm() const { return OpKind == MO_CImmediate; }
331   /// isFPImm - Tests if this is a MO_FPImmediate operand.
isFPImm()332   bool isFPImm() const { return OpKind == MO_FPImmediate; }
333   /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
isMBB()334   bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
335   /// isFI - Tests if this is a MO_FrameIndex operand.
isFI()336   bool isFI() const { return OpKind == MO_FrameIndex; }
337   /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
isCPI()338   bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
339   /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
isTargetIndex()340   bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
341   /// isJTI - Tests if this is a MO_JumpTableIndex operand.
isJTI()342   bool isJTI() const { return OpKind == MO_JumpTableIndex; }
343   /// isGlobal - Tests if this is a MO_GlobalAddress operand.
isGlobal()344   bool isGlobal() const { return OpKind == MO_GlobalAddress; }
345   /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
isSymbol()346   bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
347   /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
isBlockAddress()348   bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
349   /// isRegMask - Tests if this is a MO_RegisterMask operand.
isRegMask()350   bool isRegMask() const { return OpKind == MO_RegisterMask; }
351   /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
isRegLiveOut()352   bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
353   /// isMetadata - Tests if this is a MO_Metadata operand.
isMetadata()354   bool isMetadata() const { return OpKind == MO_Metadata; }
isMCSymbol()355   bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
isDbgInstrRef()356   bool isDbgInstrRef() const { return OpKind == MO_DbgInstrRef; }
isCFIIndex()357   bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
isIntrinsicID()358   bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
isPredicate()359   bool isPredicate() const { return OpKind == MO_Predicate; }
isShuffleMask()360   bool isShuffleMask() const { return OpKind == MO_ShuffleMask; }
361   //===--------------------------------------------------------------------===//
362   // Accessors for Register Operands
363   //===--------------------------------------------------------------------===//
364 
365   /// getReg - Returns the register number.
getReg()366   Register getReg() const {
367     assert(isReg() && "This is not a register operand!");
368     return Register(SmallContents.RegNo);
369   }
370 
getSubReg()371   unsigned getSubReg() const {
372     assert(isReg() && "Wrong MachineOperand accessor");
373     return SubReg_TargetFlags;
374   }
375 
isUse()376   bool isUse() const {
377     assert(isReg() && "Wrong MachineOperand accessor");
378     return !IsDef;
379   }
380 
isDef()381   bool isDef() const {
382     assert(isReg() && "Wrong MachineOperand accessor");
383     return IsDef;
384   }
385 
isImplicit()386   bool isImplicit() const {
387     assert(isReg() && "Wrong MachineOperand accessor");
388     return IsImp;
389   }
390 
isDead()391   bool isDead() const {
392     assert(isReg() && "Wrong MachineOperand accessor");
393     return IsDeadOrKill & IsDef;
394   }
395 
isKill()396   bool isKill() const {
397     assert(isReg() && "Wrong MachineOperand accessor");
398     return IsDeadOrKill & !IsDef;
399   }
400 
isUndef()401   bool isUndef() const {
402     assert(isReg() && "Wrong MachineOperand accessor");
403     return IsUndef;
404   }
405 
406   /// isRenamable - Returns true if this register may be renamed, i.e. it does
407   /// not generate a value that is somehow read in a way that is not represented
408   /// by the Machine IR (e.g. to meet an ABI or ISA requirement).  This is only
409   /// valid on physical register operands.  Virtual registers are assumed to
410   /// always be renamable regardless of the value of this field.
411   ///
412   /// Operands that are renamable can freely be changed to any other register
413   /// that is a member of the register class returned by
414   /// MI->getRegClassConstraint().
415   ///
416   /// isRenamable can return false for several different reasons:
417   ///
418   /// - ABI constraints (since liveness is not always precisely modeled).  We
419   ///   conservatively handle these cases by setting all physical register
420   ///   operands that didn’t start out as virtual regs to not be renamable.
421   ///   Also any physical register operands created after register allocation or
422   ///   whose register is changed after register allocation will not be
423   ///   renamable.  This state is tracked in the MachineOperand::IsRenamable
424   ///   bit.
425   ///
426   /// - Opcode/target constraints: for opcodes that have complex register class
427   ///   requirements (e.g. that depend on other operands/instructions), we set
428   ///   hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode
429   ///   description.  Operands belonging to instructions with opcodes that are
430   ///   marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from
431   ///   isRenamable().  Additionally, the AllowRegisterRenaming target property
432   ///   prevents any operands from being marked renamable for targets that don't
433   ///   have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
434   ///   values.
435   bool isRenamable() const;
436 
isInternalRead()437   bool isInternalRead() const {
438     assert(isReg() && "Wrong MachineOperand accessor");
439     return IsInternalRead;
440   }
441 
isEarlyClobber()442   bool isEarlyClobber() const {
443     assert(isReg() && "Wrong MachineOperand accessor");
444     return IsEarlyClobber;
445   }
446 
isTied()447   bool isTied() const {
448     assert(isReg() && "Wrong MachineOperand accessor");
449     return TiedTo;
450   }
451 
isDebug()452   bool isDebug() const {
453     assert(isReg() && "Wrong MachineOperand accessor");
454     return IsDebug;
455   }
456 
457   /// readsReg - Returns true if this operand reads the previous value of its
458   /// register.  A use operand with the <undef> flag set doesn't read its
459   /// register.  A sub-register def implicitly reads the other parts of the
460   /// register being redefined unless the <undef> flag is set.
461   ///
462   /// This refers to reading the register value from before the current
463   /// instruction or bundle. Internal bundle reads are not included.
readsReg()464   bool readsReg() const {
465     assert(isReg() && "Wrong MachineOperand accessor");
466     return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
467   }
468 
469   /// Return true if this operand can validly be appended to an arbitrary
470   /// operand list. i.e. this behaves like an implicit operand.
isValidExcessOperand()471   bool isValidExcessOperand() const {
472     if ((isReg() && isImplicit()) || isRegMask())
473       return true;
474 
475     // Debug operands
476     return isMetadata() || isMCSymbol();
477   }
478 
479   //===--------------------------------------------------------------------===//
480   // Mutators for Register Operands
481   //===--------------------------------------------------------------------===//
482 
483   /// Change the register this operand corresponds to.
484   ///
485   void setReg(Register Reg);
486 
setSubReg(unsigned subReg)487   void setSubReg(unsigned subReg) {
488     assert(isReg() && "Wrong MachineOperand mutator");
489     SubReg_TargetFlags = subReg;
490     assert(SubReg_TargetFlags == subReg && "SubReg out of range");
491   }
492 
493   /// substVirtReg - Substitute the current register with the virtual
494   /// subregister Reg:SubReg. Take any existing SubReg index into account,
495   /// using TargetRegisterInfo to compose the subreg indices if necessary.
496   /// Reg must be a virtual register, SubIdx can be 0.
497   ///
498   void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo&);
499 
500   /// substPhysReg - Substitute the current register with the physical register
501   /// Reg, taking any existing SubReg into account. For instance,
502   /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al.
503   ///
504   void substPhysReg(MCRegister Reg, const TargetRegisterInfo&);
505 
506   void setIsUse(bool Val = true) { setIsDef(!Val); }
507 
508   /// Change a def to a use, or a use to a def.
509   void setIsDef(bool Val = true);
510 
511   void setImplicit(bool Val = true) {
512     assert(isReg() && "Wrong MachineOperand mutator");
513     IsImp = Val;
514   }
515 
516   void setIsKill(bool Val = true) {
517     assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
518     assert((!Val || !isDebug()) && "Marking a debug operation as kill");
519     IsDeadOrKill = Val;
520   }
521 
522   void setIsDead(bool Val = true) {
523     assert(isReg() && IsDef && "Wrong MachineOperand mutator");
524     IsDeadOrKill = Val;
525   }
526 
527   void setIsUndef(bool Val = true) {
528     assert(isReg() && "Wrong MachineOperand mutator");
529     IsUndef = Val;
530   }
531 
532   void setIsRenamable(bool Val = true);
533 
534   void setIsInternalRead(bool Val = true) {
535     assert(isReg() && "Wrong MachineOperand mutator");
536     IsInternalRead = Val;
537   }
538 
539   void setIsEarlyClobber(bool Val = true) {
540     assert(isReg() && IsDef && "Wrong MachineOperand mutator");
541     IsEarlyClobber = Val;
542   }
543 
544   void setIsDebug(bool Val = true) {
545     assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
546     IsDebug = Val;
547   }
548 
549   //===--------------------------------------------------------------------===//
550   // Accessors for various operand types.
551   //===--------------------------------------------------------------------===//
552 
getImm()553   int64_t getImm() const {
554     assert(isImm() && "Wrong MachineOperand accessor");
555     return Contents.ImmVal;
556   }
557 
getCImm()558   const ConstantInt *getCImm() const {
559     assert(isCImm() && "Wrong MachineOperand accessor");
560     return Contents.CI;
561   }
562 
getFPImm()563   const ConstantFP *getFPImm() const {
564     assert(isFPImm() && "Wrong MachineOperand accessor");
565     return Contents.CFP;
566   }
567 
getMBB()568   MachineBasicBlock *getMBB() const {
569     assert(isMBB() && "Wrong MachineOperand accessor");
570     return Contents.MBB;
571   }
572 
getIndex()573   int getIndex() const {
574     assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
575            "Wrong MachineOperand accessor");
576     return Contents.OffsetedInfo.Val.Index;
577   }
578 
getGlobal()579   const GlobalValue *getGlobal() const {
580     assert(isGlobal() && "Wrong MachineOperand accessor");
581     return Contents.OffsetedInfo.Val.GV;
582   }
583 
getBlockAddress()584   const BlockAddress *getBlockAddress() const {
585     assert(isBlockAddress() && "Wrong MachineOperand accessor");
586     return Contents.OffsetedInfo.Val.BA;
587   }
588 
getMCSymbol()589   MCSymbol *getMCSymbol() const {
590     assert(isMCSymbol() && "Wrong MachineOperand accessor");
591     return Contents.Sym;
592   }
593 
getInstrRefInstrIndex()594   unsigned getInstrRefInstrIndex() const {
595     assert(isDbgInstrRef() && "Wrong MachineOperand accessor");
596     return Contents.InstrRef.InstrIdx;
597   }
598 
getInstrRefOpIndex()599   unsigned getInstrRefOpIndex() const {
600     assert(isDbgInstrRef() && "Wrong MachineOperand accessor");
601     return Contents.InstrRef.OpIdx;
602   }
603 
getCFIIndex()604   unsigned getCFIIndex() const {
605     assert(isCFIIndex() && "Wrong MachineOperand accessor");
606     return Contents.CFIIndex;
607   }
608 
getIntrinsicID()609   Intrinsic::ID getIntrinsicID() const {
610     assert(isIntrinsicID() && "Wrong MachineOperand accessor");
611     return Contents.IntrinsicID;
612   }
613 
getPredicate()614   unsigned getPredicate() const {
615     assert(isPredicate() && "Wrong MachineOperand accessor");
616     return Contents.Pred;
617   }
618 
getShuffleMask()619   ArrayRef<int> getShuffleMask() const {
620     assert(isShuffleMask() && "Wrong MachineOperand accessor");
621     return Contents.ShuffleMask;
622   }
623 
624   /// Return the offset from the symbol in this operand. This always returns 0
625   /// for ExternalSymbol operands.
getOffset()626   int64_t getOffset() const {
627     assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
628             isTargetIndex() || isBlockAddress()) &&
629            "Wrong MachineOperand accessor");
630     return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
631            SmallContents.OffsetLo;
632   }
633 
getSymbolName()634   const char *getSymbolName() const {
635     assert(isSymbol() && "Wrong MachineOperand accessor");
636     return Contents.OffsetedInfo.Val.SymbolName;
637   }
638 
639   /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
640   /// It is sometimes necessary to detach the register mask pointer from its
641   /// machine operand. This static method can be used for such detached bit
642   /// mask pointers.
clobbersPhysReg(const uint32_t * RegMask,MCRegister PhysReg)643   static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg) {
644     // See TargetRegisterInfo.h.
645     assert(PhysReg < (1u << 30) && "Not a physical register");
646     return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
647   }
648 
649   /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
clobbersPhysReg(MCRegister PhysReg)650   bool clobbersPhysReg(MCRegister PhysReg) const {
651      return clobbersPhysReg(getRegMask(), PhysReg);
652   }
653 
654   /// getRegMask - Returns a bit mask of registers preserved by this RegMask
655   /// operand.
getRegMask()656   const uint32_t *getRegMask() const {
657     assert(isRegMask() && "Wrong MachineOperand accessor");
658     return Contents.RegMask;
659   }
660 
661   /// Returns number of elements needed for a regmask array.
getRegMaskSize(unsigned NumRegs)662   static unsigned getRegMaskSize(unsigned NumRegs) {
663     return (NumRegs + 31) / 32;
664   }
665 
666   /// getRegLiveOut - Returns a bit mask of live-out registers.
getRegLiveOut()667   const uint32_t *getRegLiveOut() const {
668     assert(isRegLiveOut() && "Wrong MachineOperand accessor");
669     return Contents.RegMask;
670   }
671 
getMetadata()672   const MDNode *getMetadata() const {
673     assert(isMetadata() && "Wrong MachineOperand accessor");
674     return Contents.MD;
675   }
676 
677   //===--------------------------------------------------------------------===//
678   // Mutators for various operand types.
679   //===--------------------------------------------------------------------===//
680 
setImm(int64_t immVal)681   void setImm(int64_t immVal) {
682     assert(isImm() && "Wrong MachineOperand mutator");
683     Contents.ImmVal = immVal;
684   }
685 
setCImm(const ConstantInt * CI)686   void setCImm(const ConstantInt *CI) {
687     assert(isCImm() && "Wrong MachineOperand mutator");
688     Contents.CI = CI;
689   }
690 
setFPImm(const ConstantFP * CFP)691   void setFPImm(const ConstantFP *CFP) {
692     assert(isFPImm() && "Wrong MachineOperand mutator");
693     Contents.CFP = CFP;
694   }
695 
setOffset(int64_t Offset)696   void setOffset(int64_t Offset) {
697     assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
698             isTargetIndex() || isBlockAddress()) &&
699            "Wrong MachineOperand mutator");
700     SmallContents.OffsetLo = unsigned(Offset);
701     Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
702   }
703 
setIndex(int Idx)704   void setIndex(int Idx) {
705     assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
706            "Wrong MachineOperand mutator");
707     Contents.OffsetedInfo.Val.Index = Idx;
708   }
709 
setMetadata(const MDNode * MD)710   void setMetadata(const MDNode *MD) {
711     assert(isMetadata() && "Wrong MachineOperand mutator");
712     Contents.MD = MD;
713   }
714 
setInstrRefInstrIndex(unsigned InstrIdx)715   void setInstrRefInstrIndex(unsigned InstrIdx) {
716     assert(isDbgInstrRef() && "Wrong MachineOperand mutator");
717     Contents.InstrRef.InstrIdx = InstrIdx;
718   }
setInstrRefOpIndex(unsigned OpIdx)719   void setInstrRefOpIndex(unsigned OpIdx) {
720     assert(isDbgInstrRef() && "Wrong MachineOperand mutator");
721     Contents.InstrRef.OpIdx = OpIdx;
722   }
723 
setMBB(MachineBasicBlock * MBB)724   void setMBB(MachineBasicBlock *MBB) {
725     assert(isMBB() && "Wrong MachineOperand mutator");
726     Contents.MBB = MBB;
727   }
728 
729   /// Sets value of register mask operand referencing Mask.  The
730   /// operand does not take ownership of the memory referenced by Mask, it must
731   /// remain valid for the lifetime of the operand. See CreateRegMask().
732   /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
setRegMask(const uint32_t * RegMaskPtr)733   void setRegMask(const uint32_t *RegMaskPtr) {
734     assert(isRegMask() && "Wrong MachineOperand mutator");
735     Contents.RegMask = RegMaskPtr;
736   }
737 
setIntrinsicID(Intrinsic::ID IID)738   void setIntrinsicID(Intrinsic::ID IID) {
739     assert(isIntrinsicID() && "Wrong MachineOperand mutator");
740     Contents.IntrinsicID = IID;
741   }
742 
setPredicate(unsigned Predicate)743   void setPredicate(unsigned Predicate) {
744     assert(isPredicate() && "Wrong MachineOperand mutator");
745     Contents.Pred = Predicate;
746   }
747 
748   //===--------------------------------------------------------------------===//
749   // Other methods.
750   //===--------------------------------------------------------------------===//
751 
752   /// Returns true if this operand is identical to the specified operand except
753   /// for liveness related flags (isKill, isUndef and isDead). Note that this
754   /// should stay in sync with the hash_value overload below.
755   bool isIdenticalTo(const MachineOperand &Other) const;
756 
757   /// MachineOperand hash_value overload.
758   ///
759   /// Note that this includes the same information in the hash that
760   /// isIdenticalTo uses for comparison. It is thus suited for use in hash
761   /// tables which use that function for equality comparisons only. This must
762   /// stay exactly in sync with isIdenticalTo above.
763   friend hash_code hash_value(const MachineOperand &MO);
764 
765   /// ChangeToImmediate - Replace this operand with a new immediate operand of
766   /// the specified value.  If an operand is known to be an immediate already,
767   /// the setImm method should be used.
768   void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags = 0);
769 
770   /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
771   /// of the specified value.  If an operand is known to be an FP immediate
772   /// already, the setFPImm method should be used.
773   void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags = 0);
774 
775   /// ChangeToES - Replace this operand with a new external symbol operand.
776   void ChangeToES(const char *SymName, unsigned TargetFlags = 0);
777 
778   /// ChangeToGA - Replace this operand with a new global address operand.
779   void ChangeToGA(const GlobalValue *GV, int64_t Offset,
780                   unsigned TargetFlags = 0);
781 
782   /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
783   void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags = 0);
784 
785   /// Replace this operand with a frame index.
786   void ChangeToFrameIndex(int Idx, unsigned TargetFlags = 0);
787 
788   /// Replace this operand with a target index.
789   void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
790                            unsigned TargetFlags = 0);
791 
792   /// Replace this operand with an Instruction Reference.
793   void ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx,
794                            unsigned TargetFlags = 0);
795 
796   /// ChangeToRegister - Replace this operand with a new register operand of
797   /// the specified value.  If an operand is known to be an register already,
798   /// the setReg method should be used.
799   void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
800                         bool isKill = false, bool isDead = false,
801                         bool isUndef = false, bool isDebug = false);
802 
803   /// getTargetIndexName - If this MachineOperand is a TargetIndex that has a
804   /// name, attempt to get the name. Returns nullptr if the TargetIndex does not
805   /// have a name. Asserts if MO is not a TargetIndex.
806   const char *getTargetIndexName() const;
807 
808   //===--------------------------------------------------------------------===//
809   // Construction methods.
810   //===--------------------------------------------------------------------===//
811 
CreateImm(int64_t Val)812   static MachineOperand CreateImm(int64_t Val) {
813     MachineOperand Op(MachineOperand::MO_Immediate);
814     Op.setImm(Val);
815     return Op;
816   }
817 
CreateCImm(const ConstantInt * CI)818   static MachineOperand CreateCImm(const ConstantInt *CI) {
819     MachineOperand Op(MachineOperand::MO_CImmediate);
820     Op.Contents.CI = CI;
821     return Op;
822   }
823 
CreateFPImm(const ConstantFP * CFP)824   static MachineOperand CreateFPImm(const ConstantFP *CFP) {
825     MachineOperand Op(MachineOperand::MO_FPImmediate);
826     Op.Contents.CFP = CFP;
827     return Op;
828   }
829 
830   static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
831                                   bool isKill = false, bool isDead = false,
832                                   bool isUndef = false,
833                                   bool isEarlyClobber = false,
834                                   unsigned SubReg = 0, bool isDebug = false,
835                                   bool isInternalRead = false,
836                                   bool isRenamable = false) {
837     assert(!(isDead && !isDef) && "Dead flag on non-def");
838     assert(!(isKill && isDef) && "Kill flag on def");
839     MachineOperand Op(MachineOperand::MO_Register);
840     Op.IsDef = isDef;
841     Op.IsImp = isImp;
842     Op.IsDeadOrKill = isKill | isDead;
843     Op.IsRenamable = isRenamable;
844     Op.IsUndef = isUndef;
845     Op.IsInternalRead = isInternalRead;
846     Op.IsEarlyClobber = isEarlyClobber;
847     Op.TiedTo = 0;
848     Op.IsDebug = isDebug;
849     Op.SmallContents.RegNo = Reg;
850     Op.Contents.Reg.Prev = nullptr;
851     Op.Contents.Reg.Next = nullptr;
852     Op.setSubReg(SubReg);
853     return Op;
854   }
855   static MachineOperand CreateMBB(MachineBasicBlock *MBB,
856                                   unsigned TargetFlags = 0) {
857     MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
858     Op.setMBB(MBB);
859     Op.setTargetFlags(TargetFlags);
860     return Op;
861   }
CreateFI(int Idx)862   static MachineOperand CreateFI(int Idx) {
863     MachineOperand Op(MachineOperand::MO_FrameIndex);
864     Op.setIndex(Idx);
865     return Op;
866   }
867   static MachineOperand CreateCPI(unsigned Idx, int Offset,
868                                   unsigned TargetFlags = 0) {
869     MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
870     Op.setIndex(Idx);
871     Op.setOffset(Offset);
872     Op.setTargetFlags(TargetFlags);
873     return Op;
874   }
875   static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
876                                           unsigned TargetFlags = 0) {
877     MachineOperand Op(MachineOperand::MO_TargetIndex);
878     Op.setIndex(Idx);
879     Op.setOffset(Offset);
880     Op.setTargetFlags(TargetFlags);
881     return Op;
882   }
883   static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags = 0) {
884     MachineOperand Op(MachineOperand::MO_JumpTableIndex);
885     Op.setIndex(Idx);
886     Op.setTargetFlags(TargetFlags);
887     return Op;
888   }
889   static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
890                                  unsigned TargetFlags = 0) {
891     MachineOperand Op(MachineOperand::MO_GlobalAddress);
892     Op.Contents.OffsetedInfo.Val.GV = GV;
893     Op.setOffset(Offset);
894     Op.setTargetFlags(TargetFlags);
895     return Op;
896   }
897   static MachineOperand CreateES(const char *SymName,
898                                  unsigned TargetFlags = 0) {
899     MachineOperand Op(MachineOperand::MO_ExternalSymbol);
900     Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
901     Op.setOffset(0); // Offset is always 0.
902     Op.setTargetFlags(TargetFlags);
903     return Op;
904   }
905   static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
906                                  unsigned TargetFlags = 0) {
907     MachineOperand Op(MachineOperand::MO_BlockAddress);
908     Op.Contents.OffsetedInfo.Val.BA = BA;
909     Op.setOffset(Offset);
910     Op.setTargetFlags(TargetFlags);
911     return Op;
912   }
913   /// CreateRegMask - Creates a register mask operand referencing Mask.  The
914   /// operand does not take ownership of the memory referenced by Mask, it
915   /// must remain valid for the lifetime of the operand.
916   ///
917   /// A RegMask operand represents a set of non-clobbered physical registers
918   /// on an instruction that clobbers many registers, typically a call.  The
919   /// bit mask has a bit set for each physreg that is preserved by this
920   /// instruction, as described in the documentation for
921   /// TargetRegisterInfo::getCallPreservedMask().
922   ///
923   /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
924   ///
CreateRegMask(const uint32_t * Mask)925   static MachineOperand CreateRegMask(const uint32_t *Mask) {
926     assert(Mask && "Missing register mask");
927     MachineOperand Op(MachineOperand::MO_RegisterMask);
928     Op.Contents.RegMask = Mask;
929     return Op;
930   }
CreateRegLiveOut(const uint32_t * Mask)931   static MachineOperand CreateRegLiveOut(const uint32_t *Mask) {
932     assert(Mask && "Missing live-out register mask");
933     MachineOperand Op(MachineOperand::MO_RegisterLiveOut);
934     Op.Contents.RegMask = Mask;
935     return Op;
936   }
CreateMetadata(const MDNode * Meta)937   static MachineOperand CreateMetadata(const MDNode *Meta) {
938     MachineOperand Op(MachineOperand::MO_Metadata);
939     Op.Contents.MD = Meta;
940     return Op;
941   }
942 
943   static MachineOperand CreateMCSymbol(MCSymbol *Sym,
944                                        unsigned TargetFlags = 0) {
945     MachineOperand Op(MachineOperand::MO_MCSymbol);
946     Op.Contents.Sym = Sym;
947     Op.setOffset(0);
948     Op.setTargetFlags(TargetFlags);
949     return Op;
950   }
951 
CreateDbgInstrRef(unsigned InstrIdx,unsigned OpIdx)952   static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx) {
953     MachineOperand Op(MachineOperand::MO_DbgInstrRef);
954     Op.Contents.InstrRef.InstrIdx = InstrIdx;
955     Op.Contents.InstrRef.OpIdx = OpIdx;
956     return Op;
957   }
958 
CreateCFIIndex(unsigned CFIIndex)959   static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
960     MachineOperand Op(MachineOperand::MO_CFIIndex);
961     Op.Contents.CFIIndex = CFIIndex;
962     return Op;
963   }
964 
CreateIntrinsicID(Intrinsic::ID ID)965   static MachineOperand CreateIntrinsicID(Intrinsic::ID ID) {
966     MachineOperand Op(MachineOperand::MO_IntrinsicID);
967     Op.Contents.IntrinsicID = ID;
968     return Op;
969   }
970 
CreatePredicate(unsigned Pred)971   static MachineOperand CreatePredicate(unsigned Pred) {
972     MachineOperand Op(MachineOperand::MO_Predicate);
973     Op.Contents.Pred = Pred;
974     return Op;
975   }
976 
CreateShuffleMask(ArrayRef<int> Mask)977   static MachineOperand CreateShuffleMask(ArrayRef<int> Mask) {
978     MachineOperand Op(MachineOperand::MO_ShuffleMask);
979     Op.Contents.ShuffleMask = Mask;
980     return Op;
981   }
982 
983   friend class MachineInstr;
984   friend class MachineRegisterInfo;
985 
986 private:
987   // If this operand is currently a register operand, and if this is in a
988   // function, deregister the operand from the register's use/def list.
989   void removeRegFromUses();
990 
991   /// Artificial kinds for DenseMap usage.
992   enum : unsigned char {
993     MO_Empty = MO_Last + 1,
994     MO_Tombstone,
995   };
996 
997   friend struct DenseMapInfo<MachineOperand>;
998 
999   //===--------------------------------------------------------------------===//
1000   // Methods for handling register use/def lists.
1001   //===--------------------------------------------------------------------===//
1002 
1003   /// isOnRegUseList - Return true if this operand is on a register use/def
1004   /// list or false if not.  This can only be called for register operands
1005   /// that are part of a machine instruction.
1006   bool isOnRegUseList() const {
1007     assert(isReg() && "Can only add reg operand to use lists");
1008     return Contents.Reg.Prev != nullptr;
1009   }
1010 };
1011 
1012 template <> struct DenseMapInfo<MachineOperand> {
1013   static MachineOperand getEmptyKey() {
1014     return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
1015         MachineOperand::MO_Empty));
1016   }
1017   static MachineOperand getTombstoneKey() {
1018     return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
1019         MachineOperand::MO_Tombstone));
1020   }
1021   static unsigned getHashValue(const MachineOperand &MO) {
1022     return hash_value(MO);
1023   }
1024   static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
1025     if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
1026                              MachineOperand::MO_Empty) ||
1027         LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
1028                              MachineOperand::MO_Tombstone))
1029       return LHS.getType() == RHS.getType();
1030     return LHS.isIdenticalTo(RHS);
1031   }
1032 };
1033 
1034 inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand &MO) {
1035   MO.print(OS);
1036   return OS;
1037 }
1038 
1039 // See friend declaration above. This additional declaration is required in
1040 // order to compile LLVM with IBM xlC compiler.
1041 hash_code hash_value(const MachineOperand &MO);
1042 } // namespace llvm
1043 
1044 #endif
1045