1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2023 Intel Corporation
5 */
6 #if defined(__FreeBSD__)
7 #include <linux/delay.h>
8 #endif
9 #include "iwl-trans.h"
10 #include "iwl-prph.h"
11 #include "iwl-context-info.h"
12 #include "iwl-context-info-gen3.h"
13 #include "internal.h"
14 #include "fw/dbg.h"
15
16 #define FW_RESET_TIMEOUT (HZ / 5)
17
18 /*
19 * Start up NIC's basic functionality after it has been reset
20 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
21 * NOTE: This does not load uCode nor start the embedded processor
22 */
iwl_pcie_gen2_apm_init(struct iwl_trans * trans)23 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
24 {
25 int ret = 0;
26
27 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
28
29 /*
30 * Use "set_bit" below rather than "write", to preserve any hardware
31 * bits already set by default after reset.
32 */
33
34 /*
35 * Disable L0s without affecting L1;
36 * don't wait for ICH L0s (ICH bug W/A)
37 */
38 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
39 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
40
41 /* Set FH wait threshold to maximum (HW error during stress W/A) */
42 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
43
44 /*
45 * Enable HAP INTA (interrupt from management bus) to
46 * wake device's PCI Express link L1a -> L0s
47 */
48 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
49 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
50
51 iwl_pcie_apm_config(trans);
52
53 ret = iwl_finish_nic_init(trans);
54 if (ret)
55 return ret;
56
57 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
58
59 return 0;
60 }
61
iwl_pcie_gen2_apm_stop(struct iwl_trans * trans,bool op_mode_leave)62 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
63 {
64 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
65
66 if (op_mode_leave) {
67 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
68 iwl_pcie_gen2_apm_init(trans);
69
70 /* inform ME that we are leaving */
71 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
72 CSR_RESET_LINK_PWR_MGMT_DISABLED);
73 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
74 CSR_HW_IF_CONFIG_REG_PREPARE |
75 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
76 mdelay(1);
77 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
78 CSR_RESET_LINK_PWR_MGMT_DISABLED);
79 mdelay(5);
80 }
81
82 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
83
84 /* Stop device's DMA activity */
85 iwl_pcie_apm_stop_master(trans);
86
87 iwl_trans_sw_reset(trans, false);
88
89 /*
90 * Clear "initialization complete" bit to move adapter from
91 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
92 */
93 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
94 iwl_clear_bit(trans, CSR_GP_CNTRL,
95 CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
96 else
97 iwl_clear_bit(trans, CSR_GP_CNTRL,
98 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
99 }
100
iwl_trans_pcie_fw_reset_handshake(struct iwl_trans * trans)101 static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans)
102 {
103 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
104 int ret;
105
106 trans_pcie->fw_reset_state = FW_RESET_REQUESTED;
107
108 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
109 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
110 UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);
111 else if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
112 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
113 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
114 else
115 iwl_write32(trans, CSR_DOORBELL_VECTOR,
116 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
117
118 /* wait 200ms */
119 ret = wait_event_timeout(trans_pcie->fw_reset_waitq,
120 trans_pcie->fw_reset_state != FW_RESET_REQUESTED,
121 FW_RESET_TIMEOUT);
122 if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) {
123 u32 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
124
125 IWL_ERR(trans,
126 "timeout waiting for FW reset ACK (inta_hw=0x%x)\n",
127 inta_hw);
128
129 if (!(inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE))
130 iwl_trans_fw_error(trans, true);
131 }
132
133 trans_pcie->fw_reset_state = FW_RESET_IDLE;
134 }
135
_iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)136 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
137 {
138 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
139
140 lockdep_assert_held(&trans_pcie->mutex);
141
142 if (trans_pcie->is_down)
143 return;
144
145 if (trans->state >= IWL_TRANS_FW_STARTED)
146 if (trans_pcie->fw_reset_handshake)
147 iwl_trans_pcie_fw_reset_handshake(trans);
148
149 trans_pcie->is_down = true;
150
151 /* tell the device to stop sending interrupts */
152 iwl_disable_interrupts(trans);
153
154 /* device going down, Stop using ICT table */
155 iwl_pcie_disable_ict(trans);
156
157 /*
158 * If a HW restart happens during firmware loading,
159 * then the firmware loading might call this function
160 * and later it might be called again due to the
161 * restart. So don't process again if the device is
162 * already dead.
163 */
164 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
165 IWL_DEBUG_INFO(trans,
166 "DEVICE_ENABLED bit was set and is now cleared\n");
167 iwl_pcie_rx_napi_sync(trans);
168 iwl_txq_gen2_tx_free(trans);
169 iwl_pcie_rx_stop(trans);
170 }
171
172 iwl_pcie_ctxt_info_free_paging(trans);
173 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
174 iwl_pcie_ctxt_info_gen3_free(trans, false);
175 else
176 iwl_pcie_ctxt_info_free(trans);
177
178 /* Stop the device, and put it in low power state */
179 iwl_pcie_gen2_apm_stop(trans, false);
180
181 /* re-take ownership to prevent other users from stealing the device */
182 iwl_trans_sw_reset(trans, true);
183
184 /*
185 * Upon stop, the IVAR table gets erased, so msi-x won't
186 * work. This causes a bug in RF-KILL flows, since the interrupt
187 * that enables radio won't fire on the correct irq, and the
188 * driver won't be able to handle the interrupt.
189 * Configure the IVAR table again after reset.
190 */
191 iwl_pcie_conf_msix_hw(trans_pcie);
192
193 /*
194 * Upon stop, the APM issues an interrupt if HW RF kill is set.
195 * This is a bug in certain verions of the hardware.
196 * Certain devices also keep sending HW RF kill interrupt all
197 * the time, unless the interrupt is ACKed even if the interrupt
198 * should be masked. Re-ACK all the interrupts here.
199 */
200 iwl_disable_interrupts(trans);
201
202 /* clear all status bits */
203 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
204 clear_bit(STATUS_INT_ENABLED, &trans->status);
205 clear_bit(STATUS_TPOWER_PMI, &trans->status);
206
207 /*
208 * Even if we stop the HW, we still want the RF kill
209 * interrupt
210 */
211 iwl_enable_rfkill_int(trans);
212 }
213
iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)214 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
215 {
216 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
217 bool was_in_rfkill;
218
219 iwl_op_mode_time_point(trans->op_mode,
220 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
221 NULL);
222
223 mutex_lock(&trans_pcie->mutex);
224 trans_pcie->opmode_down = true;
225 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
226 _iwl_trans_pcie_gen2_stop_device(trans);
227 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
228 mutex_unlock(&trans_pcie->mutex);
229 }
230
iwl_pcie_gen2_nic_init(struct iwl_trans * trans)231 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
232 {
233 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
234 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
235 trans->cfg->min_txq_size);
236
237 /* TODO: most of the logic can be removed in A0 - but not in Z0 */
238 spin_lock_bh(&trans_pcie->irq_lock);
239 iwl_pcie_gen2_apm_init(trans);
240 spin_unlock_bh(&trans_pcie->irq_lock);
241
242 iwl_op_mode_nic_config(trans->op_mode);
243
244 /* Allocate the RX queue, or reset if it is already allocated */
245 if (iwl_pcie_gen2_rx_init(trans))
246 return -ENOMEM;
247
248 /* Allocate or reset and init all Tx and Command queues */
249 if (iwl_txq_gen2_init(trans, trans->txqs.cmd.q_id, queue_size))
250 return -ENOMEM;
251
252 /* enable shadow regs in HW */
253 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
254 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
255
256 return 0;
257 }
258
iwl_pcie_get_rf_name(struct iwl_trans * trans)259 static void iwl_pcie_get_rf_name(struct iwl_trans *trans)
260 {
261 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
262 char *buf = trans_pcie->rf_name;
263 size_t buflen = sizeof(trans_pcie->rf_name);
264 size_t pos;
265 u32 version;
266
267 if (buf[0])
268 return;
269
270 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
271 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF):
272 pos = scnprintf(buf, buflen, "JF");
273 break;
274 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF):
275 pos = scnprintf(buf, buflen, "GF");
276 break;
277 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4):
278 pos = scnprintf(buf, buflen, "GF4");
279 break;
280 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
281 pos = scnprintf(buf, buflen, "HR");
282 break;
283 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
284 pos = scnprintf(buf, buflen, "HR1");
285 break;
286 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
287 pos = scnprintf(buf, buflen, "HRCDB");
288 break;
289 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_MS):
290 pos = scnprintf(buf, buflen, "MS");
291 break;
292 default:
293 return;
294 }
295
296 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
297 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
298 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
299 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
300 version = iwl_read_prph(trans, CNVI_MBOX_C);
301 switch (version) {
302 case 0x20000:
303 pos += scnprintf(buf + pos, buflen - pos, " B3");
304 break;
305 case 0x120000:
306 pos += scnprintf(buf + pos, buflen - pos, " B5");
307 break;
308 default:
309 pos += scnprintf(buf + pos, buflen - pos,
310 " (0x%x)", version);
311 break;
312 }
313 break;
314 default:
315 break;
316 }
317
318 pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x",
319 trans->hw_rf_id);
320
321 IWL_INFO(trans, "Detected RF %s\n", buf);
322
323 /*
324 * also add a \n for debugfs - need to do it after printing
325 * since our IWL_INFO machinery wants to see a static \n at
326 * the end of the string
327 */
328 pos += scnprintf(buf + pos, buflen - pos, "\n");
329 }
330
iwl_trans_pcie_gen2_fw_alive(struct iwl_trans * trans,u32 scd_addr)331 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr)
332 {
333 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
334
335 iwl_pcie_reset_ict(trans);
336
337 /* make sure all queue are not stopped/used */
338 memset(trans->txqs.queue_stopped, 0,
339 sizeof(trans->txqs.queue_stopped));
340 memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
341
342 /* now that we got alive we can free the fw image & the context info.
343 * paging memory cannot be freed included since FW will still use it
344 */
345 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
346 iwl_pcie_ctxt_info_gen3_free(trans, true);
347 else
348 iwl_pcie_ctxt_info_free(trans);
349
350 /*
351 * Re-enable all the interrupts, including the RF-Kill one, now that
352 * the firmware is alive.
353 */
354 iwl_enable_interrupts(trans);
355 mutex_lock(&trans_pcie->mutex);
356 iwl_pcie_check_hw_rf_kill(trans);
357
358 iwl_pcie_get_rf_name(trans);
359 mutex_unlock(&trans_pcie->mutex);
360 }
361
iwl_pcie_set_ltr(struct iwl_trans * trans)362 static bool iwl_pcie_set_ltr(struct iwl_trans *trans)
363 {
364 u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
365 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
366 CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
367 u32_encode_bits(250,
368 CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
369 CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
370 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
371 CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
372 u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
373
374 /*
375 * To workaround hardware latency issues during the boot process,
376 * initialize the LTR to ~250 usec (see ltr_val above).
377 * The firmware initializes this again later (to a smaller value).
378 */
379 if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 ||
380 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) &&
381 !trans->trans_cfg->integrated) {
382 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
383 return true;
384 }
385
386 if (trans->trans_cfg->integrated &&
387 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) {
388 iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
389 iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);
390 return true;
391 }
392
393 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
394 /* First clear the interrupt, just in case */
395 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,
396 MSIX_HW_INT_CAUSES_REG_IML);
397 /* In this case, unfortunately the same ROM bug exists in the
398 * device (not setting LTR correctly), but we don't have control
399 * over the settings from the host due to some hardware security
400 * features. The only workaround we've been able to come up with
401 * so far is to try to keep the CPU and device busy by polling
402 * it and the IML (image loader) completed interrupt.
403 */
404 return false;
405 }
406
407 /* nothing needs to be done on other devices */
408 return true;
409 }
410
iwl_pcie_spin_for_iml(struct iwl_trans * trans)411 static void iwl_pcie_spin_for_iml(struct iwl_trans *trans)
412 {
413 /* in practice, this seems to complete in around 20-30ms at most, wait 100 */
414 #define IML_WAIT_TIMEOUT (HZ / 10)
415 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
416 unsigned long end_time = jiffies + IML_WAIT_TIMEOUT;
417 u32 value, loops = 0;
418 bool irq = false;
419
420 if (WARN_ON(!trans_pcie->iml))
421 return;
422
423 value = iwl_read32(trans, CSR_LTR_LAST_MSG);
424 IWL_DEBUG_INFO(trans, "Polling for IML load - CSR_LTR_LAST_MSG=0x%x\n",
425 value);
426
427 while (time_before(jiffies, end_time)) {
428 if (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) &
429 MSIX_HW_INT_CAUSES_REG_IML) {
430 irq = true;
431 break;
432 }
433 /* Keep the CPU and device busy. */
434 value = iwl_read32(trans, CSR_LTR_LAST_MSG);
435 loops++;
436 }
437
438 IWL_DEBUG_INFO(trans,
439 "Polled for IML load: irq=%d, loops=%d, CSR_LTR_LAST_MSG=0x%x\n",
440 irq, loops, value);
441
442 /* We don't fail here even if we timed out - maybe we get lucky and the
443 * interrupt comes in later (and we get alive from firmware) and then
444 * we're all happy - but if not we'll fail on alive timeout or get some
445 * other error out.
446 */
447 }
448
iwl_trans_pcie_gen2_start_fw(struct iwl_trans * trans,const struct fw_img * fw,bool run_in_rfkill)449 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
450 const struct fw_img *fw, bool run_in_rfkill)
451 {
452 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
453 bool hw_rfkill, keep_ram_busy;
454 int ret;
455
456 /* This may fail if AMT took ownership of the device */
457 if (iwl_pcie_prepare_card_hw(trans)) {
458 IWL_WARN(trans, "Exit HW not ready\n");
459 return -EIO;
460 }
461
462 iwl_enable_rfkill_int(trans);
463
464 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
465
466 /*
467 * We enabled the RF-Kill interrupt and the handler may very
468 * well be running. Disable the interrupts to make sure no other
469 * interrupt can be fired.
470 */
471 iwl_disable_interrupts(trans);
472
473 /* Make sure it finished running */
474 iwl_pcie_synchronize_irqs(trans);
475
476 mutex_lock(&trans_pcie->mutex);
477
478 /* If platform's RF_KILL switch is NOT set to KILL */
479 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
480 if (hw_rfkill && !run_in_rfkill) {
481 ret = -ERFKILL;
482 goto out;
483 }
484
485 /* Someone called stop_device, don't try to start_fw */
486 if (trans_pcie->is_down) {
487 IWL_WARN(trans,
488 "Can't start_fw since the HW hasn't been started\n");
489 ret = -EIO;
490 goto out;
491 }
492
493 /* make sure rfkill handshake bits are cleared */
494 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
495 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
496 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
497
498 /* clear (again), then enable host interrupts */
499 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
500
501 ret = iwl_pcie_gen2_nic_init(trans);
502 if (ret) {
503 IWL_ERR(trans, "Unable to init nic\n");
504 goto out;
505 }
506
507 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
508 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw);
509 else
510 ret = iwl_pcie_ctxt_info_init(trans, fw);
511 if (ret)
512 goto out;
513
514 keep_ram_busy = !iwl_pcie_set_ltr(trans);
515
516 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
517 iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);
518 iwl_set_bit(trans, CSR_GP_CNTRL,
519 CSR_GP_CNTRL_REG_FLAG_ROM_START);
520 } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
521 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
522 } else {
523 iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
524 }
525
526 if (keep_ram_busy)
527 iwl_pcie_spin_for_iml(trans);
528
529 /* re-check RF-Kill state since we may have missed the interrupt */
530 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
531 if (hw_rfkill && !run_in_rfkill)
532 ret = -ERFKILL;
533
534 out:
535 mutex_unlock(&trans_pcie->mutex);
536 return ret;
537 }
538