1 /*******************************************************************************
2
3 Copyright (c) 2001-2005, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 *******************************************************************************/
33
34 /* $OpenBSD: ixgb_hw.c,v 1.11 2024/05/24 06:02:58 jsg Exp $ */
35
36 /* ixgb_hw.c
37 * Shared functions for accessing and configuring the adapter
38 */
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/device.h>
43
44 #include <net/if.h>
45 #include <net/if_media.h>
46
47 #include <netinet/in.h>
48 #include <netinet/if_ether.h>
49
50 #include <uvm/uvm_extern.h>
51
52 #include <dev/pci/pcireg.h>
53 #include <dev/pci/pcivar.h>
54
55 #include <dev/pci/ixgb_hw.h>
56 #include <dev/pci/ixgb_ids.h>
57
58 /* Local function prototypes */
59
60 static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr);
61
62 static void ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value);
63
64 static void ixgb_get_bus_info(struct ixgb_hw *hw);
65
66 static boolean_t ixgb_link_reset(struct ixgb_hw *hw);
67
68 static void ixgb_optics_reset(struct ixgb_hw *hw);
69
70 static void ixgb_optics_reset_bcm(struct ixgb_hw *hw);
71
72 static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
73
74 uint32_t ixgb_mac_reset(struct ixgb_hw *hw);
75
76 uint32_t
ixgb_mac_reset(struct ixgb_hw * hw)77 ixgb_mac_reset(struct ixgb_hw *hw)
78 {
79 uint32_t ctrl_reg;
80
81 ctrl_reg = IXGB_CTRL0_RST |
82 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
83 IXGB_CTRL0_SDP2_DIR |
84 IXGB_CTRL0_SDP1_DIR |
85 IXGB_CTRL0_SDP0_DIR |
86 IXGB_CTRL0_SDP3 | /* Initial value 1101 */
87 IXGB_CTRL0_SDP2 |
88 IXGB_CTRL0_SDP0;
89
90 #ifdef HP_ZX1
91 /* Workaround for 82597EX reset errata */
92 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
93 #else
94 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
95 #endif
96
97 /* Delay a few ms just to allow the reset to complete */
98 msec_delay(IXGB_DELAY_AFTER_RESET);
99 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
100 #ifdef DBG
101 /* Make sure the self-clearing global reset bit did self clear */
102 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
103 #endif
104
105 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID) {
106 ctrl_reg = /* Enable interrupt from XFP and SerDes */
107 IXGB_CTRL1_GPI0_EN |
108 IXGB_CTRL1_SDP6_DIR |
109 IXGB_CTRL1_SDP7_DIR |
110 IXGB_CTRL1_SDP6 |
111 IXGB_CTRL1_SDP7;
112 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
113 ixgb_optics_reset_bcm(hw);
114 }
115
116 if (hw->phy_type == ixgb_phy_type_txn17401)
117 ixgb_optics_reset(hw);
118
119 return ctrl_reg;
120 }
121
122 /******************************************************************************
123 * Reset the transmit and receive units; mask and clear all interrupts.
124 *
125 * hw - Struct containing variables accessed by shared code
126 *****************************************************************************/
127 boolean_t
ixgb_adapter_stop(struct ixgb_hw * hw)128 ixgb_adapter_stop(struct ixgb_hw *hw)
129 {
130 uint32_t ctrl_reg;
131 uint32_t icr_reg;
132
133 DEBUGFUNC("ixgb_adapter_stop");
134
135 /* If we are stopped or resetting exit gracefully and wait to be
136 * started again before accessing the hardware. */
137 if(hw->adapter_stopped) {
138 DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
139 return FALSE;
140 }
141
142 /* Set the Adapter Stopped flag so other driver functions stop touching
143 * the Hardware. */
144 hw->adapter_stopped = TRUE;
145
146 /* Clear interrupt mask to stop board from generating interrupts */
147 DEBUGOUT("Masking off all interrupts\n");
148 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
149
150 /* Disable the Transmit and Receive units. Then delay to allow any
151 * pending transactions to complete before we hit the MAC with the
152 * global reset. */
153 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
154 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
155 msec_delay(IXGB_DELAY_BEFORE_RESET);
156
157 /* Issue a global reset to the MAC. This will reset the chip's
158 * transmit, receive, DMA, and link units. It will not effect the
159 * current PCI configuration. The global reset bit is self- clearing,
160 * and should clear within a microsecond. */
161 DEBUGOUT("Issuing a global reset to MAC\n");
162
163 ctrl_reg = ixgb_mac_reset(hw);
164
165 /* Clear interrupt mask to stop board from generating interrupts */
166 DEBUGOUT("Masking off all interrupts\n");
167 IXGB_WRITE_REG(hw, IMC, 0xffffffff);
168
169 /* Clear any pending interrupt events. */
170 icr_reg = IXGB_READ_REG(hw, ICR);
171
172 return (ctrl_reg & IXGB_CTRL0_RST);
173 }
174
175 /******************************************************************************
176 * Identifies the vendor of the optics module on the adapter. The SR adapters
177 * support two different types of XPAK optics, so it is necessary to determine
178 * which optics are present before applying any optics-specific workarounds.
179 *
180 * hw - Struct containing variables accessed by shared code.
181 *
182 * Returns: the vendor of the XPAK optics module.
183 *****************************************************************************/
184 static ixgb_xpak_vendor
ixgb_identify_xpak_vendor(struct ixgb_hw * hw)185 ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
186 {
187 uint32_t i;
188 uint16_t vendor_name[5];
189 ixgb_xpak_vendor xpak_vendor;
190
191 DEBUGFUNC("ixgb_identify_xpak_vendor");
192
193 /* Read the first few bytes of the vendor string from the XPAK NVR
194 * registers. These are standard XENPAK/XPAK registers, so all XPAK
195 * devices should implement them. */
196 for(i = 0; i < 5; i++) {
197 vendor_name[i] =
198 ixgb_read_phy_reg(hw, MDIO_PMA_PMD_XPAK_VENDOR_NAME + i,
199 IXGB_PHY_ADDRESS, MDIO_PMA_PMD_DID);
200 }
201
202 /* Determine the actual vendor */
203 if (vendor_name[0] == 'I' &&
204 vendor_name[1] == 'N' &&
205 vendor_name[2] == 'T' &&
206 vendor_name[3] == 'E' &&
207 vendor_name[4] == 'L') {
208 xpak_vendor = ixgb_xpak_vendor_intel;
209 }
210 else {
211 xpak_vendor = ixgb_xpak_vendor_infineon;
212 }
213 return (xpak_vendor);
214 }
215
216 /******************************************************************************
217 * Determine the physical layer module on the adapter.
218 *
219 * hw - Struct containing variables accessed by shared code. The device_id
220 * field must be (correctly) populated before calling this routine.
221 *
222 * Returns: the phy type of the adapter.
223 *****************************************************************************/
224 static ixgb_phy_type
ixgb_identify_phy(struct ixgb_hw * hw)225 ixgb_identify_phy(struct ixgb_hw *hw)
226 {
227 ixgb_phy_type phy_type;
228 ixgb_xpak_vendor xpak_vendor;
229
230 DEBUGFUNC("ixgb_identify_phy");
231
232 /* Infer the transceiver/phy type from the device id */
233 switch(hw->device_id) {
234 case IXGB_DEVICE_ID_82597EX:
235 DEBUGOUT("Identified TXN17401 optics\n");
236 phy_type = ixgb_phy_type_txn17401;
237 break;
238
239 case IXGB_DEVICE_ID_82597EX_SR:
240 /* The SR adapters carry two different types of XPAK optics
241 * modules; read the vendor identifier to determine the exact
242 * type of optics. */
243 xpak_vendor = ixgb_identify_xpak_vendor(hw);
244 if(xpak_vendor == ixgb_xpak_vendor_intel) {
245 DEBUGOUT("Identified TXN17201 optics\n");
246 phy_type = ixgb_phy_type_txn17201;
247 } else {
248 DEBUGOUT("Identified G6005 optics\n");
249 phy_type = ixgb_phy_type_g6005;
250 }
251 break;
252
253 case IXGB_DEVICE_ID_82597EX_LR:
254 DEBUGOUT("Identified G6104 optics\n");
255 phy_type = ixgb_phy_type_g6104;
256 break;
257
258 case IXGB_DEVICE_ID_82597EX_CX4:
259 DEBUGOUT("Identified CX4\n");
260 xpak_vendor = ixgb_identify_xpak_vendor(hw);
261 if(xpak_vendor == ixgb_xpak_vendor_intel) {
262 DEBUGOUT("Identified TXN17201 optics\n");
263 phy_type = ixgb_phy_type_txn17201;
264 } else {
265 DEBUGOUT("Identified G6005 optics\n");
266 phy_type = ixgb_phy_type_g6005;
267 }
268 break;
269
270 default:
271 DEBUGOUT("Unknown physical layer module\n");
272 phy_type = ixgb_phy_type_unknown;
273 break;
274 }
275
276 /* update phy type for sun specific board */
277 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID)
278 phy_type = ixgb_phy_type_bcm;
279
280 return (phy_type);
281 }
282
283 /******************************************************************************
284 * Performs basic configuration of the adapter.
285 *
286 * hw - Struct containing variables accessed by shared code
287 *
288 * Resets the controller.
289 * Reads and validates the EEPROM.
290 * Initializes the receive address registers.
291 * Initializes the multicast table.
292 * Clears all on-chip counters.
293 * Calls routine to setup flow control settings.
294 * Leaves the transmit and receive units disabled and uninitialized.
295 *
296 * Returns:
297 * TRUE if successful,
298 * FALSE if unrecoverable problems were encountered.
299 *****************************************************************************/
300 boolean_t
ixgb_init_hw(struct ixgb_hw * hw)301 ixgb_init_hw(struct ixgb_hw *hw)
302 {
303 uint32_t i;
304 uint32_t ctrl_reg;
305 boolean_t status;
306
307 DEBUGFUNC("ixgb_init_hw");
308
309 /* Issue a global reset to the MAC. This will reset the chip's
310 * transmit, receive, DMA, and link units. It will not effect the
311 * current PCI configuration. The global reset bit is self- clearing,
312 * and should clear within a microsecond. */
313 DEBUGOUT("Issuing a global reset to MAC\n");
314
315 ctrl_reg = ixgb_mac_reset(hw);
316
317 DEBUGOUT("Issuing an EE reset to MAC\n");
318 #ifdef HP_ZX1
319 /* Workaround for 82597EX reset errata */
320 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
321 #else
322 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
323 #endif
324
325 /* Delay a few ms just to allow the reset to complete */
326 msec_delay(IXGB_DELAY_AFTER_EE_RESET);
327
328 if(ixgb_get_eeprom_data(hw) == FALSE) {
329 return (FALSE);
330 }
331
332 /* Use the device id to determine the type of phy/transceiver. */
333 hw->device_id = ixgb_get_ee_device_id(hw);
334 hw->phy_type = ixgb_identify_phy(hw);
335
336 /* Setup the receive addresses. Receive Address Registers (RARs 0 -
337 * 15). */
338 ixgb_init_rx_addrs(hw);
339
340 /*
341 * Check that a valid MAC address has been set.
342 * If it is not valid, we fail hardware init.
343 */
344 if(!mac_addr_valid(hw->curr_mac_addr)) {
345 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
346 return (FALSE);
347 }
348
349 /* tell the routines in this file they can access hardware again */
350 hw->adapter_stopped = FALSE;
351
352 /* Fill in the bus_info structure */
353 ixgb_get_bus_info(hw);
354
355 /* Zero out the Multicast HASH table */
356 DEBUGOUT("Zeroing the MTA\n");
357 for(i = 0; i < IXGB_MC_TBL_SIZE; i++)
358 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
359
360 /* Zero out the VLAN Filter Table Array */
361 ixgb_clear_vfta(hw);
362
363 /* Zero all of the hardware counters */
364 ixgb_clear_hw_cntrs(hw);
365
366 /* Call a subroutine to setup flow control. */
367 status = ixgb_setup_fc(hw);
368
369 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
370 ixgb_check_for_link(hw);
371
372 return (status);
373 }
374
375 /******************************************************************************
376 * Initializes receive address filters.
377 *
378 * hw - Struct containing variables accessed by shared code
379 *
380 * Places the MAC address in receive address register 0 and clears the rest
381 * of the receive address registers. Clears the multicast table. Assumes
382 * the receiver is in reset when the routine is called.
383 *****************************************************************************/
384 void
ixgb_init_rx_addrs(struct ixgb_hw * hw)385 ixgb_init_rx_addrs(struct ixgb_hw *hw)
386 {
387 uint32_t i;
388
389 DEBUGFUNC("ixgb_init_rx_addrs");
390
391 /*
392 * If the current mac address is valid, assume it is a software override
393 * to the permanent address.
394 * Otherwise, use the permanent address from the eeprom.
395 */
396 if(!mac_addr_valid(hw->curr_mac_addr)) {
397
398 /* Get the MAC address from the eeprom for later reference */
399 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
400
401 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ",
402 hw->curr_mac_addr[0], hw->curr_mac_addr[1],
403 hw->curr_mac_addr[2]);
404 DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3],
405 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
406 } else {
407
408 /* Setup the receive address. */
409 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
410 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
411 hw->curr_mac_addr[0], hw->curr_mac_addr[1],
412 hw->curr_mac_addr[2]);
413 DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3],
414 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
415
416 ixgb_rar_set(hw, hw->curr_mac_addr, 0);
417 }
418
419 /* Zero out the other 15 receive addresses. */
420 DEBUGOUT("Clearing RAR[1-15]\n");
421 for(i = 1; i < IXGB_RAR_ENTRIES; i++) {
422 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
423 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
424 }
425
426 return;
427 }
428
429 /******************************************************************************
430 * Updates the MAC's list of multicast addresses.
431 *
432 * hw - Struct containing variables accessed by shared code
433 * mc_addr_list - the list of new multicast addresses
434 * mc_addr_count - number of addresses
435 * pad - number of bytes between addresses in the list
436 *
437 * The given list replaces any existing list. Clears the last 15 receive
438 * address registers and the multicast table. Uses receive address registers
439 * for the first 15 multicast addresses, and hashes the rest into the
440 * multicast table.
441 *****************************************************************************/
442 void
ixgb_mc_addr_list_update(struct ixgb_hw * hw,uint8_t * mc_addr_list,uint32_t mc_addr_count,uint32_t pad)443 ixgb_mc_addr_list_update(struct ixgb_hw *hw, uint8_t *mc_addr_list,
444 uint32_t mc_addr_count, uint32_t pad)
445 {
446 uint32_t hash_value;
447 uint32_t i;
448 uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */
449
450 DEBUGFUNC("ixgb_mc_addr_list_update");
451
452 /* Set the new number of MC addresses that we are being requested to
453 * use. */
454 hw->num_mc_addrs = mc_addr_count;
455
456 /* Clear RAR[1-15] */
457 DEBUGOUT(" Clearing RAR[1-15]\n");
458 for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
459 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
460 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
461 }
462
463 /* Clear the MTA */
464 DEBUGOUT(" Clearing MTA\n");
465 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) {
466 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
467 }
468
469 /* Add the new addresses */
470 for(i = 0; i < mc_addr_count; i++) {
471 DEBUGOUT(" Adding the multicast addresses:\n");
472 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
473 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
474 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 1],
475 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 2],
476 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 3],
477 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 4],
478 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 5]);
479
480 /* Place this multicast address in the RAR if there is room, *
481 * else put it in the MTA */
482 if(rar_used_count < IXGB_RAR_ENTRIES) {
483 ixgb_rar_set(hw,
484 mc_addr_list +
485 (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
486 rar_used_count);
487 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i);
488 rar_used_count++;
489 } else {
490 hash_value =
491 ixgb_hash_mc_addr(hw,
492 mc_addr_list +
493 (i *
494 (IXGB_ETH_LENGTH_OF_ADDRESS +
495 pad)));
496
497 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
498
499 ixgb_mta_set(hw, hash_value);
500 }
501 }
502
503 DEBUGOUT("MC Update Complete\n");
504 return;
505 }
506
507 /******************************************************************************
508 * Hashes an address to determine its location in the multicast table
509 *
510 * hw - Struct containing variables accessed by shared code
511 * mc_addr - the multicast address to hash
512 *
513 * Returns:
514 * The hash value
515 *****************************************************************************/
516 static uint32_t
ixgb_hash_mc_addr(struct ixgb_hw * hw,uint8_t * mc_addr)517 ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr)
518 {
519 uint32_t hash_value = 0;
520
521 DEBUGFUNC("ixgb_hash_mc_addr");
522
523 /* The portion of the address that is used for the hash table is
524 * determined by the mc_filter_type setting. */
525 switch(hw->mc_filter_type) {
526 /* [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB MSB -
527 * According to H/W docs */
528 case 0:
529 /* [47:36] i.e. 0x563 for above example address */
530 hash_value =
531 ((mc_addr[4] >> 4) | (((uint16_t)mc_addr[5]) << 4));
532 break;
533 case 1: /* [46:35] i.e. 0xAC6 for above
534 * example address */
535 hash_value =
536 ((mc_addr[4] >> 3) | (((uint16_t)mc_addr[5]) << 5));
537 break;
538 case 2: /* [45:34] i.e. 0x5D8 for above
539 * example address */
540 hash_value =
541 ((mc_addr[4] >> 2) | (((uint16_t)mc_addr[5]) << 6));
542 break;
543 case 3: /* [43:32] i.e. 0x634 for above
544 * example address */
545 hash_value = ((mc_addr[4]) | (((uint16_t)mc_addr[5]) << 8));
546 break;
547 default:
548 /* Invalid mc_filter_type, what should we do? */
549 DEBUGOUT("MC filter type param set incorrectly\n");
550 ASSERT(0);
551 break;
552 }
553
554 hash_value &= 0xFFF;
555 return (hash_value);
556 }
557
558 /******************************************************************************
559 * Sets the bit in the multicast table corresponding to the hash value.
560 *
561 * hw - Struct containing variables accessed by shared code
562 * hash_value - Multicast address hash value
563 *****************************************************************************/
564 static void
ixgb_mta_set(struct ixgb_hw * hw,uint32_t hash_value)565 ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value)
566 {
567 uint32_t hash_bit, hash_reg;
568 uint32_t mta_reg;
569
570 /* The MTA is a register array of 128 32-bit registers. It is treated
571 * like an array of 4096 bits. We want to set bit
572 * BitArray[hash_value]. So we figure out what register the bit is in,
573 * read it, OR in the new bit, then write back the new value. The
574 * register is determined by the upper 7 bits of the hash value and the
575 * bit within that register are determined by the lower 5 bits of the
576 * value. */
577 hash_reg = (hash_value >> 5) & 0x7F;
578 hash_bit = hash_value & 0x1F;
579 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
580 mta_reg |= (1 << hash_bit);
581 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
582 return;
583 }
584
585 /******************************************************************************
586 * Puts an ethernet address into a receive address register.
587 *
588 * hw - Struct containing variables accessed by shared code
589 * addr - Address to put into receive address register
590 * index - Receive address register to write
591 *****************************************************************************/
592 void
ixgb_rar_set(struct ixgb_hw * hw,uint8_t * addr,uint32_t index)593 ixgb_rar_set(struct ixgb_hw *hw, uint8_t *addr, uint32_t index)
594 {
595 uint32_t rar_low, rar_high;
596
597 DEBUGFUNC("ixgb_rar_set");
598
599 /* HW expects these in little endian so we reverse the byte order from
600 * network order (big endian) to little endian */
601 rar_low = ((uint32_t)addr[0] |
602 ((uint32_t)addr[1] << 8) |
603 ((uint32_t)addr[2] << 16) |
604 ((uint32_t)addr[3] << 24));
605
606 rar_high = ((uint32_t)addr[4] |
607 ((uint32_t)addr[5] << 8) |
608 IXGB_RAH_AV);
609
610 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
611 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
612 return;
613 }
614
615 /******************************************************************************
616 * Writes a value to the specified offset in the VLAN filter table.
617 *
618 * hw - Struct containing variables accessed by shared code
619 * offset - Offset in VLAN filer table to write
620 * value - Value to write into VLAN filter table
621 *****************************************************************************/
622 void
ixgb_write_vfta(struct ixgb_hw * hw,uint32_t offset,uint32_t value)623 ixgb_write_vfta(struct ixgb_hw *hw, uint32_t offset, uint32_t value)
624 {
625 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
626 return;
627 }
628
629 /******************************************************************************
630 * Clears the VLAN filer table
631 *
632 * hw - Struct containing variables accessed by shared code
633 *****************************************************************************/
634 void
ixgb_clear_vfta(struct ixgb_hw * hw)635 ixgb_clear_vfta(struct ixgb_hw *hw)
636 {
637 uint32_t offset;
638
639 for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
640 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
641 return;
642 }
643
644 /******************************************************************************
645 * Configures the flow control settings based on SW configuration.
646 *
647 * hw - Struct containing variables accessed by shared code
648 *****************************************************************************/
649
650 boolean_t
ixgb_setup_fc(struct ixgb_hw * hw)651 ixgb_setup_fc(struct ixgb_hw *hw)
652 {
653 uint32_t ctrl_reg;
654 uint32_t pap_reg = 0; /* by default, assume no pause time */
655 boolean_t status = TRUE;
656
657 DEBUGFUNC("ixgb_setup_fc");
658
659 /* Get the current control reg 0 settings */
660 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
661
662 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
663 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
664
665 /* The possible values of the "flow_control" parameter are:
666 * 0: Flow control is completely disabled
667 * 1: Rx flow control is enabled (we can receive pause frames but not send
668 * pause frames).
669 * 2: Tx flow control is enabled (we can send pause frames but we do not
670 * support receiving pause frames)
671 * 3: Both Rx and TX flow control (symmetric) are enabled.
672 * other: Invalid. */
673 switch(hw->fc.type) {
674 case ixgb_fc_none: /* 0 */
675 /* Set CMDC bit to disable Rx Flow control */
676 ctrl_reg |= (IXGB_CTRL0_CMDC);
677 break;
678 case ixgb_fc_rx_pause: /* 1 */
679 /* RX Flow control is enabled, and TX Flow control is disabled. */
680 ctrl_reg |= (IXGB_CTRL0_RPE);
681 break;
682 case ixgb_fc_tx_pause: /* 2 */
683 /* TX Flow control is enabled, and RX Flow control is disabled,
684 * by a software over-ride. */
685 ctrl_reg |= (IXGB_CTRL0_TPE);
686 pap_reg = hw->fc.pause_time;
687 break;
688 case ixgb_fc_full: /* 3 */
689 /* Flow control (both RX and TX) is enabled by a software
690 * over-ride. */
691 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
692 pap_reg = hw->fc.pause_time;
693 break;
694 default:
695 /* We should never get here. The value should be 0-3. */
696 DEBUGOUT("Flow control param set incorrectly\n");
697 ASSERT(0);
698 break;
699 }
700
701 /* Write the new settings */
702 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
703
704 if(pap_reg != 0) {
705 IXGB_WRITE_REG(hw, PAP, pap_reg);
706 }
707
708 /* Set the flow control receive threshold registers. Normally, these
709 * registers will be set to a default threshold that may be adjusted
710 * later by the driver's runtime code. However, if the ability to
711 * transmit pause frames in not enabled, then these registers will be
712 * set to 0. */
713 if(!(hw->fc.type & ixgb_fc_tx_pause)) {
714 IXGB_WRITE_REG(hw, FCRTL, 0);
715 IXGB_WRITE_REG(hw, FCRTH, 0);
716 } else {
717 /* We need to set up the Receive Threshold high and low water
718 * marks as well as (optionally) enabling the transmission of
719 * XON frames. */
720 if(hw->fc.send_xon) {
721 IXGB_WRITE_REG(hw, FCRTL,
722 (hw->fc.low_water | IXGB_FCRTL_XONE));
723 } else {
724 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
725 }
726 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
727 }
728 return (status);
729 }
730
731 /******************************************************************************
732 * Reads a word from a device over the Management Data Interface (MDI) bus.
733 * This interface is used to manage Physical layer devices.
734 *
735 * hw - Struct containing variables accessed by hw code
736 * reg_address - Offset of device register being read.
737 * phy_address - Address of device on MDI.
738 *
739 * Returns: Data word (16 bits) from MDI device.
740 *
741 * The 82597EX has support for several MDI access methods. This routine
742 * uses the new protocol MDI Single Command and Address Operation.
743 * This requires that first an address cycle command is sent, followed by a
744 * read command.
745 *****************************************************************************/
746 uint16_t
ixgb_read_phy_reg(struct ixgb_hw * hw,uint32_t reg_address,uint32_t phy_address,uint32_t device_type)747 ixgb_read_phy_reg(struct ixgb_hw *hw, uint32_t reg_address,
748 uint32_t phy_address, uint32_t device_type)
749 {
750 uint32_t i;
751 uint32_t data;
752 uint32_t command = 0;
753
754 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
755 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
756 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
757
758 /* Setup and write the address cycle command */
759 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
760 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
761 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
762 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
763
764 IXGB_WRITE_REG(hw, MSCA, command);
765
766 /**************************************************************
767 ** Check every 10 usec to see if the address cycle completed
768 ** The COMMAND bit will clear when the operation is complete.
769 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
770 ** from the CPU Write to the Ready bit assertion.
771 **************************************************************/
772
773 for(i = 0; i < 10; i++) {
774 usec_delay(10);
775
776 command = IXGB_READ_REG(hw, MSCA);
777
778 if((command & IXGB_MSCA_MDI_COMMAND) == 0)
779 break;
780 }
781
782 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
783
784 /* Address cycle complete, setup and write the read command */
785 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
786 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
787 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
788 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
789
790 IXGB_WRITE_REG(hw, MSCA, command);
791
792 /**************************************************************
793 ** Check every 10 usec to see if the read command completed
794 ** The COMMAND bit will clear when the operation is complete.
795 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
796 ** from the CPU Write to the Ready bit assertion.
797 **************************************************************/
798
799 for(i = 0; i < 10; i++) {
800 usec_delay(10);
801
802 command = IXGB_READ_REG(hw, MSCA);
803
804 if((command & IXGB_MSCA_MDI_COMMAND) == 0)
805 break;
806 }
807
808 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
809
810 /* Operation is complete, get the data from the MDIO Read/Write Data
811 * register and return. */
812 data = IXGB_READ_REG(hw, MSRWD);
813 data >>= IXGB_MSRWD_READ_DATA_SHIFT;
814 return ((uint16_t)data);
815 }
816
817 /******************************************************************************
818 * Writes a word to a device over the Management Data Interface (MDI) bus.
819 * This interface is used to manage Physical layer devices.
820 *
821 * hw - Struct containing variables accessed by hw code
822 * reg_address - Offset of device register being read.
823 * phy_address - Address of device on MDI.
824 * device_type - Also known as the Device ID or DID.
825 * data - 16-bit value to be written
826 *
827 * Returns: void.
828 *
829 * The 82597EX has support for several MDI access methods. This routine
830 * uses the new protocol MDI Single Command and Address Operation.
831 * This requires that first an address cycle command is sent, followed by a
832 * write command.
833 *****************************************************************************/
834 void
ixgb_write_phy_reg(struct ixgb_hw * hw,uint32_t reg_address,uint32_t phy_address,uint32_t device_type,uint16_t data)835 ixgb_write_phy_reg(struct ixgb_hw *hw, uint32_t reg_address,
836 uint32_t phy_address, uint32_t device_type, uint16_t data)
837 {
838 uint32_t i;
839 uint32_t command = 0;
840
841 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
842 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
843 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
844
845 /* Put the data in the MDIO Read/Write Data register */
846 IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data);
847
848 /* Setup and write the address cycle command */
849 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
850 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
851 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
852 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
853
854 IXGB_WRITE_REG(hw, MSCA, command);
855
856 /**************************************************************
857 ** Check every 10 usec to see if the address cycle completed
858 ** The COMMAND bit will clear when the operation is complete.
859 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
860 ** from the CPU Write to the Ready bit assertion.
861 **************************************************************/
862
863 for(i = 0; i < 10; i++) {
864 usec_delay(10);
865
866 command = IXGB_READ_REG(hw, MSCA);
867
868 if((command & IXGB_MSCA_MDI_COMMAND) == 0)
869 break;
870 }
871
872 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
873
874 /* Address cycle complete, setup and write the write command */
875 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
876 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
877 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
878 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
879
880 IXGB_WRITE_REG(hw, MSCA, command);
881
882 /**************************************************************
883 ** Check every 10 usec to see if the read command completed
884 ** The COMMAND bit will clear when the operation is complete.
885 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
886 ** from the CPU Write to the Ready bit assertion.
887 **************************************************************/
888
889 for(i = 0; i < 10; i++) {
890 usec_delay(10);
891
892 command = IXGB_READ_REG(hw, MSCA);
893
894 if((command & IXGB_MSCA_MDI_COMMAND) == 0)
895 break;
896 }
897
898 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
899
900 /* Operation is complete, return. */
901 }
902
903 /******************************************************************************
904 * Checks to see if the link status of the hardware has changed.
905 *
906 * hw - Struct containing variables accessed by hw code
907 *
908 * Called by any function that needs to check the link status of the adapter.
909 *****************************************************************************/
910 void
ixgb_check_for_link(struct ixgb_hw * hw)911 ixgb_check_for_link(struct ixgb_hw *hw)
912 {
913 uint32_t status_reg;
914 uint32_t xpcss_reg;
915
916 DEBUGFUNC("ixgb_check_for_link");
917
918 xpcss_reg = IXGB_READ_REG(hw, XPCSS);
919 status_reg = IXGB_READ_REG(hw, STATUS);
920
921 if((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
922 (status_reg & IXGB_STATUS_LU)) {
923 hw->link_up = TRUE;
924 } else if(!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
925 (status_reg & IXGB_STATUS_LU)) {
926 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n");
927 hw->link_up = ixgb_link_reset(hw);
928 } else {
929 /*
930 * 82597EX errata. Since the lane deskew problem may prevent
931 * link, reset the link before reporting link down.
932 */
933 hw->link_up = ixgb_link_reset(hw);
934 }
935 /* Anything else for 10 Gig?? */
936 }
937
938 /******************************************************************************
939 * Check for a bad link condition that may have occurred.
940 * The indication is that the RFC / LFC registers may be incrementing
941 * continually. A full adapter reset is required to recover.
942 *
943 * hw - Struct containing variables accessed by hw code
944 *
945 * Called by any function that needs to check the link status of the adapter.
946 *****************************************************************************/
947 boolean_t
ixgb_check_for_bad_link(struct ixgb_hw * hw)948 ixgb_check_for_bad_link(struct ixgb_hw *hw)
949 {
950 uint32_t newLFC, newRFC;
951 boolean_t bad_link_returncode = FALSE;
952
953 if(hw->phy_type == ixgb_phy_type_txn17401) {
954 newLFC = IXGB_READ_REG(hw, LFC);
955 newRFC = IXGB_READ_REG(hw, RFC);
956 if((hw->lastLFC + 250 < newLFC) || (hw->lastRFC + 250 < newRFC)) {
957 DEBUGOUT("BAD LINK! too many LFC/RFC since last check\n");
958 bad_link_returncode = TRUE;
959 }
960 hw->lastLFC = newLFC;
961 hw->lastRFC = newRFC;
962 }
963
964 return bad_link_returncode;
965 }
966
967 /******************************************************************************
968 * Clears all hardware statistics counters.
969 *
970 * hw - Struct containing variables accessed by shared code
971 *****************************************************************************/
972 void
ixgb_clear_hw_cntrs(struct ixgb_hw * hw)973 ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
974 {
975 volatile uint32_t temp_reg;
976
977 DEBUGFUNC("ixgb_clear_hw_cntrs");
978
979 /* if we are stopped or resetting exit gracefully */
980 if(hw->adapter_stopped) {
981 DEBUGOUT("Exiting because the adapter is stopped!!!\n");
982 return;
983 }
984
985 temp_reg = IXGB_READ_REG(hw, TPRL);
986 temp_reg = IXGB_READ_REG(hw, TPRH);
987 temp_reg = IXGB_READ_REG(hw, GPRCL);
988 temp_reg = IXGB_READ_REG(hw, GPRCH);
989 temp_reg = IXGB_READ_REG(hw, BPRCL);
990 temp_reg = IXGB_READ_REG(hw, BPRCH);
991 temp_reg = IXGB_READ_REG(hw, MPRCL);
992 temp_reg = IXGB_READ_REG(hw, MPRCH);
993 temp_reg = IXGB_READ_REG(hw, UPRCL);
994 temp_reg = IXGB_READ_REG(hw, UPRCH);
995 temp_reg = IXGB_READ_REG(hw, VPRCL);
996 temp_reg = IXGB_READ_REG(hw, VPRCH);
997 temp_reg = IXGB_READ_REG(hw, JPRCL);
998 temp_reg = IXGB_READ_REG(hw, JPRCH);
999 temp_reg = IXGB_READ_REG(hw, GORCL);
1000 temp_reg = IXGB_READ_REG(hw, GORCH);
1001 temp_reg = IXGB_READ_REG(hw, TORL);
1002 temp_reg = IXGB_READ_REG(hw, TORH);
1003 temp_reg = IXGB_READ_REG(hw, RNBC);
1004 temp_reg = IXGB_READ_REG(hw, RUC);
1005 temp_reg = IXGB_READ_REG(hw, ROC);
1006 temp_reg = IXGB_READ_REG(hw, RLEC);
1007 temp_reg = IXGB_READ_REG(hw, CRCERRS);
1008 temp_reg = IXGB_READ_REG(hw, ICBC);
1009 temp_reg = IXGB_READ_REG(hw, ECBC);
1010 temp_reg = IXGB_READ_REG(hw, MPC);
1011 temp_reg = IXGB_READ_REG(hw, TPTL);
1012 temp_reg = IXGB_READ_REG(hw, TPTH);
1013 temp_reg = IXGB_READ_REG(hw, GPTCL);
1014 temp_reg = IXGB_READ_REG(hw, GPTCH);
1015 temp_reg = IXGB_READ_REG(hw, BPTCL);
1016 temp_reg = IXGB_READ_REG(hw, BPTCH);
1017 temp_reg = IXGB_READ_REG(hw, MPTCL);
1018 temp_reg = IXGB_READ_REG(hw, MPTCH);
1019 temp_reg = IXGB_READ_REG(hw, UPTCL);
1020 temp_reg = IXGB_READ_REG(hw, UPTCH);
1021 temp_reg = IXGB_READ_REG(hw, VPTCL);
1022 temp_reg = IXGB_READ_REG(hw, VPTCH);
1023 temp_reg = IXGB_READ_REG(hw, JPTCL);
1024 temp_reg = IXGB_READ_REG(hw, JPTCH);
1025 temp_reg = IXGB_READ_REG(hw, GOTCL);
1026 temp_reg = IXGB_READ_REG(hw, GOTCH);
1027 temp_reg = IXGB_READ_REG(hw, TOTL);
1028 temp_reg = IXGB_READ_REG(hw, TOTH);
1029 temp_reg = IXGB_READ_REG(hw, DC);
1030 temp_reg = IXGB_READ_REG(hw, PLT64C);
1031 temp_reg = IXGB_READ_REG(hw, TSCTC);
1032 temp_reg = IXGB_READ_REG(hw, TSCTFC);
1033 temp_reg = IXGB_READ_REG(hw, IBIC);
1034 temp_reg = IXGB_READ_REG(hw, RFC);
1035 temp_reg = IXGB_READ_REG(hw, LFC);
1036 temp_reg = IXGB_READ_REG(hw, PFRC);
1037 temp_reg = IXGB_READ_REG(hw, PFTC);
1038 temp_reg = IXGB_READ_REG(hw, MCFRC);
1039 temp_reg = IXGB_READ_REG(hw, MCFTC);
1040 temp_reg = IXGB_READ_REG(hw, XONRXC);
1041 temp_reg = IXGB_READ_REG(hw, XONTXC);
1042 temp_reg = IXGB_READ_REG(hw, XOFFRXC);
1043 temp_reg = IXGB_READ_REG(hw, XOFFTXC);
1044 temp_reg = IXGB_READ_REG(hw, RJC);
1045 return;
1046 }
1047
1048 /******************************************************************************
1049 * Turns on the software controllable LED
1050 *
1051 * hw - Struct containing variables accessed by shared code
1052 *****************************************************************************/
1053 void
ixgb_led_on(struct ixgb_hw * hw)1054 ixgb_led_on(struct ixgb_hw *hw)
1055 {
1056 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1057
1058 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1059 ctrl0_reg &= ~IXGB_CTRL0_SDP0;
1060 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1061 return;
1062 }
1063
1064 /******************************************************************************
1065 * Turns off the software controllable LED
1066 *
1067 * hw - Struct containing variables accessed by shared code
1068 *****************************************************************************/
1069 void
ixgb_led_off(struct ixgb_hw * hw)1070 ixgb_led_off(struct ixgb_hw *hw)
1071 {
1072 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1073
1074 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1075 ctrl0_reg |= IXGB_CTRL0_SDP0;
1076 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1077 return;
1078 }
1079
1080 /******************************************************************************
1081 * Gets the current PCI bus type, speed, and width of the hardware
1082 *
1083 * hw - Struct containing variables accessed by shared code
1084 *****************************************************************************/
1085 static void
ixgb_get_bus_info(struct ixgb_hw * hw)1086 ixgb_get_bus_info(struct ixgb_hw *hw)
1087 {
1088 uint32_t status_reg;
1089
1090 status_reg = IXGB_READ_REG(hw, STATUS);
1091
1092 hw->bus.type =
1093 (status_reg & IXGB_STATUS_PCIX_MODE) ? ixgb_bus_type_pcix :
1094 ixgb_bus_type_pci;
1095
1096 if(hw->bus.type == ixgb_bus_type_pci) {
1097 hw->bus.speed =
1098 (status_reg & IXGB_STATUS_PCI_SPD) ? ixgb_bus_speed_66 :
1099 ixgb_bus_speed_33;
1100 } else {
1101 switch(status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
1102 case IXGB_STATUS_PCIX_SPD_66:
1103 hw->bus.speed = ixgb_bus_speed_66;
1104 break;
1105 case IXGB_STATUS_PCIX_SPD_100:
1106 hw->bus.speed = ixgb_bus_speed_100;
1107 break;
1108 case IXGB_STATUS_PCIX_SPD_133:
1109 hw->bus.speed = ixgb_bus_speed_133;
1110 break;
1111 default:
1112 hw->bus.speed = ixgb_bus_speed_reserved;
1113 break;
1114 }
1115 }
1116
1117 hw->bus.width =
1118 (status_reg & IXGB_STATUS_BUS64) ? ixgb_bus_width_64 :
1119 ixgb_bus_width_32;
1120
1121 return;
1122 }
1123
1124 /******************************************************************************
1125 * Tests a MAC address to ensure it is a valid Individual Address
1126 *
1127 * mac_addr - pointer to MAC address.
1128 *
1129 *****************************************************************************/
1130 boolean_t
mac_addr_valid(uint8_t * mac_addr)1131 mac_addr_valid(uint8_t *mac_addr)
1132 {
1133 boolean_t is_valid = TRUE;
1134
1135 DEBUGFUNC("mac_addr_valid");
1136
1137 /* Make sure it is not a multicast address */
1138 if(IS_MULTICAST(mac_addr)) {
1139 DEBUGOUT("MAC address is multicast\n");
1140 is_valid = FALSE;
1141 }
1142 /* Not a broadcast address */
1143 else if(IS_BROADCAST(mac_addr)) {
1144 DEBUGOUT("MAC address is broadcast\n");
1145 is_valid = FALSE;
1146 }
1147 /* Reject the zero address */
1148 else if (mac_addr[0] == 0 &&
1149 mac_addr[1] == 0 &&
1150 mac_addr[2] == 0 &&
1151 mac_addr[3] == 0 &&
1152 mac_addr[4] == 0 &&
1153 mac_addr[5] == 0) {
1154 DEBUGOUT("MAC address is all zeros\n");
1155 is_valid = FALSE;
1156 }
1157 return (is_valid);
1158 }
1159
1160 /******************************************************************************
1161 * Resets the 10GbE link. Waits the settle time and returns the state of
1162 * the link.
1163 *
1164 * hw - Struct containing variables accessed by shared code
1165 *****************************************************************************/
1166 boolean_t
ixgb_link_reset(struct ixgb_hw * hw)1167 ixgb_link_reset(struct ixgb_hw *hw)
1168 {
1169 boolean_t link_status = FALSE;
1170 uint8_t wait_retries = MAX_RESET_ITERATIONS;
1171 uint8_t lrst_retries = MAX_RESET_ITERATIONS;
1172
1173 do {
1174 /* Reset the link */
1175 IXGB_WRITE_REG(hw, CTRL0,
1176 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
1177
1178 /* Wait for link-up and lane re-alignment */
1179 do {
1180 usec_delay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
1181 link_status =
1182 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU) &&
1183 (IXGB_READ_REG(hw, XPCSS) &
1184 IXGB_XPCSS_ALIGN_STATUS)) ? TRUE : FALSE;
1185 } while(!link_status && --wait_retries);
1186
1187 } while(!link_status && --lrst_retries);
1188
1189 return link_status;
1190 }
1191
1192 /******************************************************************************
1193 * Resets the 10GbE optics module.
1194 *
1195 * hw - Struct containing variables accessed by shared code
1196 *****************************************************************************/
1197 void
ixgb_optics_reset(struct ixgb_hw * hw)1198 ixgb_optics_reset(struct ixgb_hw *hw)
1199 {
1200 if(hw->phy_type == ixgb_phy_type_txn17401) {
1201 uint16_t mdio_reg;
1202
1203 ixgb_write_phy_reg(hw,
1204 MDIO_PMA_PMD_CR1,
1205 IXGB_PHY_ADDRESS,
1206 MDIO_PMA_PMD_DID,
1207 MDIO_PMA_PMD_CR1_RESET);
1208
1209 mdio_reg = ixgb_read_phy_reg(hw,
1210 MDIO_PMA_PMD_CR1,
1211 IXGB_PHY_ADDRESS,
1212 MDIO_PMA_PMD_DID);
1213 }
1214
1215 return;
1216 }
1217
1218 /******************************************************************************
1219 * Resets the 10GbE optics module for Sun variant NIC.
1220 *
1221 * hw - Struct containing variables accessed by shared code
1222 *****************************************************************************/
1223
1224 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG 0xC803
1225 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL 0x0164
1226 #define IXGB_BCM8704_USER_CTRL_REG 0xC800
1227 #define IXGB_BCM8704_USER_CTRL_REG_VAL 0x7FBF
1228 #define IXGB_BCM8704_USER_DEV3_ADDR 0x0003
1229 #define IXGB_SUN_PHY_ADDRESS 0x0000
1230 #define IXGB_SUN_PHY_RESET_DELAY 305
1231
1232 static void
ixgb_optics_reset_bcm(struct ixgb_hw * hw)1233 ixgb_optics_reset_bcm(struct ixgb_hw *hw)
1234 {
1235 uint32_t ctrl = IXGB_READ_REG(hw, CTRL0);
1236 ctrl &= ~IXGB_CTRL0_SDP2;
1237 ctrl |= IXGB_CTRL0_SDP3;
1238 IXGB_WRITE_REG(hw, CTRL0, ctrl);
1239
1240 /* SerDes needs extra delay */
1241 msec_delay(IXGB_SUN_PHY_RESET_DELAY);
1242
1243 /* Broadcom 7408L configuration */
1244 /* Reference clock config */
1245 ixgb_write_phy_reg(hw,
1246 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1247 IXGB_SUN_PHY_ADDRESS,
1248 IXGB_BCM8704_USER_DEV3_ADDR,
1249 IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL);
1250 /* we must read the registers twice */
1251 ixgb_read_phy_reg(hw,
1252 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1253 IXGB_SUN_PHY_ADDRESS,
1254 IXGB_BCM8704_USER_DEV3_ADDR);
1255 ixgb_read_phy_reg(hw,
1256 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1257 IXGB_SUN_PHY_ADDRESS,
1258 IXGB_BCM8704_USER_DEV3_ADDR);
1259
1260 ixgb_write_phy_reg(hw,
1261 IXGB_BCM8704_USER_CTRL_REG,
1262 IXGB_SUN_PHY_ADDRESS,
1263 IXGB_BCM8704_USER_DEV3_ADDR,
1264 IXGB_BCM8704_USER_CTRL_REG_VAL);
1265 ixgb_read_phy_reg(hw,
1266 IXGB_BCM8704_USER_CTRL_REG,
1267 IXGB_SUN_PHY_ADDRESS,
1268 IXGB_BCM8704_USER_DEV3_ADDR);
1269 ixgb_read_phy_reg(hw,
1270 IXGB_BCM8704_USER_CTRL_REG,
1271 IXGB_SUN_PHY_ADDRESS,
1272 IXGB_BCM8704_USER_DEV3_ADDR);
1273
1274 /* SerDes needs extra delay */
1275 msec_delay(IXGB_SUN_PHY_RESET_DELAY);
1276
1277 return;
1278 }
1279