1 /* $OpenBSD: ixgbe_phy.c,v 1.23 2022/01/09 05:42:56 jsg Exp $ */
2
3 /******************************************************************************
4 SPDX-License-Identifier: BSD-3-Clause
5
6 Copyright (c) 2001-2017, Intel Corporation
7 All rights reserved.
8
9 Redistribution and use in source and binary forms, with or without
10 modification, are permitted provided that the following conditions are met:
11
12 1. Redistributions of source code must retain the above copyright notice,
13 this list of conditions and the following disclaimer.
14
15 2. Redistributions in binary form must reproduce the above copyright
16 notice, this list of conditions and the following disclaimer in the
17 documentation and/or other materials provided with the distribution.
18
19 3. Neither the name of the Intel Corporation nor the names of its
20 contributors may be used to endorse or promote products derived from
21 this software without specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 POSSIBILITY OF SUCH DAMAGE.
34
35 ******************************************************************************/
36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 331224 2018-03-19 20:55:05Z erj $*/
37
38 #include <dev/pci/ixgbe.h>
39 #include <dev/pci/ixgbe_type.h>
40
41 void ixgbe_i2c_start(struct ixgbe_hw *hw);
42 void ixgbe_i2c_stop(struct ixgbe_hw *hw);
43 int32_t ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, uint8_t *data);
44 int32_t ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, uint8_t data);
45 int32_t ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
46 int32_t ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
47 int32_t ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
48 void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl);
49 void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl);
50 int32_t ixgbe_set_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl, bool data);
51 bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl);
52
53 /**
54 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
55 * @hw: pointer to the hardware structure
56 * @byte: byte to send
57 *
58 * Returns an error code on error.
59 */
ixgbe_out_i2c_byte_ack(struct ixgbe_hw * hw,uint8_t byte)60 static int32_t ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, uint8_t byte)
61 {
62 int32_t status;
63
64 status = ixgbe_clock_out_i2c_byte(hw, byte);
65 if (status)
66 return status;
67 return ixgbe_get_i2c_ack(hw);
68 }
69
70 /**
71 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
72 * @hw: pointer to the hardware structure
73 * @byte: pointer to a uint8_t to receive the byte
74 *
75 * Returns an error code on error.
76 */
ixgbe_in_i2c_byte_ack(struct ixgbe_hw * hw,uint8_t * byte)77 static int32_t ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, uint8_t *byte)
78 {
79 int32_t status;
80
81 status = ixgbe_clock_in_i2c_byte(hw, byte);
82 if (status)
83 return status;
84 /* ACK */
85 return ixgbe_clock_out_i2c_bit(hw, FALSE);
86 }
87
88 /**
89 * ixgbe_ones_comp_byte_add - Perform one's complement addition
90 * @add1: addend 1
91 * @add2: addend 2
92 *
93 * Returns one's complement 8-bit sum.
94 */
ixgbe_ones_comp_byte_add(uint8_t add1,uint8_t add2)95 static uint8_t ixgbe_ones_comp_byte_add(uint8_t add1, uint8_t add2)
96 {
97 uint16_t sum = add1 + add2;
98
99 sum = (sum & 0xFF) + (sum >> 8);
100 return sum & 0xFF;
101 }
102
103 /**
104 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
105 * @hw: pointer to the hardware structure
106 * @addr: I2C bus address to read from
107 * @reg: I2C device register to read from
108 * @val: pointer to location to receive read value
109 * @lock: TRUE if to take and release semaphore
110 *
111 * Returns an error code on error.
112 */
ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw * hw,uint8_t addr,uint16_t reg,uint16_t * val,bool lock)113 int32_t ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, uint8_t addr,
114 uint16_t reg, uint16_t *val,
115 bool lock)
116 {
117 uint32_t swfw_mask = hw->phy.phy_semaphore_mask;
118 int max_retry = 3;
119 int retry = 0;
120 uint8_t csum_byte;
121 uint8_t high_bits;
122 uint8_t low_bits;
123 uint8_t reg_high;
124 uint8_t csum;
125
126 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
127 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
128 csum = ~csum;
129 do {
130 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
131 return IXGBE_ERR_SWFW_SYNC;
132 ixgbe_i2c_start(hw);
133 /* Device Address and write indication */
134 if (ixgbe_out_i2c_byte_ack(hw, addr))
135 goto fail;
136 /* Write bits 14:8 */
137 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
138 goto fail;
139 /* Write bits 7:0 */
140 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
141 goto fail;
142 /* Write csum */
143 if (ixgbe_out_i2c_byte_ack(hw, csum))
144 goto fail;
145 /* Re-start condition */
146 ixgbe_i2c_start(hw);
147 /* Device Address and read indication */
148 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
149 goto fail;
150 /* Get upper bits */
151 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
152 goto fail;
153 /* Get low bits */
154 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
155 goto fail;
156 /* Get csum */
157 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
158 goto fail;
159 /* NACK */
160 if (ixgbe_clock_out_i2c_bit(hw, FALSE))
161 goto fail;
162 ixgbe_i2c_stop(hw);
163 if (lock)
164 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
165 *val = (high_bits << 8) | low_bits;
166 return 0;
167
168 fail:
169 ixgbe_i2c_bus_clear(hw);
170 if (lock)
171 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
172 retry++;
173 if (retry < max_retry)
174 DEBUGOUT("I2C byte read combined error - Retrying.\n");
175 else
176 DEBUGOUT("I2C byte read combined error.\n");
177 } while (retry < max_retry);
178
179 return IXGBE_ERR_I2C;
180 }
181
182 /**
183 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
184 * @hw: pointer to the hardware structure
185 * @addr: I2C bus address to read from
186 * @reg: I2C device register to read from
187 * @val: pointer to location to receive read value
188 *
189 * Returns an error code on error.
190 **/
ixgbe_read_i2c_combined_generic(struct ixgbe_hw * hw,uint8_t addr,uint16_t reg,uint16_t * val)191 int32_t ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, uint8_t addr,
192 uint16_t reg, uint16_t *val)
193 {
194 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE);
195 }
196
197 /**
198 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
199 * @hw: pointer to the hardware structure
200 * @addr: I2C bus address to read from
201 * @reg: I2C device register to read from
202 * @val: pointer to location to receive read value
203 *
204 * Returns an error code on error.
205 **/
ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw * hw,uint8_t addr,uint16_t reg,uint16_t * val)206 int32_t ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, uint8_t addr,
207 uint16_t reg, uint16_t *val)
208 {
209 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE);
210 }
211
212
213 /**
214 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
215 * @hw: pointer to the hardware structure
216 * @addr: I2C bus address to write to
217 * @reg: I2C device register to write to
218 * @val: value to write
219 * @lock: TRUE if to take and release semaphore
220 *
221 * Returns an error code on error.
222 */
ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw * hw,uint8_t addr,uint16_t reg,uint16_t val,bool lock)223 int32_t ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, uint8_t addr,
224 uint16_t reg, uint16_t val, bool lock)
225 {
226 uint32_t swfw_mask = hw->phy.phy_semaphore_mask;
227 int max_retry = 1;
228 int retry = 0;
229 uint8_t reg_high;
230 uint8_t csum;
231
232 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
233 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
234 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
235 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
236 csum = ~csum;
237 do {
238 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
239 return IXGBE_ERR_SWFW_SYNC;
240 ixgbe_i2c_start(hw);
241 /* Device Address and write indication */
242 if (ixgbe_out_i2c_byte_ack(hw, addr))
243 goto fail;
244 /* Write bits 14:8 */
245 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
246 goto fail;
247 /* Write bits 7:0 */
248 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
249 goto fail;
250 /* Write data 15:8 */
251 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
252 goto fail;
253 /* Write data 7:0 */
254 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
255 goto fail;
256 /* Write csum */
257 if (ixgbe_out_i2c_byte_ack(hw, csum))
258 goto fail;
259 ixgbe_i2c_stop(hw);
260 if (lock)
261 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
262 return 0;
263
264 fail:
265 ixgbe_i2c_bus_clear(hw);
266 if (lock)
267 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
268 retry++;
269 if (retry < max_retry)
270 DEBUGOUT("I2C byte write combined error - Retrying.\n");
271 else
272 DEBUGOUT("I2C byte write combined error.\n");
273 } while (retry < max_retry);
274
275 return IXGBE_ERR_I2C;
276 }
277
278 /**
279 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
280 * @hw: pointer to the hardware structure
281 * @addr: I2C bus address to write to
282 * @reg: I2C device register to write to
283 * @val: value to write
284 *
285 * Returns an error code on error.
286 **/
ixgbe_write_i2c_combined_generic(struct ixgbe_hw * hw,uint8_t addr,uint16_t reg,uint16_t val)287 int32_t ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
288 uint8_t addr, uint16_t reg, uint16_t val)
289 {
290 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE);
291 }
292
293 /**
294 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
295 * @hw: pointer to the hardware structure
296 * @addr: I2C bus address to write to
297 * @reg: I2C device register to write to
298 * @val: value to write
299 *
300 * Returns an error code on error.
301 **/
302 int32_t
ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw * hw,uint8_t addr,uint16_t reg,uint16_t val)303 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
304 uint8_t addr, uint16_t reg, uint16_t val)
305 {
306 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE);
307 }
308
309 /**
310 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
311 * @hw: pointer to the hardware structure
312 *
313 * Initialize the function pointers.
314 **/
ixgbe_init_phy_ops_generic(struct ixgbe_hw * hw)315 int32_t ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
316 {
317 struct ixgbe_phy_info *phy = &hw->phy;
318
319 DEBUGFUNC("ixgbe_init_phy_ops_generic");
320
321 /* PHY */
322 phy->ops.identify = ixgbe_identify_phy_generic;
323 phy->ops.reset = ixgbe_reset_phy_generic;
324 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
325 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
326 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
327 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
328 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
329 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
330 phy->ops.check_link = NULL;
331 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
332 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
333 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
334 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
335 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
336 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
337 phy->ops.identify_sfp = ixgbe_identify_module_generic;
338 phy->sfp_type = ixgbe_sfp_type_unknown;
339 phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;
340 phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;
341 phy->ops.read_i2c_combined_unlocked =
342 ixgbe_read_i2c_combined_generic_unlocked;
343 phy->ops.write_i2c_combined_unlocked =
344 ixgbe_write_i2c_combined_generic_unlocked;
345 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
346 phy->ops.write_i2c_byte_unlocked =
347 ixgbe_write_i2c_byte_generic_unlocked;
348 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
349 return IXGBE_SUCCESS;
350 }
351
352 /**
353 * ixgbe_probe_phy - Probe a single address for a PHY
354 * @hw: pointer to hardware structure
355 * @phy_addr: PHY address to probe
356 *
357 * Returns TRUE if PHY found
358 */
ixgbe_probe_phy(struct ixgbe_hw * hw,uint16_t phy_addr)359 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, uint16_t phy_addr)
360 {
361 uint16_t ext_ability = 0;
362
363 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
364 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
365 phy_addr);
366 return FALSE;
367 }
368
369 if (ixgbe_get_phy_id(hw))
370 return FALSE;
371
372 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
373
374 if (hw->phy.type == ixgbe_phy_unknown) {
375 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
376 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
377 if (ext_ability &
378 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
379 IXGBE_MDIO_PHY_1000BASET_ABILITY))
380 hw->phy.type = ixgbe_phy_cu_unknown;
381 else
382 hw->phy.type = ixgbe_phy_generic;
383 }
384
385 return TRUE;
386 }
387
388 /**
389 * ixgbe_identify_phy_generic - Get physical layer module
390 * @hw: pointer to hardware structure
391 *
392 * Determines the physical layer module found on the current adapter.
393 **/
ixgbe_identify_phy_generic(struct ixgbe_hw * hw)394 int32_t ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
395 {
396 int32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
397 uint16_t phy_addr;
398
399 DEBUGFUNC("ixgbe_identify_phy_generic");
400
401 if (!hw->phy.phy_semaphore_mask) {
402 if (hw->bus.lan_id)
403 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
404 else
405 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
406 }
407
408 if (hw->phy.type != ixgbe_phy_unknown)
409 return IXGBE_SUCCESS;
410
411 if (hw->phy.nw_mng_if_sel) {
412 phy_addr = (hw->phy.nw_mng_if_sel &
413 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
414 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
415 if (ixgbe_probe_phy(hw, phy_addr))
416 return IXGBE_SUCCESS;
417 else
418 return IXGBE_ERR_PHY_ADDR_INVALID;
419 }
420
421 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
422 if (ixgbe_probe_phy(hw, phy_addr)) {
423 status = IXGBE_SUCCESS;
424 break;
425 }
426 }
427
428 /* Certain media types do not have a phy so an address will not
429 * be found and the code will take this path. Caller has to
430 * decide if it is an error or not.
431 */
432 if (status != IXGBE_SUCCESS)
433 hw->phy.addr = 0;
434
435 return status;
436 }
437
438 /**
439 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
440 * @hw: pointer to the hardware structure
441 *
442 * This function checks the MMNGC.MNG_VETO bit to see if there are
443 * any constraints on link from manageability. For MAC's that don't
444 * have this bit just return faluse since the link can not be blocked
445 * via this method.
446 **/
ixgbe_check_reset_blocked(struct ixgbe_hw * hw)447 int32_t ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
448 {
449 uint32_t mmngc;
450
451 DEBUGFUNC("ixgbe_check_reset_blocked");
452
453 /* If we don't have this bit, it can't be blocking */
454 if (hw->mac.type == ixgbe_mac_82598EB)
455 return FALSE;
456
457 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
458 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
459 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
460 "MNG_VETO bit detected.\n");
461 return TRUE;
462 }
463
464 return FALSE;
465 }
466
467 /**
468 * ixgbe_validate_phy_addr - Determines phy address is valid
469 * @hw: pointer to hardware structure
470 * @phy_addr: PHY address
471 *
472 **/
ixgbe_validate_phy_addr(struct ixgbe_hw * hw,uint32_t phy_addr)473 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, uint32_t phy_addr)
474 {
475 uint16_t phy_id = 0;
476 bool valid = FALSE;
477
478 DEBUGFUNC("ixgbe_validate_phy_addr");
479
480 hw->phy.addr = phy_addr;
481 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
482 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
483
484 if (phy_id != 0xFFFF && phy_id != 0x0)
485 valid = TRUE;
486
487 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
488
489 return valid;
490 }
491
492 /**
493 * ixgbe_get_phy_id - Get the phy type
494 * @hw: pointer to hardware structure
495 *
496 **/
ixgbe_get_phy_id(struct ixgbe_hw * hw)497 int32_t ixgbe_get_phy_id(struct ixgbe_hw *hw)
498 {
499 uint32_t status;
500 uint16_t phy_id_high = 0;
501 uint16_t phy_id_low = 0;
502
503 DEBUGFUNC("ixgbe_get_phy_id");
504
505 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
506 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
507 &phy_id_high);
508
509 if (status == IXGBE_SUCCESS) {
510 hw->phy.id = (uint32_t)(phy_id_high << 16);
511 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
512 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
513 &phy_id_low);
514 hw->phy.id |= (uint32_t)(phy_id_low & IXGBE_PHY_REVISION_MASK);
515 hw->phy.revision =
516 (uint32_t)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
517 }
518 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
519 phy_id_high, phy_id_low);
520
521 return status;
522 }
523
524 /**
525 * ixgbe_get_phy_type_from_id - Get the phy type
526 * @phy_id: PHY ID information
527 *
528 **/
ixgbe_get_phy_type_from_id(uint32_t phy_id)529 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(uint32_t phy_id)
530 {
531 enum ixgbe_phy_type phy_type;
532
533 DEBUGFUNC("ixgbe_get_phy_type_from_id");
534
535 switch (phy_id) {
536 case TN1010_PHY_ID:
537 phy_type = ixgbe_phy_tn;
538 break;
539 case X550_PHY_ID2:
540 case X550_PHY_ID3:
541 case X540_PHY_ID:
542 phy_type = ixgbe_phy_aq;
543 break;
544 case QT2022_PHY_ID:
545 phy_type = ixgbe_phy_qt;
546 break;
547 case ATH_PHY_ID:
548 phy_type = ixgbe_phy_nl;
549 break;
550 case X557_PHY_ID:
551 case X557_PHY_ID2:
552 phy_type = ixgbe_phy_x550em_ext_t;
553 break;
554 case IXGBE_M88E1500_E_PHY_ID:
555 case IXGBE_M88E1543_E_PHY_ID:
556 phy_type = ixgbe_phy_ext_1g_t;
557 break;
558 default:
559 phy_type = ixgbe_phy_unknown;
560 break;
561 }
562 return phy_type;
563 }
564
565 /**
566 * ixgbe_reset_phy_generic - Performs a PHY reset
567 * @hw: pointer to hardware structure
568 **/
ixgbe_reset_phy_generic(struct ixgbe_hw * hw)569 int32_t ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
570 {
571 uint32_t i;
572 uint16_t ctrl = 0;
573 int32_t status = IXGBE_SUCCESS;
574
575 DEBUGFUNC("ixgbe_reset_phy_generic");
576
577 if (hw->phy.type == ixgbe_phy_unknown)
578 status = ixgbe_identify_phy_generic(hw);
579
580 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
581 goto out;
582
583 /* Don't reset PHY if it's shut down due to overtemp. */
584 if (!hw->phy.reset_if_overtemp &&
585 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
586 goto out;
587
588 /* Blocked by MNG FW so bail */
589 if (ixgbe_check_reset_blocked(hw))
590 goto out;
591
592 /*
593 * Perform soft PHY reset to the PHY_XS.
594 * This will cause a soft reset to the PHY
595 */
596 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
597 IXGBE_MDIO_PHY_XS_DEV_TYPE,
598 IXGBE_MDIO_PHY_XS_RESET);
599
600 /*
601 * Poll for reset bit to self-clear indicating reset is complete.
602 * Some PHYs could take up to 3 seconds to complete and need about
603 * 1.7 usec delay after the reset is complete.
604 */
605 for (i = 0; i < 30; i++) {
606 msec_delay(100);
607 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
608 status = hw->phy.ops.read_reg(hw,
609 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
610 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
611 &ctrl);
612 if (status != IXGBE_SUCCESS)
613 return status;
614
615 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
616 usec_delay(2);
617 break;
618 }
619 } else {
620 status = hw->phy.ops.read_reg(hw,
621 IXGBE_MDIO_PHY_XS_CONTROL,
622 IXGBE_MDIO_PHY_XS_DEV_TYPE,
623 &ctrl);
624 if (status != IXGBE_SUCCESS)
625 return status;
626
627 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
628 usec_delay(2);
629 break;
630 }
631 }
632 }
633
634 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
635 status = IXGBE_ERR_RESET_FAILED;
636 ERROR_REPORT1(IXGBE_ERROR_POLLING,
637 "PHY reset polling failed to complete.\n");
638 }
639
640 out:
641 return status;
642 }
643
644 /**
645 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
646 * the SWFW lock
647 * @hw: pointer to hardware structure
648 * @reg_addr: 32 bit address of PHY register to read
649 * @device_type: 5 bit device type
650 * @phy_data: Pointer to read data from PHY register
651 **/
ixgbe_read_phy_reg_mdi(struct ixgbe_hw * hw,uint32_t reg_addr,uint32_t device_type,uint16_t * phy_data)652 int32_t ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, uint32_t reg_addr,
653 uint32_t device_type, uint16_t *phy_data)
654 {
655 uint32_t i, data, command;
656
657 /* Setup and write the address cycle command */
658 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
659 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
660 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
661 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
662
663 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
664
665 /*
666 * Check every 10 usec to see if the address cycle completed.
667 * The MDI Command bit will clear when the operation is
668 * complete
669 */
670 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
671 usec_delay(10);
672
673 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
674 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
675 break;
676 }
677
678
679 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
680 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
681 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
682 return IXGBE_ERR_PHY;
683 }
684
685 /*
686 * Address cycle complete, setup and write the read
687 * command
688 */
689 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
690 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
691 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
692 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
693
694 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
695
696 /*
697 * Check every 10 usec to see if the address cycle
698 * completed. The MDI Command bit will clear when the
699 * operation is complete
700 */
701 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
702 usec_delay(10);
703
704 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
705 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
706 break;
707 }
708
709 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
710 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
711 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
712 return IXGBE_ERR_PHY;
713 }
714
715 /*
716 * Read operation is complete. Get the data
717 * from MSRWD
718 */
719 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
720 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
721 *phy_data = (uint16_t)(data);
722
723 return IXGBE_SUCCESS;
724 }
725
726 /**
727 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
728 * using the SWFW lock - this function is needed in most cases
729 * @hw: pointer to hardware structure
730 * @reg_addr: 32 bit address of PHY register to read
731 * @device_type: 5 bit device type
732 * @phy_data: Pointer to read data from PHY register
733 **/
ixgbe_read_phy_reg_generic(struct ixgbe_hw * hw,uint32_t reg_addr,uint32_t device_type,uint16_t * phy_data)734 int32_t ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr,
735 uint32_t device_type, uint16_t *phy_data)
736 {
737 int32_t status;
738 uint32_t gssr = hw->phy.phy_semaphore_mask;
739
740 DEBUGFUNC("ixgbe_read_phy_reg_generic");
741
742 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
743 return IXGBE_ERR_SWFW_SYNC;
744
745 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
746
747 hw->mac.ops.release_swfw_sync(hw, gssr);
748
749 return status;
750 }
751
752 /**
753 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
754 * without SWFW lock
755 * @hw: pointer to hardware structure
756 * @reg_addr: 32 bit PHY register to write
757 * @device_type: 5 bit device type
758 * @phy_data: Data to write to the PHY register
759 **/
ixgbe_write_phy_reg_mdi(struct ixgbe_hw * hw,uint32_t reg_addr,uint32_t device_type,uint16_t phy_data)760 int32_t ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, uint32_t reg_addr,
761 uint32_t device_type, uint16_t phy_data)
762 {
763 uint32_t i, command;
764
765 /* Put the data in the MDI single read and write data register*/
766 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (uint32_t)phy_data);
767
768 /* Setup and write the address cycle command */
769 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
770 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
771 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
772 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
773
774 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
775
776 /*
777 * Check every 10 usec to see if the address cycle completed.
778 * The MDI Command bit will clear when the operation is
779 * complete
780 */
781 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
782 usec_delay(10);
783
784 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
785 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
786 break;
787 }
788
789 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
790 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
791 return IXGBE_ERR_PHY;
792 }
793
794 /*
795 * Address cycle complete, setup and write the write
796 * command
797 */
798 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
799 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
800 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
801 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
802
803 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
804
805 /*
806 * Check every 10 usec to see if the address cycle
807 * completed. The MDI Command bit will clear when the
808 * operation is complete
809 */
810 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
811 usec_delay(10);
812
813 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
814 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
815 break;
816 }
817
818 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
819 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
820 return IXGBE_ERR_PHY;
821 }
822
823 return IXGBE_SUCCESS;
824 }
825
826 /**
827 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
828 * using SWFW lock- this function is needed in most cases
829 * @hw: pointer to hardware structure
830 * @reg_addr: 32 bit PHY register to write
831 * @device_type: 5 bit device type
832 * @phy_data: Data to write to the PHY register
833 **/
ixgbe_write_phy_reg_generic(struct ixgbe_hw * hw,uint32_t reg_addr,uint32_t device_type,uint16_t phy_data)834 int32_t ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr,
835 uint32_t device_type, uint16_t phy_data)
836 {
837 int32_t status;
838 uint32_t gssr = hw->phy.phy_semaphore_mask;
839
840 DEBUGFUNC("ixgbe_write_phy_reg_generic");
841
842 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
843 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
844 phy_data);
845 hw->mac.ops.release_swfw_sync(hw, gssr);
846 } else {
847 status = IXGBE_ERR_SWFW_SYNC;
848 }
849
850 return status;
851 }
852
853 /**
854 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
855 * @hw: pointer to hardware structure
856 *
857 * Restart auto-negotiation and PHY and waits for completion.
858 **/
ixgbe_setup_phy_link_generic(struct ixgbe_hw * hw)859 int32_t ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
860 {
861 int32_t status = IXGBE_SUCCESS;
862 uint16_t autoneg_reg = IXGBE_MII_AUTONEG_REG;
863 bool autoneg = FALSE;
864 ixgbe_link_speed speed;
865
866 DEBUGFUNC("ixgbe_setup_phy_link_generic");
867
868 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
869
870 /* Set or unset auto-negotiation 10G advertisement */
871 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
872 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
873 &autoneg_reg);
874
875 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
876 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
877 (speed & IXGBE_LINK_SPEED_10GB_FULL))
878 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
879
880 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
881 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
882 autoneg_reg);
883
884 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
885 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
886 &autoneg_reg);
887
888 if (hw->mac.type == ixgbe_mac_X550) {
889 /* Set or unset auto-negotiation 5G advertisement */
890 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
891 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
892 (speed & IXGBE_LINK_SPEED_5GB_FULL))
893 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
894
895 /* Set or unset auto-negotiation 2.5G advertisement */
896 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
897 if ((hw->phy.autoneg_advertised &
898 IXGBE_LINK_SPEED_2_5GB_FULL) &&
899 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
900 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
901 }
902
903 /* Set or unset auto-negotiation 1G advertisement */
904 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
905 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
906 (speed & IXGBE_LINK_SPEED_1GB_FULL))
907 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
908
909 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
910 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
911 autoneg_reg);
912
913 /* Set or unset auto-negotiation 100M advertisement */
914 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
915 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
916 &autoneg_reg);
917
918 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
919 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
920 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
921 (speed & IXGBE_LINK_SPEED_100_FULL))
922 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
923
924 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
925 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
926 autoneg_reg);
927
928 /* Blocked by MNG FW so don't reset PHY */
929 if (ixgbe_check_reset_blocked(hw))
930 return status;
931
932 /* Restart PHY auto-negotiation. */
933 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
934 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
935
936 autoneg_reg |= IXGBE_MII_RESTART;
937
938 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
939 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
940
941 return status;
942 }
943
944 /**
945 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
946 * @hw: pointer to hardware structure
947 * @speed: new link speed
948 * @autoneg_wait_to_complete: unused
949 **/
ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)950 int32_t ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
951 ixgbe_link_speed speed,
952 bool autoneg_wait_to_complete)
953 {
954 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
955
956 /*
957 * Clear autoneg_advertised and set new values based on input link
958 * speed.
959 */
960 hw->phy.autoneg_advertised = 0;
961
962 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
963 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
964
965 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
966 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
967
968 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
969 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
970
971 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
972 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
973
974 if (speed & IXGBE_LINK_SPEED_100_FULL)
975 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
976
977 if (speed & IXGBE_LINK_SPEED_10_FULL)
978 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
979
980 /* Setup link based on the new speed settings */
981 hw->phy.ops.setup_link(hw);
982
983 return IXGBE_SUCCESS;
984 }
985
986 /**
987 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
988 * @hw: pointer to hardware structure
989 *
990 * Determines the supported link capabilities by reading the PHY auto
991 * negotiation register.
992 **/
ixgbe_get_copper_speeds_supported(struct ixgbe_hw * hw)993 int32_t ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
994 {
995 int32_t status;
996 uint16_t speed_ability;
997
998 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
999 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1000 &speed_ability);
1001 if (status)
1002 return status;
1003
1004 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
1005 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
1006 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
1007 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
1008 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
1009 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
1010
1011 switch (hw->mac.type) {
1012 case ixgbe_mac_X550:
1013 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
1014 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
1015 break;
1016 case ixgbe_mac_X550EM_x:
1017 case ixgbe_mac_X550EM_a:
1018 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
1019 break;
1020 default:
1021 break;
1022 }
1023
1024 return status;
1025 }
1026
1027 /**
1028 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1029 * @hw: pointer to hardware structure
1030 * @speed: pointer to link speed
1031 * @autoneg: boolean auto-negotiation value
1032 **/
ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * autoneg)1033 int32_t ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1034 ixgbe_link_speed *speed,
1035 bool *autoneg)
1036 {
1037 int32_t status = IXGBE_SUCCESS;
1038
1039 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
1040
1041 *autoneg = TRUE;
1042 if (!hw->phy.speeds_supported)
1043 status = ixgbe_get_copper_speeds_supported(hw);
1044
1045 *speed = hw->phy.speeds_supported;
1046 return status;
1047 }
1048
1049 /**
1050 * ixgbe_check_phy_link_tnx - Determine link and speed status
1051 * @hw: pointer to hardware structure
1052 * @speed: current link speed
1053 * @link_up: TRUE is link is up, FALSE otherwise
1054 *
1055 * Reads the VS1 register to determine if link is up and the current speed for
1056 * the PHY.
1057 **/
ixgbe_check_phy_link_tnx(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up)1058 int32_t ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1059 bool *link_up)
1060 {
1061 int32_t status = IXGBE_SUCCESS;
1062 uint32_t time_out;
1063 uint32_t max_time_out = 10;
1064 uint16_t phy_link = 0;
1065 uint16_t phy_speed = 0;
1066 uint16_t phy_data = 0;
1067
1068 DEBUGFUNC("ixgbe_check_phy_link_tnx");
1069
1070 /* Initialize speed and link to default case */
1071 *link_up = FALSE;
1072 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1073
1074 /*
1075 * Check current speed and link status of the PHY register.
1076 * This is a vendor specific register and may have to
1077 * be changed for other copper PHYs.
1078 */
1079 for (time_out = 0; time_out < max_time_out; time_out++) {
1080 usec_delay(10);
1081 status = hw->phy.ops.read_reg(hw,
1082 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1083 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1084 &phy_data);
1085 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1086 phy_speed = phy_data &
1087 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1088 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1089 *link_up = TRUE;
1090 if (phy_speed ==
1091 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1092 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1093 break;
1094 }
1095 }
1096
1097 return status;
1098 }
1099
1100 /**
1101 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1102 * @hw: pointer to hardware structure
1103 *
1104 * Restart auto-negotiation and PHY and waits for completion.
1105 **/
ixgbe_setup_phy_link_tnx(struct ixgbe_hw * hw)1106 int32_t ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1107 {
1108 int32_t status = IXGBE_SUCCESS;
1109 uint16_t autoneg_reg = IXGBE_MII_AUTONEG_REG;
1110 bool autoneg = FALSE;
1111 ixgbe_link_speed speed;
1112
1113 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1114
1115 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1116
1117 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1118 /* Set or unset auto-negotiation 10G advertisement */
1119 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1120 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1121 &autoneg_reg);
1122
1123 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1124 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1125 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1126
1127 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1128 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1129 autoneg_reg);
1130 }
1131
1132 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1133 /* Set or unset auto-negotiation 1G advertisement */
1134 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1135 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1136 &autoneg_reg);
1137
1138 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1139 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1140 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1141
1142 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1143 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1144 autoneg_reg);
1145 }
1146
1147 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1148 /* Set or unset auto-negotiation 100M advertisement */
1149 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1150 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1151 &autoneg_reg);
1152
1153 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1154 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1155 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1156
1157 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1158 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1159 autoneg_reg);
1160 }
1161
1162 /* Blocked by MNG FW so don't reset PHY */
1163 if (ixgbe_check_reset_blocked(hw))
1164 return status;
1165
1166 /* Restart PHY auto-negotiation. */
1167 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1168 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1169
1170 autoneg_reg |= IXGBE_MII_RESTART;
1171
1172 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1173 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1174
1175 return status;
1176 }
1177
1178 /**
1179 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1180 * @hw: pointer to hardware structure
1181 * @firmware_version: pointer to the PHY Firmware Version
1182 **/
ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw * hw,uint16_t * firmware_version)1183 int32_t ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1184 uint16_t *firmware_version)
1185 {
1186 int32_t status;
1187
1188 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1189
1190 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1191 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1192 firmware_version);
1193
1194 return status;
1195 }
1196
1197 /**
1198 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1199 * @hw: pointer to hardware structure
1200 * @firmware_version: pointer to the PHY Firmware Version
1201 **/
ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw * hw,uint16_t * firmware_version)1202 int32_t ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1203 uint16_t *firmware_version)
1204 {
1205 int32_t status;
1206
1207 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1208
1209 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1210 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1211 firmware_version);
1212
1213 return status;
1214 }
1215
1216 /**
1217 * ixgbe_reset_phy_nl - Performs a PHY reset
1218 * @hw: pointer to hardware structure
1219 **/
ixgbe_reset_phy_nl(struct ixgbe_hw * hw)1220 int32_t ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1221 {
1222 uint16_t phy_offset, control, eword, edata, block_crc;
1223 bool end_data = FALSE;
1224 uint16_t list_offset, data_offset;
1225 uint16_t phy_data = 0;
1226 int32_t ret_val = IXGBE_SUCCESS;
1227 uint32_t i;
1228
1229 DEBUGFUNC("ixgbe_reset_phy_nl");
1230
1231 /* Blocked by MNG FW so bail */
1232 if (ixgbe_check_reset_blocked(hw))
1233 goto out;
1234
1235 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1236 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1237
1238 /* reset the PHY and poll for completion */
1239 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1240 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1241 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1242
1243 for (i = 0; i < 100; i++) {
1244 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1245 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1246 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1247 break;
1248 msec_delay(10);
1249 }
1250
1251 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1252 DEBUGOUT("PHY reset did not complete.\n");
1253 ret_val = IXGBE_ERR_PHY;
1254 goto out;
1255 }
1256
1257 /* Get init offsets */
1258 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1259 &data_offset);
1260 if (ret_val != IXGBE_SUCCESS)
1261 goto out;
1262
1263 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1264 data_offset++;
1265 while (!end_data) {
1266 /*
1267 * Read control word from PHY init contents offset
1268 */
1269 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1270 if (ret_val)
1271 goto err_eeprom;
1272 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1273 IXGBE_CONTROL_SHIFT_NL;
1274 edata = eword & IXGBE_DATA_MASK_NL;
1275 switch (control) {
1276 case IXGBE_DELAY_NL:
1277 data_offset++;
1278 DEBUGOUT1("DELAY: %d MS\n", edata);
1279 msec_delay(edata);
1280 break;
1281 case IXGBE_DATA_NL:
1282 DEBUGOUT("DATA:\n");
1283 data_offset++;
1284 ret_val = hw->eeprom.ops.read(hw, data_offset,
1285 &phy_offset);
1286 if (ret_val)
1287 goto err_eeprom;
1288 data_offset++;
1289 for (i = 0; i < edata; i++) {
1290 ret_val = hw->eeprom.ops.read(hw, data_offset,
1291 &eword);
1292 if (ret_val)
1293 goto err_eeprom;
1294 hw->phy.ops.write_reg(hw, phy_offset,
1295 IXGBE_TWINAX_DEV, eword);
1296 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1297 phy_offset);
1298 data_offset++;
1299 phy_offset++;
1300 }
1301 break;
1302 case IXGBE_CONTROL_NL:
1303 data_offset++;
1304 DEBUGOUT("CONTROL:\n");
1305 if (edata == IXGBE_CONTROL_EOL_NL) {
1306 DEBUGOUT("EOL\n");
1307 end_data = TRUE;
1308 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1309 DEBUGOUT("SOL\n");
1310 } else {
1311 DEBUGOUT("Bad control value\n");
1312 ret_val = IXGBE_ERR_PHY;
1313 goto out;
1314 }
1315 break;
1316 default:
1317 DEBUGOUT("Bad control type\n");
1318 ret_val = IXGBE_ERR_PHY;
1319 goto out;
1320 }
1321 }
1322
1323 out:
1324 return ret_val;
1325
1326 err_eeprom:
1327 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1328 "eeprom read at offset %d failed", data_offset);
1329 return IXGBE_ERR_PHY;
1330 }
1331
1332 bool
ixgbe_is_sfp(struct ixgbe_hw * hw)1333 ixgbe_is_sfp(struct ixgbe_hw *hw)
1334 {
1335 switch (hw->phy.type) {
1336 case ixgbe_phy_sfp_avago:
1337 case ixgbe_phy_sfp_ftl:
1338 case ixgbe_phy_sfp_intel:
1339 case ixgbe_phy_sfp_unknown:
1340 case ixgbe_phy_sfp_passive_tyco:
1341 case ixgbe_phy_sfp_passive_unknown:
1342 case ixgbe_phy_qsfp_passive_unknown:
1343 case ixgbe_phy_qsfp_active_unknown:
1344 case ixgbe_phy_qsfp_intel:
1345 case ixgbe_phy_qsfp_unknown:
1346 return TRUE;
1347 default:
1348 return FALSE;
1349 }
1350 }
1351
1352 /**
1353 * ixgbe_identify_module_generic - Identifies module type
1354 * @hw: pointer to hardware structure
1355 *
1356 * Determines HW type and calls appropriate function.
1357 **/
ixgbe_identify_module_generic(struct ixgbe_hw * hw)1358 int32_t ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1359 {
1360 int32_t status = IXGBE_ERR_SFP_NOT_PRESENT;
1361
1362 DEBUGFUNC("ixgbe_identify_module_generic");
1363
1364 switch (hw->mac.ops.get_media_type(hw)) {
1365 case ixgbe_media_type_fiber:
1366 status = ixgbe_identify_sfp_module_generic(hw);
1367 break;
1368
1369 case ixgbe_media_type_fiber_qsfp:
1370 status = ixgbe_identify_qsfp_module_generic(hw);
1371 break;
1372
1373 default:
1374 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1375 status = IXGBE_ERR_SFP_NOT_PRESENT;
1376 break;
1377 }
1378
1379 return status;
1380 }
1381
1382 /**
1383 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1384 * @hw: pointer to hardware structure
1385 *
1386 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1387 **/
ixgbe_identify_sfp_module_generic(struct ixgbe_hw * hw)1388 int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1389 {
1390 int32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
1391 uint32_t vendor_oui = 0;
1392 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1393 uint8_t identifier = 0;
1394 uint8_t comp_codes_1g = 0;
1395 uint8_t comp_codes_10g = 0;
1396 uint8_t oui_bytes[3] = {0, 0, 0};
1397 uint8_t cable_tech = 0;
1398 uint8_t cable_spec = 0;
1399
1400 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1401
1402 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1403 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1404 status = IXGBE_ERR_SFP_NOT_PRESENT;
1405 goto out;
1406 }
1407
1408 /* LAN ID is needed for I2C access */
1409 hw->mac.ops.set_lan_id(hw);
1410
1411 status = hw->phy.ops.read_i2c_eeprom(hw,
1412 IXGBE_SFF_IDENTIFIER,
1413 &identifier);
1414
1415 if (status != IXGBE_SUCCESS)
1416 goto err_read_i2c_eeprom;
1417
1418 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1419 hw->phy.type = ixgbe_phy_sfp_unsupported;
1420 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1421 } else {
1422 status = hw->phy.ops.read_i2c_eeprom(hw,
1423 IXGBE_SFF_1GBE_COMP_CODES,
1424 &comp_codes_1g);
1425
1426 if (status != IXGBE_SUCCESS)
1427 goto err_read_i2c_eeprom;
1428
1429 status = hw->phy.ops.read_i2c_eeprom(hw,
1430 IXGBE_SFF_10GBE_COMP_CODES,
1431 &comp_codes_10g);
1432
1433 if (status != IXGBE_SUCCESS)
1434 goto err_read_i2c_eeprom;
1435 status = hw->phy.ops.read_i2c_eeprom(hw,
1436 IXGBE_SFF_CABLE_TECHNOLOGY,
1437 &cable_tech);
1438
1439 if (status != IXGBE_SUCCESS)
1440 goto err_read_i2c_eeprom;
1441
1442 /* ID Module
1443 * =========
1444 * 0 SFP_DA_CU
1445 * 1 SFP_SR
1446 * 2 SFP_LR
1447 * 3 SFP_DA_CORE0 - 82599-specific
1448 * 4 SFP_DA_CORE1 - 82599-specific
1449 * 5 SFP_SR/LR_CORE0 - 82599-specific
1450 * 6 SFP_SR/LR_CORE1 - 82599-specific
1451 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1452 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1453 * 9 SFP_1g_cu_CORE0 - 82599-specific
1454 * 10 SFP_1g_cu_CORE1 - 82599-specific
1455 * 11 SFP_1g_sx_CORE0 - 82599-specific
1456 * 12 SFP_1g_sx_CORE1 - 82599-specific
1457 */
1458 if (hw->mac.type == ixgbe_mac_82598EB) {
1459 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1460 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1461 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1462 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1463 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1464 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1465 else if (comp_codes_10g & IXGBE_SFF_DA_BAD_HP_CABLE)
1466 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1467 else
1468 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1469 } else {
1470 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1471 if (hw->bus.lan_id == 0)
1472 hw->phy.sfp_type =
1473 ixgbe_sfp_type_da_cu_core0;
1474 else
1475 hw->phy.sfp_type =
1476 ixgbe_sfp_type_da_cu_core1;
1477 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1478 hw->phy.ops.read_i2c_eeprom(
1479 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1480 &cable_spec);
1481 if (cable_spec &
1482 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1483 if (hw->bus.lan_id == 0)
1484 hw->phy.sfp_type =
1485 ixgbe_sfp_type_da_act_lmt_core0;
1486 else
1487 hw->phy.sfp_type =
1488 ixgbe_sfp_type_da_act_lmt_core1;
1489 } else {
1490 hw->phy.sfp_type =
1491 ixgbe_sfp_type_unknown;
1492 }
1493 } else if (comp_codes_10g &
1494 (IXGBE_SFF_10GBASESR_CAPABLE |
1495 IXGBE_SFF_10GBASELR_CAPABLE)) {
1496 if (hw->bus.lan_id == 0)
1497 hw->phy.sfp_type =
1498 ixgbe_sfp_type_srlr_core0;
1499 else
1500 hw->phy.sfp_type =
1501 ixgbe_sfp_type_srlr_core1;
1502 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1503 if (hw->bus.lan_id == 0)
1504 hw->phy.sfp_type =
1505 ixgbe_sfp_type_1g_cu_core0;
1506 else
1507 hw->phy.sfp_type =
1508 ixgbe_sfp_type_1g_cu_core1;
1509 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1510 if (hw->bus.lan_id == 0)
1511 hw->phy.sfp_type =
1512 ixgbe_sfp_type_1g_sx_core0;
1513 else
1514 hw->phy.sfp_type =
1515 ixgbe_sfp_type_1g_sx_core1;
1516 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1517 if (hw->bus.lan_id == 0)
1518 hw->phy.sfp_type =
1519 ixgbe_sfp_type_1g_lx_core0;
1520 else
1521 hw->phy.sfp_type =
1522 ixgbe_sfp_type_1g_lx_core1;
1523 } else {
1524 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1525 }
1526 }
1527
1528 if (hw->phy.sfp_type != stored_sfp_type)
1529 hw->phy.sfp_setup_needed = TRUE;
1530
1531 /* Determine if the SFP+ PHY is dual speed or not. */
1532 hw->phy.multispeed_fiber = FALSE;
1533 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1534 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1535 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1536 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1537 hw->phy.multispeed_fiber = TRUE;
1538
1539 /* Determine PHY vendor */
1540 if (hw->phy.type != ixgbe_phy_nl) {
1541 hw->phy.id = identifier;
1542 status = hw->phy.ops.read_i2c_eeprom(hw,
1543 IXGBE_SFF_VENDOR_OUI_BYTE0,
1544 &oui_bytes[0]);
1545
1546 if (status != IXGBE_SUCCESS)
1547 goto err_read_i2c_eeprom;
1548
1549 status = hw->phy.ops.read_i2c_eeprom(hw,
1550 IXGBE_SFF_VENDOR_OUI_BYTE1,
1551 &oui_bytes[1]);
1552
1553 if (status != IXGBE_SUCCESS)
1554 goto err_read_i2c_eeprom;
1555
1556 status = hw->phy.ops.read_i2c_eeprom(hw,
1557 IXGBE_SFF_VENDOR_OUI_BYTE2,
1558 &oui_bytes[2]);
1559
1560 if (status != IXGBE_SUCCESS)
1561 goto err_read_i2c_eeprom;
1562
1563 vendor_oui =
1564 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1565 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1566 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1567
1568 switch (vendor_oui) {
1569 case IXGBE_SFF_VENDOR_OUI_TYCO:
1570 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1571 hw->phy.type =
1572 ixgbe_phy_sfp_passive_tyco;
1573 break;
1574 case IXGBE_SFF_VENDOR_OUI_FTL:
1575 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1576 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1577 else
1578 hw->phy.type = ixgbe_phy_sfp_ftl;
1579 break;
1580 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1581 hw->phy.type = ixgbe_phy_sfp_avago;
1582 break;
1583 case IXGBE_SFF_VENDOR_OUI_INTEL:
1584 hw->phy.type = ixgbe_phy_sfp_intel;
1585 break;
1586 default:
1587 hw->phy.type = ixgbe_phy_sfp_unknown;
1588 break;
1589 }
1590 }
1591
1592 /* Allow any DA cable vendor */
1593 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1594 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1595 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1596 hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1597 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1598 hw->phy.type = ixgbe_phy_sfp_active_unknown;
1599 status = IXGBE_SUCCESS;
1600 goto out;
1601 }
1602
1603 /* Verify supported 1G SFP modules */
1604 if (comp_codes_10g == 0 &&
1605 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1606 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1607 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1608 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1609 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1610 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1611 hw->phy.type = ixgbe_phy_sfp_unsupported;
1612 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1613 goto out;
1614 }
1615
1616 /*
1617 * We do not limit the definition of "supported SFP modules"
1618 * to the vendor/make whitelist.
1619 */
1620 status = IXGBE_SUCCESS;
1621 }
1622
1623 out:
1624 return status;
1625
1626 err_read_i2c_eeprom:
1627 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1628 if (hw->phy.type != ixgbe_phy_nl) {
1629 hw->phy.id = 0;
1630 hw->phy.type = ixgbe_phy_unknown;
1631 }
1632 return IXGBE_ERR_SFP_NOT_PRESENT;
1633 }
1634
1635 /**
1636 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1637 * @hw: pointer to hardware structure
1638 *
1639 * Determines physical layer capabilities of the current SFP.
1640 */
ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw * hw)1641 uint64_t ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1642 {
1643 uint64_t physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1644 uint8_t comp_codes_10g = 0;
1645 uint8_t comp_codes_1g = 0;
1646
1647 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1648
1649 hw->phy.ops.identify_sfp(hw);
1650 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1651 return physical_layer;
1652
1653 switch (hw->phy.type) {
1654 case ixgbe_phy_sfp_passive_tyco:
1655 case ixgbe_phy_sfp_passive_unknown:
1656 case ixgbe_phy_qsfp_passive_unknown:
1657 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1658 break;
1659 case ixgbe_phy_sfp_ftl_active:
1660 case ixgbe_phy_sfp_active_unknown:
1661 case ixgbe_phy_qsfp_active_unknown:
1662 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1663 break;
1664 case ixgbe_phy_sfp_avago:
1665 case ixgbe_phy_sfp_ftl:
1666 case ixgbe_phy_sfp_intel:
1667 case ixgbe_phy_sfp_unknown:
1668 hw->phy.ops.read_i2c_eeprom(hw,
1669 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1670 hw->phy.ops.read_i2c_eeprom(hw,
1671 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1672 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1673 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1674 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1675 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1676 else if (comp_codes_10g &
1677 (IXGBE_SFF_DA_PASSIVE_CABLE | IXGBE_SFF_DA_BAD_HP_CABLE))
1678 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1679 else if (comp_codes_10g & IXGBE_SFF_DA_ACTIVE_CABLE)
1680 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1681 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1682 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1683 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1684 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1685 else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE)
1686 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_LX;
1687 break;
1688 case ixgbe_phy_qsfp_intel:
1689 case ixgbe_phy_qsfp_unknown:
1690 hw->phy.ops.read_i2c_eeprom(hw,
1691 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1692 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1693 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1694 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1695 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1696 break;
1697 default:
1698 break;
1699 }
1700
1701 return physical_layer;
1702 }
1703
1704 /**
1705 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1706 * @hw: pointer to hardware structure
1707 *
1708 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1709 **/
ixgbe_identify_qsfp_module_generic(struct ixgbe_hw * hw)1710 int32_t ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1711 {
1712 int32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
1713 uint32_t vendor_oui = 0;
1714 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1715 uint8_t identifier = 0;
1716 uint8_t comp_codes_1g = 0;
1717 uint8_t comp_codes_10g = 0;
1718 uint8_t oui_bytes[3] = {0, 0, 0};
1719 uint8_t connector = 0;
1720 uint8_t cable_length = 0;
1721 uint8_t device_tech = 0;
1722 bool active_cable = FALSE;
1723
1724 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1725
1726 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1727 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1728 status = IXGBE_ERR_SFP_NOT_PRESENT;
1729 goto out;
1730 }
1731
1732 /* LAN ID is needed for I2C access */
1733 hw->mac.ops.set_lan_id(hw);
1734
1735 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1736 &identifier);
1737
1738 if (status != IXGBE_SUCCESS)
1739 goto err_read_i2c_eeprom;
1740
1741 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1742 hw->phy.type = ixgbe_phy_sfp_unsupported;
1743 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1744 goto out;
1745 }
1746
1747 hw->phy.id = identifier;
1748
1749 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1750 &comp_codes_10g);
1751
1752 if (status != IXGBE_SUCCESS)
1753 goto err_read_i2c_eeprom;
1754
1755 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1756 &comp_codes_1g);
1757
1758 if (status != IXGBE_SUCCESS)
1759 goto err_read_i2c_eeprom;
1760
1761 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1762 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1763 if (hw->bus.lan_id == 0)
1764 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1765 else
1766 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1767 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1768 IXGBE_SFF_10GBASELR_CAPABLE)) {
1769 if (hw->bus.lan_id == 0)
1770 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1771 else
1772 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1773 } else {
1774 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1775 active_cable = TRUE;
1776
1777 if (!active_cable) {
1778 /* check for active DA cables that pre-date
1779 * SFF-8436 v3.6 */
1780 hw->phy.ops.read_i2c_eeprom(hw,
1781 IXGBE_SFF_QSFP_CONNECTOR,
1782 &connector);
1783
1784 hw->phy.ops.read_i2c_eeprom(hw,
1785 IXGBE_SFF_QSFP_CABLE_LENGTH,
1786 &cable_length);
1787
1788 hw->phy.ops.read_i2c_eeprom(hw,
1789 IXGBE_SFF_QSFP_DEVICE_TECH,
1790 &device_tech);
1791
1792 if ((connector ==
1793 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1794 (cable_length > 0) &&
1795 ((device_tech >> 4) ==
1796 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1797 active_cable = TRUE;
1798 }
1799
1800 if (active_cable) {
1801 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1802 if (hw->bus.lan_id == 0)
1803 hw->phy.sfp_type =
1804 ixgbe_sfp_type_da_act_lmt_core0;
1805 else
1806 hw->phy.sfp_type =
1807 ixgbe_sfp_type_da_act_lmt_core1;
1808 } else {
1809 /* unsupported module type */
1810 hw->phy.type = ixgbe_phy_sfp_unsupported;
1811 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1812 goto out;
1813 }
1814 }
1815
1816 if (hw->phy.sfp_type != stored_sfp_type)
1817 hw->phy.sfp_setup_needed = TRUE;
1818
1819 /* Determine if the QSFP+ PHY is dual speed or not. */
1820 hw->phy.multispeed_fiber = FALSE;
1821 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1822 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1823 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1824 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1825 hw->phy.multispeed_fiber = TRUE;
1826
1827 /* Determine PHY vendor for optical modules */
1828 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1829 IXGBE_SFF_10GBASELR_CAPABLE)) {
1830 status = hw->phy.ops.read_i2c_eeprom(hw,
1831 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1832 &oui_bytes[0]);
1833
1834 if (status != IXGBE_SUCCESS)
1835 goto err_read_i2c_eeprom;
1836
1837 status = hw->phy.ops.read_i2c_eeprom(hw,
1838 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1839 &oui_bytes[1]);
1840
1841 if (status != IXGBE_SUCCESS)
1842 goto err_read_i2c_eeprom;
1843
1844 status = hw->phy.ops.read_i2c_eeprom(hw,
1845 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1846 &oui_bytes[2]);
1847
1848 if (status != IXGBE_SUCCESS)
1849 goto err_read_i2c_eeprom;
1850
1851 vendor_oui =
1852 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1853 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1854 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1855
1856 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1857 hw->phy.type = ixgbe_phy_qsfp_intel;
1858 else
1859 hw->phy.type = ixgbe_phy_qsfp_unknown;
1860
1861 /*
1862 * We do not limit the definition of "supported QSFP modules"
1863 * to the vendor/make whitelist.
1864 */
1865 status = IXGBE_SUCCESS;
1866 }
1867
1868 out:
1869 return status;
1870
1871 err_read_i2c_eeprom:
1872 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1873 hw->phy.id = 0;
1874 hw->phy.type = ixgbe_phy_unknown;
1875
1876 return IXGBE_ERR_SFP_NOT_PRESENT;
1877 }
1878
1879
1880 /**
1881 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1882 * @hw: pointer to hardware structure
1883 * @list_offset: offset to the SFP ID list
1884 * @data_offset: offset to the SFP data block
1885 *
1886 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1887 * so it returns the offsets to the phy init sequence block.
1888 **/
ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw * hw,uint16_t * list_offset,uint16_t * data_offset)1889 int32_t ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1890 uint16_t *list_offset,
1891 uint16_t *data_offset)
1892 {
1893 uint16_t sfp_id;
1894 uint16_t sfp_type = hw->phy.sfp_type;
1895
1896 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1897
1898 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1899 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1900
1901 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1902 return IXGBE_ERR_SFP_NOT_PRESENT;
1903
1904 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1905 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1906 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1907
1908 /*
1909 * Limiting active cables and 1G Phys must be initialized as
1910 * SR modules
1911 */
1912 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1913 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1914 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1915 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1916 sfp_type = ixgbe_sfp_type_srlr_core0;
1917 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1918 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1919 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1920 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1921 sfp_type = ixgbe_sfp_type_srlr_core1;
1922
1923 /* Read offset to PHY init contents */
1924 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1925 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1926 "eeprom read at offset %d failed",
1927 IXGBE_PHY_INIT_OFFSET_NL);
1928 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1929 }
1930
1931 if ((!*list_offset) || (*list_offset == 0xFFFF))
1932 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1933
1934 /* Shift offset to first ID word */
1935 (*list_offset)++;
1936
1937 /*
1938 * Find the matching SFP ID in the EEPROM
1939 * and program the init sequence
1940 */
1941 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1942 goto err_phy;
1943
1944 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1945 if (sfp_id == sfp_type) {
1946 (*list_offset)++;
1947 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1948 goto err_phy;
1949 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1950 DEBUGOUT("SFP+ module not supported\n");
1951 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1952 } else {
1953 break;
1954 }
1955 } else {
1956 (*list_offset) += 2;
1957 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1958 goto err_phy;
1959 }
1960 }
1961
1962 /*
1963 * the 82598EB SFP+ card officially supports only direct attached cables
1964 * but works fine with optical SFP+ modules as well. Even though the
1965 * EEPROM has no matching ID for them. So just accept the module.
1966 */
1967 if (sfp_id == IXGBE_PHY_INIT_END_NL &&
1968 hw->mac.type == ixgbe_mac_82598EB) {
1969 /* refetch offset for the first phy entry */
1970 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1971 (*list_offset) += 2;
1972 hw->eeprom.ops.read(hw, *list_offset, data_offset);
1973 } else if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1974 DEBUGOUT("No matching SFP+ module found\n");
1975 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1976 }
1977
1978 return IXGBE_SUCCESS;
1979
1980 err_phy:
1981 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1982 "eeprom read at offset %d failed", *list_offset);
1983 return IXGBE_ERR_PHY;
1984 }
1985
1986 /**
1987 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1988 * @hw: pointer to hardware structure
1989 * @byte_offset: EEPROM byte offset to read
1990 * @eeprom_data: value read
1991 *
1992 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1993 **/
ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw * hw,uint8_t byte_offset,uint8_t * eeprom_data)1994 int32_t ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset,
1995 uint8_t *eeprom_data)
1996 {
1997 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1998
1999 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2000 IXGBE_I2C_EEPROM_DEV_ADDR,
2001 eeprom_data);
2002 }
2003
2004 /**
2005 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
2006 * @hw: pointer to hardware structure
2007 * @byte_offset: EEPROM byte offset to write
2008 * @eeprom_data: value to write
2009 *
2010 * Performs byte write operation to SFP module's EEPROM over I2C interface.
2011 **/
ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw * hw,uint8_t byte_offset,uint8_t eeprom_data)2012 int32_t ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset,
2013 uint8_t eeprom_data)
2014 {
2015 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
2016
2017 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2018 IXGBE_I2C_EEPROM_DEV_ADDR,
2019 eeprom_data);
2020 }
2021
2022 /**
2023 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected
2024 * @hw: pointer to hardware structure
2025 * @offset: eeprom offset to be read
2026 * @addr: I2C address to be read
2027 */
ixgbe_is_sfp_probe(struct ixgbe_hw * hw,uint8_t offset,uint8_t addr)2028 bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, uint8_t offset, uint8_t addr)
2029 {
2030 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2031 offset == IXGBE_SFF_IDENTIFIER &&
2032 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2033 return TRUE;
2034 return FALSE;
2035 }
2036
2037 /**
2038 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2039 * @hw: pointer to hardware structure
2040 * @byte_offset: byte offset to read
2041 * @dev_addr: address to read from
2042 * @data: value read
2043 * @lock: TRUE if to take and release semaphore
2044 *
2045 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2046 * a specified device address.
2047 **/
ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw * hw,uint8_t byte_offset,uint8_t dev_addr,uint8_t * data,bool lock)2048 int32_t ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, uint8_t byte_offset,
2049 uint8_t dev_addr, uint8_t *data, bool lock)
2050 {
2051 int32_t status;
2052 uint32_t max_retry = 10;
2053 uint32_t retry = 0;
2054 uint32_t swfw_mask = hw->phy.phy_semaphore_mask;
2055 bool nack = 1;
2056 *data = 0;
2057
2058 DEBUGFUNC("ixgbe_read_i2c_byte_generic_int");
2059
2060 if (hw->mac.type >= ixgbe_mac_X550)
2061 max_retry = 3;
2062 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2063 max_retry = IXGBE_SFP_DETECT_RETRIES;
2064
2065 do {
2066 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2067 return IXGBE_ERR_SWFW_SYNC;
2068
2069 ixgbe_i2c_start(hw);
2070
2071 /* Device Address and write indication */
2072 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2073 if (status != IXGBE_SUCCESS)
2074 goto fail;
2075
2076 status = ixgbe_get_i2c_ack(hw);
2077 if (status != IXGBE_SUCCESS)
2078 goto fail;
2079
2080 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2081 if (status != IXGBE_SUCCESS)
2082 goto fail;
2083
2084 status = ixgbe_get_i2c_ack(hw);
2085 if (status != IXGBE_SUCCESS)
2086 goto fail;
2087
2088 ixgbe_i2c_start(hw);
2089
2090 /* Device Address and read indication */
2091 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2092 if (status != IXGBE_SUCCESS)
2093 goto fail;
2094
2095 status = ixgbe_get_i2c_ack(hw);
2096 if (status != IXGBE_SUCCESS)
2097 goto fail;
2098
2099 status = ixgbe_clock_in_i2c_byte(hw, data);
2100 if (status != IXGBE_SUCCESS)
2101 goto fail;
2102
2103 status = ixgbe_clock_out_i2c_bit(hw, nack);
2104 if (status != IXGBE_SUCCESS)
2105 goto fail;
2106
2107 ixgbe_i2c_stop(hw);
2108 if (lock)
2109 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2110 return IXGBE_SUCCESS;
2111
2112 fail:
2113 ixgbe_i2c_bus_clear(hw);
2114 if (lock) {
2115 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2116 msec_delay(100);
2117 }
2118 retry++;
2119 if (retry < max_retry)
2120 DEBUGOUT("I2C byte read error - Retrying.\n");
2121 else
2122 DEBUGOUT("I2C byte read error.\n");
2123
2124 } while (retry < max_retry);
2125
2126 return status;
2127 }
2128
2129 /**
2130 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2131 * @hw: pointer to hardware structure
2132 * @byte_offset: byte offset to read
2133 * @dev_addr: address to read from
2134 * @data: value read
2135 *
2136 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2137 * a specified device address.
2138 **/
ixgbe_read_i2c_byte_generic(struct ixgbe_hw * hw,uint8_t byte_offset,uint8_t dev_addr,uint8_t * data)2139 int32_t ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, uint8_t byte_offset,
2140 uint8_t dev_addr, uint8_t *data)
2141 {
2142 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2143 data, TRUE);
2144 }
2145
2146 /**
2147 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2148 * @hw: pointer to hardware structure
2149 * @byte_offset: byte offset to read
2150 * @dev_addr: address to read from
2151 * @data: value read
2152 *
2153 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2154 * a specified device address.
2155 **/
ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,uint8_t byte_offset,uint8_t dev_addr,uint8_t * data)2156 int32_t ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, uint8_t byte_offset,
2157 uint8_t dev_addr, uint8_t *data)
2158 {
2159 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2160 data, FALSE);
2161 }
2162
2163 /**
2164 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2165 * @hw: pointer to hardware structure
2166 * @byte_offset: byte offset to write
2167 * @dev_addr: address to write to
2168 * @data: value to write
2169 * @lock: TRUE if to take and release semaphore
2170 *
2171 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2172 * a specified device address.
2173 **/
ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw * hw,uint8_t byte_offset,uint8_t dev_addr,uint8_t data,bool lock)2174 int32_t ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, uint8_t byte_offset,
2175 uint8_t dev_addr, uint8_t data, bool lock)
2176 {
2177 int32_t status;
2178 uint32_t max_retry = 1;
2179 uint32_t retry = 0;
2180 uint32_t swfw_mask = hw->phy.phy_semaphore_mask;
2181
2182 DEBUGFUNC("ixgbe_write_i2c_byte_generic_int");
2183
2184 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2185 IXGBE_SUCCESS)
2186 return IXGBE_ERR_SWFW_SYNC;
2187
2188 do {
2189 ixgbe_i2c_start(hw);
2190
2191 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2192 if (status != IXGBE_SUCCESS)
2193 goto fail;
2194
2195 status = ixgbe_get_i2c_ack(hw);
2196 if (status != IXGBE_SUCCESS)
2197 goto fail;
2198
2199 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2200 if (status != IXGBE_SUCCESS)
2201 goto fail;
2202
2203 status = ixgbe_get_i2c_ack(hw);
2204 if (status != IXGBE_SUCCESS)
2205 goto fail;
2206
2207 status = ixgbe_clock_out_i2c_byte(hw, data);
2208 if (status != IXGBE_SUCCESS)
2209 goto fail;
2210
2211 status = ixgbe_get_i2c_ack(hw);
2212 if (status != IXGBE_SUCCESS)
2213 goto fail;
2214
2215 ixgbe_i2c_stop(hw);
2216 if (lock)
2217 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2218 return IXGBE_SUCCESS;
2219
2220 fail:
2221 ixgbe_i2c_bus_clear(hw);
2222 retry++;
2223 if (retry < max_retry)
2224 DEBUGOUT("I2C byte write error - Retrying.\n");
2225 else
2226 DEBUGOUT("I2C byte write error.\n");
2227 } while (retry < max_retry);
2228
2229 if (lock)
2230 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2231
2232 return status;
2233 }
2234
2235 /**
2236 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2237 * @hw: pointer to hardware structure
2238 * @byte_offset: byte offset to write
2239 * @dev_addr: address to write to
2240 * @data: value to write
2241 *
2242 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2243 * a specified device address.
2244 **/
ixgbe_write_i2c_byte_generic(struct ixgbe_hw * hw,uint8_t byte_offset,uint8_t dev_addr,uint8_t data)2245 int32_t ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, uint8_t byte_offset,
2246 uint8_t dev_addr, uint8_t data)
2247 {
2248 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2249 data, TRUE);
2250 }
2251
2252 /**
2253 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2254 * @hw: pointer to hardware structure
2255 * @byte_offset: byte offset to write
2256 * @dev_addr: address to write to
2257 * @data: value to write
2258 *
2259 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2260 * a specified device address.
2261 **/
ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,uint8_t byte_offset,uint8_t dev_addr,uint8_t data)2262 int32_t ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, uint8_t byte_offset,
2263 uint8_t dev_addr, uint8_t data)
2264 {
2265 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2266 data, FALSE);
2267 }
2268
2269 /**
2270 * ixgbe_i2c_start - Sets I2C start condition
2271 * @hw: pointer to hardware structure
2272 *
2273 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2274 * Set bit-bang mode on X550 hardware.
2275 **/
ixgbe_i2c_start(struct ixgbe_hw * hw)2276 void ixgbe_i2c_start(struct ixgbe_hw *hw)
2277 {
2278 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2279
2280 DEBUGFUNC("ixgbe_i2c_start");
2281
2282 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2283
2284 /* Start condition must begin with data and clock high */
2285 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2286 ixgbe_raise_i2c_clk(hw, &i2cctl);
2287
2288 /* Setup time for start condition (4.7us) */
2289 usec_delay(IXGBE_I2C_T_SU_STA);
2290
2291 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2292
2293 /* Hold time for start condition (4us) */
2294 usec_delay(IXGBE_I2C_T_HD_STA);
2295
2296 ixgbe_lower_i2c_clk(hw, &i2cctl);
2297
2298 /* Minimum low period of clock is 4.7 us */
2299 usec_delay(IXGBE_I2C_T_LOW);
2300
2301 }
2302
2303 /**
2304 * ixgbe_i2c_stop - Sets I2C stop condition
2305 * @hw: pointer to hardware structure
2306 *
2307 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2308 * Disables bit-bang mode and negates data output enable on X550
2309 * hardware.
2310 **/
ixgbe_i2c_stop(struct ixgbe_hw * hw)2311 void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2312 {
2313 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2314 uint32_t data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2315 uint32_t clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2316 uint32_t bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2317
2318 DEBUGFUNC("ixgbe_i2c_stop");
2319
2320 /* Stop condition must begin with data low and clock high */
2321 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2322 ixgbe_raise_i2c_clk(hw, &i2cctl);
2323
2324 /* Setup time for stop condition (4us) */
2325 usec_delay(IXGBE_I2C_T_SU_STO);
2326
2327 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2328
2329 /* bus free time between stop and start (4.7us)*/
2330 usec_delay(IXGBE_I2C_T_BUF);
2331
2332 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2333 i2cctl &= ~bb_en_bit;
2334 i2cctl |= data_oe_bit | clk_oe_bit;
2335 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2336 IXGBE_WRITE_FLUSH(hw);
2337 }
2338 }
2339
2340 /**
2341 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2342 * @hw: pointer to hardware structure
2343 * @data: data byte to clock in
2344 *
2345 * Clocks in one byte data via I2C data/clock
2346 **/
ixgbe_clock_in_i2c_byte(struct ixgbe_hw * hw,uint8_t * data)2347 int32_t ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, uint8_t *data)
2348 {
2349 int32_t i;
2350 bool bit = 0;
2351
2352 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2353
2354 *data = 0;
2355 for (i = 7; i >= 0; i--) {
2356 ixgbe_clock_in_i2c_bit(hw, &bit);
2357 *data |= bit << i;
2358 }
2359
2360 return IXGBE_SUCCESS;
2361 }
2362
2363 /**
2364 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2365 * @hw: pointer to hardware structure
2366 * @data: data byte clocked out
2367 *
2368 * Clocks out one byte data via I2C data/clock
2369 **/
ixgbe_clock_out_i2c_byte(struct ixgbe_hw * hw,uint8_t data)2370 int32_t ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, uint8_t data)
2371 {
2372 int32_t status = IXGBE_SUCCESS;
2373 int32_t i;
2374 uint32_t i2cctl;
2375 bool bit;
2376
2377 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2378
2379 for (i = 7; i >= 0; i--) {
2380 bit = (data >> i) & 0x1;
2381 status = ixgbe_clock_out_i2c_bit(hw, bit);
2382
2383 if (status != IXGBE_SUCCESS)
2384 break;
2385 }
2386
2387 /* Release SDA line (set high) */
2388 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2389 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2390 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2391 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2392 IXGBE_WRITE_FLUSH(hw);
2393
2394 return status;
2395 }
2396
2397 /**
2398 * ixgbe_get_i2c_ack - Polls for I2C ACK
2399 * @hw: pointer to hardware structure
2400 *
2401 * Clocks in/out one bit via I2C data/clock
2402 **/
ixgbe_get_i2c_ack(struct ixgbe_hw * hw)2403 int32_t ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2404 {
2405 uint32_t data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2406 int32_t status = IXGBE_SUCCESS;
2407 uint32_t i = 0;
2408 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2409 uint32_t timeout = 10;
2410 bool ack = 1;
2411
2412 DEBUGFUNC("ixgbe_get_i2c_ack");
2413
2414 if (data_oe_bit) {
2415 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2416 i2cctl |= data_oe_bit;
2417 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2418 IXGBE_WRITE_FLUSH(hw);
2419 }
2420 ixgbe_raise_i2c_clk(hw, &i2cctl);
2421
2422 /* Minimum high period of clock is 4us */
2423 usec_delay(IXGBE_I2C_T_HIGH);
2424
2425 /* Poll for ACK. Note that ACK in I2C spec is
2426 * transition from 1 to 0 */
2427 for (i = 0; i < timeout; i++) {
2428 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2429 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2430
2431 usec_delay(1);
2432 if (!ack)
2433 break;
2434 }
2435
2436 if (ack) {
2437 DEBUGOUT("I2C ack was not received.\n");
2438 status = IXGBE_ERR_I2C;
2439 }
2440
2441 ixgbe_lower_i2c_clk(hw, &i2cctl);
2442
2443 /* Minimum low period of clock is 4.7 us */
2444 usec_delay(IXGBE_I2C_T_LOW);
2445
2446 return status;
2447 }
2448
2449 /**
2450 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2451 * @hw: pointer to hardware structure
2452 * @data: read data value
2453 *
2454 * Clocks in one bit via I2C data/clock
2455 **/
ixgbe_clock_in_i2c_bit(struct ixgbe_hw * hw,bool * data)2456 int32_t ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2457 {
2458 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2459 uint32_t data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2460
2461 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2462
2463 if (data_oe_bit) {
2464 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2465 i2cctl |= data_oe_bit;
2466 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2467 IXGBE_WRITE_FLUSH(hw);
2468 }
2469 ixgbe_raise_i2c_clk(hw, &i2cctl);
2470
2471 /* Minimum high period of clock is 4us */
2472 usec_delay(IXGBE_I2C_T_HIGH);
2473
2474 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2475 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2476
2477 ixgbe_lower_i2c_clk(hw, &i2cctl);
2478
2479 /* Minimum low period of clock is 4.7 us */
2480 usec_delay(IXGBE_I2C_T_LOW);
2481
2482 return IXGBE_SUCCESS;
2483 }
2484
2485 /**
2486 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2487 * @hw: pointer to hardware structure
2488 * @data: data value to write
2489 *
2490 * Clocks out one bit via I2C data/clock
2491 **/
ixgbe_clock_out_i2c_bit(struct ixgbe_hw * hw,bool data)2492 int32_t ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2493 {
2494 int32_t status;
2495 uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2496
2497 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2498
2499 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2500 if (status == IXGBE_SUCCESS) {
2501 ixgbe_raise_i2c_clk(hw, &i2cctl);
2502
2503 /* Minimum high period of clock is 4us */
2504 usec_delay(IXGBE_I2C_T_HIGH);
2505
2506 ixgbe_lower_i2c_clk(hw, &i2cctl);
2507
2508 /* Minimum low period of clock is 4.7 us.
2509 * This also takes care of the data hold time.
2510 */
2511 usec_delay(IXGBE_I2C_T_LOW);
2512 } else {
2513 status = IXGBE_ERR_I2C;
2514 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2515 "I2C data was not set to %X\n", data);
2516 }
2517
2518 return status;
2519 }
2520
2521 /**
2522 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2523 * @hw: pointer to hardware structure
2524 * @i2cctl: Current value of I2CCTL register
2525 *
2526 * Raises the I2C clock line '0'->'1'
2527 * Negates the I2C clock output enable on X550 hardware.
2528 **/
ixgbe_raise_i2c_clk(struct ixgbe_hw * hw,uint32_t * i2cctl)2529 void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl)
2530 {
2531 uint32_t clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2532 uint32_t i = 0;
2533 uint32_t timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2534 uint32_t i2cctl_r = 0;
2535
2536 DEBUGFUNC("ixgbe_raise_i2c_clk");
2537
2538 if (clk_oe_bit) {
2539 *i2cctl |= clk_oe_bit;
2540 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2541 }
2542
2543 for (i = 0; i < timeout; i++) {
2544 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2545
2546 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2547 IXGBE_WRITE_FLUSH(hw);
2548 /* SCL rise time (1000ns) */
2549 usec_delay(IXGBE_I2C_T_RISE);
2550
2551 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2552 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2553 break;
2554 }
2555 }
2556
2557 /**
2558 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2559 * @hw: pointer to hardware structure
2560 * @i2cctl: Current value of I2CCTL register
2561 *
2562 * Lowers the I2C clock line '1'->'0'
2563 * Asserts the I2C clock output enable on X550 hardware.
2564 **/
ixgbe_lower_i2c_clk(struct ixgbe_hw * hw,uint32_t * i2cctl)2565 void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl)
2566 {
2567 DEBUGFUNC("ixgbe_lower_i2c_clk");
2568
2569 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2570 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2571
2572 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2573 IXGBE_WRITE_FLUSH(hw);
2574
2575 /* SCL fall time (300ns) */
2576 usec_delay(IXGBE_I2C_T_FALL);
2577 }
2578
2579 /**
2580 * ixgbe_set_i2c_data - Sets the I2C data bit
2581 * @hw: pointer to hardware structure
2582 * @i2cctl: Current value of I2CCTL register
2583 * @data: I2C data value (0 or 1) to set
2584 *
2585 * Sets the I2C data bit
2586 * Asserts the I2C data output enable on X550 hardware.
2587 **/
ixgbe_set_i2c_data(struct ixgbe_hw * hw,uint32_t * i2cctl,bool data)2588 int32_t ixgbe_set_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl, bool data)
2589 {
2590 uint32_t data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2591 int32_t status = IXGBE_SUCCESS;
2592
2593 DEBUGFUNC("ixgbe_set_i2c_data");
2594
2595 if (data)
2596 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2597 else
2598 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2599 *i2cctl &= ~data_oe_bit;
2600
2601 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2602 IXGBE_WRITE_FLUSH(hw);
2603
2604 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2605 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2606
2607 if (!data) /* Can't verify data in this case */
2608 return IXGBE_SUCCESS;
2609 if (data_oe_bit) {
2610 *i2cctl |= data_oe_bit;
2611 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2612 IXGBE_WRITE_FLUSH(hw);
2613 }
2614
2615 /* Verify data was set correctly */
2616 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2617 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2618 status = IXGBE_ERR_I2C;
2619 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2620 "Error - I2C data was not set to %X.\n",
2621 data);
2622 }
2623
2624 return status;
2625 }
2626
2627 /**
2628 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2629 * @hw: pointer to hardware structure
2630 * @i2cctl: Current value of I2CCTL register
2631 *
2632 * Returns the I2C data bit value
2633 * Negates the I2C data output enable on X550 hardware.
2634 **/
ixgbe_get_i2c_data(struct ixgbe_hw * hw,uint32_t * i2cctl)2635 bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl)
2636 {
2637 bool data;
2638 uint32_t data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2639
2640 DEBUGFUNC("ixgbe_get_i2c_data");
2641
2642 if (data_oe_bit) {
2643 *i2cctl |= data_oe_bit;
2644 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2645 IXGBE_WRITE_FLUSH(hw);
2646 usec_delay(IXGBE_I2C_T_FALL);
2647 }
2648
2649 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2650 data = 1;
2651 else
2652 data = 0;
2653
2654 return data;
2655 }
2656
2657 /**
2658 * ixgbe_i2c_bus_clear - Clears the I2C bus
2659 * @hw: pointer to hardware structure
2660 *
2661 * Clears the I2C bus by sending nine clock pulses.
2662 * Used when data line is stuck low.
2663 **/
ixgbe_i2c_bus_clear(struct ixgbe_hw * hw)2664 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2665 {
2666 uint32_t i2cctl;
2667 uint32_t i;
2668
2669 DEBUGFUNC("ixgbe_i2c_bus_clear");
2670
2671 ixgbe_i2c_start(hw);
2672 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2673
2674 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2675
2676 for (i = 0; i < 9; i++) {
2677 ixgbe_raise_i2c_clk(hw, &i2cctl);
2678
2679 /* Min high period of clock is 4us */
2680 usec_delay(IXGBE_I2C_T_HIGH);
2681
2682 ixgbe_lower_i2c_clk(hw, &i2cctl);
2683
2684 /* Min low period of clock is 4.7us*/
2685 usec_delay(IXGBE_I2C_T_LOW);
2686 }
2687
2688 ixgbe_i2c_start(hw);
2689
2690 /* Put the i2c bus back to default state */
2691 ixgbe_i2c_stop(hw);
2692 }
2693
2694 /**
2695 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2696 * @hw: pointer to hardware structure
2697 *
2698 * Checks if the LASI temp alarm status was triggered due to overtemp
2699 **/
ixgbe_tn_check_overtemp(struct ixgbe_hw * hw)2700 int32_t ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2701 {
2702 int32_t status = IXGBE_SUCCESS;
2703 uint16_t phy_data = 0;
2704
2705 DEBUGFUNC("ixgbe_tn_check_overtemp");
2706
2707 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2708 goto out;
2709
2710 /* Check that the LASI temp alarm status was triggered */
2711 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2712 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2713
2714 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2715 goto out;
2716
2717 status = IXGBE_ERR_OVERTEMP;
2718 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2719 out:
2720 return status;
2721 }
2722
2723 /**
2724 * ixgbe_set_copper_phy_power - Control power for copper phy
2725 * @hw: pointer to hardware structure
2726 * @on: TRUE for on, FALSE for off
2727 */
ixgbe_set_copper_phy_power(struct ixgbe_hw * hw,bool on)2728 int32_t ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2729 {
2730 uint32_t status;
2731 uint16_t reg;
2732
2733 if (!on && ixgbe_mng_present(hw))
2734 return 0;
2735
2736 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2737 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2738 ®);
2739 if (status)
2740 return status;
2741
2742 if (on) {
2743 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2744 } else {
2745 if (ixgbe_check_reset_blocked(hw))
2746 return 0;
2747 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2748 }
2749
2750 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2751 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2752 reg);
2753 return status;
2754 }
2755