1 /* $OpenBSD: ixgbe_82598.c,v 1.21 2024/05/13 01:15:51 jsg Exp $ */
2
3 /******************************************************************************
4 SPDX-License-Identifier: BSD-3-Clause
5
6 Copyright (c) 2001-2017, Intel Corporation
7 All rights reserved.
8
9 Redistribution and use in source and binary forms, with or without
10 modification, are permitted provided that the following conditions are met:
11
12 1. Redistributions of source code must retain the above copyright notice,
13 this list of conditions and the following disclaimer.
14
15 2. Redistributions in binary form must reproduce the above copyright
16 notice, this list of conditions and the following disclaimer in the
17 documentation and/or other materials provided with the distribution.
18
19 3. Neither the name of the Intel Corporation nor the names of its
20 contributors may be used to endorse or promote products derived from
21 this software without specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 POSSIBILITY OF SUCH DAMAGE.
34
35 ******************************************************************************/
36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82598.c 331224 2018-03-19 20:55:05Z erj $*/
37
38
39 #include <dev/pci/ixgbe.h>
40 #include <dev/pci/ixgbe_type.h>
41
42 #define IXGBE_82598_MAX_TX_QUEUES 32
43 #define IXGBE_82598_MAX_RX_QUEUES 64
44 #define IXGBE_82598_RAR_ENTRIES 16
45 #define IXGBE_82598_MC_TBL_SIZE 128
46 #define IXGBE_82598_VFT_TBL_SIZE 128
47 #define IXGBE_82598_RX_PB_SIZE 512
48
49 int32_t ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
50 ixgbe_link_speed *speed,
51 bool *autoneg);
52 enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
53 int32_t ixgbe_fc_enable_82598(struct ixgbe_hw *hw);
54 int32_t ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
55 bool autoneg_wait_to_complete);
56 int32_t ixgbe_validate_link_ready(struct ixgbe_hw *hw);
57 int32_t ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
58 ixgbe_link_speed *speed, bool *link_up,
59 bool link_up_wait_to_complete);
60 int32_t ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
61 ixgbe_link_speed speed,
62 bool autoneg_wait_to_complete);
63 int32_t ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
64 ixgbe_link_speed speed,
65 bool autoneg_wait_to_complete);
66 int32_t ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
67
68 int32_t ixgbe_start_hw_82598(struct ixgbe_hw *hw);
69 int32_t ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq);
70 int32_t ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq);
71 int32_t ixgbe_set_vfta_82598(struct ixgbe_hw *hw, uint32_t vlan,
72 uint32_t vind, bool vlan_on, bool vlvf_bypass);
73 int32_t ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
74 int32_t ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val);
75 int32_t ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t val);
76 int32_t ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, uint8_t dev_addr,
77 uint8_t byte_offset, uint8_t *eeprom_data);
78 int32_t ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, uint8_t byte_offset,
79 uint8_t *eeprom_data);
80 uint64_t ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
81 int32_t ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);
82 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);
83 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw);
84 int32_t ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, uint32_t regval);
85
86 /**
87 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
88 * @hw: pointer to the HW structure
89 *
90 * The defaults for 82598 should be in the range of 50us to 50ms,
91 * however the hardware default for these parts is 500us to 1ms which is less
92 * than the 10ms recommended by the pci-e spec. To address this we need to
93 * increase the value to either 10ms to 250ms for capability version 1 config,
94 * or 16ms to 55ms for version 2.
95 **/
ixgbe_set_pcie_completion_timeout(struct ixgbe_hw * hw)96 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
97 {
98 uint32_t gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
99 uint16_t pcie_devctl2;
100
101 /* only take action if timeout value is defaulted to 0 */
102 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
103 goto out;
104
105 /*
106 * if capabilities version is type 1 we can write the
107 * timeout of 10ms to 250ms through the GCR register
108 */
109 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
110 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
111 goto out;
112 }
113
114 /*
115 * for version 2 capabilities we need to write the config space
116 * directly in order to set the completion timeout value for
117 * 16ms to 55ms
118 */
119 pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
120 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
121 IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
122 out:
123 /* disable completion timeout resend */
124 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
125 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
126 }
127
128 /**
129 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
130 * @hw: pointer to hardware structure
131 *
132 * Initialize the function pointers and assign the MAC type for 82598.
133 * Does not touch the hardware.
134 **/
ixgbe_init_ops_82598(struct ixgbe_hw * hw)135 int32_t ixgbe_init_ops_82598(struct ixgbe_hw *hw)
136 {
137 struct ixgbe_mac_info *mac = &hw->mac;
138 struct ixgbe_phy_info *phy = &hw->phy;
139 int32_t ret_val;
140
141 DEBUGFUNC("ixgbe_init_ops_82598");
142
143 ret_val = ixgbe_init_phy_ops_generic(hw);
144 ret_val = ixgbe_init_ops_generic(hw);
145
146 /* PHY */
147 phy->ops.init = ixgbe_init_phy_ops_82598;
148
149 /* MAC */
150 mac->ops.start_hw = ixgbe_start_hw_82598;
151 mac->ops.reset_hw = ixgbe_reset_hw_82598;
152 mac->ops.get_media_type = ixgbe_get_media_type_82598;
153 mac->ops.get_supported_physical_layer =
154 ixgbe_get_supported_physical_layer_82598;
155 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82598;
156 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82598;
157 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie_82598;
158 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82598;
159
160 /* RAR, Multicast, VLAN */
161 mac->ops.set_vmdq = ixgbe_set_vmdq_82598;
162 mac->ops.clear_vmdq = ixgbe_clear_vmdq_82598;
163 mac->ops.set_vfta = ixgbe_set_vfta_82598;
164 mac->ops.set_vlvf = NULL;
165 mac->ops.clear_vfta = ixgbe_clear_vfta_82598;
166
167 /* Flow Control */
168 mac->ops.fc_enable = ixgbe_fc_enable_82598;
169
170 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
171 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
172 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
173 mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE;
174 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
175 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
176 mac->max_msix_vectors = 0 /*ixgbe_get_pcie_msix_count_generic(hw)*/;
177
178 /* SFP+ Module */
179 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_82598;
180
181 /* Link */
182 mac->ops.check_link = ixgbe_check_mac_link_82598;
183 mac->ops.setup_link = ixgbe_setup_mac_link_82598;
184 mac->ops.flap_tx_laser = NULL;
185 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82598;
186
187 return ret_val;
188 }
189
190 /**
191 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
192 * @hw: pointer to hardware structure
193 *
194 * Initialize any function pointers that were not able to be
195 * set during init_shared_code because the PHY/SFP type was
196 * not known. Perform the SFP init if necessary.
197 *
198 **/
ixgbe_init_phy_ops_82598(struct ixgbe_hw * hw)199 int32_t ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
200 {
201 struct ixgbe_mac_info *mac = &hw->mac;
202 struct ixgbe_phy_info *phy = &hw->phy;
203 int32_t ret_val = IXGBE_SUCCESS;
204 uint16_t list_offset, data_offset;
205
206 DEBUGFUNC("ixgbe_init_phy_ops_82598");
207
208 /* Identify the PHY */
209 phy->ops.identify(hw);
210
211 /* Overwrite the link function pointers if copper PHY */
212 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
213 mac->ops.setup_link = ixgbe_setup_copper_link_82598;
214 mac->ops.get_link_capabilities =
215 ixgbe_get_copper_link_capabilities_generic;
216 }
217
218 switch (hw->phy.type) {
219 case ixgbe_phy_tn:
220 phy->ops.setup_link = ixgbe_setup_phy_link_tnx;
221 phy->ops.check_link = ixgbe_check_phy_link_tnx;
222 phy->ops.get_firmware_version =
223 ixgbe_get_phy_firmware_version_tnx;
224 break;
225 case ixgbe_phy_nl:
226 phy->ops.reset = ixgbe_reset_phy_nl;
227
228 /* Call SFP+ identify routine to get the SFP+ module type */
229 ret_val = phy->ops.identify_sfp(hw);
230 if (ret_val != IXGBE_SUCCESS)
231 goto out;
232 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
233 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
234 goto out;
235 }
236
237 /* Check to see if SFP+ module is supported */
238 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
239 &list_offset,
240 &data_offset);
241 if (ret_val != IXGBE_SUCCESS) {
242 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
243 goto out;
244 }
245 break;
246 default:
247 break;
248 }
249
250 out:
251 return ret_val;
252 }
253
254 /**
255 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
256 * @hw: pointer to hardware structure
257 *
258 * Starts the hardware using the generic start_hw function.
259 * Disables relaxed ordering Then set pcie completion timeout
260 *
261 **/
ixgbe_start_hw_82598(struct ixgbe_hw * hw)262 int32_t ixgbe_start_hw_82598(struct ixgbe_hw *hw)
263 {
264 uint32_t regval;
265 uint32_t i;
266 int32_t ret_val = IXGBE_SUCCESS;
267
268 DEBUGFUNC("ixgbe_start_hw_82598");
269
270 ret_val = ixgbe_start_hw_generic(hw);
271 if (ret_val)
272 return ret_val;
273
274 /* Disable relaxed ordering */
275 for (i = 0; ((i < hw->mac.max_tx_queues) &&
276 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
277 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
278 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
279 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
280 }
281
282 for (i = 0; ((i < hw->mac.max_rx_queues) &&
283 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
284 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
285 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
286 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
287 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
288 }
289
290 /* set the completion timeout for interface */
291 ixgbe_set_pcie_completion_timeout(hw);
292
293 return ret_val;
294 }
295
296 /**
297 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
298 * @hw: pointer to hardware structure
299 * @speed: pointer to link speed
300 * @autoneg: boolean auto-negotiation value
301 *
302 * Determines the link capabilities by reading the AUTOC register.
303 **/
ixgbe_get_link_capabilities_82598(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * autoneg)304 int32_t ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
305 ixgbe_link_speed *speed,
306 bool *autoneg)
307 {
308 int32_t status = IXGBE_SUCCESS;
309 uint32_t autoc = 0;
310
311 DEBUGFUNC("ixgbe_get_link_capabilities_82598");
312
313 /*
314 * Determine link capabilities based on the stored value of AUTOC,
315 * which represents EEPROM defaults. If AUTOC value has not been
316 * stored, use the current register value.
317 */
318 if (hw->mac.orig_link_settings_stored)
319 autoc = hw->mac.orig_autoc;
320 else
321 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
322
323 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
324 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
325 *speed = IXGBE_LINK_SPEED_1GB_FULL;
326 *autoneg = FALSE;
327 break;
328
329 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
330 *speed = IXGBE_LINK_SPEED_10GB_FULL;
331 *autoneg = FALSE;
332 break;
333
334 case IXGBE_AUTOC_LMS_1G_AN:
335 *speed = IXGBE_LINK_SPEED_1GB_FULL;
336 *autoneg = TRUE;
337 break;
338
339 case IXGBE_AUTOC_LMS_KX4_AN:
340 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
341 *speed = IXGBE_LINK_SPEED_UNKNOWN;
342 if (autoc & IXGBE_AUTOC_KX4_SUPP)
343 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
344 if (autoc & IXGBE_AUTOC_KX_SUPP)
345 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
346 *autoneg = TRUE;
347 break;
348
349 default:
350 status = IXGBE_ERR_LINK_SETUP;
351 break;
352 }
353
354 return status;
355 }
356
357 /**
358 * ixgbe_get_media_type_82598 - Determines media type
359 * @hw: pointer to hardware structure
360 *
361 * Returns the media type (fiber, copper, backplane)
362 **/
ixgbe_get_media_type_82598(struct ixgbe_hw * hw)363 enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
364 {
365 enum ixgbe_media_type media_type;
366
367 DEBUGFUNC("ixgbe_get_media_type_82598");
368
369 /* Detect if there is a copper PHY attached. */
370 switch (hw->phy.type) {
371 case ixgbe_phy_cu_unknown:
372 case ixgbe_phy_tn:
373 media_type = ixgbe_media_type_copper;
374 goto out;
375 default:
376 break;
377 }
378
379 /* Media type for I82598 is based on device ID */
380 switch (hw->device_id) {
381 case IXGBE_DEV_ID_82598:
382 case IXGBE_DEV_ID_82598_BX:
383 /* Default device ID is mezzanine card KX/KX4 */
384 media_type = ixgbe_media_type_backplane;
385 break;
386 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
387 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
388 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
389 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
390 case IXGBE_DEV_ID_82598EB_XF_LR:
391 case IXGBE_DEV_ID_82598EB_SFP_LOM:
392 media_type = ixgbe_media_type_fiber;
393 break;
394 case IXGBE_DEV_ID_82598EB_CX4:
395 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
396 media_type = ixgbe_media_type_cx4;
397 break;
398 case IXGBE_DEV_ID_82598AT:
399 case IXGBE_DEV_ID_82598AT2:
400 media_type = ixgbe_media_type_copper;
401 break;
402 default:
403 media_type = ixgbe_media_type_unknown;
404 break;
405 }
406 out:
407 return media_type;
408 }
409
410 /**
411 * ixgbe_fc_enable_82598 - Enable flow control
412 * @hw: pointer to hardware structure
413 *
414 * Enable flow control according to the current settings.
415 **/
ixgbe_fc_enable_82598(struct ixgbe_hw * hw)416 int32_t ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
417 {
418 int32_t ret_val = IXGBE_SUCCESS;
419 uint32_t fctrl_reg;
420 uint32_t rmcs_reg;
421 uint32_t reg;
422 uint32_t fcrtl, fcrth;
423 uint32_t link_speed = 0;
424 int i;
425 bool link_up;
426
427 DEBUGFUNC("ixgbe_fc_enable_82598");
428
429 /* Validate the water mark configuration */
430 if (!hw->fc.pause_time) {
431 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
432 goto out;
433 }
434
435 /* Low water mark of zero causes XOFF floods */
436 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
437 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
438 hw->fc.high_water[i]) {
439 if (!hw->fc.low_water[i] ||
440 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
441 DEBUGOUT("Invalid water mark configuration\n");
442 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
443 goto out;
444 }
445 }
446 }
447
448 /*
449 * On 82598 having Rx FC on causes resets while doing 1G
450 * so if it's on turn it off once we know link_speed. For
451 * more details see 82598 Specification update.
452 */
453 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
454 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
455 switch (hw->fc.requested_mode) {
456 case ixgbe_fc_full:
457 hw->fc.requested_mode = ixgbe_fc_tx_pause;
458 break;
459 case ixgbe_fc_rx_pause:
460 hw->fc.requested_mode = ixgbe_fc_none;
461 break;
462 default:
463 /* no change */
464 break;
465 }
466 }
467
468 /* Negotiate the fc mode to use */
469 ixgbe_fc_autoneg(hw);
470
471 /* Disable any previous flow control settings */
472 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
473 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
474
475 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
476 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
477
478 /*
479 * The possible values of fc.current_mode are:
480 * 0: Flow control is completely disabled
481 * 1: Rx flow control is enabled (we can receive pause frames,
482 * but not send pause frames).
483 * 2: Tx flow control is enabled (we can send pause frames but
484 * we do not support receiving pause frames).
485 * 3: Both Rx and Tx flow control (symmetric) are enabled.
486 * other: Invalid.
487 */
488 switch (hw->fc.current_mode) {
489 case ixgbe_fc_none:
490 /*
491 * Flow control is disabled by software override or autoneg.
492 * The code below will actually disable it in the HW.
493 */
494 break;
495 case ixgbe_fc_rx_pause:
496 /*
497 * Rx Flow control is enabled and Tx Flow control is
498 * disabled by software override. Since there really
499 * isn't a way to advertise that we are capable of RX
500 * Pause ONLY, we will advertise that we support both
501 * symmetric and asymmetric Rx PAUSE. Later, we will
502 * disable the adapter's ability to send PAUSE frames.
503 */
504 fctrl_reg |= IXGBE_FCTRL_RFCE;
505 break;
506 case ixgbe_fc_tx_pause:
507 /*
508 * Tx Flow control is enabled, and Rx Flow control is
509 * disabled by software override.
510 */
511 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
512 break;
513 case ixgbe_fc_full:
514 /* Flow control (both Rx and Tx) is enabled by SW override. */
515 fctrl_reg |= IXGBE_FCTRL_RFCE;
516 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
517 break;
518 default:
519 DEBUGOUT("Flow control param set incorrectly\n");
520 ret_val = IXGBE_ERR_CONFIG;
521 goto out;
522 break;
523 }
524
525 /* Set 802.3x based flow control settings. */
526 fctrl_reg |= IXGBE_FCTRL_DPF;
527 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
528 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
529
530 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
531 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
532 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
533 hw->fc.high_water[i]) {
534 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
535 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
536 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
537 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
538 } else {
539 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
540 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
541 }
542
543 }
544
545 /* Configure pause time (2 TCs per register) */
546 reg = (uint32_t)hw->fc.pause_time * 0x00010001;
547 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
548 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
549
550 /* Configure flow control refresh threshold value */
551 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
552
553 out:
554 return ret_val;
555 }
556
557 /**
558 * ixgbe_start_mac_link_82598 - Configures MAC link settings
559 * @hw: pointer to hardware structure
560 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
561 *
562 * Configures link settings based on values in the ixgbe_hw struct.
563 * Restarts the link. Performs autonegotiation if needed.
564 **/
ixgbe_start_mac_link_82598(struct ixgbe_hw * hw,bool autoneg_wait_to_complete)565 int32_t ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
566 bool autoneg_wait_to_complete)
567 {
568 uint32_t autoc_reg;
569 uint32_t links_reg;
570 uint32_t i;
571 int32_t status = IXGBE_SUCCESS;
572
573 DEBUGFUNC("ixgbe_start_mac_link_82598");
574
575 /* Restart link */
576 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
577 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
578 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
579
580 /* Only poll for autoneg to complete if specified to do so */
581 if (autoneg_wait_to_complete) {
582 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
583 IXGBE_AUTOC_LMS_KX4_AN ||
584 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
585 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
586 links_reg = 0; /* Just in case Autoneg time = 0 */
587 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
588 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
589 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
590 break;
591 msec_delay(100);
592 }
593 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
594 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
595 DEBUGOUT("Autonegotiation did not complete.\n");
596 }
597 }
598 }
599
600 /* Add delay to filter out noises during initial link setup */
601 msec_delay(50);
602
603 return status;
604 }
605
606 /**
607 * ixgbe_validate_link_ready - Function looks for phy link
608 * @hw: pointer to hardware structure
609 *
610 * Function indicates success when phy link is available. If phy is not ready
611 * within 5 seconds of MAC indicating link, the function returns error.
612 **/
ixgbe_validate_link_ready(struct ixgbe_hw * hw)613 int32_t ixgbe_validate_link_ready(struct ixgbe_hw *hw)
614 {
615 uint32_t timeout;
616 uint16_t an_reg;
617
618 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
619 return IXGBE_SUCCESS;
620
621 for (timeout = 0;
622 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
623 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
624 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg);
625
626 if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) &&
627 (an_reg & IXGBE_MII_AUTONEG_LINK_UP))
628 break;
629
630 msec_delay(100);
631 }
632
633 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
634 DEBUGOUT("Link was indicated but link is down\n");
635 return IXGBE_ERR_LINK_SETUP;
636 }
637
638 return IXGBE_SUCCESS;
639 }
640
641 /**
642 * ixgbe_check_mac_link_82598 - Get link/speed status
643 * @hw: pointer to hardware structure
644 * @speed: pointer to link speed
645 * @link_up: TRUE is link is up, FALSE otherwise
646 * @link_up_wait_to_complete: bool used to wait for link up or not
647 *
648 * Reads the links register to determine if link is up and the current speed
649 **/
ixgbe_check_mac_link_82598(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up,bool link_up_wait_to_complete)650 int32_t ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
651 ixgbe_link_speed *speed, bool *link_up,
652 bool link_up_wait_to_complete)
653 {
654 uint32_t links_reg;
655 uint32_t i;
656 uint16_t link_reg, adapt_comp_reg;
657
658 DEBUGFUNC("ixgbe_check_mac_link_82598");
659
660 /*
661 * SERDES PHY requires us to read link status from undocumented
662 * register 0xC79F. Bit 0 set indicates link is up/ready; clear
663 * indicates link down. OxC00C is read to check that the XAUI lanes
664 * are active. Bit 0 clear indicates active; set indicates inactive.
665 */
666 if (hw->phy.type == ixgbe_phy_nl) {
667 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
668 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
669 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
670 &adapt_comp_reg);
671 if (link_up_wait_to_complete) {
672 for (i = 0; i < hw->mac.max_link_up_time; i++) {
673 if ((link_reg & 1) &&
674 ((adapt_comp_reg & 1) == 0)) {
675 *link_up = TRUE;
676 break;
677 } else {
678 *link_up = FALSE;
679 }
680 msec_delay(100);
681 hw->phy.ops.read_reg(hw, 0xC79F,
682 IXGBE_TWINAX_DEV,
683 &link_reg);
684 hw->phy.ops.read_reg(hw, 0xC00C,
685 IXGBE_TWINAX_DEV,
686 &adapt_comp_reg);
687 }
688 } else {
689 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
690 *link_up = TRUE;
691 else
692 *link_up = FALSE;
693 }
694
695 if (*link_up == FALSE)
696 goto out;
697 }
698
699 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
700 if (link_up_wait_to_complete) {
701 for (i = 0; i < hw->mac.max_link_up_time; i++) {
702 if (links_reg & IXGBE_LINKS_UP) {
703 *link_up = TRUE;
704 break;
705 } else {
706 *link_up = FALSE;
707 }
708 msec_delay(100);
709 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
710 }
711 } else {
712 if (links_reg & IXGBE_LINKS_UP)
713 *link_up = TRUE;
714 else
715 *link_up = FALSE;
716 }
717
718 if (links_reg & IXGBE_LINKS_SPEED)
719 *speed = IXGBE_LINK_SPEED_10GB_FULL;
720 else
721 *speed = IXGBE_LINK_SPEED_1GB_FULL;
722
723 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == TRUE) &&
724 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
725 *link_up = FALSE;
726
727 out:
728 return IXGBE_SUCCESS;
729 }
730
731 /**
732 * ixgbe_setup_mac_link_82598 - Set MAC link speed
733 * @hw: pointer to hardware structure
734 * @speed: new link speed
735 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
736 *
737 * Set the link speed in the AUTOC register and restarts link.
738 **/
ixgbe_setup_mac_link_82598(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)739 int32_t ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
740 ixgbe_link_speed speed,
741 bool autoneg_wait_to_complete)
742 {
743 bool autoneg = FALSE;
744 int32_t status = IXGBE_SUCCESS;
745 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
746 uint32_t curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
747 uint32_t autoc = curr_autoc;
748 uint32_t link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
749
750 DEBUGFUNC("ixgbe_setup_mac_link_82598");
751
752 /* Check to see if speed passed in is supported. */
753 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
754 speed &= link_capabilities;
755
756 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
757 status = IXGBE_ERR_LINK_SETUP;
758
759 /* Set KX4/KX support according to speed requested */
760 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
761 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
762 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
763 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
764 autoc |= IXGBE_AUTOC_KX4_SUPP;
765 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
766 autoc |= IXGBE_AUTOC_KX_SUPP;
767 if (autoc != curr_autoc)
768 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
769 }
770
771 if (status == IXGBE_SUCCESS) {
772 /*
773 * Setup and restart the link based on the new values in
774 * ixgbe_hw This will write the AUTOC register based on the new
775 * stored values
776 */
777 status = ixgbe_start_mac_link_82598(hw,
778 autoneg_wait_to_complete);
779 }
780
781 return status;
782 }
783
784
785 /**
786 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
787 * @hw: pointer to hardware structure
788 * @speed: new link speed
789 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
790 *
791 * Sets the link speed in the AUTOC register in the MAC and restarts link.
792 **/
ixgbe_setup_copper_link_82598(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)793 int32_t ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
794 ixgbe_link_speed speed,
795 bool autoneg_wait_to_complete)
796 {
797 int32_t status;
798
799 DEBUGFUNC("ixgbe_setup_copper_link_82598");
800
801 /* Setup the PHY according to input speed */
802 status = hw->phy.ops.setup_link_speed(hw, speed,
803 autoneg_wait_to_complete);
804 /* Set up MAC */
805 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
806
807 return status;
808 }
809
810 /**
811 * ixgbe_reset_hw_82598 - Performs hardware reset
812 * @hw: pointer to hardware structure
813 *
814 * Resets the hardware by resetting the transmit and receive units, masks and
815 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
816 * reset.
817 **/
ixgbe_reset_hw_82598(struct ixgbe_hw * hw)818 int32_t ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
819 {
820 int32_t status = IXGBE_SUCCESS;
821 int32_t phy_status = IXGBE_SUCCESS;
822 uint32_t ctrl;
823 uint32_t gheccr;
824 uint32_t i;
825 uint32_t autoc;
826 uint8_t analog_val;
827
828 DEBUGFUNC("ixgbe_reset_hw_82598");
829
830 /* Call adapter stop to disable tx/rx and clear interrupts */
831 status = hw->mac.ops.stop_adapter(hw);
832 if (status != IXGBE_SUCCESS)
833 goto reset_hw_out;
834
835 /*
836 * Power up the Atlas Tx lanes if they are currently powered down.
837 * Atlas Tx lanes are powered down for MAC loopback tests, but
838 * they are not automatically restored on reset.
839 */
840 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
841 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
842 /* Enable Tx Atlas so packets can be transmitted again */
843 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
844 &analog_val);
845 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
846 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
847 analog_val);
848
849 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
850 &analog_val);
851 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
852 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
853 analog_val);
854
855 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
856 &analog_val);
857 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
858 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
859 analog_val);
860
861 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
862 &analog_val);
863 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
864 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
865 analog_val);
866 }
867
868 /* Reset PHY */
869 if (hw->phy.reset_disable == FALSE) {
870 /* PHY ops must be identified and initialized prior to reset */
871
872 /* Init PHY and function pointers, perform SFP setup */
873 phy_status = hw->phy.ops.init(hw);
874 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
875 goto reset_hw_out;
876 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
877 goto mac_reset_top;
878
879 hw->phy.ops.reset(hw);
880 }
881
882 mac_reset_top:
883 /*
884 * Issue global reset to the MAC. This needs to be a SW reset.
885 * If link reset is used, it might reset the MAC when mng is using it
886 */
887 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
888 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
889 IXGBE_WRITE_FLUSH(hw);
890
891 /* Poll for reset bit to self-clear indicating reset is complete */
892 for (i = 0; i < 10; i++) {
893 usec_delay(1);
894 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
895 if (!(ctrl & IXGBE_CTRL_RST))
896 break;
897 }
898 if (ctrl & IXGBE_CTRL_RST) {
899 status = IXGBE_ERR_RESET_FAILED;
900 DEBUGOUT("Reset polling failed to complete.\n");
901 }
902
903 msec_delay(50);
904
905 /*
906 * Double resets are required for recovery from certain error
907 * conditions. Between resets, it is necessary to stall to allow time
908 * for any pending HW events to complete.
909 */
910 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
911 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
912 goto mac_reset_top;
913 }
914
915 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
916 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
917 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
918
919 /*
920 * Store the original AUTOC value if it has not been
921 * stored off yet. Otherwise restore the stored original
922 * AUTOC value since the reset operation sets back to defaults.
923 */
924 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
925 if (hw->mac.orig_link_settings_stored == FALSE) {
926 hw->mac.orig_autoc = autoc;
927 hw->mac.orig_link_settings_stored = TRUE;
928 } else if (autoc != hw->mac.orig_autoc) {
929 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
930 }
931
932 /* Store the permanent mac address */
933 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
934
935 /*
936 * Store MAC address from RAR0, clear receive address registers, and
937 * clear the multicast table
938 */
939 hw->mac.ops.init_rx_addrs(hw);
940
941 reset_hw_out:
942 if (phy_status != IXGBE_SUCCESS)
943 status = phy_status;
944
945 return status;
946 }
947
948 /**
949 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
950 * @hw: pointer to hardware struct
951 * @rar: receive address register index to associate with a VMDq index
952 * @vmdq: VMDq set index
953 **/
ixgbe_set_vmdq_82598(struct ixgbe_hw * hw,uint32_t rar,uint32_t vmdq)954 int32_t ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq)
955 {
956 uint32_t rar_high;
957 uint32_t rar_entries = hw->mac.num_rar_entries;
958
959 DEBUGFUNC("ixgbe_set_vmdq_82598");
960
961 /* Make sure we are using a valid rar index range */
962 if (rar >= rar_entries) {
963 DEBUGOUT1("RAR index %d is out of range.\n", rar);
964 return IXGBE_ERR_INVALID_ARGUMENT;
965 }
966
967 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
968 rar_high &= ~IXGBE_RAH_VIND_MASK;
969 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
970 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
971 return IXGBE_SUCCESS;
972 }
973
974 /**
975 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
976 * @hw: pointer to hardware struct
977 * @rar: receive address register index to associate with a VMDq index
978 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
979 **/
ixgbe_clear_vmdq_82598(struct ixgbe_hw * hw,uint32_t rar,uint32_t vmdq)980 int32_t ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq)
981 {
982 uint32_t rar_high;
983 uint32_t rar_entries = hw->mac.num_rar_entries;
984
985 /* Make sure we are using a valid rar index range */
986 if (rar >= rar_entries) {
987 DEBUGOUT1("RAR index %d is out of range.\n", rar);
988 return IXGBE_ERR_INVALID_ARGUMENT;
989 }
990
991 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
992 if (rar_high & IXGBE_RAH_VIND_MASK) {
993 rar_high &= ~IXGBE_RAH_VIND_MASK;
994 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
995 }
996
997 return IXGBE_SUCCESS;
998 }
999
1000 /**
1001 * ixgbe_set_vfta_82598 - Set VLAN filter table
1002 * @hw: pointer to hardware structure
1003 * @vlan: VLAN id to write to VLAN filter
1004 * @vind: VMDq output index that maps queue to VLAN id in VFTA
1005 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
1006 * @vlvf_bypass: boolean flag - unused
1007 *
1008 * Turn on/off specified VLAN in the VLAN filter table.
1009 **/
ixgbe_set_vfta_82598(struct ixgbe_hw * hw,uint32_t vlan,uint32_t vind,bool vlan_on,bool vlvf_bypass)1010 int32_t ixgbe_set_vfta_82598(struct ixgbe_hw *hw, uint32_t vlan, uint32_t vind,
1011 bool vlan_on, bool vlvf_bypass)
1012 {
1013 uint32_t regindex;
1014 uint32_t bitindex;
1015 uint32_t bits;
1016 uint32_t vftabyte;
1017
1018 DEBUGFUNC("ixgbe_set_vfta_82598");
1019
1020 if (vlan > 4095)
1021 return IXGBE_ERR_PARAM;
1022
1023 /* Determine 32-bit word position in array */
1024 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
1025
1026 /* Determine the location of the (VMD) queue index */
1027 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
1028 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
1029
1030 /* Set the nibble for VMD queue index */
1031 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
1032 bits &= (~(0x0F << bitindex));
1033 bits |= (vind << bitindex);
1034 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
1035
1036 /* Determine the location of the bit for this VLAN id */
1037 bitindex = vlan & 0x1F; /* lower five bits */
1038
1039 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1040 if (vlan_on)
1041 /* Turn on this VLAN id */
1042 bits |= (1 << bitindex);
1043 else
1044 /* Turn off this VLAN id */
1045 bits &= ~(1 << bitindex);
1046 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1047
1048 return IXGBE_SUCCESS;
1049 }
1050
1051 /**
1052 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
1053 * @hw: pointer to hardware structure
1054 *
1055 * Clears the VLAN filer table, and the VMDq index associated with the filter
1056 **/
ixgbe_clear_vfta_82598(struct ixgbe_hw * hw)1057 int32_t ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
1058 {
1059 uint32_t offset;
1060 uint32_t vlanbyte;
1061
1062 DEBUGFUNC("ixgbe_clear_vfta_82598");
1063
1064 for (offset = 0; offset < hw->mac.vft_size; offset++)
1065 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1066
1067 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
1068 for (offset = 0; offset < hw->mac.vft_size; offset++)
1069 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
1070 0);
1071
1072 return IXGBE_SUCCESS;
1073 }
1074
1075 /**
1076 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
1077 * @hw: pointer to hardware structure
1078 * @reg: analog register to read
1079 * @val: read value
1080 *
1081 * Performs read operation to Atlas analog register specified.
1082 **/
ixgbe_read_analog_reg8_82598(struct ixgbe_hw * hw,uint32_t reg,uint8_t * val)1083 int32_t ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val)
1084 {
1085 uint32_t atlas_ctl;
1086
1087 DEBUGFUNC("ixgbe_read_analog_reg8_82598");
1088
1089 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
1090 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1091 IXGBE_WRITE_FLUSH(hw);
1092 usec_delay(10);
1093 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1094 *val = (uint8_t)atlas_ctl;
1095
1096 return IXGBE_SUCCESS;
1097 }
1098
1099 /**
1100 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
1101 * @hw: pointer to hardware structure
1102 * @reg: atlas register to write
1103 * @val: value to write
1104 *
1105 * Performs write operation to Atlas analog register specified.
1106 **/
ixgbe_write_analog_reg8_82598(struct ixgbe_hw * hw,uint32_t reg,uint8_t val)1107 int32_t ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t val)
1108 {
1109 uint32_t atlas_ctl;
1110
1111 DEBUGFUNC("ixgbe_write_analog_reg8_82598");
1112
1113 atlas_ctl = (reg << 8) | val;
1114 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1115 IXGBE_WRITE_FLUSH(hw);
1116 usec_delay(10);
1117
1118 return IXGBE_SUCCESS;
1119 }
1120
1121 /**
1122 * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
1123 * @hw: pointer to hardware structure
1124 * @dev_addr: address to read from
1125 * @byte_offset: byte offset to read from dev_addr
1126 * @eeprom_data: value read
1127 *
1128 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1129 **/
ixgbe_read_i2c_phy_82598(struct ixgbe_hw * hw,uint8_t dev_addr,uint8_t byte_offset,uint8_t * eeprom_data)1130 int32_t ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, uint8_t dev_addr,
1131 uint8_t byte_offset, uint8_t *eeprom_data)
1132 {
1133 int32_t status = IXGBE_SUCCESS;
1134 uint16_t sfp_addr = 0;
1135 uint16_t sfp_data = 0;
1136 uint16_t sfp_stat = 0;
1137 uint16_t gssr;
1138 uint32_t i;
1139
1140 DEBUGFUNC("ixgbe_read_i2c_phy_82598");
1141
1142 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1143 gssr = IXGBE_GSSR_PHY1_SM;
1144 else
1145 gssr = IXGBE_GSSR_PHY0_SM;
1146
1147 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
1148 return IXGBE_ERR_SWFW_SYNC;
1149
1150 if (hw->phy.type == ixgbe_phy_nl) {
1151 /*
1152 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
1153 * 0xC30D. These registers are used to talk to the SFP+
1154 * module's EEPROM through the SDA/SCL (I2C) interface.
1155 */
1156 sfp_addr = (dev_addr << 8) + byte_offset;
1157 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1158 hw->phy.ops.write_reg_mdi(hw,
1159 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1160 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1161 sfp_addr);
1162
1163 /* Poll status */
1164 for (i = 0; i < 100; i++) {
1165 hw->phy.ops.read_reg_mdi(hw,
1166 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1167 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1168 &sfp_stat);
1169 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1170 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1171 break;
1172 msec_delay(10);
1173 }
1174
1175 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1176 DEBUGOUT("EEPROM read did not pass.\n");
1177 status = IXGBE_ERR_SFP_NOT_PRESENT;
1178 goto out;
1179 }
1180
1181 /* Read data */
1182 hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1183 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1184
1185 *eeprom_data = (uint8_t)(sfp_data >> 8);
1186 } else {
1187 status = IXGBE_ERR_PHY;
1188 }
1189
1190 out:
1191 hw->mac.ops.release_swfw_sync(hw, gssr);
1192 return status;
1193 }
1194
1195 /**
1196 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1197 * @hw: pointer to hardware structure
1198 * @byte_offset: EEPROM byte offset to read
1199 * @eeprom_data: value read
1200 *
1201 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1202 **/
ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw * hw,uint8_t byte_offset,uint8_t * eeprom_data)1203 int32_t ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, uint8_t byte_offset,
1204 uint8_t *eeprom_data)
1205 {
1206 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,
1207 byte_offset, eeprom_data);
1208 }
1209
1210 /**
1211 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1212 * @hw: pointer to hardware structure
1213 *
1214 * Determines physical layer capabilities of the current configuration.
1215 **/
ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw * hw)1216 uint64_t ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1217 {
1218 uint64_t physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1219 uint32_t autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1220 uint32_t pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1221 uint32_t pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1222 uint16_t ext_ability = 0;
1223
1224 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598");
1225
1226 hw->phy.ops.identify(hw);
1227
1228 /* Copper PHY must be checked before AUTOC LMS to determine correct
1229 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1230 switch (hw->phy.type) {
1231 case ixgbe_phy_tn:
1232 case ixgbe_phy_cu_unknown:
1233 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1234 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1235 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1236 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1237 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1238 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1239 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1240 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1241 goto out;
1242 default:
1243 break;
1244 }
1245
1246 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1247 case IXGBE_AUTOC_LMS_1G_AN:
1248 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1249 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1250 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1251 else
1252 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1253 break;
1254 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1255 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1256 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1257 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1258 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1259 else /* XAUI */
1260 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1261 break;
1262 case IXGBE_AUTOC_LMS_KX4_AN:
1263 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1264 if (autoc & IXGBE_AUTOC_KX_SUPP)
1265 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1266 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1267 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1268 break;
1269 default:
1270 break;
1271 }
1272
1273 if (hw->phy.type == ixgbe_phy_nl) {
1274 hw->phy.ops.identify_sfp(hw);
1275
1276 switch (hw->phy.sfp_type) {
1277 case ixgbe_sfp_type_da_cu:
1278 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1279 break;
1280 case ixgbe_sfp_type_sr:
1281 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1282 break;
1283 case ixgbe_sfp_type_lr:
1284 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1285 break;
1286 default:
1287 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1288 break;
1289 }
1290 }
1291
1292 switch (hw->device_id) {
1293 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1294 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1295 break;
1296 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1297 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1298 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1299 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1300 break;
1301 case IXGBE_DEV_ID_82598EB_XF_LR:
1302 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1303 break;
1304 default:
1305 break;
1306 }
1307
1308 out:
1309 return physical_layer;
1310 }
1311
1312 /**
1313 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1314 * port devices.
1315 * @hw: pointer to the HW structure
1316 *
1317 * Calls common function and corrects issue with some single port devices
1318 * that enable LAN1 but not LAN0.
1319 **/
ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw * hw)1320 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1321 {
1322 struct ixgbe_bus_info *bus = &hw->bus;
1323 uint16_t pci_gen = 0;
1324 uint16_t pci_ctrl2 = 0;
1325
1326 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie_82598");
1327
1328 ixgbe_set_lan_id_multi_port_pcie(hw);
1329
1330 /* check if LAN0 is disabled */
1331 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1332 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1333
1334 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
1335
1336 /* if LAN0 is completely disabled force function to 0 */
1337 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
1338 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
1339 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
1340
1341 bus->func = 0;
1342 }
1343 }
1344 }
1345
1346 /**
1347 * ixgbe_enable_rx_dma_82598 - Enable the Rx DMA unit
1348 * @hw: pointer to hardware structure
1349 * @regval: register value to write to RXCTRL
1350 *
1351 * Enables the Rx DMA unit
1352 **/
ixgbe_enable_rx_dma_82598(struct ixgbe_hw * hw,uint32_t regval)1353 int32_t ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, uint32_t regval)
1354 {
1355 DEBUGFUNC("ixgbe_enable_rx_dma_82598");
1356
1357 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1358
1359 return IXGBE_SUCCESS;
1360 }
1361