1 /******************************************************************************
2
3 Copyright (c) 2001-2020, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
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20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33
34 #include "ixgbe.h"
35
36 inline u16
ixgbe_read_pci_cfg(struct ixgbe_hw * hw,u32 reg)37 ixgbe_read_pci_cfg(struct ixgbe_hw *hw, u32 reg)
38 {
39 return pci_read_config(((struct ixgbe_softc *)hw->back)->dev, reg, 2);
40 }
41
42 inline void
ixgbe_write_pci_cfg(struct ixgbe_hw * hw,u32 reg,u16 value)43 ixgbe_write_pci_cfg(struct ixgbe_hw *hw, u32 reg, u16 value)
44 {
45 pci_write_config(((struct ixgbe_softc *)hw->back)->dev, reg, value, 2);
46 }
47
48 inline u32
ixgbe_read_reg(struct ixgbe_hw * hw,u32 reg)49 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
50 {
51 return bus_space_read_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
52 ((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle, reg);
53 }
54
55 inline void
ixgbe_write_reg(struct ixgbe_hw * hw,u32 reg,u32 val)56 ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 val)
57 {
58 bus_space_write_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
59 ((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle,
60 reg, val);
61 }
62
63 inline u32
ixgbe_read_reg_array(struct ixgbe_hw * hw,u32 reg,u32 offset)64 ixgbe_read_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset)
65 {
66 return bus_space_read_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
67 ((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle,
68 reg + (offset << 2));
69 }
70
71 inline void
ixgbe_write_reg_array(struct ixgbe_hw * hw,u32 reg,u32 offset,u32 val)72 ixgbe_write_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset, u32 val)
73 {
74 bus_space_write_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
75 ((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle,
76 reg + (offset << 2), val);
77 }
78
79 uint64_t
ixgbe_link_speed_to_baudrate(ixgbe_link_speed speed)80 ixgbe_link_speed_to_baudrate(ixgbe_link_speed speed)
81 {
82 uint64_t baudrate;
83
84 switch (speed) {
85 case IXGBE_LINK_SPEED_10GB_FULL:
86 baudrate = IF_Gbps(10);
87 break;
88 case IXGBE_LINK_SPEED_5GB_FULL:
89 baudrate = IF_Gbps(5);
90 break;
91 case IXGBE_LINK_SPEED_2_5GB_FULL:
92 baudrate = IF_Mbps(2500);
93 break;
94 case IXGBE_LINK_SPEED_1GB_FULL:
95 baudrate = IF_Gbps(1);
96 break;
97 case IXGBE_LINK_SPEED_100_FULL:
98 baudrate = IF_Mbps(100);
99 break;
100 case IXGBE_LINK_SPEED_10_FULL:
101 baudrate = IF_Mbps(10);
102 break;
103 case IXGBE_LINK_SPEED_UNKNOWN:
104 default:
105 baudrate = 0;
106 break;
107 }
108
109 return baudrate;
110 }
111