1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 1999 Brian Fundakowski Feldman
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/kernel.h>
31 #include <sys/systm.h>
32 #include <sys/malloc.h>
33 #include <sys/memrange.h>
34
35 #include <machine/cputypes.h>
36 #include <machine/md_var.h>
37 #include <machine/specialreg.h>
38
39 /*
40 * A K6-2 MTRR is defined as the highest 15 bits having the address, the next
41 * 15 having the mask, the 1st bit being "write-combining" and the 0th bit
42 * being "uncacheable".
43 *
44 * Address Mask WC UC
45 * | XXXXXXXXXXXXXXX | XXXXXXXXXXXXXXX | X | X |
46 *
47 * There are two of these in the 64-bit UWCCR.
48 */
49
50 #define UWCCR 0xc0000085
51
52 #define K6_REG_GET(reg, addr, mask, wc, uc) do { \
53 addr = (reg) & 0xfffe0000; \
54 mask = ((reg) & 0x1fffc) >> 2; \
55 wc = ((reg) & 0x2) >> 1; \
56 uc = (reg) & 0x1; \
57 } while (0)
58
59 #define K6_REG_MAKE(addr, mask, wc, uc) \
60 ((addr) | ((mask) << 2) | ((wc) << 1) | uc)
61
62 static void k6_mrinit(struct mem_range_softc *sc);
63 static int k6_mrset(struct mem_range_softc *, struct mem_range_desc *,
64 int *);
65 static __inline int k6_mrmake(struct mem_range_desc *, u_int32_t *);
66 static void k6_mem_drvinit(void *);
67
68 static struct mem_range_ops k6_mrops =
69 {
70 k6_mrinit,
71 k6_mrset,
72 NULL,
73 NULL
74 };
75
76 static __inline int
k6_mrmake(struct mem_range_desc * desc,u_int32_t * mtrr)77 k6_mrmake(struct mem_range_desc *desc, u_int32_t *mtrr)
78 {
79 u_int32_t len = 0, wc, uc;
80 int bit;
81
82 if (desc->mr_base &~ 0xfffe0000)
83 return (EINVAL);
84 if (desc->mr_len < 131072 || !powerof2(desc->mr_len))
85 return (EINVAL);
86 if (desc->mr_flags &~ (MDF_WRITECOMBINE|MDF_UNCACHEABLE|MDF_FORCE))
87 return (EOPNOTSUPP);
88
89 for (bit = ffs(desc->mr_len >> 17) - 1; bit < 15; bit++)
90 len |= 1 << bit;
91 wc = (desc->mr_flags & MDF_WRITECOMBINE) ? 1 : 0;
92 uc = (desc->mr_flags & MDF_UNCACHEABLE) ? 1 : 0;
93
94 *mtrr = K6_REG_MAKE(desc->mr_base, len, wc, uc);
95 return (0);
96 }
97
98 static void
k6_mrinit(struct mem_range_softc * sc)99 k6_mrinit(struct mem_range_softc *sc)
100 {
101 u_int64_t reg;
102 u_int32_t addr, mask, wc, uc;
103 int d;
104
105 sc->mr_cap = 0;
106 sc->mr_ndesc = 2; /* XXX (BFF) For now, we only have one msr for this */
107 sc->mr_desc = malloc(sc->mr_ndesc * sizeof(struct mem_range_desc),
108 M_MEMDESC, M_NOWAIT | M_ZERO);
109 if (sc->mr_desc == NULL)
110 panic("k6_mrinit: malloc returns NULL");
111
112 reg = rdmsr(UWCCR);
113 for (d = 0; d < sc->mr_ndesc; d++) {
114 u_int32_t one = (reg & (0xffffffff << (32 * d))) >> (32 * d);
115
116 K6_REG_GET(one, addr, mask, wc, uc);
117 sc->mr_desc[d].mr_base = addr;
118 sc->mr_desc[d].mr_len = ffs(mask) << 17;
119 if (wc)
120 sc->mr_desc[d].mr_flags |= MDF_WRITECOMBINE;
121 if (uc)
122 sc->mr_desc[d].mr_flags |= MDF_UNCACHEABLE;
123 }
124
125 printf("K6-family MTRR support enabled (%d registers)\n", sc->mr_ndesc);
126 }
127
128 static int
k6_mrset(struct mem_range_softc * sc,struct mem_range_desc * desc,int * arg)129 k6_mrset(struct mem_range_softc *sc, struct mem_range_desc *desc, int *arg)
130 {
131 u_int64_t reg;
132 u_int32_t mtrr;
133 int error, d;
134
135 switch (*arg) {
136 case MEMRANGE_SET_UPDATE:
137 error = k6_mrmake(desc, &mtrr);
138 if (error)
139 return (error);
140 for (d = 0; d < sc->mr_ndesc; d++) {
141 if (!sc->mr_desc[d].mr_len) {
142 sc->mr_desc[d] = *desc;
143 goto out;
144 }
145 if (sc->mr_desc[d].mr_base == desc->mr_base &&
146 sc->mr_desc[d].mr_len == desc->mr_len)
147 return (EEXIST);
148 }
149 return (ENOSPC);
150 case MEMRANGE_SET_REMOVE:
151 mtrr = 0;
152 for (d = 0; d < sc->mr_ndesc; d++)
153 if (sc->mr_desc[d].mr_base == desc->mr_base &&
154 sc->mr_desc[d].mr_len == desc->mr_len) {
155 bzero(&sc->mr_desc[d], sizeof(sc->mr_desc[d]));
156 goto out;
157 }
158 return (ENOENT);
159 default:
160 return (EOPNOTSUPP);
161 }
162 out:
163 disable_intr();
164 wbinvd();
165 reg = rdmsr(UWCCR);
166 reg &= ~(0xffffffff << (32 * d));
167 reg |= mtrr << (32 * d);
168 wrmsr(UWCCR, reg);
169 wbinvd();
170 enable_intr();
171
172 return (0);
173 }
174
175 static void
k6_mem_drvinit(void * unused)176 k6_mem_drvinit(void *unused)
177 {
178
179 if (cpu_vendor_id != CPU_VENDOR_AMD)
180 return;
181 if ((cpu_id & 0xf00) != 0x500)
182 return;
183 if ((cpu_id & 0xf0) < 0x80 ||
184 ((cpu_id & 0xf0) == 0x80 && (cpu_id & 0xf) <= 0x7))
185 return;
186 mem_range_softc.mr_op = &k6_mrops;
187 }
188 SYSINIT(k6memdev, SI_SUB_DRIVERS, SI_ORDER_FIRST, k6_mem_drvinit, NULL);
189