1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #ifndef __AMDGPU_MES_H__
25 #define __AMDGPU_MES_H__
26
27 #include "amdgpu_irq.h"
28 #include "kgd_kfd_interface.h"
29 #include "amdgpu_gfx.h"
30 #include "amdgpu_doorbell.h"
31 #include <linux/sched/mm.h>
32
33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8
34 #define AMDGPU_MES_MAX_GFX_PIPES 2
35 #define AMDGPU_MES_MAX_SDMA_PIPES 2
36
37 #define AMDGPU_MES_API_VERSION_SHIFT 12
38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24
39
40 #define AMDGPU_MES_VERSION_MASK 0x00000fff
41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000
42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000
43
44 enum amdgpu_mes_priority_level {
45 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0,
46 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1,
47 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2,
48 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3,
49 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4,
50 AMDGPU_MES_PRIORITY_NUM_LEVELS
51 };
52
53 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */
54 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */
55 #define AMDGPU_MES_LOG_BUFFER_SIZE 0x4000 /* Maximu log buffer size for MES */
56
57 struct amdgpu_mes_funcs;
58
59 enum admgpu_mes_pipe {
60 AMDGPU_MES_SCHED_PIPE = 0,
61 AMDGPU_MES_KIQ_PIPE,
62 AMDGPU_MAX_MES_PIPES = 2,
63 };
64
65 struct amdgpu_mes {
66 struct amdgpu_device *adev;
67
68 struct mutex mutex_hidden;
69
70 struct idr pasid_idr;
71 struct idr gang_id_idr;
72 struct idr queue_id_idr;
73 struct ida doorbell_ida;
74
75 spinlock_t queue_id_lock;
76
77 uint32_t sched_version;
78 uint32_t kiq_version;
79
80 uint32_t total_max_queue;
81 uint32_t max_doorbell_slices;
82
83 uint64_t default_process_quantum;
84 uint64_t default_gang_quantum;
85
86 struct amdgpu_ring ring;
87 spinlock_t ring_lock;
88
89 const struct firmware *fw[AMDGPU_MAX_MES_PIPES];
90
91 /* mes ucode */
92 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES];
93 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
94 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES];
95 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES];
96
97 /* mes ucode data */
98 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES];
99 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
100 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES];
101 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES];
102
103 /* eop gpu obj */
104 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES];
105 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES];
106
107 void *mqd_backup[AMDGPU_MAX_MES_PIPES];
108 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES];
109
110 uint32_t vmid_mask_gfxhub;
111 uint32_t vmid_mask_mmhub;
112 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
113 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
114 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
115 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
116 uint32_t sch_ctx_offs;
117 uint64_t sch_ctx_gpu_addr;
118 uint64_t *sch_ctx_ptr;
119 uint32_t query_status_fence_offs;
120 uint64_t query_status_fence_gpu_addr;
121 uint64_t *query_status_fence_ptr;
122 uint32_t read_val_offs;
123 uint64_t read_val_gpu_addr;
124 uint32_t *read_val_ptr;
125
126 uint32_t saved_flags;
127
128 /* initialize kiq pipe */
129 int (*kiq_hw_init)(struct amdgpu_device *adev);
130 int (*kiq_hw_fini)(struct amdgpu_device *adev);
131
132 /* MES doorbells */
133 uint32_t db_start_dw_offset;
134 uint32_t num_mes_dbs;
135 unsigned long *doorbell_bitmap;
136
137 /* MES event log buffer */
138 struct amdgpu_bo *event_log_gpu_obj;
139 uint64_t event_log_gpu_addr;
140 void *event_log_cpu_addr;
141
142 /* ip specific functions */
143 const struct amdgpu_mes_funcs *funcs;
144
145 /* mes resource_1 bo*/
146 struct amdgpu_bo *resource_1;
147 uint64_t resource_1_gpu_addr;
148 void *resource_1_addr;
149
150 };
151
152 struct amdgpu_mes_process {
153 int pasid;
154 struct amdgpu_vm *vm;
155 uint64_t pd_gpu_addr;
156 struct amdgpu_bo *proc_ctx_bo;
157 uint64_t proc_ctx_gpu_addr;
158 void *proc_ctx_cpu_ptr;
159 uint64_t process_quantum;
160 struct list_head gang_list;
161 uint32_t doorbell_index;
162 struct mutex doorbell_lock;
163 };
164
165 struct amdgpu_mes_gang {
166 int gang_id;
167 int priority;
168 int inprocess_gang_priority;
169 int global_priority_level;
170 struct list_head list;
171 struct amdgpu_mes_process *process;
172 struct amdgpu_bo *gang_ctx_bo;
173 uint64_t gang_ctx_gpu_addr;
174 void *gang_ctx_cpu_ptr;
175 uint64_t gang_quantum;
176 struct list_head queue_list;
177 };
178
179 struct amdgpu_mes_queue {
180 struct list_head list;
181 struct amdgpu_mes_gang *gang;
182 int queue_id;
183 uint64_t doorbell_off;
184 struct amdgpu_bo *mqd_obj;
185 void *mqd_cpu_ptr;
186 uint64_t mqd_gpu_addr;
187 uint64_t wptr_gpu_addr;
188 int queue_type;
189 int paging;
190 struct amdgpu_ring *ring;
191 };
192
193 struct amdgpu_mes_queue_properties {
194 int queue_type;
195 uint64_t hqd_base_gpu_addr;
196 uint64_t rptr_gpu_addr;
197 uint64_t wptr_gpu_addr;
198 uint64_t wptr_mc_addr;
199 uint32_t queue_size;
200 uint64_t eop_gpu_addr;
201 uint32_t hqd_pipe_priority;
202 uint32_t hqd_queue_priority;
203 bool paging;
204 struct amdgpu_ring *ring;
205 /* out */
206 uint64_t doorbell_off;
207 };
208
209 struct amdgpu_mes_gang_properties {
210 uint32_t priority;
211 uint32_t gang_quantum;
212 uint32_t inprocess_gang_priority;
213 uint32_t priority_level;
214 int global_priority_level;
215 };
216
217 struct mes_add_queue_input {
218 uint32_t process_id;
219 uint64_t page_table_base_addr;
220 uint64_t process_va_start;
221 uint64_t process_va_end;
222 uint64_t process_quantum;
223 uint64_t process_context_addr;
224 uint64_t gang_quantum;
225 uint64_t gang_context_addr;
226 uint32_t inprocess_gang_priority;
227 uint32_t gang_global_priority_level;
228 uint32_t doorbell_offset;
229 uint64_t mqd_addr;
230 uint64_t wptr_addr;
231 uint64_t wptr_mc_addr;
232 uint32_t queue_type;
233 uint32_t paging;
234 uint32_t gws_base;
235 uint32_t gws_size;
236 uint64_t tba_addr;
237 uint64_t tma_addr;
238 uint32_t trap_en;
239 uint32_t skip_process_ctx_clear;
240 uint32_t is_kfd_process;
241 uint32_t is_aql_queue;
242 uint32_t queue_size;
243 uint32_t exclusively_scheduled;
244 };
245
246 struct mes_remove_queue_input {
247 uint32_t doorbell_offset;
248 uint64_t gang_context_addr;
249 };
250
251 struct mes_map_legacy_queue_input {
252 uint32_t queue_type;
253 uint32_t doorbell_offset;
254 uint32_t pipe_id;
255 uint32_t queue_id;
256 uint64_t mqd_addr;
257 uint64_t wptr_addr;
258 };
259
260 struct mes_unmap_legacy_queue_input {
261 enum amdgpu_unmap_queues_action action;
262 uint32_t queue_type;
263 uint32_t doorbell_offset;
264 uint32_t pipe_id;
265 uint32_t queue_id;
266 uint64_t trail_fence_addr;
267 uint64_t trail_fence_data;
268 };
269
270 struct mes_suspend_gang_input {
271 bool suspend_all_gangs;
272 uint64_t gang_context_addr;
273 uint64_t suspend_fence_addr;
274 uint32_t suspend_fence_value;
275 };
276
277 struct mes_resume_gang_input {
278 bool resume_all_gangs;
279 uint64_t gang_context_addr;
280 };
281
282 enum mes_misc_opcode {
283 MES_MISC_OP_WRITE_REG,
284 MES_MISC_OP_READ_REG,
285 MES_MISC_OP_WRM_REG_WAIT,
286 MES_MISC_OP_WRM_REG_WR_WAIT,
287 MES_MISC_OP_SET_SHADER_DEBUGGER,
288 };
289
290 struct mes_misc_op_input {
291 enum mes_misc_opcode op;
292
293 union {
294 struct {
295 uint32_t reg_offset;
296 uint64_t buffer_addr;
297 } read_reg;
298
299 struct {
300 uint32_t reg_offset;
301 uint32_t reg_value;
302 } write_reg;
303
304 struct {
305 uint32_t ref;
306 uint32_t mask;
307 uint32_t reg0;
308 uint32_t reg1;
309 } wrm_reg;
310
311 struct {
312 uint64_t process_context_addr;
313 union {
314 struct {
315 uint32_t single_memop : 1;
316 uint32_t single_alu_op : 1;
317 uint32_t reserved: 29;
318 uint32_t process_ctx_flush: 1;
319 };
320 uint32_t u32all;
321 } flags;
322 uint32_t spi_gdbg_per_vmid_cntl;
323 uint32_t tcp_watch_cntl[4];
324 uint32_t trap_en;
325 } set_shader_debugger;
326 };
327 };
328
329 struct amdgpu_mes_funcs {
330 int (*add_hw_queue)(struct amdgpu_mes *mes,
331 struct mes_add_queue_input *input);
332
333 int (*remove_hw_queue)(struct amdgpu_mes *mes,
334 struct mes_remove_queue_input *input);
335
336 int (*map_legacy_queue)(struct amdgpu_mes *mes,
337 struct mes_map_legacy_queue_input *input);
338
339 int (*unmap_legacy_queue)(struct amdgpu_mes *mes,
340 struct mes_unmap_legacy_queue_input *input);
341
342 int (*suspend_gang)(struct amdgpu_mes *mes,
343 struct mes_suspend_gang_input *input);
344
345 int (*resume_gang)(struct amdgpu_mes *mes,
346 struct mes_resume_gang_input *input);
347
348 int (*misc_op)(struct amdgpu_mes *mes,
349 struct mes_misc_op_input *input);
350 };
351
352 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
353 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev))
354
355 signed long amdgpu_mes_fence_wait_polling(u64 *fence,
356 u64 wait_seq,
357 signed long timeout);
358
359 int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs);
360
361 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe);
362 int amdgpu_mes_init(struct amdgpu_device *adev);
363 void amdgpu_mes_fini(struct amdgpu_device *adev);
364
365 int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid,
366 struct amdgpu_vm *vm);
367 void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid);
368
369 int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid,
370 struct amdgpu_mes_gang_properties *gprops,
371 int *gang_id);
372 int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id);
373
374 int amdgpu_mes_suspend(struct amdgpu_device *adev);
375 int amdgpu_mes_resume(struct amdgpu_device *adev);
376
377 int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id,
378 struct amdgpu_mes_queue_properties *qprops,
379 int *queue_id);
380 int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id);
381
382 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,
383 struct amdgpu_ring *ring);
384 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
385 struct amdgpu_ring *ring,
386 enum amdgpu_unmap_queues_action action,
387 u64 gpu_addr, u64 seq);
388
389 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);
390 int amdgpu_mes_wreg(struct amdgpu_device *adev,
391 uint32_t reg, uint32_t val);
392 int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
393 uint32_t val, uint32_t mask);
394 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
395 uint32_t reg0, uint32_t reg1,
396 uint32_t ref, uint32_t mask);
397 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,
398 uint64_t process_context_addr,
399 uint32_t spi_gdbg_per_vmid_cntl,
400 const uint32_t *tcp_watch_cntl,
401 uint32_t flags,
402 bool trap_en);
403 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,
404 uint64_t process_context_addr);
405 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
406 int queue_type, int idx,
407 struct amdgpu_mes_ctx_data *ctx_data,
408 struct amdgpu_ring **out);
409 void amdgpu_mes_remove_ring(struct amdgpu_device *adev,
410 struct amdgpu_ring *ring);
411
412 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,
413 enum amdgpu_mes_priority_level prio);
414
415 int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev,
416 struct amdgpu_mes_ctx_data *ctx_data);
417 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data);
418 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev,
419 struct amdgpu_vm *vm,
420 struct amdgpu_mes_ctx_data *ctx_data);
421 int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev,
422 struct amdgpu_mes_ctx_data *ctx_data);
423
424 int amdgpu_mes_self_test(struct amdgpu_device *adev);
425
426 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev);
427
428 /*
429 * MES lock can be taken in MMU notifiers.
430 *
431 * A bit more detail about why to set no-FS reclaim with MES lock:
432 *
433 * The purpose of the MMU notifier is to stop GPU access to memory so
434 * that the Linux VM subsystem can move pages around safely. This is
435 * done by preempting user mode queues for the affected process. When
436 * MES is used, MES lock needs to be taken to preempt the queues.
437 *
438 * The MMU notifier callback entry point in the driver is
439 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from
440 * there is:
441 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm ->
442 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues
443 *
444 * The last part of the chain is a function pointer where we take the
445 * MES lock.
446 *
447 * The problem with taking locks in the MMU notifier is, that MMU
448 * notifiers can be called in reclaim-FS context. That's where the
449 * kernel frees up pages to make room for new page allocations under
450 * memory pressure. While we are running in reclaim-FS context, we must
451 * not trigger another memory reclaim operation because that would
452 * recursively reenter the reclaim code and cause a deadlock. The
453 * memalloc_nofs_save/restore calls guarantee that.
454 *
455 * In addition we also need to avoid lock dependencies on other locks taken
456 * under the MES lock, for example reservation locks. Here is a possible
457 * scenario of a deadlock:
458 * Thread A: takes and holds reservation lock | triggers reclaim-FS |
459 * MMU notifier | blocks trying to take MES lock
460 * Thread B: takes and holds MES lock | blocks trying to take reservation lock
461 *
462 * In this scenario Thread B gets involved in a deadlock even without
463 * triggering a reclaim-FS operation itself.
464 * To fix this and break the lock dependency chain you'd need to either:
465 * 1. protect reservation locks with memalloc_nofs_save/restore, or
466 * 2. avoid taking reservation locks under the MES lock.
467 *
468 * Reservation locks are taken all over the kernel in different subsystems, we
469 * have no control over them and their lock dependencies.So the only workable
470 * solution is to avoid taking other locks under the MES lock.
471 * As a result, make sure no reclaim-FS happens while holding this lock anywhere
472 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context.
473 */
amdgpu_mes_lock(struct amdgpu_mes * mes)474 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes)
475 {
476 mutex_lock(&mes->mutex_hidden);
477 mes->saved_flags = memalloc_noreclaim_save();
478 }
479
amdgpu_mes_unlock(struct amdgpu_mes * mes)480 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes)
481 {
482 memalloc_noreclaim_restore(mes->saved_flags);
483 mutex_unlock(&mes->mutex_hidden);
484 }
485 #endif /* __AMDGPU_MES_H__ */
486