1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Microchip KSZ8795 switch driver
4 *
5 * Copyright (C) 2017 Microchip Technology Inc.
6 * Tristram Ha <Tristram.Ha@microchip.com>
7 */
8
9 #include <linux/bitfield.h>
10 #include <linux/delay.h>
11 #include <linux/export.h>
12 #include <linux/gpio.h>
13 #include <linux/if_vlan.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/platform_data/microchip-ksz.h>
17 #include <linux/phy.h>
18 #include <linux/etherdevice.h>
19 #include <linux/if_bridge.h>
20 #include <linux/micrel_phy.h>
21 #include <net/dsa.h>
22 #include <net/switchdev.h>
23 #include <linux/phylink.h>
24
25 #include "ksz_common.h"
26 #include "ksz8795_reg.h"
27 #include "ksz8.h"
28
ksz_cfg(struct ksz_device * dev,u32 addr,u8 bits,bool set)29 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
30 {
31 regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0);
32 }
33
ksz_port_cfg(struct ksz_device * dev,int port,int offset,u8 bits,bool set)34 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
35 bool set)
36 {
37 regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset),
38 bits, set ? bits : 0);
39 }
40
ksz8_ind_write8(struct ksz_device * dev,u8 table,u16 addr,u8 data)41 static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data)
42 {
43 const u16 *regs;
44 u16 ctrl_addr;
45 int ret = 0;
46
47 regs = dev->info->regs;
48
49 mutex_lock(&dev->alu_mutex);
50
51 ctrl_addr = IND_ACC_TABLE(table) | addr;
52 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
53 if (!ret)
54 ret = ksz_write8(dev, regs[REG_IND_BYTE], data);
55
56 mutex_unlock(&dev->alu_mutex);
57
58 return ret;
59 }
60
ksz8_reset_switch(struct ksz_device * dev)61 int ksz8_reset_switch(struct ksz_device *dev)
62 {
63 if (ksz_is_ksz88x3(dev)) {
64 /* reset switch */
65 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
66 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true);
67 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
68 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false);
69 } else {
70 /* reset switch */
71 ksz_write8(dev, REG_POWER_MANAGEMENT_1,
72 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S);
73 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0);
74 }
75
76 return 0;
77 }
78
ksz8863_change_mtu(struct ksz_device * dev,int frame_size)79 static int ksz8863_change_mtu(struct ksz_device *dev, int frame_size)
80 {
81 u8 ctrl2 = 0;
82
83 if (frame_size <= KSZ8_LEGAL_PACKET_SIZE)
84 ctrl2 |= KSZ8863_LEGAL_PACKET_ENABLE;
85 else if (frame_size > KSZ8863_NORMAL_PACKET_SIZE)
86 ctrl2 |= KSZ8863_HUGE_PACKET_ENABLE;
87
88 return ksz_rmw8(dev, REG_SW_CTRL_2, KSZ8863_LEGAL_PACKET_ENABLE |
89 KSZ8863_HUGE_PACKET_ENABLE, ctrl2);
90 }
91
ksz8795_change_mtu(struct ksz_device * dev,int frame_size)92 static int ksz8795_change_mtu(struct ksz_device *dev, int frame_size)
93 {
94 u8 ctrl1 = 0, ctrl2 = 0;
95 int ret;
96
97 if (frame_size > KSZ8_LEGAL_PACKET_SIZE)
98 ctrl2 |= SW_LEGAL_PACKET_DISABLE;
99 if (frame_size > KSZ8863_NORMAL_PACKET_SIZE)
100 ctrl1 |= SW_HUGE_PACKET;
101
102 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_HUGE_PACKET, ctrl1);
103 if (ret)
104 return ret;
105
106 return ksz_rmw8(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, ctrl2);
107 }
108
ksz8_change_mtu(struct ksz_device * dev,int port,int mtu)109 int ksz8_change_mtu(struct ksz_device *dev, int port, int mtu)
110 {
111 u16 frame_size;
112
113 if (!dsa_is_cpu_port(dev->ds, port))
114 return 0;
115
116 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
117
118 switch (dev->chip_id) {
119 case KSZ8795_CHIP_ID:
120 case KSZ8794_CHIP_ID:
121 case KSZ8765_CHIP_ID:
122 return ksz8795_change_mtu(dev, frame_size);
123 case KSZ8830_CHIP_ID:
124 return ksz8863_change_mtu(dev, frame_size);
125 }
126
127 return -EOPNOTSUPP;
128 }
129
ksz8_port_queue_split(struct ksz_device * dev,int port,int queues)130 static int ksz8_port_queue_split(struct ksz_device *dev, int port, int queues)
131 {
132 u8 mask_4q, mask_2q;
133 u8 reg_4q, reg_2q;
134 u8 data_4q = 0;
135 u8 data_2q = 0;
136 int ret;
137
138 if (ksz_is_ksz88x3(dev)) {
139 mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN;
140 mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN;
141 reg_4q = REG_PORT_CTRL_0;
142 reg_2q = REG_PORT_CTRL_2;
143
144 /* KSZ8795 family switches have Weighted Fair Queueing (WFQ)
145 * enabled by default. Enable it for KSZ8873 family switches
146 * too. Default value for KSZ8873 family is strict priority,
147 * which should be enabled by using TC_SETUP_QDISC_ETS, not
148 * by default.
149 */
150 ret = ksz_rmw8(dev, REG_SW_CTRL_3, WEIGHTED_FAIR_QUEUE_ENABLE,
151 WEIGHTED_FAIR_QUEUE_ENABLE);
152 if (ret)
153 return ret;
154 } else {
155 mask_4q = KSZ8795_PORT_4QUEUE_SPLIT_EN;
156 mask_2q = KSZ8795_PORT_2QUEUE_SPLIT_EN;
157 reg_4q = REG_PORT_CTRL_13;
158 reg_2q = REG_PORT_CTRL_0;
159
160 /* TODO: this is legacy from initial KSZ8795 driver, should be
161 * moved to appropriate place in the future.
162 */
163 ret = ksz_rmw8(dev, REG_SW_CTRL_19,
164 SW_OUT_RATE_LIMIT_QUEUE_BASED,
165 SW_OUT_RATE_LIMIT_QUEUE_BASED);
166 if (ret)
167 return ret;
168 }
169
170 if (queues == 4)
171 data_4q = mask_4q;
172 else if (queues == 2)
173 data_2q = mask_2q;
174
175 ret = ksz_prmw8(dev, port, reg_4q, mask_4q, data_4q);
176 if (ret)
177 return ret;
178
179 return ksz_prmw8(dev, port, reg_2q, mask_2q, data_2q);
180 }
181
ksz8_all_queues_split(struct ksz_device * dev,int queues)182 int ksz8_all_queues_split(struct ksz_device *dev, int queues)
183 {
184 struct dsa_switch *ds = dev->ds;
185 const struct dsa_port *dp;
186
187 dsa_switch_for_each_port(dp, ds) {
188 int ret = ksz8_port_queue_split(dev, dp->index, queues);
189
190 if (ret)
191 return ret;
192 }
193
194 return 0;
195 }
196
ksz8_r_mib_cnt(struct ksz_device * dev,int port,u16 addr,u64 * cnt)197 void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt)
198 {
199 const u32 *masks;
200 const u16 *regs;
201 u16 ctrl_addr;
202 u32 data;
203 u8 check;
204 int loop;
205
206 masks = dev->info->masks;
207 regs = dev->info->regs;
208
209 ctrl_addr = addr + dev->info->reg_mib_cnt * port;
210 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
211
212 mutex_lock(&dev->alu_mutex);
213 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
214
215 /* It is almost guaranteed to always read the valid bit because of
216 * slow SPI speed.
217 */
218 for (loop = 2; loop > 0; loop--) {
219 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
220
221 if (check & masks[MIB_COUNTER_VALID]) {
222 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
223 if (check & masks[MIB_COUNTER_OVERFLOW])
224 *cnt += MIB_COUNTER_VALUE + 1;
225 *cnt += data & MIB_COUNTER_VALUE;
226 break;
227 }
228 }
229 mutex_unlock(&dev->alu_mutex);
230 }
231
ksz8795_r_mib_pkt(struct ksz_device * dev,int port,u16 addr,u64 * dropped,u64 * cnt)232 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
233 u64 *dropped, u64 *cnt)
234 {
235 const u32 *masks;
236 const u16 *regs;
237 u16 ctrl_addr;
238 u32 data;
239 u8 check;
240 int loop;
241
242 masks = dev->info->masks;
243 regs = dev->info->regs;
244
245 addr -= dev->info->reg_mib_cnt;
246 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port;
247 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0;
248 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
249
250 mutex_lock(&dev->alu_mutex);
251 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
252
253 /* It is almost guaranteed to always read the valid bit because of
254 * slow SPI speed.
255 */
256 for (loop = 2; loop > 0; loop--) {
257 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
258
259 if (check & masks[MIB_COUNTER_VALID]) {
260 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
261 if (addr < 2) {
262 u64 total;
263
264 total = check & MIB_TOTAL_BYTES_H;
265 total <<= 32;
266 *cnt += total;
267 *cnt += data;
268 if (check & masks[MIB_COUNTER_OVERFLOW]) {
269 total = MIB_TOTAL_BYTES_H + 1;
270 total <<= 32;
271 *cnt += total;
272 }
273 } else {
274 if (check & masks[MIB_COUNTER_OVERFLOW])
275 *cnt += MIB_PACKET_DROPPED + 1;
276 *cnt += data & MIB_PACKET_DROPPED;
277 }
278 break;
279 }
280 }
281 mutex_unlock(&dev->alu_mutex);
282 }
283
ksz8863_r_mib_pkt(struct ksz_device * dev,int port,u16 addr,u64 * dropped,u64 * cnt)284 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
285 u64 *dropped, u64 *cnt)
286 {
287 u32 *last = (u32 *)dropped;
288 const u16 *regs;
289 u16 ctrl_addr;
290 u32 data;
291 u32 cur;
292
293 regs = dev->info->regs;
294
295 addr -= dev->info->reg_mib_cnt;
296 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 :
297 KSZ8863_MIB_PACKET_DROPPED_RX_0;
298 ctrl_addr += port;
299 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
300
301 mutex_lock(&dev->alu_mutex);
302 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
303 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
304 mutex_unlock(&dev->alu_mutex);
305
306 data &= MIB_PACKET_DROPPED;
307 cur = last[addr];
308 if (data != cur) {
309 last[addr] = data;
310 if (data < cur)
311 data += MIB_PACKET_DROPPED + 1;
312 data -= cur;
313 *cnt += data;
314 }
315 }
316
ksz8_r_mib_pkt(struct ksz_device * dev,int port,u16 addr,u64 * dropped,u64 * cnt)317 void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
318 u64 *dropped, u64 *cnt)
319 {
320 if (ksz_is_ksz88x3(dev))
321 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt);
322 else
323 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt);
324 }
325
ksz8_freeze_mib(struct ksz_device * dev,int port,bool freeze)326 void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze)
327 {
328 if (ksz_is_ksz88x3(dev))
329 return;
330
331 /* enable the port for flush/freeze function */
332 if (freeze)
333 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
334 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze);
335
336 /* disable the port after freeze is done */
337 if (!freeze)
338 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
339 }
340
ksz8_port_init_cnt(struct ksz_device * dev,int port)341 void ksz8_port_init_cnt(struct ksz_device *dev, int port)
342 {
343 struct ksz_port_mib *mib = &dev->ports[port].mib;
344 u64 *dropped;
345
346 if (!ksz_is_ksz88x3(dev)) {
347 /* flush all enabled port MIB counters */
348 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
349 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true);
350 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
351 }
352
353 mib->cnt_ptr = 0;
354
355 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
356 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
357 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
358 &mib->counters[mib->cnt_ptr]);
359 ++mib->cnt_ptr;
360 }
361
362 /* last one in storage */
363 dropped = &mib->counters[dev->info->mib_cnt];
364
365 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
366 while (mib->cnt_ptr < dev->info->mib_cnt) {
367 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
368 dropped, &mib->counters[mib->cnt_ptr]);
369 ++mib->cnt_ptr;
370 }
371 }
372
ksz8_r_table(struct ksz_device * dev,int table,u16 addr,u64 * data)373 static int ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data)
374 {
375 const u16 *regs;
376 u16 ctrl_addr;
377 int ret;
378
379 regs = dev->info->regs;
380
381 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
382
383 mutex_lock(&dev->alu_mutex);
384 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
385 if (ret)
386 goto unlock_alu;
387
388 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], data);
389 unlock_alu:
390 mutex_unlock(&dev->alu_mutex);
391
392 return ret;
393 }
394
ksz8_w_table(struct ksz_device * dev,int table,u16 addr,u64 data)395 static int ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data)
396 {
397 const u16 *regs;
398 u16 ctrl_addr;
399 int ret;
400
401 regs = dev->info->regs;
402
403 ctrl_addr = IND_ACC_TABLE(table) | addr;
404
405 mutex_lock(&dev->alu_mutex);
406 ret = ksz_write64(dev, regs[REG_IND_DATA_HI], data);
407 if (ret)
408 goto unlock_alu;
409
410 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
411 unlock_alu:
412 mutex_unlock(&dev->alu_mutex);
413
414 return ret;
415 }
416
ksz8_valid_dyn_entry(struct ksz_device * dev,u8 * data)417 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data)
418 {
419 int timeout = 100;
420 const u32 *masks;
421 const u16 *regs;
422 int ret;
423
424 masks = dev->info->masks;
425 regs = dev->info->regs;
426
427 do {
428 ret = ksz_read8(dev, regs[REG_IND_DATA_CHECK], data);
429 if (ret)
430 return ret;
431
432 timeout--;
433 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout);
434
435 /* Entry is not ready for accessing. */
436 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY])
437 return -ETIMEDOUT;
438
439 /* Entry is ready for accessing. */
440 return ksz_read8(dev, regs[REG_IND_DATA_8], data);
441 }
442
ksz8_r_dyn_mac_table(struct ksz_device * dev,u16 addr,u8 * mac_addr,u8 * fid,u8 * src_port,u16 * entries)443 static int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr,
444 u8 *fid, u8 *src_port, u16 *entries)
445 {
446 u32 data_hi, data_lo;
447 const u8 *shifts;
448 const u32 *masks;
449 const u16 *regs;
450 u16 ctrl_addr;
451 u64 buf = 0;
452 u8 data;
453 int cnt;
454 int ret;
455
456 shifts = dev->info->shifts;
457 masks = dev->info->masks;
458 regs = dev->info->regs;
459
460 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
461
462 mutex_lock(&dev->alu_mutex);
463 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
464 if (ret)
465 goto unlock_alu;
466
467 ret = ksz8_valid_dyn_entry(dev, &data);
468 if (ret)
469 goto unlock_alu;
470
471 if (data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY]) {
472 *entries = 0;
473 goto unlock_alu;
474 }
475
476 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], &buf);
477 if (ret)
478 goto unlock_alu;
479
480 data_hi = (u32)(buf >> 32);
481 data_lo = (u32)buf;
482
483 /* Check out how many valid entry in the table. */
484 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H];
485 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H];
486 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >>
487 shifts[DYNAMIC_MAC_ENTRIES];
488 *entries = cnt + 1;
489
490 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >>
491 shifts[DYNAMIC_MAC_FID];
492 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >>
493 shifts[DYNAMIC_MAC_SRC_PORT];
494
495 mac_addr[5] = (u8)data_lo;
496 mac_addr[4] = (u8)(data_lo >> 8);
497 mac_addr[3] = (u8)(data_lo >> 16);
498 mac_addr[2] = (u8)(data_lo >> 24);
499
500 mac_addr[1] = (u8)data_hi;
501 mac_addr[0] = (u8)(data_hi >> 8);
502
503 unlock_alu:
504 mutex_unlock(&dev->alu_mutex);
505
506 return ret;
507 }
508
ksz8_r_sta_mac_table(struct ksz_device * dev,u16 addr,struct alu_struct * alu,bool * valid)509 static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr,
510 struct alu_struct *alu, bool *valid)
511 {
512 u32 data_hi, data_lo;
513 const u8 *shifts;
514 const u32 *masks;
515 u64 data;
516 int ret;
517
518 shifts = dev->info->shifts;
519 masks = dev->info->masks;
520
521 ret = ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data);
522 if (ret)
523 return ret;
524
525 data_hi = data >> 32;
526 data_lo = (u32)data;
527
528 if (!(data_hi & (masks[STATIC_MAC_TABLE_VALID] |
529 masks[STATIC_MAC_TABLE_OVERRIDE]))) {
530 *valid = false;
531 return 0;
532 }
533
534 alu->mac[5] = (u8)data_lo;
535 alu->mac[4] = (u8)(data_lo >> 8);
536 alu->mac[3] = (u8)(data_lo >> 16);
537 alu->mac[2] = (u8)(data_lo >> 24);
538 alu->mac[1] = (u8)data_hi;
539 alu->mac[0] = (u8)(data_hi >> 8);
540 alu->port_forward =
541 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >>
542 shifts[STATIC_MAC_FWD_PORTS];
543 alu->is_override = (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0;
544
545 /* KSZ8795 family switches have STATIC_MAC_TABLE_USE_FID and
546 * STATIC_MAC_TABLE_FID definitions off by 1 when doing read on the
547 * static MAC table compared to doing write.
548 */
549 if (ksz_is_ksz87xx(dev))
550 data_hi >>= 1;
551 alu->is_static = true;
552 alu->is_use_fid = (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0;
553 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >>
554 shifts[STATIC_MAC_FID];
555
556 *valid = true;
557
558 return 0;
559 }
560
ksz8_w_sta_mac_table(struct ksz_device * dev,u16 addr,struct alu_struct * alu)561 static int ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr,
562 struct alu_struct *alu)
563 {
564 u32 data_hi, data_lo;
565 const u8 *shifts;
566 const u32 *masks;
567 u64 data;
568
569 shifts = dev->info->shifts;
570 masks = dev->info->masks;
571
572 data_lo = ((u32)alu->mac[2] << 24) |
573 ((u32)alu->mac[3] << 16) |
574 ((u32)alu->mac[4] << 8) | alu->mac[5];
575 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1];
576 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS];
577
578 if (alu->is_override)
579 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE];
580 if (alu->is_use_fid) {
581 data_hi |= masks[STATIC_MAC_TABLE_USE_FID];
582 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID];
583 }
584 if (alu->is_static)
585 data_hi |= masks[STATIC_MAC_TABLE_VALID];
586 else
587 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE];
588
589 data = (u64)data_hi << 32 | data_lo;
590
591 return ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data);
592 }
593
ksz8_from_vlan(struct ksz_device * dev,u32 vlan,u8 * fid,u8 * member,u8 * valid)594 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid,
595 u8 *member, u8 *valid)
596 {
597 const u8 *shifts;
598 const u32 *masks;
599
600 shifts = dev->info->shifts;
601 masks = dev->info->masks;
602
603 *fid = vlan & masks[VLAN_TABLE_FID];
604 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >>
605 shifts[VLAN_TABLE_MEMBERSHIP_S];
606 *valid = !!(vlan & masks[VLAN_TABLE_VALID]);
607 }
608
ksz8_to_vlan(struct ksz_device * dev,u8 fid,u8 member,u8 valid,u16 * vlan)609 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid,
610 u16 *vlan)
611 {
612 const u8 *shifts;
613 const u32 *masks;
614
615 shifts = dev->info->shifts;
616 masks = dev->info->masks;
617
618 *vlan = fid;
619 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S];
620 if (valid)
621 *vlan |= masks[VLAN_TABLE_VALID];
622 }
623
ksz8_r_vlan_entries(struct ksz_device * dev,u16 addr)624 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr)
625 {
626 const u8 *shifts;
627 u64 data;
628 int i;
629
630 shifts = dev->info->shifts;
631
632 ksz8_r_table(dev, TABLE_VLAN, addr, &data);
633 addr *= 4;
634 for (i = 0; i < 4; i++) {
635 dev->vlan_cache[addr + i].table[0] = (u16)data;
636 data >>= shifts[VLAN_TABLE];
637 }
638 }
639
ksz8_r_vlan_table(struct ksz_device * dev,u16 vid,u16 * vlan)640 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan)
641 {
642 int index;
643 u16 *data;
644 u16 addr;
645 u64 buf;
646
647 data = (u16 *)&buf;
648 addr = vid / 4;
649 index = vid & 3;
650 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
651 *vlan = data[index];
652 }
653
ksz8_w_vlan_table(struct ksz_device * dev,u16 vid,u16 vlan)654 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan)
655 {
656 int index;
657 u16 *data;
658 u16 addr;
659 u64 buf;
660
661 data = (u16 *)&buf;
662 addr = vid / 4;
663 index = vid & 3;
664 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
665 data[index] = vlan;
666 dev->vlan_cache[vid].table[0] = vlan;
667 ksz8_w_table(dev, TABLE_VLAN, addr, buf);
668 }
669
670 /**
671 * ksz879x_get_loopback - KSZ879x specific function to get loopback
672 * configuration status for a specific port
673 * @dev: Pointer to the device structure
674 * @port: Port number to query
675 * @val: Pointer to store the result
676 *
677 * This function reads the SMI registers to determine whether loopback mode
678 * is enabled for a specific port.
679 *
680 * Return: 0 on success, error code on failure.
681 */
ksz879x_get_loopback(struct ksz_device * dev,u16 port,u16 * val)682 static int ksz879x_get_loopback(struct ksz_device *dev, u16 port,
683 u16 *val)
684 {
685 u8 stat3;
686 int ret;
687
688 ret = ksz_pread8(dev, port, REG_PORT_STATUS_3, &stat3);
689 if (ret)
690 return ret;
691
692 if (stat3 & PORT_PHY_LOOPBACK)
693 *val |= BMCR_LOOPBACK;
694
695 return 0;
696 }
697
698 /**
699 * ksz879x_set_loopback - KSZ879x specific function to set loopback mode for
700 * a specific port
701 * @dev: Pointer to the device structure.
702 * @port: Port number to modify.
703 * @val: Value indicating whether to enable or disable loopback mode.
704 *
705 * This function translates loopback bit of the BMCR register into the
706 * corresponding hardware register bit value and writes it to the SMI interface.
707 *
708 * Return: 0 on success, error code on failure.
709 */
ksz879x_set_loopback(struct ksz_device * dev,u16 port,u16 val)710 static int ksz879x_set_loopback(struct ksz_device *dev, u16 port, u16 val)
711 {
712 u8 stat3 = 0;
713
714 if (val & BMCR_LOOPBACK)
715 stat3 |= PORT_PHY_LOOPBACK;
716
717 return ksz_prmw8(dev, port, REG_PORT_STATUS_3, PORT_PHY_LOOPBACK,
718 stat3);
719 }
720
721 /**
722 * ksz8_r_phy_ctrl - Translates and reads from the SMI interface to a MIIM PHY
723 * Control register (Reg. 31).
724 * @dev: The KSZ device instance.
725 * @port: The port number to be read.
726 * @val: The value read from the SMI interface.
727 *
728 * This function reads the SMI interface and translates the hardware register
729 * bit values into their corresponding control settings for a MIIM PHY Control
730 * register.
731 *
732 * Return: 0 on success, error code on failure.
733 */
ksz8_r_phy_ctrl(struct ksz_device * dev,int port,u16 * val)734 static int ksz8_r_phy_ctrl(struct ksz_device *dev, int port, u16 *val)
735 {
736 const u16 *regs = dev->info->regs;
737 u8 reg_val;
738 int ret;
739
740 *val = 0;
741
742 ret = ksz_pread8(dev, port, regs[P_LINK_STATUS], ®_val);
743 if (ret < 0)
744 return ret;
745
746 if (reg_val & PORT_MDIX_STATUS)
747 *val |= KSZ886X_CTRL_MDIX_STAT;
748
749 ret = ksz_pread8(dev, port, REG_PORT_LINK_MD_CTRL, ®_val);
750 if (ret < 0)
751 return ret;
752
753 if (reg_val & PORT_FORCE_LINK)
754 *val |= KSZ886X_CTRL_FORCE_LINK;
755
756 if (reg_val & PORT_POWER_SAVING)
757 *val |= KSZ886X_CTRL_PWRSAVE;
758
759 if (reg_val & PORT_PHY_REMOTE_LOOPBACK)
760 *val |= KSZ886X_CTRL_REMOTE_LOOPBACK;
761
762 return 0;
763 }
764
765 /**
766 * ksz8_r_phy_bmcr - Translates and reads from the SMI interface to a MIIM PHY
767 * Basic mode control register (Reg. 0).
768 * @dev: The KSZ device instance.
769 * @port: The port number to be read.
770 * @val: The value read from the SMI interface.
771 *
772 * This function reads the SMI interface and translates the hardware register
773 * bit values into their corresponding control settings for a MIIM PHY Basic
774 * mode control register.
775 *
776 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873
777 * -------------------------------------------------------------------
778 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit
779 * ----------------------------+-----------------------------+----------------
780 * Bit 15 - Soft Reset | 0xF/4 | Not supported
781 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY)
782 * Bit 13 - Force 100 | 0xC/6 = 0xC/6
783 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7
784 * Bit 11 - Power Down | 0xD/3 = 0xD/3
785 * Bit 10 - PHY Isolate | 0xF/5 | Not supported
786 * Bit 9 - Restart AN | 0xD/5 = 0xD/5
787 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5
788 * Bit 7 - Collision Test/Res. | Not supported | Not supported
789 * Bit 6 - Reserved | Not supported | Not supported
790 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7
791 * Bit 4 - Force MDI | 0xD/1 = 0xD/1
792 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2
793 * Bit 2 - Disable Far-End F. | ???? | 0xD/4
794 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6
795 * Bit 0 - Disable LED | 0xD/7 = 0xD/7
796 * -------------------------------------------------------------------
797 *
798 * Return: 0 on success, error code on failure.
799 */
ksz8_r_phy_bmcr(struct ksz_device * dev,u16 port,u16 * val)800 static int ksz8_r_phy_bmcr(struct ksz_device *dev, u16 port, u16 *val)
801 {
802 const u16 *regs = dev->info->regs;
803 u8 restart, speed, ctrl;
804 int ret;
805
806 *val = 0;
807
808 ret = ksz_pread8(dev, port, regs[P_NEG_RESTART_CTRL], &restart);
809 if (ret)
810 return ret;
811
812 ret = ksz_pread8(dev, port, regs[P_SPEED_STATUS], &speed);
813 if (ret)
814 return ret;
815
816 ret = ksz_pread8(dev, port, regs[P_FORCE_CTRL], &ctrl);
817 if (ret)
818 return ret;
819
820 if (ctrl & PORT_FORCE_100_MBIT)
821 *val |= BMCR_SPEED100;
822
823 if (ksz_is_ksz88x3(dev)) {
824 if (restart & KSZ8873_PORT_PHY_LOOPBACK)
825 *val |= BMCR_LOOPBACK;
826
827 if ((ctrl & PORT_AUTO_NEG_ENABLE))
828 *val |= BMCR_ANENABLE;
829 } else {
830 ret = ksz879x_get_loopback(dev, port, val);
831 if (ret)
832 return ret;
833
834 if (!(ctrl & PORT_AUTO_NEG_DISABLE))
835 *val |= BMCR_ANENABLE;
836 }
837
838 if (restart & PORT_POWER_DOWN)
839 *val |= BMCR_PDOWN;
840
841 if (restart & PORT_AUTO_NEG_RESTART)
842 *val |= BMCR_ANRESTART;
843
844 if (ctrl & PORT_FORCE_FULL_DUPLEX)
845 *val |= BMCR_FULLDPLX;
846
847 if (speed & PORT_HP_MDIX)
848 *val |= KSZ886X_BMCR_HP_MDIX;
849
850 if (restart & PORT_FORCE_MDIX)
851 *val |= KSZ886X_BMCR_FORCE_MDI;
852
853 if (restart & PORT_AUTO_MDIX_DISABLE)
854 *val |= KSZ886X_BMCR_DISABLE_AUTO_MDIX;
855
856 if (restart & PORT_TX_DISABLE)
857 *val |= KSZ886X_BMCR_DISABLE_TRANSMIT;
858
859 if (restart & PORT_LED_OFF)
860 *val |= KSZ886X_BMCR_DISABLE_LED;
861
862 return 0;
863 }
864
ksz8_r_phy(struct ksz_device * dev,u16 phy,u16 reg,u16 * val)865 int ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
866 {
867 u8 ctrl, link, val1, val2;
868 int processed = true;
869 const u16 *regs;
870 u16 data = 0;
871 u16 p = phy;
872 int ret;
873
874 regs = dev->info->regs;
875
876 switch (reg) {
877 case MII_BMCR:
878 ret = ksz8_r_phy_bmcr(dev, p, &data);
879 if (ret)
880 return ret;
881 break;
882 case MII_BMSR:
883 ret = ksz_pread8(dev, p, regs[P_LINK_STATUS], &link);
884 if (ret)
885 return ret;
886
887 data = BMSR_100FULL |
888 BMSR_100HALF |
889 BMSR_10FULL |
890 BMSR_10HALF |
891 BMSR_ANEGCAPABLE;
892 if (link & PORT_AUTO_NEG_COMPLETE)
893 data |= BMSR_ANEGCOMPLETE;
894 if (link & PORT_STAT_LINK_GOOD)
895 data |= BMSR_LSTATUS;
896 break;
897 case MII_PHYSID1:
898 data = KSZ8795_ID_HI;
899 break;
900 case MII_PHYSID2:
901 if (ksz_is_ksz88x3(dev))
902 data = KSZ8863_ID_LO;
903 else
904 data = KSZ8795_ID_LO;
905 break;
906 case MII_ADVERTISE:
907 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
908 if (ret)
909 return ret;
910
911 data = ADVERTISE_CSMA;
912 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE)
913 data |= ADVERTISE_PAUSE_CAP;
914 if (ctrl & PORT_AUTO_NEG_100BTX_FD)
915 data |= ADVERTISE_100FULL;
916 if (ctrl & PORT_AUTO_NEG_100BTX)
917 data |= ADVERTISE_100HALF;
918 if (ctrl & PORT_AUTO_NEG_10BT_FD)
919 data |= ADVERTISE_10FULL;
920 if (ctrl & PORT_AUTO_NEG_10BT)
921 data |= ADVERTISE_10HALF;
922 break;
923 case MII_LPA:
924 ret = ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link);
925 if (ret)
926 return ret;
927
928 data = LPA_SLCT;
929 if (link & PORT_REMOTE_SYM_PAUSE)
930 data |= LPA_PAUSE_CAP;
931 if (link & PORT_REMOTE_100BTX_FD)
932 data |= LPA_100FULL;
933 if (link & PORT_REMOTE_100BTX)
934 data |= LPA_100HALF;
935 if (link & PORT_REMOTE_10BT_FD)
936 data |= LPA_10FULL;
937 if (link & PORT_REMOTE_10BT)
938 data |= LPA_10HALF;
939 if (data & ~LPA_SLCT)
940 data |= LPA_LPACK;
941 break;
942 case PHY_REG_LINK_MD:
943 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1);
944 if (ret)
945 return ret;
946
947 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2);
948 if (ret)
949 return ret;
950
951 if (val1 & PORT_START_CABLE_DIAG)
952 data |= PHY_START_CABLE_DIAG;
953
954 if (val1 & PORT_CABLE_10M_SHORT)
955 data |= PHY_CABLE_10M_SHORT;
956
957 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M,
958 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1));
959
960 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M,
961 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) |
962 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2));
963 break;
964 case PHY_REG_PHY_CTRL:
965 ret = ksz8_r_phy_ctrl(dev, p, &data);
966 if (ret)
967 return ret;
968
969 break;
970 default:
971 processed = false;
972 break;
973 }
974 if (processed)
975 *val = data;
976
977 return 0;
978 }
979
980 /**
981 * ksz8_w_phy_ctrl - Translates and writes to the SMI interface from a MIIM PHY
982 * Control register (Reg. 31).
983 * @dev: The KSZ device instance.
984 * @port: The port number to be configured.
985 * @val: The register value to be written.
986 *
987 * This function translates control settings from a MIIM PHY Control register
988 * into their corresponding hardware register bit values for the SMI
989 * interface.
990 *
991 * Return: 0 on success, error code on failure.
992 */
ksz8_w_phy_ctrl(struct ksz_device * dev,int port,u16 val)993 static int ksz8_w_phy_ctrl(struct ksz_device *dev, int port, u16 val)
994 {
995 u8 reg_val = 0;
996 int ret;
997
998 if (val & KSZ886X_CTRL_FORCE_LINK)
999 reg_val |= PORT_FORCE_LINK;
1000
1001 if (val & KSZ886X_CTRL_PWRSAVE)
1002 reg_val |= PORT_POWER_SAVING;
1003
1004 if (val & KSZ886X_CTRL_REMOTE_LOOPBACK)
1005 reg_val |= PORT_PHY_REMOTE_LOOPBACK;
1006
1007 ret = ksz_prmw8(dev, port, REG_PORT_LINK_MD_CTRL, PORT_FORCE_LINK |
1008 PORT_POWER_SAVING | PORT_PHY_REMOTE_LOOPBACK, reg_val);
1009 return ret;
1010 }
1011
1012 /**
1013 * ksz8_w_phy_bmcr - Translates and writes to the SMI interface from a MIIM PHY
1014 * Basic mode control register (Reg. 0).
1015 * @dev: The KSZ device instance.
1016 * @port: The port number to be configured.
1017 * @val: The register value to be written.
1018 *
1019 * This function translates control settings from a MIIM PHY Basic mode control
1020 * register into their corresponding hardware register bit values for the SMI
1021 * interface.
1022 *
1023 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873
1024 * -------------------------------------------------------------------
1025 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit
1026 * ----------------------------+-----------------------------+----------------
1027 * Bit 15 - Soft Reset | 0xF/4 | Not supported
1028 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY)
1029 * Bit 13 - Force 100 | 0xC/6 = 0xC/6
1030 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7
1031 * Bit 11 - Power Down | 0xD/3 = 0xD/3
1032 * Bit 10 - PHY Isolate | 0xF/5 | Not supported
1033 * Bit 9 - Restart AN | 0xD/5 = 0xD/5
1034 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5
1035 * Bit 7 - Collision Test/Res. | Not supported | Not supported
1036 * Bit 6 - Reserved | Not supported | Not supported
1037 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7
1038 * Bit 4 - Force MDI | 0xD/1 = 0xD/1
1039 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2
1040 * Bit 2 - Disable Far-End F. | ???? | 0xD/4
1041 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6
1042 * Bit 0 - Disable LED | 0xD/7 = 0xD/7
1043 * -------------------------------------------------------------------
1044 *
1045 * Return: 0 on success, error code on failure.
1046 */
ksz8_w_phy_bmcr(struct ksz_device * dev,u16 port,u16 val)1047 static int ksz8_w_phy_bmcr(struct ksz_device *dev, u16 port, u16 val)
1048 {
1049 u8 restart, speed, ctrl, restart_mask;
1050 const u16 *regs = dev->info->regs;
1051 int ret;
1052
1053 /* Do not support PHY reset function. */
1054 if (val & BMCR_RESET)
1055 return 0;
1056
1057 speed = 0;
1058 if (val & KSZ886X_BMCR_HP_MDIX)
1059 speed |= PORT_HP_MDIX;
1060
1061 ret = ksz_prmw8(dev, port, regs[P_SPEED_STATUS], PORT_HP_MDIX, speed);
1062 if (ret)
1063 return ret;
1064
1065 ctrl = 0;
1066 if (ksz_is_ksz88x3(dev)) {
1067 if ((val & BMCR_ANENABLE))
1068 ctrl |= PORT_AUTO_NEG_ENABLE;
1069 } else {
1070 if (!(val & BMCR_ANENABLE))
1071 ctrl |= PORT_AUTO_NEG_DISABLE;
1072
1073 /* Fiber port does not support auto-negotiation. */
1074 if (dev->ports[port].fiber)
1075 ctrl |= PORT_AUTO_NEG_DISABLE;
1076 }
1077
1078 if (val & BMCR_SPEED100)
1079 ctrl |= PORT_FORCE_100_MBIT;
1080
1081 if (val & BMCR_FULLDPLX)
1082 ctrl |= PORT_FORCE_FULL_DUPLEX;
1083
1084 ret = ksz_prmw8(dev, port, regs[P_FORCE_CTRL], PORT_FORCE_100_MBIT |
1085 /* PORT_AUTO_NEG_ENABLE and PORT_AUTO_NEG_DISABLE are the same
1086 * bits
1087 */
1088 PORT_FORCE_FULL_DUPLEX | PORT_AUTO_NEG_ENABLE, ctrl);
1089 if (ret)
1090 return ret;
1091
1092 restart = 0;
1093 restart_mask = PORT_LED_OFF | PORT_TX_DISABLE | PORT_AUTO_NEG_RESTART |
1094 PORT_POWER_DOWN | PORT_AUTO_MDIX_DISABLE | PORT_FORCE_MDIX;
1095
1096 if (val & KSZ886X_BMCR_DISABLE_LED)
1097 restart |= PORT_LED_OFF;
1098
1099 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT)
1100 restart |= PORT_TX_DISABLE;
1101
1102 if (val & BMCR_ANRESTART)
1103 restart |= PORT_AUTO_NEG_RESTART;
1104
1105 if (val & BMCR_PDOWN)
1106 restart |= PORT_POWER_DOWN;
1107
1108 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX)
1109 restart |= PORT_AUTO_MDIX_DISABLE;
1110
1111 if (val & KSZ886X_BMCR_FORCE_MDI)
1112 restart |= PORT_FORCE_MDIX;
1113
1114 if (ksz_is_ksz88x3(dev)) {
1115 restart_mask |= KSZ8873_PORT_PHY_LOOPBACK;
1116
1117 if (val & BMCR_LOOPBACK)
1118 restart |= KSZ8873_PORT_PHY_LOOPBACK;
1119 } else {
1120 ret = ksz879x_set_loopback(dev, port, val);
1121 if (ret)
1122 return ret;
1123 }
1124
1125 return ksz_prmw8(dev, port, regs[P_NEG_RESTART_CTRL], restart_mask,
1126 restart);
1127 }
1128
ksz8_w_phy(struct ksz_device * dev,u16 phy,u16 reg,u16 val)1129 int ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
1130 {
1131 const u16 *regs;
1132 u8 ctrl, data;
1133 u16 p = phy;
1134 int ret;
1135
1136 regs = dev->info->regs;
1137
1138 switch (reg) {
1139 case MII_BMCR:
1140 ret = ksz8_w_phy_bmcr(dev, p, val);
1141 if (ret)
1142 return ret;
1143 break;
1144 case MII_ADVERTISE:
1145 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
1146 if (ret)
1147 return ret;
1148
1149 data = ctrl;
1150 data &= ~(PORT_AUTO_NEG_SYM_PAUSE |
1151 PORT_AUTO_NEG_100BTX_FD |
1152 PORT_AUTO_NEG_100BTX |
1153 PORT_AUTO_NEG_10BT_FD |
1154 PORT_AUTO_NEG_10BT);
1155 if (val & ADVERTISE_PAUSE_CAP)
1156 data |= PORT_AUTO_NEG_SYM_PAUSE;
1157 if (val & ADVERTISE_100FULL)
1158 data |= PORT_AUTO_NEG_100BTX_FD;
1159 if (val & ADVERTISE_100HALF)
1160 data |= PORT_AUTO_NEG_100BTX;
1161 if (val & ADVERTISE_10FULL)
1162 data |= PORT_AUTO_NEG_10BT_FD;
1163 if (val & ADVERTISE_10HALF)
1164 data |= PORT_AUTO_NEG_10BT;
1165
1166 if (data != ctrl) {
1167 ret = ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data);
1168 if (ret)
1169 return ret;
1170 }
1171 break;
1172 case PHY_REG_LINK_MD:
1173 if (val & PHY_START_CABLE_DIAG)
1174 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true);
1175 break;
1176
1177 case PHY_REG_PHY_CTRL:
1178 ret = ksz8_w_phy_ctrl(dev, p, val);
1179 if (ret)
1180 return ret;
1181 break;
1182 default:
1183 break;
1184 }
1185
1186 return 0;
1187 }
1188
ksz8_cfg_port_member(struct ksz_device * dev,int port,u8 member)1189 void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member)
1190 {
1191 u8 data;
1192
1193 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1194 data &= ~PORT_VLAN_MEMBERSHIP;
1195 data |= (member & dev->port_mask);
1196 ksz_pwrite8(dev, port, P_MIRROR_CTRL, data);
1197 }
1198
ksz8_flush_dyn_mac_table(struct ksz_device * dev,int port)1199 void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port)
1200 {
1201 u8 learn[DSA_MAX_PORTS];
1202 int first, index, cnt;
1203 const u16 *regs;
1204
1205 regs = dev->info->regs;
1206
1207 if ((uint)port < dev->info->port_cnt) {
1208 first = port;
1209 cnt = port + 1;
1210 } else {
1211 /* Flush all ports. */
1212 first = 0;
1213 cnt = dev->info->port_cnt;
1214 }
1215 for (index = first; index < cnt; index++) {
1216 ksz_pread8(dev, index, regs[P_STP_CTRL], &learn[index]);
1217 if (!(learn[index] & PORT_LEARN_DISABLE))
1218 ksz_pwrite8(dev, index, regs[P_STP_CTRL],
1219 learn[index] | PORT_LEARN_DISABLE);
1220 }
1221 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
1222 for (index = first; index < cnt; index++) {
1223 if (!(learn[index] & PORT_LEARN_DISABLE))
1224 ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]);
1225 }
1226 }
1227
ksz8_fdb_dump(struct ksz_device * dev,int port,dsa_fdb_dump_cb_t * cb,void * data)1228 int ksz8_fdb_dump(struct ksz_device *dev, int port,
1229 dsa_fdb_dump_cb_t *cb, void *data)
1230 {
1231 u8 mac[ETH_ALEN];
1232 u8 src_port, fid;
1233 u16 entries = 0;
1234 int ret, i;
1235
1236 for (i = 0; i < KSZ8_DYN_MAC_ENTRIES; i++) {
1237 ret = ksz8_r_dyn_mac_table(dev, i, mac, &fid, &src_port,
1238 &entries);
1239 if (ret)
1240 return ret;
1241
1242 if (i >= entries)
1243 return 0;
1244
1245 if (port == src_port) {
1246 ret = cb(mac, fid, false, data);
1247 if (ret)
1248 return ret;
1249 }
1250 }
1251
1252 return 0;
1253 }
1254
ksz8_add_sta_mac(struct ksz_device * dev,int port,const unsigned char * addr,u16 vid)1255 static int ksz8_add_sta_mac(struct ksz_device *dev, int port,
1256 const unsigned char *addr, u16 vid)
1257 {
1258 struct alu_struct alu;
1259 int index, ret;
1260 int empty = 0;
1261
1262 alu.port_forward = 0;
1263 for (index = 0; index < dev->info->num_statics; index++) {
1264 bool valid;
1265
1266 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid);
1267 if (ret)
1268 return ret;
1269 if (!valid) {
1270 /* Remember the first empty entry. */
1271 if (!empty)
1272 empty = index + 1;
1273 continue;
1274 }
1275
1276 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid)
1277 break;
1278 }
1279
1280 /* no available entry */
1281 if (index == dev->info->num_statics && !empty)
1282 return -ENOSPC;
1283
1284 /* add entry */
1285 if (index == dev->info->num_statics) {
1286 index = empty - 1;
1287 memset(&alu, 0, sizeof(alu));
1288 memcpy(alu.mac, addr, ETH_ALEN);
1289 alu.is_static = true;
1290 }
1291 alu.port_forward |= BIT(port);
1292 if (vid) {
1293 alu.is_use_fid = true;
1294
1295 /* Need a way to map VID to FID. */
1296 alu.fid = vid;
1297 }
1298
1299 return ksz8_w_sta_mac_table(dev, index, &alu);
1300 }
1301
ksz8_del_sta_mac(struct ksz_device * dev,int port,const unsigned char * addr,u16 vid)1302 static int ksz8_del_sta_mac(struct ksz_device *dev, int port,
1303 const unsigned char *addr, u16 vid)
1304 {
1305 struct alu_struct alu;
1306 int index, ret;
1307
1308 for (index = 0; index < dev->info->num_statics; index++) {
1309 bool valid;
1310
1311 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid);
1312 if (ret)
1313 return ret;
1314 if (!valid)
1315 continue;
1316
1317 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid)
1318 break;
1319 }
1320
1321 /* no available entry */
1322 if (index == dev->info->num_statics)
1323 return 0;
1324
1325 /* clear port */
1326 alu.port_forward &= ~BIT(port);
1327 if (!alu.port_forward)
1328 alu.is_static = false;
1329
1330 return ksz8_w_sta_mac_table(dev, index, &alu);
1331 }
1332
ksz8_mdb_add(struct ksz_device * dev,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1333 int ksz8_mdb_add(struct ksz_device *dev, int port,
1334 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
1335 {
1336 return ksz8_add_sta_mac(dev, port, mdb->addr, mdb->vid);
1337 }
1338
ksz8_mdb_del(struct ksz_device * dev,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1339 int ksz8_mdb_del(struct ksz_device *dev, int port,
1340 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
1341 {
1342 return ksz8_del_sta_mac(dev, port, mdb->addr, mdb->vid);
1343 }
1344
ksz8_fdb_add(struct ksz_device * dev,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1345 int ksz8_fdb_add(struct ksz_device *dev, int port, const unsigned char *addr,
1346 u16 vid, struct dsa_db db)
1347 {
1348 return ksz8_add_sta_mac(dev, port, addr, vid);
1349 }
1350
ksz8_fdb_del(struct ksz_device * dev,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1351 int ksz8_fdb_del(struct ksz_device *dev, int port, const unsigned char *addr,
1352 u16 vid, struct dsa_db db)
1353 {
1354 return ksz8_del_sta_mac(dev, port, addr, vid);
1355 }
1356
ksz8_port_vlan_filtering(struct ksz_device * dev,int port,bool flag,struct netlink_ext_ack * extack)1357 int ksz8_port_vlan_filtering(struct ksz_device *dev, int port, bool flag,
1358 struct netlink_ext_ack *extack)
1359 {
1360 if (ksz_is_ksz88x3(dev))
1361 return -ENOTSUPP;
1362
1363 /* Discard packets with VID not enabled on the switch */
1364 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag);
1365
1366 /* Discard packets with VID not enabled on the ingress port */
1367 for (port = 0; port < dev->phy_port_cnt; ++port)
1368 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER,
1369 flag);
1370
1371 return 0;
1372 }
1373
ksz8_port_enable_pvid(struct ksz_device * dev,int port,bool state)1374 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state)
1375 {
1376 if (ksz_is_ksz88x3(dev)) {
1377 ksz_cfg(dev, REG_SW_INSERT_SRC_PVID,
1378 0x03 << (4 - 2 * port), state);
1379 } else {
1380 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00);
1381 }
1382 }
1383
ksz8_port_vlan_add(struct ksz_device * dev,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1384 int ksz8_port_vlan_add(struct ksz_device *dev, int port,
1385 const struct switchdev_obj_port_vlan *vlan,
1386 struct netlink_ext_ack *extack)
1387 {
1388 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1389 struct ksz_port *p = &dev->ports[port];
1390 u16 data, new_pvid = 0;
1391 u8 fid, member, valid;
1392
1393 if (ksz_is_ksz88x3(dev))
1394 return -ENOTSUPP;
1395
1396 /* If a VLAN is added with untagged flag different from the
1397 * port's Remove Tag flag, we need to change the latter.
1398 * Ignore VID 0, which is always untagged.
1399 * Ignore CPU port, which will always be tagged.
1400 */
1401 if (untagged != p->remove_tag && vlan->vid != 0 &&
1402 port != dev->cpu_port) {
1403 unsigned int vid;
1404
1405 /* Reject attempts to add a VLAN that requires the
1406 * Remove Tag flag to be changed, unless there are no
1407 * other VLANs currently configured.
1408 */
1409 for (vid = 1; vid < dev->info->num_vlans; ++vid) {
1410 /* Skip the VID we are going to add or reconfigure */
1411 if (vid == vlan->vid)
1412 continue;
1413
1414 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0],
1415 &fid, &member, &valid);
1416 if (valid && (member & BIT(port)))
1417 return -EINVAL;
1418 }
1419
1420 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
1421 p->remove_tag = untagged;
1422 }
1423
1424 ksz8_r_vlan_table(dev, vlan->vid, &data);
1425 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1426
1427 /* First time to setup the VLAN entry. */
1428 if (!valid) {
1429 /* Need to find a way to map VID to FID. */
1430 fid = 1;
1431 valid = 1;
1432 }
1433 member |= BIT(port);
1434
1435 ksz8_to_vlan(dev, fid, member, valid, &data);
1436 ksz8_w_vlan_table(dev, vlan->vid, data);
1437
1438 /* change PVID */
1439 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1440 new_pvid = vlan->vid;
1441
1442 if (new_pvid) {
1443 u16 vid;
1444
1445 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid);
1446 vid &= ~VLAN_VID_MASK;
1447 vid |= new_pvid;
1448 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid);
1449
1450 ksz8_port_enable_pvid(dev, port, true);
1451 }
1452
1453 return 0;
1454 }
1455
ksz8_port_vlan_del(struct ksz_device * dev,int port,const struct switchdev_obj_port_vlan * vlan)1456 int ksz8_port_vlan_del(struct ksz_device *dev, int port,
1457 const struct switchdev_obj_port_vlan *vlan)
1458 {
1459 u16 data, pvid;
1460 u8 fid, member, valid;
1461
1462 if (ksz_is_ksz88x3(dev))
1463 return -ENOTSUPP;
1464
1465 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid);
1466 pvid = pvid & 0xFFF;
1467
1468 ksz8_r_vlan_table(dev, vlan->vid, &data);
1469 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1470
1471 member &= ~BIT(port);
1472
1473 /* Invalidate the entry if no more member. */
1474 if (!member) {
1475 fid = 0;
1476 valid = 0;
1477 }
1478
1479 ksz8_to_vlan(dev, fid, member, valid, &data);
1480 ksz8_w_vlan_table(dev, vlan->vid, data);
1481
1482 if (pvid == vlan->vid)
1483 ksz8_port_enable_pvid(dev, port, false);
1484
1485 return 0;
1486 }
1487
ksz8_port_mirror_add(struct ksz_device * dev,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)1488 int ksz8_port_mirror_add(struct ksz_device *dev, int port,
1489 struct dsa_mall_mirror_tc_entry *mirror,
1490 bool ingress, struct netlink_ext_ack *extack)
1491 {
1492 if (ingress) {
1493 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
1494 dev->mirror_rx |= BIT(port);
1495 } else {
1496 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
1497 dev->mirror_tx |= BIT(port);
1498 }
1499
1500 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
1501
1502 /* configure mirror port */
1503 if (dev->mirror_rx || dev->mirror_tx)
1504 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1505 PORT_MIRROR_SNIFFER, true);
1506
1507 return 0;
1508 }
1509
ksz8_port_mirror_del(struct ksz_device * dev,int port,struct dsa_mall_mirror_tc_entry * mirror)1510 void ksz8_port_mirror_del(struct ksz_device *dev, int port,
1511 struct dsa_mall_mirror_tc_entry *mirror)
1512 {
1513 u8 data;
1514
1515 if (mirror->ingress) {
1516 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
1517 dev->mirror_rx &= ~BIT(port);
1518 } else {
1519 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
1520 dev->mirror_tx &= ~BIT(port);
1521 }
1522
1523 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1524
1525 if (!dev->mirror_rx && !dev->mirror_tx)
1526 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1527 PORT_MIRROR_SNIFFER, false);
1528 }
1529
ksz8795_cpu_interface_select(struct ksz_device * dev,int port)1530 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
1531 {
1532 struct ksz_port *p = &dev->ports[port];
1533
1534 if (!ksz_is_ksz87xx(dev))
1535 return;
1536
1537 if (!p->interface && dev->compat_interface) {
1538 dev_warn(dev->dev,
1539 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
1540 "Please update your device tree.\n",
1541 port);
1542 p->interface = dev->compat_interface;
1543 }
1544 }
1545
ksz8_port_setup(struct ksz_device * dev,int port,bool cpu_port)1546 void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1547 {
1548 struct dsa_switch *ds = dev->ds;
1549 const u32 *masks;
1550 int queues;
1551 u8 member;
1552
1553 masks = dev->info->masks;
1554
1555 /* enable broadcast storm limit */
1556 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1557
1558 /* For KSZ88x3 enable only one queue by default, otherwise we won't
1559 * be able to get rid of PCP prios on Port 2.
1560 */
1561 if (ksz_is_ksz88x3(dev))
1562 queues = 1;
1563 else
1564 queues = dev->info->num_tx_queues;
1565
1566 ksz8_port_queue_split(dev, port, queues);
1567
1568 /* replace priority */
1569 ksz_port_cfg(dev, port, P_802_1P_CTRL,
1570 masks[PORT_802_1P_REMAPPING], false);
1571
1572 if (cpu_port)
1573 member = dsa_user_ports(ds);
1574 else
1575 member = BIT(dsa_upstream_port(ds, port));
1576
1577 ksz8_cfg_port_member(dev, port, member);
1578 }
1579
ksz88x3_config_rmii_clk(struct ksz_device * dev)1580 static void ksz88x3_config_rmii_clk(struct ksz_device *dev)
1581 {
1582 struct dsa_port *cpu_dp = dsa_to_port(dev->ds, dev->cpu_port);
1583 bool rmii_clk_internal;
1584
1585 if (!ksz_is_ksz88x3(dev))
1586 return;
1587
1588 rmii_clk_internal = of_property_read_bool(cpu_dp->dn,
1589 "microchip,rmii-clk-internal");
1590
1591 ksz_cfg(dev, KSZ88X3_REG_FVID_AND_HOST_MODE,
1592 KSZ88X3_PORT3_RMII_CLK_INTERNAL, rmii_clk_internal);
1593 }
1594
ksz8_config_cpu_port(struct dsa_switch * ds)1595 void ksz8_config_cpu_port(struct dsa_switch *ds)
1596 {
1597 struct ksz_device *dev = ds->priv;
1598 struct ksz_port *p;
1599 const u32 *masks;
1600 const u16 *regs;
1601 u8 remote;
1602 int i;
1603
1604 masks = dev->info->masks;
1605 regs = dev->info->regs;
1606
1607 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true);
1608
1609 ksz8_port_setup(dev, dev->cpu_port, true);
1610
1611 ksz8795_cpu_interface_select(dev, dev->cpu_port);
1612 ksz88x3_config_rmii_clk(dev);
1613
1614 for (i = 0; i < dev->phy_port_cnt; i++) {
1615 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1616 }
1617 for (i = 0; i < dev->phy_port_cnt; i++) {
1618 p = &dev->ports[i];
1619
1620 if (!ksz_is_ksz88x3(dev)) {
1621 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote);
1622 if (remote & KSZ8_PORT_FIBER_MODE)
1623 p->fiber = 1;
1624 }
1625 if (p->fiber)
1626 ksz_port_cfg(dev, i, regs[P_STP_CTRL],
1627 PORT_FORCE_FLOW_CTRL, true);
1628 else
1629 ksz_port_cfg(dev, i, regs[P_STP_CTRL],
1630 PORT_FORCE_FLOW_CTRL, false);
1631 }
1632 }
1633
1634 /**
1635 * ksz8_phy_port_link_up - Configures ports with integrated PHYs
1636 * @dev: The KSZ device instance.
1637 * @port: The port number to configure.
1638 * @duplex: The desired duplex mode.
1639 * @tx_pause: If true, enables transmit pause.
1640 * @rx_pause: If true, enables receive pause.
1641 *
1642 * Description:
1643 * The function configures flow control settings for a given port based on the
1644 * desired settings and current duplex mode.
1645 *
1646 * According to the KSZ8873 datasheet, the PORT_FORCE_FLOW_CTRL bit in the
1647 * Port Control 2 register (0x1A for Port 1, 0x22 for Port 2, 0x32 for Port 3)
1648 * determines how flow control is handled on the port:
1649 * "1 = will always enable full-duplex flow control on the port, regardless
1650 * of AN result.
1651 * 0 = full-duplex flow control is enabled based on AN result."
1652 *
1653 * This means that the flow control behavior depends on the state of this bit:
1654 * - If PORT_FORCE_FLOW_CTRL is set to 1, the switch will ignore AN results and
1655 * force flow control on the port.
1656 * - If PORT_FORCE_FLOW_CTRL is set to 0, the switch will enable or disable
1657 * flow control based on the AN results.
1658 *
1659 * However, there is a potential limitation in this configuration. It is
1660 * currently not possible to force disable flow control on a port if we still
1661 * advertise pause support. While such a configuration is not currently
1662 * supported by Linux, and may not make practical sense, it's important to be
1663 * aware of this limitation when working with the KSZ8873 and similar devices.
1664 */
ksz8_phy_port_link_up(struct ksz_device * dev,int port,int duplex,bool tx_pause,bool rx_pause)1665 static void ksz8_phy_port_link_up(struct ksz_device *dev, int port, int duplex,
1666 bool tx_pause, bool rx_pause)
1667 {
1668 const u16 *regs = dev->info->regs;
1669 u8 sctrl = 0;
1670
1671 /* The KSZ8795 switch differs from the KSZ8873 by supporting
1672 * asymmetric pause control. However, since a single bit is used to
1673 * control both RX and TX pause, we can't enforce asymmetric pause
1674 * control - both TX and RX pause will be either enabled or disabled
1675 * together.
1676 *
1677 * If auto-negotiation is enabled, we usually allow the flow control to
1678 * be determined by the auto-negotiation process based on the
1679 * capabilities of both link partners. However, for KSZ8873, the
1680 * PORT_FORCE_FLOW_CTRL bit may be set by the hardware bootstrap,
1681 * ignoring the auto-negotiation result. Thus, even in auto-negotiation
1682 * mode, we need to ensure that the PORT_FORCE_FLOW_CTRL bit is
1683 * properly cleared.
1684 *
1685 * In the absence of pause auto-negotiation, we will enforce symmetric
1686 * pause control for both variants of switches - KSZ8873 and KSZ8795.
1687 *
1688 * Autoneg Pause Autoneg rx,tx PORT_FORCE_FLOW_CTRL
1689 * 1 1 x 0
1690 * 0 1 x 0 (flow control probably disabled)
1691 * x 0 1 1 (flow control force enabled)
1692 * 1 0 0 0 (flow control still depends on
1693 * aneg result due to hardware)
1694 * 0 0 0 0 (flow control probably disabled)
1695 */
1696 if (dev->ports[port].manual_flow && tx_pause)
1697 sctrl |= PORT_FORCE_FLOW_CTRL;
1698
1699 ksz_prmw8(dev, port, regs[P_STP_CTRL], PORT_FORCE_FLOW_CTRL, sctrl);
1700 }
1701
1702 /**
1703 * ksz8_cpu_port_link_up - Configures the CPU port of the switch.
1704 * @dev: The KSZ device instance.
1705 * @speed: The desired link speed.
1706 * @duplex: The desired duplex mode.
1707 * @tx_pause: If true, enables transmit pause.
1708 * @rx_pause: If true, enables receive pause.
1709 *
1710 * Description:
1711 * The function configures flow control and speed settings for the CPU
1712 * port of the switch based on the desired settings, current duplex mode, and
1713 * speed.
1714 */
ksz8_cpu_port_link_up(struct ksz_device * dev,int speed,int duplex,bool tx_pause,bool rx_pause)1715 static void ksz8_cpu_port_link_up(struct ksz_device *dev, int speed, int duplex,
1716 bool tx_pause, bool rx_pause)
1717 {
1718 const u16 *regs = dev->info->regs;
1719 u8 ctrl = 0;
1720
1721 /* SW_FLOW_CTRL, SW_HALF_DUPLEX, and SW_10_MBIT bits are bootstrappable
1722 * at least on KSZ8873. They can have different values depending on your
1723 * board setup.
1724 */
1725 if (tx_pause || rx_pause)
1726 ctrl |= SW_FLOW_CTRL;
1727
1728 if (duplex == DUPLEX_HALF)
1729 ctrl |= SW_HALF_DUPLEX;
1730
1731 /* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10
1732 * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0.
1733 */
1734 if (speed == SPEED_10)
1735 ctrl |= SW_10_MBIT;
1736
1737 ksz_rmw8(dev, regs[S_BROADCAST_CTRL], SW_HALF_DUPLEX | SW_FLOW_CTRL |
1738 SW_10_MBIT, ctrl);
1739 }
1740
ksz8_phylink_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)1741 void ksz8_phylink_mac_link_up(struct phylink_config *config,
1742 struct phy_device *phydev, unsigned int mode,
1743 phy_interface_t interface, int speed, int duplex,
1744 bool tx_pause, bool rx_pause)
1745 {
1746 struct dsa_port *dp = dsa_phylink_to_port(config);
1747 struct ksz_device *dev = dp->ds->priv;
1748 int port = dp->index;
1749
1750 /* If the port is the CPU port, apply special handling. Only the CPU
1751 * port is configured via global registers.
1752 */
1753 if (dev->cpu_port == port)
1754 ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause);
1755 else if (dev->info->internal_phy[port])
1756 ksz8_phy_port_link_up(dev, port, duplex, tx_pause, rx_pause);
1757 }
1758
ksz8_handle_global_errata(struct dsa_switch * ds)1759 static int ksz8_handle_global_errata(struct dsa_switch *ds)
1760 {
1761 struct ksz_device *dev = ds->priv;
1762 int ret = 0;
1763
1764 /* KSZ87xx Errata DS80000687C.
1765 * Module 2: Link drops with some EEE link partners.
1766 * An issue with the EEE next page exchange between the
1767 * KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in
1768 * the link dropping.
1769 */
1770 if (dev->info->ksz87xx_eee_link_erratum)
1771 ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0);
1772
1773 return ret;
1774 }
1775
ksz8_enable_stp_addr(struct ksz_device * dev)1776 int ksz8_enable_stp_addr(struct ksz_device *dev)
1777 {
1778 struct alu_struct alu;
1779
1780 /* Setup STP address for STP operation. */
1781 memset(&alu, 0, sizeof(alu));
1782 ether_addr_copy(alu.mac, eth_stp_addr);
1783 alu.is_static = true;
1784 alu.is_override = true;
1785 alu.port_forward = dev->info->cpu_ports;
1786
1787 return ksz8_w_sta_mac_table(dev, 0, &alu);
1788 }
1789
ksz8_setup(struct dsa_switch * ds)1790 int ksz8_setup(struct dsa_switch *ds)
1791 {
1792 struct ksz_device *dev = ds->priv;
1793 int i;
1794
1795 ds->mtu_enforcement_ingress = true;
1796
1797 /* We rely on software untagging on the CPU port, so that we
1798 * can support both tagged and untagged VLANs
1799 */
1800 ds->untag_bridge_pvid = true;
1801
1802 /* VLAN filtering is partly controlled by the global VLAN
1803 * Enable flag
1804 */
1805 ds->vlan_filtering_is_global = true;
1806
1807 /* Enable automatic fast aging when link changed detected. */
1808 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
1809
1810 /* Enable aggressive back off algorithm in half duplex mode. */
1811 regmap_update_bits(ksz_regmap_8(dev), REG_SW_CTRL_1,
1812 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF);
1813
1814 /*
1815 * Make sure unicast VLAN boundary is set as default and
1816 * enable no excessive collision drop.
1817 */
1818 regmap_update_bits(ksz_regmap_8(dev), REG_SW_CTRL_2,
1819 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP,
1820 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP);
1821
1822 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false);
1823
1824 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
1825
1826 if (!ksz_is_ksz88x3(dev))
1827 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true);
1828
1829 for (i = 0; i < (dev->info->num_vlans / 4); i++)
1830 ksz8_r_vlan_entries(dev, i);
1831
1832 return ksz8_handle_global_errata(ds);
1833 }
1834
ksz8_get_caps(struct ksz_device * dev,int port,struct phylink_config * config)1835 void ksz8_get_caps(struct ksz_device *dev, int port,
1836 struct phylink_config *config)
1837 {
1838 config->mac_capabilities = MAC_10 | MAC_100;
1839
1840 /* Silicon Errata Sheet (DS80000830A):
1841 * "Port 1 does not respond to received flow control PAUSE frames"
1842 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3
1843 * switches.
1844 */
1845 if (!ksz_is_ksz88x3(dev) || port)
1846 config->mac_capabilities |= MAC_SYM_PAUSE;
1847
1848 /* Asym pause is not supported on KSZ8863 and KSZ8873 */
1849 if (!ksz_is_ksz88x3(dev))
1850 config->mac_capabilities |= MAC_ASYM_PAUSE;
1851 }
1852
ksz8_get_port_addr(int port,int offset)1853 u32 ksz8_get_port_addr(int port, int offset)
1854 {
1855 return PORT_CTRL_ADDR(port, offset);
1856 }
1857
ksz8_switch_init(struct ksz_device * dev)1858 int ksz8_switch_init(struct ksz_device *dev)
1859 {
1860 dev->cpu_port = fls(dev->info->cpu_ports) - 1;
1861 dev->phy_port_cnt = dev->info->port_cnt - 1;
1862 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports;
1863
1864 return 0;
1865 }
1866
ksz8_switch_exit(struct ksz_device * dev)1867 void ksz8_switch_exit(struct ksz_device *dev)
1868 {
1869 ksz8_reset_switch(dev);
1870 }
1871
1872 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
1873 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver");
1874 MODULE_LICENSE("GPL");
1875