1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Microchip switch driver main logic
4 *
5 * Copyright (C) 2017-2019 Microchip Technology Inc.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/dsa/ksz_common.h>
10 #include <linux/export.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_data/microchip-ksz.h>
15 #include <linux/phy.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_bridge.h>
18 #include <linux/if_vlan.h>
19 #include <linux/if_hsr.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/of.h>
23 #include <linux/of_mdio.h>
24 #include <linux/of_net.h>
25 #include <linux/micrel_phy.h>
26 #include <net/dsa.h>
27 #include <net/ieee8021q.h>
28 #include <net/pkt_cls.h>
29 #include <net/switchdev.h>
30
31 #include "ksz_common.h"
32 #include "ksz_dcb.h"
33 #include "ksz_ptp.h"
34 #include "ksz8.h"
35 #include "ksz9477.h"
36 #include "lan937x.h"
37
38 #define MIB_COUNTER_NUM 0x20
39
40 struct ksz_stats_raw {
41 u64 rx_hi;
42 u64 rx_undersize;
43 u64 rx_fragments;
44 u64 rx_oversize;
45 u64 rx_jabbers;
46 u64 rx_symbol_err;
47 u64 rx_crc_err;
48 u64 rx_align_err;
49 u64 rx_mac_ctrl;
50 u64 rx_pause;
51 u64 rx_bcast;
52 u64 rx_mcast;
53 u64 rx_ucast;
54 u64 rx_64_or_less;
55 u64 rx_65_127;
56 u64 rx_128_255;
57 u64 rx_256_511;
58 u64 rx_512_1023;
59 u64 rx_1024_1522;
60 u64 rx_1523_2000;
61 u64 rx_2001;
62 u64 tx_hi;
63 u64 tx_late_col;
64 u64 tx_pause;
65 u64 tx_bcast;
66 u64 tx_mcast;
67 u64 tx_ucast;
68 u64 tx_deferred;
69 u64 tx_total_col;
70 u64 tx_exc_col;
71 u64 tx_single_col;
72 u64 tx_mult_col;
73 u64 rx_total;
74 u64 tx_total;
75 u64 rx_discards;
76 u64 tx_discards;
77 };
78
79 struct ksz88xx_stats_raw {
80 u64 rx;
81 u64 rx_hi;
82 u64 rx_undersize;
83 u64 rx_fragments;
84 u64 rx_oversize;
85 u64 rx_jabbers;
86 u64 rx_symbol_err;
87 u64 rx_crc_err;
88 u64 rx_align_err;
89 u64 rx_mac_ctrl;
90 u64 rx_pause;
91 u64 rx_bcast;
92 u64 rx_mcast;
93 u64 rx_ucast;
94 u64 rx_64_or_less;
95 u64 rx_65_127;
96 u64 rx_128_255;
97 u64 rx_256_511;
98 u64 rx_512_1023;
99 u64 rx_1024_1522;
100 u64 tx;
101 u64 tx_hi;
102 u64 tx_late_col;
103 u64 tx_pause;
104 u64 tx_bcast;
105 u64 tx_mcast;
106 u64 tx_ucast;
107 u64 tx_deferred;
108 u64 tx_total_col;
109 u64 tx_exc_col;
110 u64 tx_single_col;
111 u64 tx_mult_col;
112 u64 rx_discards;
113 u64 tx_discards;
114 };
115
116 static const struct ksz_mib_names ksz88xx_mib_names[] = {
117 { 0x00, "rx" },
118 { 0x01, "rx_hi" },
119 { 0x02, "rx_undersize" },
120 { 0x03, "rx_fragments" },
121 { 0x04, "rx_oversize" },
122 { 0x05, "rx_jabbers" },
123 { 0x06, "rx_symbol_err" },
124 { 0x07, "rx_crc_err" },
125 { 0x08, "rx_align_err" },
126 { 0x09, "rx_mac_ctrl" },
127 { 0x0a, "rx_pause" },
128 { 0x0b, "rx_bcast" },
129 { 0x0c, "rx_mcast" },
130 { 0x0d, "rx_ucast" },
131 { 0x0e, "rx_64_or_less" },
132 { 0x0f, "rx_65_127" },
133 { 0x10, "rx_128_255" },
134 { 0x11, "rx_256_511" },
135 { 0x12, "rx_512_1023" },
136 { 0x13, "rx_1024_1522" },
137 { 0x14, "tx" },
138 { 0x15, "tx_hi" },
139 { 0x16, "tx_late_col" },
140 { 0x17, "tx_pause" },
141 { 0x18, "tx_bcast" },
142 { 0x19, "tx_mcast" },
143 { 0x1a, "tx_ucast" },
144 { 0x1b, "tx_deferred" },
145 { 0x1c, "tx_total_col" },
146 { 0x1d, "tx_exc_col" },
147 { 0x1e, "tx_single_col" },
148 { 0x1f, "tx_mult_col" },
149 { 0x100, "rx_discards" },
150 { 0x101, "tx_discards" },
151 };
152
153 static const struct ksz_mib_names ksz9477_mib_names[] = {
154 { 0x00, "rx_hi" },
155 { 0x01, "rx_undersize" },
156 { 0x02, "rx_fragments" },
157 { 0x03, "rx_oversize" },
158 { 0x04, "rx_jabbers" },
159 { 0x05, "rx_symbol_err" },
160 { 0x06, "rx_crc_err" },
161 { 0x07, "rx_align_err" },
162 { 0x08, "rx_mac_ctrl" },
163 { 0x09, "rx_pause" },
164 { 0x0A, "rx_bcast" },
165 { 0x0B, "rx_mcast" },
166 { 0x0C, "rx_ucast" },
167 { 0x0D, "rx_64_or_less" },
168 { 0x0E, "rx_65_127" },
169 { 0x0F, "rx_128_255" },
170 { 0x10, "rx_256_511" },
171 { 0x11, "rx_512_1023" },
172 { 0x12, "rx_1024_1522" },
173 { 0x13, "rx_1523_2000" },
174 { 0x14, "rx_2001" },
175 { 0x15, "tx_hi" },
176 { 0x16, "tx_late_col" },
177 { 0x17, "tx_pause" },
178 { 0x18, "tx_bcast" },
179 { 0x19, "tx_mcast" },
180 { 0x1A, "tx_ucast" },
181 { 0x1B, "tx_deferred" },
182 { 0x1C, "tx_total_col" },
183 { 0x1D, "tx_exc_col" },
184 { 0x1E, "tx_single_col" },
185 { 0x1F, "tx_mult_col" },
186 { 0x80, "rx_total" },
187 { 0x81, "tx_total" },
188 { 0x82, "rx_discards" },
189 { 0x83, "tx_discards" },
190 };
191
192 struct ksz_driver_strength_prop {
193 const char *name;
194 int offset;
195 int value;
196 };
197
198 enum ksz_driver_strength_type {
199 KSZ_DRIVER_STRENGTH_HI,
200 KSZ_DRIVER_STRENGTH_LO,
201 KSZ_DRIVER_STRENGTH_IO,
202 };
203
204 /**
205 * struct ksz_drive_strength - drive strength mapping
206 * @reg_val: register value
207 * @microamp: microamp value
208 */
209 struct ksz_drive_strength {
210 u32 reg_val;
211 u32 microamp;
212 };
213
214 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants
215 *
216 * This values are not documented in KSZ9477 variants but confirmed by
217 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893
218 * and KSZ8563 are using same register (drive strength) settings like KSZ8795.
219 *
220 * Documentation in KSZ8795CLX provides more information with some
221 * recommendations:
222 * - for high speed signals
223 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using
224 * 2.5V or 3.3V VDDIO.
225 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with
226 * using 1.8V VDDIO.
227 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V
228 * or 3.3V VDDIO.
229 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO.
230 * 5. In same interface, the heavy loading should use higher one of the
231 * drive current strength.
232 * - for low speed signals
233 * 1. 3.3V VDDIO, use either 4 mA or 8 mA.
234 * 2. 2.5V VDDIO, use either 8 mA or 12 mA.
235 * 3. 1.8V VDDIO, use either 12 mA or 16 mA.
236 * 4. If it is heavy loading, can use higher drive current strength.
237 */
238 static const struct ksz_drive_strength ksz9477_drive_strengths[] = {
239 { SW_DRIVE_STRENGTH_2MA, 2000 },
240 { SW_DRIVE_STRENGTH_4MA, 4000 },
241 { SW_DRIVE_STRENGTH_8MA, 8000 },
242 { SW_DRIVE_STRENGTH_12MA, 12000 },
243 { SW_DRIVE_STRENGTH_16MA, 16000 },
244 { SW_DRIVE_STRENGTH_20MA, 20000 },
245 { SW_DRIVE_STRENGTH_24MA, 24000 },
246 { SW_DRIVE_STRENGTH_28MA, 28000 },
247 };
248
249 /* ksz8830_drive_strengths - Drive strength mapping for KSZ8830, KSZ8873, ..
250 * variants.
251 * This values are documented in KSZ8873 and KSZ8863 datasheets.
252 */
253 static const struct ksz_drive_strength ksz8830_drive_strengths[] = {
254 { 0, 8000 },
255 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 },
256 };
257
258 static void ksz8830_phylink_mac_config(struct phylink_config *config,
259 unsigned int mode,
260 const struct phylink_link_state *state);
261 static void ksz_phylink_mac_config(struct phylink_config *config,
262 unsigned int mode,
263 const struct phylink_link_state *state);
264 static void ksz_phylink_mac_link_down(struct phylink_config *config,
265 unsigned int mode,
266 phy_interface_t interface);
267
268 static const struct phylink_mac_ops ksz8830_phylink_mac_ops = {
269 .mac_config = ksz8830_phylink_mac_config,
270 .mac_link_down = ksz_phylink_mac_link_down,
271 .mac_link_up = ksz8_phylink_mac_link_up,
272 };
273
274 static const struct phylink_mac_ops ksz8_phylink_mac_ops = {
275 .mac_config = ksz_phylink_mac_config,
276 .mac_link_down = ksz_phylink_mac_link_down,
277 .mac_link_up = ksz8_phylink_mac_link_up,
278 };
279
280 static const struct ksz_dev_ops ksz8_dev_ops = {
281 .setup = ksz8_setup,
282 .get_port_addr = ksz8_get_port_addr,
283 .cfg_port_member = ksz8_cfg_port_member,
284 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
285 .port_setup = ksz8_port_setup,
286 .r_phy = ksz8_r_phy,
287 .w_phy = ksz8_w_phy,
288 .r_mib_cnt = ksz8_r_mib_cnt,
289 .r_mib_pkt = ksz8_r_mib_pkt,
290 .r_mib_stat64 = ksz88xx_r_mib_stats64,
291 .freeze_mib = ksz8_freeze_mib,
292 .port_init_cnt = ksz8_port_init_cnt,
293 .fdb_dump = ksz8_fdb_dump,
294 .fdb_add = ksz8_fdb_add,
295 .fdb_del = ksz8_fdb_del,
296 .mdb_add = ksz8_mdb_add,
297 .mdb_del = ksz8_mdb_del,
298 .vlan_filtering = ksz8_port_vlan_filtering,
299 .vlan_add = ksz8_port_vlan_add,
300 .vlan_del = ksz8_port_vlan_del,
301 .mirror_add = ksz8_port_mirror_add,
302 .mirror_del = ksz8_port_mirror_del,
303 .get_caps = ksz8_get_caps,
304 .config_cpu_port = ksz8_config_cpu_port,
305 .enable_stp_addr = ksz8_enable_stp_addr,
306 .reset = ksz8_reset_switch,
307 .init = ksz8_switch_init,
308 .exit = ksz8_switch_exit,
309 .change_mtu = ksz8_change_mtu,
310 };
311
312 static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
313 struct phy_device *phydev,
314 unsigned int mode,
315 phy_interface_t interface,
316 int speed, int duplex, bool tx_pause,
317 bool rx_pause);
318
319 static const struct phylink_mac_ops ksz9477_phylink_mac_ops = {
320 .mac_config = ksz_phylink_mac_config,
321 .mac_link_down = ksz_phylink_mac_link_down,
322 .mac_link_up = ksz9477_phylink_mac_link_up,
323 };
324
325 static const struct ksz_dev_ops ksz9477_dev_ops = {
326 .setup = ksz9477_setup,
327 .get_port_addr = ksz9477_get_port_addr,
328 .cfg_port_member = ksz9477_cfg_port_member,
329 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
330 .port_setup = ksz9477_port_setup,
331 .set_ageing_time = ksz9477_set_ageing_time,
332 .r_phy = ksz9477_r_phy,
333 .w_phy = ksz9477_w_phy,
334 .r_mib_cnt = ksz9477_r_mib_cnt,
335 .r_mib_pkt = ksz9477_r_mib_pkt,
336 .r_mib_stat64 = ksz_r_mib_stats64,
337 .freeze_mib = ksz9477_freeze_mib,
338 .port_init_cnt = ksz9477_port_init_cnt,
339 .vlan_filtering = ksz9477_port_vlan_filtering,
340 .vlan_add = ksz9477_port_vlan_add,
341 .vlan_del = ksz9477_port_vlan_del,
342 .mirror_add = ksz9477_port_mirror_add,
343 .mirror_del = ksz9477_port_mirror_del,
344 .get_caps = ksz9477_get_caps,
345 .fdb_dump = ksz9477_fdb_dump,
346 .fdb_add = ksz9477_fdb_add,
347 .fdb_del = ksz9477_fdb_del,
348 .mdb_add = ksz9477_mdb_add,
349 .mdb_del = ksz9477_mdb_del,
350 .change_mtu = ksz9477_change_mtu,
351 .get_wol = ksz9477_get_wol,
352 .set_wol = ksz9477_set_wol,
353 .wol_pre_shutdown = ksz9477_wol_pre_shutdown,
354 .config_cpu_port = ksz9477_config_cpu_port,
355 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc,
356 .enable_stp_addr = ksz9477_enable_stp_addr,
357 .reset = ksz9477_reset_switch,
358 .init = ksz9477_switch_init,
359 .exit = ksz9477_switch_exit,
360 };
361
362 static const struct phylink_mac_ops lan937x_phylink_mac_ops = {
363 .mac_config = ksz_phylink_mac_config,
364 .mac_link_down = ksz_phylink_mac_link_down,
365 .mac_link_up = ksz9477_phylink_mac_link_up,
366 };
367
368 static const struct ksz_dev_ops lan937x_dev_ops = {
369 .setup = lan937x_setup,
370 .teardown = lan937x_teardown,
371 .get_port_addr = ksz9477_get_port_addr,
372 .cfg_port_member = ksz9477_cfg_port_member,
373 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
374 .port_setup = lan937x_port_setup,
375 .set_ageing_time = lan937x_set_ageing_time,
376 .r_phy = lan937x_r_phy,
377 .w_phy = lan937x_w_phy,
378 .r_mib_cnt = ksz9477_r_mib_cnt,
379 .r_mib_pkt = ksz9477_r_mib_pkt,
380 .r_mib_stat64 = ksz_r_mib_stats64,
381 .freeze_mib = ksz9477_freeze_mib,
382 .port_init_cnt = ksz9477_port_init_cnt,
383 .vlan_filtering = ksz9477_port_vlan_filtering,
384 .vlan_add = ksz9477_port_vlan_add,
385 .vlan_del = ksz9477_port_vlan_del,
386 .mirror_add = ksz9477_port_mirror_add,
387 .mirror_del = ksz9477_port_mirror_del,
388 .get_caps = lan937x_phylink_get_caps,
389 .setup_rgmii_delay = lan937x_setup_rgmii_delay,
390 .fdb_dump = ksz9477_fdb_dump,
391 .fdb_add = ksz9477_fdb_add,
392 .fdb_del = ksz9477_fdb_del,
393 .mdb_add = ksz9477_mdb_add,
394 .mdb_del = ksz9477_mdb_del,
395 .change_mtu = lan937x_change_mtu,
396 .config_cpu_port = lan937x_config_cpu_port,
397 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc,
398 .enable_stp_addr = ksz9477_enable_stp_addr,
399 .reset = lan937x_reset_switch,
400 .init = lan937x_switch_init,
401 .exit = lan937x_switch_exit,
402 };
403
404 static const u16 ksz8795_regs[] = {
405 [REG_SW_MAC_ADDR] = 0x68,
406 [REG_IND_CTRL_0] = 0x6E,
407 [REG_IND_DATA_8] = 0x70,
408 [REG_IND_DATA_CHECK] = 0x72,
409 [REG_IND_DATA_HI] = 0x71,
410 [REG_IND_DATA_LO] = 0x75,
411 [REG_IND_MIB_CHECK] = 0x74,
412 [REG_IND_BYTE] = 0xA0,
413 [P_FORCE_CTRL] = 0x0C,
414 [P_LINK_STATUS] = 0x0E,
415 [P_LOCAL_CTRL] = 0x07,
416 [P_NEG_RESTART_CTRL] = 0x0D,
417 [P_REMOTE_STATUS] = 0x08,
418 [P_SPEED_STATUS] = 0x09,
419 [S_TAIL_TAG_CTRL] = 0x0C,
420 [P_STP_CTRL] = 0x02,
421 [S_START_CTRL] = 0x01,
422 [S_BROADCAST_CTRL] = 0x06,
423 [S_MULTICAST_CTRL] = 0x04,
424 [P_XMII_CTRL_0] = 0x06,
425 [P_XMII_CTRL_1] = 0x06,
426 };
427
428 static const u32 ksz8795_masks[] = {
429 [PORT_802_1P_REMAPPING] = BIT(7),
430 [SW_TAIL_TAG_ENABLE] = BIT(1),
431 [MIB_COUNTER_OVERFLOW] = BIT(6),
432 [MIB_COUNTER_VALID] = BIT(5),
433 [VLAN_TABLE_FID] = GENMASK(6, 0),
434 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
435 [VLAN_TABLE_VALID] = BIT(12),
436 [STATIC_MAC_TABLE_VALID] = BIT(21),
437 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
438 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
439 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
440 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
441 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
442 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
443 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
444 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
445 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
446 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
447 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
448 [P_MII_TX_FLOW_CTRL] = BIT(5),
449 [P_MII_RX_FLOW_CTRL] = BIT(5),
450 };
451
452 static const u8 ksz8795_xmii_ctrl0[] = {
453 [P_MII_100MBIT] = 0,
454 [P_MII_10MBIT] = 1,
455 [P_MII_FULL_DUPLEX] = 0,
456 [P_MII_HALF_DUPLEX] = 1,
457 };
458
459 static const u8 ksz8795_xmii_ctrl1[] = {
460 [P_RGMII_SEL] = 3,
461 [P_GMII_SEL] = 2,
462 [P_RMII_SEL] = 1,
463 [P_MII_SEL] = 0,
464 [P_GMII_1GBIT] = 1,
465 [P_GMII_NOT_1GBIT] = 0,
466 };
467
468 static const u8 ksz8795_shifts[] = {
469 [VLAN_TABLE_MEMBERSHIP_S] = 7,
470 [VLAN_TABLE] = 16,
471 [STATIC_MAC_FWD_PORTS] = 16,
472 [STATIC_MAC_FID] = 24,
473 [DYNAMIC_MAC_ENTRIES_H] = 3,
474 [DYNAMIC_MAC_ENTRIES] = 29,
475 [DYNAMIC_MAC_FID] = 16,
476 [DYNAMIC_MAC_TIMESTAMP] = 27,
477 [DYNAMIC_MAC_SRC_PORT] = 24,
478 };
479
480 static const u16 ksz8863_regs[] = {
481 [REG_SW_MAC_ADDR] = 0x70,
482 [REG_IND_CTRL_0] = 0x79,
483 [REG_IND_DATA_8] = 0x7B,
484 [REG_IND_DATA_CHECK] = 0x7B,
485 [REG_IND_DATA_HI] = 0x7C,
486 [REG_IND_DATA_LO] = 0x80,
487 [REG_IND_MIB_CHECK] = 0x80,
488 [P_FORCE_CTRL] = 0x0C,
489 [P_LINK_STATUS] = 0x0E,
490 [P_LOCAL_CTRL] = 0x0C,
491 [P_NEG_RESTART_CTRL] = 0x0D,
492 [P_REMOTE_STATUS] = 0x0E,
493 [P_SPEED_STATUS] = 0x0F,
494 [S_TAIL_TAG_CTRL] = 0x03,
495 [P_STP_CTRL] = 0x02,
496 [S_START_CTRL] = 0x01,
497 [S_BROADCAST_CTRL] = 0x06,
498 [S_MULTICAST_CTRL] = 0x04,
499 };
500
501 static const u32 ksz8863_masks[] = {
502 [PORT_802_1P_REMAPPING] = BIT(3),
503 [SW_TAIL_TAG_ENABLE] = BIT(6),
504 [MIB_COUNTER_OVERFLOW] = BIT(7),
505 [MIB_COUNTER_VALID] = BIT(6),
506 [VLAN_TABLE_FID] = GENMASK(15, 12),
507 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
508 [VLAN_TABLE_VALID] = BIT(19),
509 [STATIC_MAC_TABLE_VALID] = BIT(19),
510 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
511 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
512 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
513 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
514 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
515 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
516 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
517 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
518 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
519 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
520 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
521 };
522
523 static u8 ksz8863_shifts[] = {
524 [VLAN_TABLE_MEMBERSHIP_S] = 16,
525 [STATIC_MAC_FWD_PORTS] = 16,
526 [STATIC_MAC_FID] = 22,
527 [DYNAMIC_MAC_ENTRIES_H] = 8,
528 [DYNAMIC_MAC_ENTRIES] = 24,
529 [DYNAMIC_MAC_FID] = 16,
530 [DYNAMIC_MAC_TIMESTAMP] = 22,
531 [DYNAMIC_MAC_SRC_PORT] = 20,
532 };
533
534 static const u16 ksz9477_regs[] = {
535 [REG_SW_MAC_ADDR] = 0x0302,
536 [P_STP_CTRL] = 0x0B04,
537 [S_START_CTRL] = 0x0300,
538 [S_BROADCAST_CTRL] = 0x0332,
539 [S_MULTICAST_CTRL] = 0x0331,
540 [P_XMII_CTRL_0] = 0x0300,
541 [P_XMII_CTRL_1] = 0x0301,
542 };
543
544 static const u32 ksz9477_masks[] = {
545 [ALU_STAT_WRITE] = 0,
546 [ALU_STAT_READ] = 1,
547 [P_MII_TX_FLOW_CTRL] = BIT(5),
548 [P_MII_RX_FLOW_CTRL] = BIT(3),
549 };
550
551 static const u8 ksz9477_shifts[] = {
552 [ALU_STAT_INDEX] = 16,
553 };
554
555 static const u8 ksz9477_xmii_ctrl0[] = {
556 [P_MII_100MBIT] = 1,
557 [P_MII_10MBIT] = 0,
558 [P_MII_FULL_DUPLEX] = 1,
559 [P_MII_HALF_DUPLEX] = 0,
560 };
561
562 static const u8 ksz9477_xmii_ctrl1[] = {
563 [P_RGMII_SEL] = 0,
564 [P_RMII_SEL] = 1,
565 [P_GMII_SEL] = 2,
566 [P_MII_SEL] = 3,
567 [P_GMII_1GBIT] = 0,
568 [P_GMII_NOT_1GBIT] = 1,
569 };
570
571 static const u32 lan937x_masks[] = {
572 [ALU_STAT_WRITE] = 1,
573 [ALU_STAT_READ] = 2,
574 [P_MII_TX_FLOW_CTRL] = BIT(5),
575 [P_MII_RX_FLOW_CTRL] = BIT(3),
576 };
577
578 static const u8 lan937x_shifts[] = {
579 [ALU_STAT_INDEX] = 8,
580 };
581
582 static const struct regmap_range ksz8563_valid_regs[] = {
583 regmap_reg_range(0x0000, 0x0003),
584 regmap_reg_range(0x0006, 0x0006),
585 regmap_reg_range(0x000f, 0x001f),
586 regmap_reg_range(0x0100, 0x0100),
587 regmap_reg_range(0x0104, 0x0107),
588 regmap_reg_range(0x010d, 0x010d),
589 regmap_reg_range(0x0110, 0x0113),
590 regmap_reg_range(0x0120, 0x012b),
591 regmap_reg_range(0x0201, 0x0201),
592 regmap_reg_range(0x0210, 0x0213),
593 regmap_reg_range(0x0300, 0x0300),
594 regmap_reg_range(0x0302, 0x031b),
595 regmap_reg_range(0x0320, 0x032b),
596 regmap_reg_range(0x0330, 0x0336),
597 regmap_reg_range(0x0338, 0x033e),
598 regmap_reg_range(0x0340, 0x035f),
599 regmap_reg_range(0x0370, 0x0370),
600 regmap_reg_range(0x0378, 0x0378),
601 regmap_reg_range(0x037c, 0x037d),
602 regmap_reg_range(0x0390, 0x0393),
603 regmap_reg_range(0x0400, 0x040e),
604 regmap_reg_range(0x0410, 0x042f),
605 regmap_reg_range(0x0500, 0x0519),
606 regmap_reg_range(0x0520, 0x054b),
607 regmap_reg_range(0x0550, 0x05b3),
608
609 /* port 1 */
610 regmap_reg_range(0x1000, 0x1001),
611 regmap_reg_range(0x1004, 0x100b),
612 regmap_reg_range(0x1013, 0x1013),
613 regmap_reg_range(0x1017, 0x1017),
614 regmap_reg_range(0x101b, 0x101b),
615 regmap_reg_range(0x101f, 0x1021),
616 regmap_reg_range(0x1030, 0x1030),
617 regmap_reg_range(0x1100, 0x1111),
618 regmap_reg_range(0x111a, 0x111d),
619 regmap_reg_range(0x1122, 0x1127),
620 regmap_reg_range(0x112a, 0x112b),
621 regmap_reg_range(0x1136, 0x1139),
622 regmap_reg_range(0x113e, 0x113f),
623 regmap_reg_range(0x1400, 0x1401),
624 regmap_reg_range(0x1403, 0x1403),
625 regmap_reg_range(0x1410, 0x1417),
626 regmap_reg_range(0x1420, 0x1423),
627 regmap_reg_range(0x1500, 0x1507),
628 regmap_reg_range(0x1600, 0x1612),
629 regmap_reg_range(0x1800, 0x180f),
630 regmap_reg_range(0x1900, 0x1907),
631 regmap_reg_range(0x1914, 0x191b),
632 regmap_reg_range(0x1a00, 0x1a03),
633 regmap_reg_range(0x1a04, 0x1a08),
634 regmap_reg_range(0x1b00, 0x1b01),
635 regmap_reg_range(0x1b04, 0x1b04),
636 regmap_reg_range(0x1c00, 0x1c05),
637 regmap_reg_range(0x1c08, 0x1c1b),
638
639 /* port 2 */
640 regmap_reg_range(0x2000, 0x2001),
641 regmap_reg_range(0x2004, 0x200b),
642 regmap_reg_range(0x2013, 0x2013),
643 regmap_reg_range(0x2017, 0x2017),
644 regmap_reg_range(0x201b, 0x201b),
645 regmap_reg_range(0x201f, 0x2021),
646 regmap_reg_range(0x2030, 0x2030),
647 regmap_reg_range(0x2100, 0x2111),
648 regmap_reg_range(0x211a, 0x211d),
649 regmap_reg_range(0x2122, 0x2127),
650 regmap_reg_range(0x212a, 0x212b),
651 regmap_reg_range(0x2136, 0x2139),
652 regmap_reg_range(0x213e, 0x213f),
653 regmap_reg_range(0x2400, 0x2401),
654 regmap_reg_range(0x2403, 0x2403),
655 regmap_reg_range(0x2410, 0x2417),
656 regmap_reg_range(0x2420, 0x2423),
657 regmap_reg_range(0x2500, 0x2507),
658 regmap_reg_range(0x2600, 0x2612),
659 regmap_reg_range(0x2800, 0x280f),
660 regmap_reg_range(0x2900, 0x2907),
661 regmap_reg_range(0x2914, 0x291b),
662 regmap_reg_range(0x2a00, 0x2a03),
663 regmap_reg_range(0x2a04, 0x2a08),
664 regmap_reg_range(0x2b00, 0x2b01),
665 regmap_reg_range(0x2b04, 0x2b04),
666 regmap_reg_range(0x2c00, 0x2c05),
667 regmap_reg_range(0x2c08, 0x2c1b),
668
669 /* port 3 */
670 regmap_reg_range(0x3000, 0x3001),
671 regmap_reg_range(0x3004, 0x300b),
672 regmap_reg_range(0x3013, 0x3013),
673 regmap_reg_range(0x3017, 0x3017),
674 regmap_reg_range(0x301b, 0x301b),
675 regmap_reg_range(0x301f, 0x3021),
676 regmap_reg_range(0x3030, 0x3030),
677 regmap_reg_range(0x3300, 0x3301),
678 regmap_reg_range(0x3303, 0x3303),
679 regmap_reg_range(0x3400, 0x3401),
680 regmap_reg_range(0x3403, 0x3403),
681 regmap_reg_range(0x3410, 0x3417),
682 regmap_reg_range(0x3420, 0x3423),
683 regmap_reg_range(0x3500, 0x3507),
684 regmap_reg_range(0x3600, 0x3612),
685 regmap_reg_range(0x3800, 0x380f),
686 regmap_reg_range(0x3900, 0x3907),
687 regmap_reg_range(0x3914, 0x391b),
688 regmap_reg_range(0x3a00, 0x3a03),
689 regmap_reg_range(0x3a04, 0x3a08),
690 regmap_reg_range(0x3b00, 0x3b01),
691 regmap_reg_range(0x3b04, 0x3b04),
692 regmap_reg_range(0x3c00, 0x3c05),
693 regmap_reg_range(0x3c08, 0x3c1b),
694 };
695
696 static const struct regmap_access_table ksz8563_register_set = {
697 .yes_ranges = ksz8563_valid_regs,
698 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
699 };
700
701 static const struct regmap_range ksz9477_valid_regs[] = {
702 regmap_reg_range(0x0000, 0x0003),
703 regmap_reg_range(0x0006, 0x0006),
704 regmap_reg_range(0x0010, 0x001f),
705 regmap_reg_range(0x0100, 0x0100),
706 regmap_reg_range(0x0103, 0x0107),
707 regmap_reg_range(0x010d, 0x010d),
708 regmap_reg_range(0x0110, 0x0113),
709 regmap_reg_range(0x0120, 0x012b),
710 regmap_reg_range(0x0201, 0x0201),
711 regmap_reg_range(0x0210, 0x0213),
712 regmap_reg_range(0x0300, 0x0300),
713 regmap_reg_range(0x0302, 0x031b),
714 regmap_reg_range(0x0320, 0x032b),
715 regmap_reg_range(0x0330, 0x0336),
716 regmap_reg_range(0x0338, 0x033b),
717 regmap_reg_range(0x033e, 0x033e),
718 regmap_reg_range(0x0340, 0x035f),
719 regmap_reg_range(0x0370, 0x0370),
720 regmap_reg_range(0x0378, 0x0378),
721 regmap_reg_range(0x037c, 0x037d),
722 regmap_reg_range(0x0390, 0x0393),
723 regmap_reg_range(0x0400, 0x040e),
724 regmap_reg_range(0x0410, 0x042f),
725 regmap_reg_range(0x0444, 0x044b),
726 regmap_reg_range(0x0450, 0x046f),
727 regmap_reg_range(0x0500, 0x0519),
728 regmap_reg_range(0x0520, 0x054b),
729 regmap_reg_range(0x0550, 0x05b3),
730 regmap_reg_range(0x0604, 0x060b),
731 regmap_reg_range(0x0610, 0x0612),
732 regmap_reg_range(0x0614, 0x062c),
733 regmap_reg_range(0x0640, 0x0645),
734 regmap_reg_range(0x0648, 0x064d),
735
736 /* port 1 */
737 regmap_reg_range(0x1000, 0x1001),
738 regmap_reg_range(0x1013, 0x1013),
739 regmap_reg_range(0x1017, 0x1017),
740 regmap_reg_range(0x101b, 0x101b),
741 regmap_reg_range(0x101f, 0x1020),
742 regmap_reg_range(0x1030, 0x1030),
743 regmap_reg_range(0x1100, 0x1115),
744 regmap_reg_range(0x111a, 0x111f),
745 regmap_reg_range(0x1120, 0x112b),
746 regmap_reg_range(0x1134, 0x113b),
747 regmap_reg_range(0x113c, 0x113f),
748 regmap_reg_range(0x1400, 0x1401),
749 regmap_reg_range(0x1403, 0x1403),
750 regmap_reg_range(0x1410, 0x1417),
751 regmap_reg_range(0x1420, 0x1423),
752 regmap_reg_range(0x1500, 0x1507),
753 regmap_reg_range(0x1600, 0x1613),
754 regmap_reg_range(0x1800, 0x180f),
755 regmap_reg_range(0x1820, 0x1827),
756 regmap_reg_range(0x1830, 0x1837),
757 regmap_reg_range(0x1840, 0x184b),
758 regmap_reg_range(0x1900, 0x1907),
759 regmap_reg_range(0x1914, 0x191b),
760 regmap_reg_range(0x1920, 0x1920),
761 regmap_reg_range(0x1923, 0x1927),
762 regmap_reg_range(0x1a00, 0x1a03),
763 regmap_reg_range(0x1a04, 0x1a07),
764 regmap_reg_range(0x1b00, 0x1b01),
765 regmap_reg_range(0x1b04, 0x1b04),
766 regmap_reg_range(0x1c00, 0x1c05),
767 regmap_reg_range(0x1c08, 0x1c1b),
768
769 /* port 2 */
770 regmap_reg_range(0x2000, 0x2001),
771 regmap_reg_range(0x2013, 0x2013),
772 regmap_reg_range(0x2017, 0x2017),
773 regmap_reg_range(0x201b, 0x201b),
774 regmap_reg_range(0x201f, 0x2020),
775 regmap_reg_range(0x2030, 0x2030),
776 regmap_reg_range(0x2100, 0x2115),
777 regmap_reg_range(0x211a, 0x211f),
778 regmap_reg_range(0x2120, 0x212b),
779 regmap_reg_range(0x2134, 0x213b),
780 regmap_reg_range(0x213c, 0x213f),
781 regmap_reg_range(0x2400, 0x2401),
782 regmap_reg_range(0x2403, 0x2403),
783 regmap_reg_range(0x2410, 0x2417),
784 regmap_reg_range(0x2420, 0x2423),
785 regmap_reg_range(0x2500, 0x2507),
786 regmap_reg_range(0x2600, 0x2613),
787 regmap_reg_range(0x2800, 0x280f),
788 regmap_reg_range(0x2820, 0x2827),
789 regmap_reg_range(0x2830, 0x2837),
790 regmap_reg_range(0x2840, 0x284b),
791 regmap_reg_range(0x2900, 0x2907),
792 regmap_reg_range(0x2914, 0x291b),
793 regmap_reg_range(0x2920, 0x2920),
794 regmap_reg_range(0x2923, 0x2927),
795 regmap_reg_range(0x2a00, 0x2a03),
796 regmap_reg_range(0x2a04, 0x2a07),
797 regmap_reg_range(0x2b00, 0x2b01),
798 regmap_reg_range(0x2b04, 0x2b04),
799 regmap_reg_range(0x2c00, 0x2c05),
800 regmap_reg_range(0x2c08, 0x2c1b),
801
802 /* port 3 */
803 regmap_reg_range(0x3000, 0x3001),
804 regmap_reg_range(0x3013, 0x3013),
805 regmap_reg_range(0x3017, 0x3017),
806 regmap_reg_range(0x301b, 0x301b),
807 regmap_reg_range(0x301f, 0x3020),
808 regmap_reg_range(0x3030, 0x3030),
809 regmap_reg_range(0x3100, 0x3115),
810 regmap_reg_range(0x311a, 0x311f),
811 regmap_reg_range(0x3120, 0x312b),
812 regmap_reg_range(0x3134, 0x313b),
813 regmap_reg_range(0x313c, 0x313f),
814 regmap_reg_range(0x3400, 0x3401),
815 regmap_reg_range(0x3403, 0x3403),
816 regmap_reg_range(0x3410, 0x3417),
817 regmap_reg_range(0x3420, 0x3423),
818 regmap_reg_range(0x3500, 0x3507),
819 regmap_reg_range(0x3600, 0x3613),
820 regmap_reg_range(0x3800, 0x380f),
821 regmap_reg_range(0x3820, 0x3827),
822 regmap_reg_range(0x3830, 0x3837),
823 regmap_reg_range(0x3840, 0x384b),
824 regmap_reg_range(0x3900, 0x3907),
825 regmap_reg_range(0x3914, 0x391b),
826 regmap_reg_range(0x3920, 0x3920),
827 regmap_reg_range(0x3923, 0x3927),
828 regmap_reg_range(0x3a00, 0x3a03),
829 regmap_reg_range(0x3a04, 0x3a07),
830 regmap_reg_range(0x3b00, 0x3b01),
831 regmap_reg_range(0x3b04, 0x3b04),
832 regmap_reg_range(0x3c00, 0x3c05),
833 regmap_reg_range(0x3c08, 0x3c1b),
834
835 /* port 4 */
836 regmap_reg_range(0x4000, 0x4001),
837 regmap_reg_range(0x4013, 0x4013),
838 regmap_reg_range(0x4017, 0x4017),
839 regmap_reg_range(0x401b, 0x401b),
840 regmap_reg_range(0x401f, 0x4020),
841 regmap_reg_range(0x4030, 0x4030),
842 regmap_reg_range(0x4100, 0x4115),
843 regmap_reg_range(0x411a, 0x411f),
844 regmap_reg_range(0x4120, 0x412b),
845 regmap_reg_range(0x4134, 0x413b),
846 regmap_reg_range(0x413c, 0x413f),
847 regmap_reg_range(0x4400, 0x4401),
848 regmap_reg_range(0x4403, 0x4403),
849 regmap_reg_range(0x4410, 0x4417),
850 regmap_reg_range(0x4420, 0x4423),
851 regmap_reg_range(0x4500, 0x4507),
852 regmap_reg_range(0x4600, 0x4613),
853 regmap_reg_range(0x4800, 0x480f),
854 regmap_reg_range(0x4820, 0x4827),
855 regmap_reg_range(0x4830, 0x4837),
856 regmap_reg_range(0x4840, 0x484b),
857 regmap_reg_range(0x4900, 0x4907),
858 regmap_reg_range(0x4914, 0x491b),
859 regmap_reg_range(0x4920, 0x4920),
860 regmap_reg_range(0x4923, 0x4927),
861 regmap_reg_range(0x4a00, 0x4a03),
862 regmap_reg_range(0x4a04, 0x4a07),
863 regmap_reg_range(0x4b00, 0x4b01),
864 regmap_reg_range(0x4b04, 0x4b04),
865 regmap_reg_range(0x4c00, 0x4c05),
866 regmap_reg_range(0x4c08, 0x4c1b),
867
868 /* port 5 */
869 regmap_reg_range(0x5000, 0x5001),
870 regmap_reg_range(0x5013, 0x5013),
871 regmap_reg_range(0x5017, 0x5017),
872 regmap_reg_range(0x501b, 0x501b),
873 regmap_reg_range(0x501f, 0x5020),
874 regmap_reg_range(0x5030, 0x5030),
875 regmap_reg_range(0x5100, 0x5115),
876 regmap_reg_range(0x511a, 0x511f),
877 regmap_reg_range(0x5120, 0x512b),
878 regmap_reg_range(0x5134, 0x513b),
879 regmap_reg_range(0x513c, 0x513f),
880 regmap_reg_range(0x5400, 0x5401),
881 regmap_reg_range(0x5403, 0x5403),
882 regmap_reg_range(0x5410, 0x5417),
883 regmap_reg_range(0x5420, 0x5423),
884 regmap_reg_range(0x5500, 0x5507),
885 regmap_reg_range(0x5600, 0x5613),
886 regmap_reg_range(0x5800, 0x580f),
887 regmap_reg_range(0x5820, 0x5827),
888 regmap_reg_range(0x5830, 0x5837),
889 regmap_reg_range(0x5840, 0x584b),
890 regmap_reg_range(0x5900, 0x5907),
891 regmap_reg_range(0x5914, 0x591b),
892 regmap_reg_range(0x5920, 0x5920),
893 regmap_reg_range(0x5923, 0x5927),
894 regmap_reg_range(0x5a00, 0x5a03),
895 regmap_reg_range(0x5a04, 0x5a07),
896 regmap_reg_range(0x5b00, 0x5b01),
897 regmap_reg_range(0x5b04, 0x5b04),
898 regmap_reg_range(0x5c00, 0x5c05),
899 regmap_reg_range(0x5c08, 0x5c1b),
900
901 /* port 6 */
902 regmap_reg_range(0x6000, 0x6001),
903 regmap_reg_range(0x6013, 0x6013),
904 regmap_reg_range(0x6017, 0x6017),
905 regmap_reg_range(0x601b, 0x601b),
906 regmap_reg_range(0x601f, 0x6020),
907 regmap_reg_range(0x6030, 0x6030),
908 regmap_reg_range(0x6300, 0x6301),
909 regmap_reg_range(0x6400, 0x6401),
910 regmap_reg_range(0x6403, 0x6403),
911 regmap_reg_range(0x6410, 0x6417),
912 regmap_reg_range(0x6420, 0x6423),
913 regmap_reg_range(0x6500, 0x6507),
914 regmap_reg_range(0x6600, 0x6613),
915 regmap_reg_range(0x6800, 0x680f),
916 regmap_reg_range(0x6820, 0x6827),
917 regmap_reg_range(0x6830, 0x6837),
918 regmap_reg_range(0x6840, 0x684b),
919 regmap_reg_range(0x6900, 0x6907),
920 regmap_reg_range(0x6914, 0x691b),
921 regmap_reg_range(0x6920, 0x6920),
922 regmap_reg_range(0x6923, 0x6927),
923 regmap_reg_range(0x6a00, 0x6a03),
924 regmap_reg_range(0x6a04, 0x6a07),
925 regmap_reg_range(0x6b00, 0x6b01),
926 regmap_reg_range(0x6b04, 0x6b04),
927 regmap_reg_range(0x6c00, 0x6c05),
928 regmap_reg_range(0x6c08, 0x6c1b),
929
930 /* port 7 */
931 regmap_reg_range(0x7000, 0x7001),
932 regmap_reg_range(0x7013, 0x7013),
933 regmap_reg_range(0x7017, 0x7017),
934 regmap_reg_range(0x701b, 0x701b),
935 regmap_reg_range(0x701f, 0x7020),
936 regmap_reg_range(0x7030, 0x7030),
937 regmap_reg_range(0x7200, 0x7203),
938 regmap_reg_range(0x7206, 0x7207),
939 regmap_reg_range(0x7300, 0x7301),
940 regmap_reg_range(0x7400, 0x7401),
941 regmap_reg_range(0x7403, 0x7403),
942 regmap_reg_range(0x7410, 0x7417),
943 regmap_reg_range(0x7420, 0x7423),
944 regmap_reg_range(0x7500, 0x7507),
945 regmap_reg_range(0x7600, 0x7613),
946 regmap_reg_range(0x7800, 0x780f),
947 regmap_reg_range(0x7820, 0x7827),
948 regmap_reg_range(0x7830, 0x7837),
949 regmap_reg_range(0x7840, 0x784b),
950 regmap_reg_range(0x7900, 0x7907),
951 regmap_reg_range(0x7914, 0x791b),
952 regmap_reg_range(0x7920, 0x7920),
953 regmap_reg_range(0x7923, 0x7927),
954 regmap_reg_range(0x7a00, 0x7a03),
955 regmap_reg_range(0x7a04, 0x7a07),
956 regmap_reg_range(0x7b00, 0x7b01),
957 regmap_reg_range(0x7b04, 0x7b04),
958 regmap_reg_range(0x7c00, 0x7c05),
959 regmap_reg_range(0x7c08, 0x7c1b),
960 };
961
962 static const struct regmap_access_table ksz9477_register_set = {
963 .yes_ranges = ksz9477_valid_regs,
964 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
965 };
966
967 static const struct regmap_range ksz9896_valid_regs[] = {
968 regmap_reg_range(0x0000, 0x0003),
969 regmap_reg_range(0x0006, 0x0006),
970 regmap_reg_range(0x0010, 0x001f),
971 regmap_reg_range(0x0100, 0x0100),
972 regmap_reg_range(0x0103, 0x0107),
973 regmap_reg_range(0x010d, 0x010d),
974 regmap_reg_range(0x0110, 0x0113),
975 regmap_reg_range(0x0120, 0x0127),
976 regmap_reg_range(0x0201, 0x0201),
977 regmap_reg_range(0x0210, 0x0213),
978 regmap_reg_range(0x0300, 0x0300),
979 regmap_reg_range(0x0302, 0x030b),
980 regmap_reg_range(0x0310, 0x031b),
981 regmap_reg_range(0x0320, 0x032b),
982 regmap_reg_range(0x0330, 0x0336),
983 regmap_reg_range(0x0338, 0x033b),
984 regmap_reg_range(0x033e, 0x033e),
985 regmap_reg_range(0x0340, 0x035f),
986 regmap_reg_range(0x0370, 0x0370),
987 regmap_reg_range(0x0378, 0x0378),
988 regmap_reg_range(0x037c, 0x037d),
989 regmap_reg_range(0x0390, 0x0393),
990 regmap_reg_range(0x0400, 0x040e),
991 regmap_reg_range(0x0410, 0x042f),
992
993 /* port 1 */
994 regmap_reg_range(0x1000, 0x1001),
995 regmap_reg_range(0x1013, 0x1013),
996 regmap_reg_range(0x1017, 0x1017),
997 regmap_reg_range(0x101b, 0x101b),
998 regmap_reg_range(0x101f, 0x1020),
999 regmap_reg_range(0x1030, 0x1030),
1000 regmap_reg_range(0x1100, 0x1115),
1001 regmap_reg_range(0x111a, 0x111f),
1002 regmap_reg_range(0x1122, 0x1127),
1003 regmap_reg_range(0x112a, 0x112b),
1004 regmap_reg_range(0x1136, 0x1139),
1005 regmap_reg_range(0x113e, 0x113f),
1006 regmap_reg_range(0x1400, 0x1401),
1007 regmap_reg_range(0x1403, 0x1403),
1008 regmap_reg_range(0x1410, 0x1417),
1009 regmap_reg_range(0x1420, 0x1423),
1010 regmap_reg_range(0x1500, 0x1507),
1011 regmap_reg_range(0x1600, 0x1612),
1012 regmap_reg_range(0x1800, 0x180f),
1013 regmap_reg_range(0x1820, 0x1827),
1014 regmap_reg_range(0x1830, 0x1837),
1015 regmap_reg_range(0x1840, 0x184b),
1016 regmap_reg_range(0x1900, 0x1907),
1017 regmap_reg_range(0x1914, 0x1915),
1018 regmap_reg_range(0x1a00, 0x1a03),
1019 regmap_reg_range(0x1a04, 0x1a07),
1020 regmap_reg_range(0x1b00, 0x1b01),
1021 regmap_reg_range(0x1b04, 0x1b04),
1022
1023 /* port 2 */
1024 regmap_reg_range(0x2000, 0x2001),
1025 regmap_reg_range(0x2013, 0x2013),
1026 regmap_reg_range(0x2017, 0x2017),
1027 regmap_reg_range(0x201b, 0x201b),
1028 regmap_reg_range(0x201f, 0x2020),
1029 regmap_reg_range(0x2030, 0x2030),
1030 regmap_reg_range(0x2100, 0x2115),
1031 regmap_reg_range(0x211a, 0x211f),
1032 regmap_reg_range(0x2122, 0x2127),
1033 regmap_reg_range(0x212a, 0x212b),
1034 regmap_reg_range(0x2136, 0x2139),
1035 regmap_reg_range(0x213e, 0x213f),
1036 regmap_reg_range(0x2400, 0x2401),
1037 regmap_reg_range(0x2403, 0x2403),
1038 regmap_reg_range(0x2410, 0x2417),
1039 regmap_reg_range(0x2420, 0x2423),
1040 regmap_reg_range(0x2500, 0x2507),
1041 regmap_reg_range(0x2600, 0x2612),
1042 regmap_reg_range(0x2800, 0x280f),
1043 regmap_reg_range(0x2820, 0x2827),
1044 regmap_reg_range(0x2830, 0x2837),
1045 regmap_reg_range(0x2840, 0x284b),
1046 regmap_reg_range(0x2900, 0x2907),
1047 regmap_reg_range(0x2914, 0x2915),
1048 regmap_reg_range(0x2a00, 0x2a03),
1049 regmap_reg_range(0x2a04, 0x2a07),
1050 regmap_reg_range(0x2b00, 0x2b01),
1051 regmap_reg_range(0x2b04, 0x2b04),
1052
1053 /* port 3 */
1054 regmap_reg_range(0x3000, 0x3001),
1055 regmap_reg_range(0x3013, 0x3013),
1056 regmap_reg_range(0x3017, 0x3017),
1057 regmap_reg_range(0x301b, 0x301b),
1058 regmap_reg_range(0x301f, 0x3020),
1059 regmap_reg_range(0x3030, 0x3030),
1060 regmap_reg_range(0x3100, 0x3115),
1061 regmap_reg_range(0x311a, 0x311f),
1062 regmap_reg_range(0x3122, 0x3127),
1063 regmap_reg_range(0x312a, 0x312b),
1064 regmap_reg_range(0x3136, 0x3139),
1065 regmap_reg_range(0x313e, 0x313f),
1066 regmap_reg_range(0x3400, 0x3401),
1067 regmap_reg_range(0x3403, 0x3403),
1068 regmap_reg_range(0x3410, 0x3417),
1069 regmap_reg_range(0x3420, 0x3423),
1070 regmap_reg_range(0x3500, 0x3507),
1071 regmap_reg_range(0x3600, 0x3612),
1072 regmap_reg_range(0x3800, 0x380f),
1073 regmap_reg_range(0x3820, 0x3827),
1074 regmap_reg_range(0x3830, 0x3837),
1075 regmap_reg_range(0x3840, 0x384b),
1076 regmap_reg_range(0x3900, 0x3907),
1077 regmap_reg_range(0x3914, 0x3915),
1078 regmap_reg_range(0x3a00, 0x3a03),
1079 regmap_reg_range(0x3a04, 0x3a07),
1080 regmap_reg_range(0x3b00, 0x3b01),
1081 regmap_reg_range(0x3b04, 0x3b04),
1082
1083 /* port 4 */
1084 regmap_reg_range(0x4000, 0x4001),
1085 regmap_reg_range(0x4013, 0x4013),
1086 regmap_reg_range(0x4017, 0x4017),
1087 regmap_reg_range(0x401b, 0x401b),
1088 regmap_reg_range(0x401f, 0x4020),
1089 regmap_reg_range(0x4030, 0x4030),
1090 regmap_reg_range(0x4100, 0x4115),
1091 regmap_reg_range(0x411a, 0x411f),
1092 regmap_reg_range(0x4122, 0x4127),
1093 regmap_reg_range(0x412a, 0x412b),
1094 regmap_reg_range(0x4136, 0x4139),
1095 regmap_reg_range(0x413e, 0x413f),
1096 regmap_reg_range(0x4400, 0x4401),
1097 regmap_reg_range(0x4403, 0x4403),
1098 regmap_reg_range(0x4410, 0x4417),
1099 regmap_reg_range(0x4420, 0x4423),
1100 regmap_reg_range(0x4500, 0x4507),
1101 regmap_reg_range(0x4600, 0x4612),
1102 regmap_reg_range(0x4800, 0x480f),
1103 regmap_reg_range(0x4820, 0x4827),
1104 regmap_reg_range(0x4830, 0x4837),
1105 regmap_reg_range(0x4840, 0x484b),
1106 regmap_reg_range(0x4900, 0x4907),
1107 regmap_reg_range(0x4914, 0x4915),
1108 regmap_reg_range(0x4a00, 0x4a03),
1109 regmap_reg_range(0x4a04, 0x4a07),
1110 regmap_reg_range(0x4b00, 0x4b01),
1111 regmap_reg_range(0x4b04, 0x4b04),
1112
1113 /* port 5 */
1114 regmap_reg_range(0x5000, 0x5001),
1115 regmap_reg_range(0x5013, 0x5013),
1116 regmap_reg_range(0x5017, 0x5017),
1117 regmap_reg_range(0x501b, 0x501b),
1118 regmap_reg_range(0x501f, 0x5020),
1119 regmap_reg_range(0x5030, 0x5030),
1120 regmap_reg_range(0x5100, 0x5115),
1121 regmap_reg_range(0x511a, 0x511f),
1122 regmap_reg_range(0x5122, 0x5127),
1123 regmap_reg_range(0x512a, 0x512b),
1124 regmap_reg_range(0x5136, 0x5139),
1125 regmap_reg_range(0x513e, 0x513f),
1126 regmap_reg_range(0x5400, 0x5401),
1127 regmap_reg_range(0x5403, 0x5403),
1128 regmap_reg_range(0x5410, 0x5417),
1129 regmap_reg_range(0x5420, 0x5423),
1130 regmap_reg_range(0x5500, 0x5507),
1131 regmap_reg_range(0x5600, 0x5612),
1132 regmap_reg_range(0x5800, 0x580f),
1133 regmap_reg_range(0x5820, 0x5827),
1134 regmap_reg_range(0x5830, 0x5837),
1135 regmap_reg_range(0x5840, 0x584b),
1136 regmap_reg_range(0x5900, 0x5907),
1137 regmap_reg_range(0x5914, 0x5915),
1138 regmap_reg_range(0x5a00, 0x5a03),
1139 regmap_reg_range(0x5a04, 0x5a07),
1140 regmap_reg_range(0x5b00, 0x5b01),
1141 regmap_reg_range(0x5b04, 0x5b04),
1142
1143 /* port 6 */
1144 regmap_reg_range(0x6000, 0x6001),
1145 regmap_reg_range(0x6013, 0x6013),
1146 regmap_reg_range(0x6017, 0x6017),
1147 regmap_reg_range(0x601b, 0x601b),
1148 regmap_reg_range(0x601f, 0x6020),
1149 regmap_reg_range(0x6030, 0x6030),
1150 regmap_reg_range(0x6100, 0x6115),
1151 regmap_reg_range(0x611a, 0x611f),
1152 regmap_reg_range(0x6122, 0x6127),
1153 regmap_reg_range(0x612a, 0x612b),
1154 regmap_reg_range(0x6136, 0x6139),
1155 regmap_reg_range(0x613e, 0x613f),
1156 regmap_reg_range(0x6300, 0x6301),
1157 regmap_reg_range(0x6400, 0x6401),
1158 regmap_reg_range(0x6403, 0x6403),
1159 regmap_reg_range(0x6410, 0x6417),
1160 regmap_reg_range(0x6420, 0x6423),
1161 regmap_reg_range(0x6500, 0x6507),
1162 regmap_reg_range(0x6600, 0x6612),
1163 regmap_reg_range(0x6800, 0x680f),
1164 regmap_reg_range(0x6820, 0x6827),
1165 regmap_reg_range(0x6830, 0x6837),
1166 regmap_reg_range(0x6840, 0x684b),
1167 regmap_reg_range(0x6900, 0x6907),
1168 regmap_reg_range(0x6914, 0x6915),
1169 regmap_reg_range(0x6a00, 0x6a03),
1170 regmap_reg_range(0x6a04, 0x6a07),
1171 regmap_reg_range(0x6b00, 0x6b01),
1172 regmap_reg_range(0x6b04, 0x6b04),
1173 };
1174
1175 static const struct regmap_access_table ksz9896_register_set = {
1176 .yes_ranges = ksz9896_valid_regs,
1177 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1178 };
1179
1180 static const struct regmap_range ksz8873_valid_regs[] = {
1181 regmap_reg_range(0x00, 0x01),
1182 /* global control register */
1183 regmap_reg_range(0x02, 0x0f),
1184
1185 /* port registers */
1186 regmap_reg_range(0x10, 0x1d),
1187 regmap_reg_range(0x1e, 0x1f),
1188 regmap_reg_range(0x20, 0x2d),
1189 regmap_reg_range(0x2e, 0x2f),
1190 regmap_reg_range(0x30, 0x39),
1191 regmap_reg_range(0x3f, 0x3f),
1192
1193 /* advanced control registers */
1194 regmap_reg_range(0x60, 0x6f),
1195 regmap_reg_range(0x70, 0x75),
1196 regmap_reg_range(0x76, 0x78),
1197 regmap_reg_range(0x79, 0x7a),
1198 regmap_reg_range(0x7b, 0x83),
1199 regmap_reg_range(0x8e, 0x99),
1200 regmap_reg_range(0x9a, 0xa5),
1201 regmap_reg_range(0xa6, 0xa6),
1202 regmap_reg_range(0xa7, 0xaa),
1203 regmap_reg_range(0xab, 0xae),
1204 regmap_reg_range(0xaf, 0xba),
1205 regmap_reg_range(0xbb, 0xbc),
1206 regmap_reg_range(0xbd, 0xbd),
1207 regmap_reg_range(0xc0, 0xc0),
1208 regmap_reg_range(0xc2, 0xc2),
1209 regmap_reg_range(0xc3, 0xc3),
1210 regmap_reg_range(0xc4, 0xc4),
1211 regmap_reg_range(0xc6, 0xc6),
1212 };
1213
1214 static const struct regmap_access_table ksz8873_register_set = {
1215 .yes_ranges = ksz8873_valid_regs,
1216 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs),
1217 };
1218
1219 const struct ksz_chip_data ksz_switch_chips[] = {
1220 [KSZ8563] = {
1221 .chip_id = KSZ8563_CHIP_ID,
1222 .dev_name = "KSZ8563",
1223 .num_vlans = 4096,
1224 .num_alus = 4096,
1225 .num_statics = 16,
1226 .cpu_ports = 0x07, /* can be configured as cpu port */
1227 .port_cnt = 3, /* total port count */
1228 .port_nirqs = 3,
1229 .num_tx_queues = 4,
1230 .num_ipms = 8,
1231 .tc_cbs_supported = true,
1232 .ops = &ksz9477_dev_ops,
1233 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1234 .mib_names = ksz9477_mib_names,
1235 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1236 .reg_mib_cnt = MIB_COUNTER_NUM,
1237 .regs = ksz9477_regs,
1238 .masks = ksz9477_masks,
1239 .shifts = ksz9477_shifts,
1240 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1241 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1242 .supports_mii = {false, false, true},
1243 .supports_rmii = {false, false, true},
1244 .supports_rgmii = {false, false, true},
1245 .internal_phy = {true, true, false},
1246 .gbit_capable = {false, false, true},
1247 .wr_table = &ksz8563_register_set,
1248 .rd_table = &ksz8563_register_set,
1249 },
1250
1251 [KSZ8795] = {
1252 .chip_id = KSZ8795_CHIP_ID,
1253 .dev_name = "KSZ8795",
1254 .num_vlans = 4096,
1255 .num_alus = 0,
1256 .num_statics = 8,
1257 .cpu_ports = 0x10, /* can be configured as cpu port */
1258 .port_cnt = 5, /* total cpu and user ports */
1259 .num_tx_queues = 4,
1260 .num_ipms = 4,
1261 .ops = &ksz8_dev_ops,
1262 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1263 .ksz87xx_eee_link_erratum = true,
1264 .mib_names = ksz9477_mib_names,
1265 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1266 .reg_mib_cnt = MIB_COUNTER_NUM,
1267 .regs = ksz8795_regs,
1268 .masks = ksz8795_masks,
1269 .shifts = ksz8795_shifts,
1270 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1271 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1272 .supports_mii = {false, false, false, false, true},
1273 .supports_rmii = {false, false, false, false, true},
1274 .supports_rgmii = {false, false, false, false, true},
1275 .internal_phy = {true, true, true, true, false},
1276 },
1277
1278 [KSZ8794] = {
1279 /* WARNING
1280 * =======
1281 * KSZ8794 is similar to KSZ8795, except the port map
1282 * contains a gap between external and CPU ports, the
1283 * port map is NOT continuous. The per-port register
1284 * map is shifted accordingly too, i.e. registers at
1285 * offset 0x40 are NOT used on KSZ8794 and they ARE
1286 * used on KSZ8795 for external port 3.
1287 * external cpu
1288 * KSZ8794 0,1,2 4
1289 * KSZ8795 0,1,2,3 4
1290 * KSZ8765 0,1,2,3 4
1291 * port_cnt is configured as 5, even though it is 4
1292 */
1293 .chip_id = KSZ8794_CHIP_ID,
1294 .dev_name = "KSZ8794",
1295 .num_vlans = 4096,
1296 .num_alus = 0,
1297 .num_statics = 8,
1298 .cpu_ports = 0x10, /* can be configured as cpu port */
1299 .port_cnt = 5, /* total cpu and user ports */
1300 .num_tx_queues = 4,
1301 .num_ipms = 4,
1302 .ops = &ksz8_dev_ops,
1303 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1304 .ksz87xx_eee_link_erratum = true,
1305 .mib_names = ksz9477_mib_names,
1306 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1307 .reg_mib_cnt = MIB_COUNTER_NUM,
1308 .regs = ksz8795_regs,
1309 .masks = ksz8795_masks,
1310 .shifts = ksz8795_shifts,
1311 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1312 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1313 .supports_mii = {false, false, false, false, true},
1314 .supports_rmii = {false, false, false, false, true},
1315 .supports_rgmii = {false, false, false, false, true},
1316 .internal_phy = {true, true, true, false, false},
1317 },
1318
1319 [KSZ8765] = {
1320 .chip_id = KSZ8765_CHIP_ID,
1321 .dev_name = "KSZ8765",
1322 .num_vlans = 4096,
1323 .num_alus = 0,
1324 .num_statics = 8,
1325 .cpu_ports = 0x10, /* can be configured as cpu port */
1326 .port_cnt = 5, /* total cpu and user ports */
1327 .num_tx_queues = 4,
1328 .num_ipms = 4,
1329 .ops = &ksz8_dev_ops,
1330 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1331 .ksz87xx_eee_link_erratum = true,
1332 .mib_names = ksz9477_mib_names,
1333 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1334 .reg_mib_cnt = MIB_COUNTER_NUM,
1335 .regs = ksz8795_regs,
1336 .masks = ksz8795_masks,
1337 .shifts = ksz8795_shifts,
1338 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1339 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1340 .supports_mii = {false, false, false, false, true},
1341 .supports_rmii = {false, false, false, false, true},
1342 .supports_rgmii = {false, false, false, false, true},
1343 .internal_phy = {true, true, true, true, false},
1344 },
1345
1346 [KSZ8830] = {
1347 .chip_id = KSZ8830_CHIP_ID,
1348 .dev_name = "KSZ8863/KSZ8873",
1349 .num_vlans = 16,
1350 .num_alus = 0,
1351 .num_statics = 8,
1352 .cpu_ports = 0x4, /* can be configured as cpu port */
1353 .port_cnt = 3,
1354 .num_tx_queues = 4,
1355 .num_ipms = 4,
1356 .ops = &ksz8_dev_ops,
1357 .phylink_mac_ops = &ksz8830_phylink_mac_ops,
1358 .mib_names = ksz88xx_mib_names,
1359 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1360 .reg_mib_cnt = MIB_COUNTER_NUM,
1361 .regs = ksz8863_regs,
1362 .masks = ksz8863_masks,
1363 .shifts = ksz8863_shifts,
1364 .supports_mii = {false, false, true},
1365 .supports_rmii = {false, false, true},
1366 .internal_phy = {true, true, false},
1367 .wr_table = &ksz8873_register_set,
1368 .rd_table = &ksz8873_register_set,
1369 },
1370
1371 [KSZ9477] = {
1372 .chip_id = KSZ9477_CHIP_ID,
1373 .dev_name = "KSZ9477",
1374 .num_vlans = 4096,
1375 .num_alus = 4096,
1376 .num_statics = 16,
1377 .cpu_ports = 0x7F, /* can be configured as cpu port */
1378 .port_cnt = 7, /* total physical port count */
1379 .port_nirqs = 4,
1380 .num_tx_queues = 4,
1381 .num_ipms = 8,
1382 .tc_cbs_supported = true,
1383 .ops = &ksz9477_dev_ops,
1384 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1385 .mib_names = ksz9477_mib_names,
1386 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1387 .reg_mib_cnt = MIB_COUNTER_NUM,
1388 .regs = ksz9477_regs,
1389 .masks = ksz9477_masks,
1390 .shifts = ksz9477_shifts,
1391 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1392 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1393 .supports_mii = {false, false, false, false,
1394 false, true, false},
1395 .supports_rmii = {false, false, false, false,
1396 false, true, false},
1397 .supports_rgmii = {false, false, false, false,
1398 false, true, false},
1399 .internal_phy = {true, true, true, true,
1400 true, false, false},
1401 .gbit_capable = {true, true, true, true, true, true, true},
1402 .wr_table = &ksz9477_register_set,
1403 .rd_table = &ksz9477_register_set,
1404 },
1405
1406 [KSZ9896] = {
1407 .chip_id = KSZ9896_CHIP_ID,
1408 .dev_name = "KSZ9896",
1409 .num_vlans = 4096,
1410 .num_alus = 4096,
1411 .num_statics = 16,
1412 .cpu_ports = 0x3F, /* can be configured as cpu port */
1413 .port_cnt = 6, /* total physical port count */
1414 .port_nirqs = 2,
1415 .num_tx_queues = 4,
1416 .num_ipms = 8,
1417 .ops = &ksz9477_dev_ops,
1418 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1419 .mib_names = ksz9477_mib_names,
1420 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1421 .reg_mib_cnt = MIB_COUNTER_NUM,
1422 .regs = ksz9477_regs,
1423 .masks = ksz9477_masks,
1424 .shifts = ksz9477_shifts,
1425 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1426 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1427 .supports_mii = {false, false, false, false,
1428 false, true},
1429 .supports_rmii = {false, false, false, false,
1430 false, true},
1431 .supports_rgmii = {false, false, false, false,
1432 false, true},
1433 .internal_phy = {true, true, true, true,
1434 true, false},
1435 .gbit_capable = {true, true, true, true, true, true},
1436 .wr_table = &ksz9896_register_set,
1437 .rd_table = &ksz9896_register_set,
1438 },
1439
1440 [KSZ9897] = {
1441 .chip_id = KSZ9897_CHIP_ID,
1442 .dev_name = "KSZ9897",
1443 .num_vlans = 4096,
1444 .num_alus = 4096,
1445 .num_statics = 16,
1446 .cpu_ports = 0x7F, /* can be configured as cpu port */
1447 .port_cnt = 7, /* total physical port count */
1448 .port_nirqs = 2,
1449 .num_tx_queues = 4,
1450 .num_ipms = 8,
1451 .ops = &ksz9477_dev_ops,
1452 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1453 .mib_names = ksz9477_mib_names,
1454 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1455 .reg_mib_cnt = MIB_COUNTER_NUM,
1456 .regs = ksz9477_regs,
1457 .masks = ksz9477_masks,
1458 .shifts = ksz9477_shifts,
1459 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1460 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1461 .supports_mii = {false, false, false, false,
1462 false, true, true},
1463 .supports_rmii = {false, false, false, false,
1464 false, true, true},
1465 .supports_rgmii = {false, false, false, false,
1466 false, true, true},
1467 .internal_phy = {true, true, true, true,
1468 true, false, false},
1469 .gbit_capable = {true, true, true, true, true, true, true},
1470 },
1471
1472 [KSZ9893] = {
1473 .chip_id = KSZ9893_CHIP_ID,
1474 .dev_name = "KSZ9893",
1475 .num_vlans = 4096,
1476 .num_alus = 4096,
1477 .num_statics = 16,
1478 .cpu_ports = 0x07, /* can be configured as cpu port */
1479 .port_cnt = 3, /* total port count */
1480 .port_nirqs = 2,
1481 .num_tx_queues = 4,
1482 .num_ipms = 8,
1483 .ops = &ksz9477_dev_ops,
1484 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1485 .mib_names = ksz9477_mib_names,
1486 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1487 .reg_mib_cnt = MIB_COUNTER_NUM,
1488 .regs = ksz9477_regs,
1489 .masks = ksz9477_masks,
1490 .shifts = ksz9477_shifts,
1491 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1492 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1493 .supports_mii = {false, false, true},
1494 .supports_rmii = {false, false, true},
1495 .supports_rgmii = {false, false, true},
1496 .internal_phy = {true, true, false},
1497 .gbit_capable = {true, true, true},
1498 },
1499
1500 [KSZ9563] = {
1501 .chip_id = KSZ9563_CHIP_ID,
1502 .dev_name = "KSZ9563",
1503 .num_vlans = 4096,
1504 .num_alus = 4096,
1505 .num_statics = 16,
1506 .cpu_ports = 0x07, /* can be configured as cpu port */
1507 .port_cnt = 3, /* total port count */
1508 .port_nirqs = 3,
1509 .num_tx_queues = 4,
1510 .num_ipms = 8,
1511 .tc_cbs_supported = true,
1512 .ops = &ksz9477_dev_ops,
1513 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1514 .mib_names = ksz9477_mib_names,
1515 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1516 .reg_mib_cnt = MIB_COUNTER_NUM,
1517 .regs = ksz9477_regs,
1518 .masks = ksz9477_masks,
1519 .shifts = ksz9477_shifts,
1520 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1521 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1522 .supports_mii = {false, false, true},
1523 .supports_rmii = {false, false, true},
1524 .supports_rgmii = {false, false, true},
1525 .internal_phy = {true, true, false},
1526 .gbit_capable = {true, true, true},
1527 },
1528
1529 [KSZ8567] = {
1530 .chip_id = KSZ8567_CHIP_ID,
1531 .dev_name = "KSZ8567",
1532 .num_vlans = 4096,
1533 .num_alus = 4096,
1534 .num_statics = 16,
1535 .cpu_ports = 0x7F, /* can be configured as cpu port */
1536 .port_cnt = 7, /* total port count */
1537 .port_nirqs = 3,
1538 .num_tx_queues = 4,
1539 .num_ipms = 8,
1540 .tc_cbs_supported = true,
1541 .ops = &ksz9477_dev_ops,
1542 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1543 .mib_names = ksz9477_mib_names,
1544 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1545 .reg_mib_cnt = MIB_COUNTER_NUM,
1546 .regs = ksz9477_regs,
1547 .masks = ksz9477_masks,
1548 .shifts = ksz9477_shifts,
1549 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1550 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1551 .supports_mii = {false, false, false, false,
1552 false, true, true},
1553 .supports_rmii = {false, false, false, false,
1554 false, true, true},
1555 .supports_rgmii = {false, false, false, false,
1556 false, true, true},
1557 .internal_phy = {true, true, true, true,
1558 true, false, false},
1559 .gbit_capable = {false, false, false, false, false,
1560 true, true},
1561 },
1562
1563 [KSZ9567] = {
1564 .chip_id = KSZ9567_CHIP_ID,
1565 .dev_name = "KSZ9567",
1566 .num_vlans = 4096,
1567 .num_alus = 4096,
1568 .num_statics = 16,
1569 .cpu_ports = 0x7F, /* can be configured as cpu port */
1570 .port_cnt = 7, /* total physical port count */
1571 .port_nirqs = 3,
1572 .num_tx_queues = 4,
1573 .num_ipms = 8,
1574 .tc_cbs_supported = true,
1575 .ops = &ksz9477_dev_ops,
1576 .mib_names = ksz9477_mib_names,
1577 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1578 .reg_mib_cnt = MIB_COUNTER_NUM,
1579 .regs = ksz9477_regs,
1580 .masks = ksz9477_masks,
1581 .shifts = ksz9477_shifts,
1582 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1583 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1584 .supports_mii = {false, false, false, false,
1585 false, true, true},
1586 .supports_rmii = {false, false, false, false,
1587 false, true, true},
1588 .supports_rgmii = {false, false, false, false,
1589 false, true, true},
1590 .internal_phy = {true, true, true, true,
1591 true, false, false},
1592 .gbit_capable = {true, true, true, true, true, true, true},
1593 },
1594
1595 [LAN9370] = {
1596 .chip_id = LAN9370_CHIP_ID,
1597 .dev_name = "LAN9370",
1598 .num_vlans = 4096,
1599 .num_alus = 1024,
1600 .num_statics = 256,
1601 .cpu_ports = 0x10, /* can be configured as cpu port */
1602 .port_cnt = 5, /* total physical port count */
1603 .port_nirqs = 6,
1604 .num_tx_queues = 8,
1605 .num_ipms = 8,
1606 .tc_cbs_supported = true,
1607 .ops = &lan937x_dev_ops,
1608 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1609 .mib_names = ksz9477_mib_names,
1610 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1611 .reg_mib_cnt = MIB_COUNTER_NUM,
1612 .regs = ksz9477_regs,
1613 .masks = lan937x_masks,
1614 .shifts = lan937x_shifts,
1615 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1616 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1617 .supports_mii = {false, false, false, false, true},
1618 .supports_rmii = {false, false, false, false, true},
1619 .supports_rgmii = {false, false, false, false, true},
1620 .internal_phy = {true, true, true, true, false},
1621 },
1622
1623 [LAN9371] = {
1624 .chip_id = LAN9371_CHIP_ID,
1625 .dev_name = "LAN9371",
1626 .num_vlans = 4096,
1627 .num_alus = 1024,
1628 .num_statics = 256,
1629 .cpu_ports = 0x30, /* can be configured as cpu port */
1630 .port_cnt = 6, /* total physical port count */
1631 .port_nirqs = 6,
1632 .num_tx_queues = 8,
1633 .num_ipms = 8,
1634 .tc_cbs_supported = true,
1635 .ops = &lan937x_dev_ops,
1636 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1637 .mib_names = ksz9477_mib_names,
1638 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1639 .reg_mib_cnt = MIB_COUNTER_NUM,
1640 .regs = ksz9477_regs,
1641 .masks = lan937x_masks,
1642 .shifts = lan937x_shifts,
1643 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1644 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1645 .supports_mii = {false, false, false, false, true, true},
1646 .supports_rmii = {false, false, false, false, true, true},
1647 .supports_rgmii = {false, false, false, false, true, true},
1648 .internal_phy = {true, true, true, true, false, false},
1649 },
1650
1651 [LAN9372] = {
1652 .chip_id = LAN9372_CHIP_ID,
1653 .dev_name = "LAN9372",
1654 .num_vlans = 4096,
1655 .num_alus = 1024,
1656 .num_statics = 256,
1657 .cpu_ports = 0x30, /* can be configured as cpu port */
1658 .port_cnt = 8, /* total physical port count */
1659 .port_nirqs = 6,
1660 .num_tx_queues = 8,
1661 .num_ipms = 8,
1662 .tc_cbs_supported = true,
1663 .ops = &lan937x_dev_ops,
1664 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1665 .mib_names = ksz9477_mib_names,
1666 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1667 .reg_mib_cnt = MIB_COUNTER_NUM,
1668 .regs = ksz9477_regs,
1669 .masks = lan937x_masks,
1670 .shifts = lan937x_shifts,
1671 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1672 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1673 .supports_mii = {false, false, false, false,
1674 true, true, false, false},
1675 .supports_rmii = {false, false, false, false,
1676 true, true, false, false},
1677 .supports_rgmii = {false, false, false, false,
1678 true, true, false, false},
1679 .internal_phy = {true, true, true, true,
1680 false, false, true, true},
1681 },
1682
1683 [LAN9373] = {
1684 .chip_id = LAN9373_CHIP_ID,
1685 .dev_name = "LAN9373",
1686 .num_vlans = 4096,
1687 .num_alus = 1024,
1688 .num_statics = 256,
1689 .cpu_ports = 0x38, /* can be configured as cpu port */
1690 .port_cnt = 5, /* total physical port count */
1691 .port_nirqs = 6,
1692 .num_tx_queues = 8,
1693 .num_ipms = 8,
1694 .tc_cbs_supported = true,
1695 .ops = &lan937x_dev_ops,
1696 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1697 .mib_names = ksz9477_mib_names,
1698 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1699 .reg_mib_cnt = MIB_COUNTER_NUM,
1700 .regs = ksz9477_regs,
1701 .masks = lan937x_masks,
1702 .shifts = lan937x_shifts,
1703 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1704 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1705 .supports_mii = {false, false, false, false,
1706 true, true, false, false},
1707 .supports_rmii = {false, false, false, false,
1708 true, true, false, false},
1709 .supports_rgmii = {false, false, false, false,
1710 true, true, false, false},
1711 .internal_phy = {true, true, true, false,
1712 false, false, true, true},
1713 },
1714
1715 [LAN9374] = {
1716 .chip_id = LAN9374_CHIP_ID,
1717 .dev_name = "LAN9374",
1718 .num_vlans = 4096,
1719 .num_alus = 1024,
1720 .num_statics = 256,
1721 .cpu_ports = 0x30, /* can be configured as cpu port */
1722 .port_cnt = 8, /* total physical port count */
1723 .port_nirqs = 6,
1724 .num_tx_queues = 8,
1725 .num_ipms = 8,
1726 .tc_cbs_supported = true,
1727 .ops = &lan937x_dev_ops,
1728 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1729 .mib_names = ksz9477_mib_names,
1730 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1731 .reg_mib_cnt = MIB_COUNTER_NUM,
1732 .regs = ksz9477_regs,
1733 .masks = lan937x_masks,
1734 .shifts = lan937x_shifts,
1735 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1736 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1737 .supports_mii = {false, false, false, false,
1738 true, true, false, false},
1739 .supports_rmii = {false, false, false, false,
1740 true, true, false, false},
1741 .supports_rgmii = {false, false, false, false,
1742 true, true, false, false},
1743 .internal_phy = {true, true, true, true,
1744 false, false, true, true},
1745 },
1746 };
1747 EXPORT_SYMBOL_GPL(ksz_switch_chips);
1748
ksz_lookup_info(unsigned int prod_num)1749 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
1750 {
1751 int i;
1752
1753 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1754 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1755
1756 if (chip->chip_id == prod_num)
1757 return chip;
1758 }
1759
1760 return NULL;
1761 }
1762
ksz_check_device_id(struct ksz_device * dev)1763 static int ksz_check_device_id(struct ksz_device *dev)
1764 {
1765 const struct ksz_chip_data *expected_chip_data;
1766 u32 expected_chip_id;
1767
1768 if (dev->pdata) {
1769 expected_chip_id = dev->pdata->chip_id;
1770 expected_chip_data = ksz_lookup_info(expected_chip_id);
1771 if (WARN_ON(!expected_chip_data))
1772 return -ENODEV;
1773 } else {
1774 expected_chip_data = of_device_get_match_data(dev->dev);
1775 expected_chip_id = expected_chip_data->chip_id;
1776 }
1777
1778 if (expected_chip_id != dev->chip_id) {
1779 dev_err(dev->dev,
1780 "Device tree specifies chip %s but found %s, please fix it!\n",
1781 expected_chip_data->dev_name, dev->info->dev_name);
1782 return -ENODEV;
1783 }
1784
1785 return 0;
1786 }
1787
ksz_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1788 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
1789 struct phylink_config *config)
1790 {
1791 struct ksz_device *dev = ds->priv;
1792
1793 if (dev->info->supports_mii[port])
1794 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1795
1796 if (dev->info->supports_rmii[port])
1797 __set_bit(PHY_INTERFACE_MODE_RMII,
1798 config->supported_interfaces);
1799
1800 if (dev->info->supports_rgmii[port])
1801 phy_interface_set_rgmii(config->supported_interfaces);
1802
1803 if (dev->info->internal_phy[port]) {
1804 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1805 config->supported_interfaces);
1806 /* Compatibility for phylib's default interface type when the
1807 * phy-mode property is absent
1808 */
1809 __set_bit(PHY_INTERFACE_MODE_GMII,
1810 config->supported_interfaces);
1811 }
1812
1813 if (dev->dev_ops->get_caps)
1814 dev->dev_ops->get_caps(dev, port, config);
1815 }
1816
ksz_r_mib_stats64(struct ksz_device * dev,int port)1817 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
1818 {
1819 struct ethtool_pause_stats *pstats;
1820 struct rtnl_link_stats64 *stats;
1821 struct ksz_stats_raw *raw;
1822 struct ksz_port_mib *mib;
1823
1824 mib = &dev->ports[port].mib;
1825 stats = &mib->stats64;
1826 pstats = &mib->pause_stats;
1827 raw = (struct ksz_stats_raw *)mib->counters;
1828
1829 spin_lock(&mib->stats64_lock);
1830
1831 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1832 raw->rx_pause;
1833 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1834 raw->tx_pause;
1835
1836 /* HW counters are counting bytes + FCS which is not acceptable
1837 * for rtnl_link_stats64 interface
1838 */
1839 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
1840 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
1841
1842 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1843 raw->rx_oversize;
1844
1845 stats->rx_crc_errors = raw->rx_crc_err;
1846 stats->rx_frame_errors = raw->rx_align_err;
1847 stats->rx_dropped = raw->rx_discards;
1848 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1849 stats->rx_frame_errors + stats->rx_dropped;
1850
1851 stats->tx_window_errors = raw->tx_late_col;
1852 stats->tx_fifo_errors = raw->tx_discards;
1853 stats->tx_aborted_errors = raw->tx_exc_col;
1854 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1855 stats->tx_aborted_errors;
1856
1857 stats->multicast = raw->rx_mcast;
1858 stats->collisions = raw->tx_total_col;
1859
1860 pstats->tx_pause_frames = raw->tx_pause;
1861 pstats->rx_pause_frames = raw->rx_pause;
1862
1863 spin_unlock(&mib->stats64_lock);
1864 }
1865
ksz88xx_r_mib_stats64(struct ksz_device * dev,int port)1866 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
1867 {
1868 struct ethtool_pause_stats *pstats;
1869 struct rtnl_link_stats64 *stats;
1870 struct ksz88xx_stats_raw *raw;
1871 struct ksz_port_mib *mib;
1872
1873 mib = &dev->ports[port].mib;
1874 stats = &mib->stats64;
1875 pstats = &mib->pause_stats;
1876 raw = (struct ksz88xx_stats_raw *)mib->counters;
1877
1878 spin_lock(&mib->stats64_lock);
1879
1880 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1881 raw->rx_pause;
1882 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1883 raw->tx_pause;
1884
1885 /* HW counters are counting bytes + FCS which is not acceptable
1886 * for rtnl_link_stats64 interface
1887 */
1888 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
1889 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
1890
1891 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1892 raw->rx_oversize;
1893
1894 stats->rx_crc_errors = raw->rx_crc_err;
1895 stats->rx_frame_errors = raw->rx_align_err;
1896 stats->rx_dropped = raw->rx_discards;
1897 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1898 stats->rx_frame_errors + stats->rx_dropped;
1899
1900 stats->tx_window_errors = raw->tx_late_col;
1901 stats->tx_fifo_errors = raw->tx_discards;
1902 stats->tx_aborted_errors = raw->tx_exc_col;
1903 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1904 stats->tx_aborted_errors;
1905
1906 stats->multicast = raw->rx_mcast;
1907 stats->collisions = raw->tx_total_col;
1908
1909 pstats->tx_pause_frames = raw->tx_pause;
1910 pstats->rx_pause_frames = raw->rx_pause;
1911
1912 spin_unlock(&mib->stats64_lock);
1913 }
1914
ksz_get_stats64(struct dsa_switch * ds,int port,struct rtnl_link_stats64 * s)1915 static void ksz_get_stats64(struct dsa_switch *ds, int port,
1916 struct rtnl_link_stats64 *s)
1917 {
1918 struct ksz_device *dev = ds->priv;
1919 struct ksz_port_mib *mib;
1920
1921 mib = &dev->ports[port].mib;
1922
1923 spin_lock(&mib->stats64_lock);
1924 memcpy(s, &mib->stats64, sizeof(*s));
1925 spin_unlock(&mib->stats64_lock);
1926 }
1927
ksz_get_pause_stats(struct dsa_switch * ds,int port,struct ethtool_pause_stats * pause_stats)1928 static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
1929 struct ethtool_pause_stats *pause_stats)
1930 {
1931 struct ksz_device *dev = ds->priv;
1932 struct ksz_port_mib *mib;
1933
1934 mib = &dev->ports[port].mib;
1935
1936 spin_lock(&mib->stats64_lock);
1937 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
1938 spin_unlock(&mib->stats64_lock);
1939 }
1940
ksz_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * buf)1941 static void ksz_get_strings(struct dsa_switch *ds, int port,
1942 u32 stringset, uint8_t *buf)
1943 {
1944 struct ksz_device *dev = ds->priv;
1945 int i;
1946
1947 if (stringset != ETH_SS_STATS)
1948 return;
1949
1950 for (i = 0; i < dev->info->mib_cnt; i++) {
1951 memcpy(buf + i * ETH_GSTRING_LEN,
1952 dev->info->mib_names[i].string, ETH_GSTRING_LEN);
1953 }
1954 }
1955
1956 /**
1957 * ksz_update_port_member - Adjust port forwarding rules based on STP state and
1958 * isolation settings.
1959 * @dev: A pointer to the struct ksz_device representing the device.
1960 * @port: The port number to adjust.
1961 *
1962 * This function dynamically adjusts the port membership configuration for a
1963 * specified port and other device ports, based on Spanning Tree Protocol (STP)
1964 * states and port isolation settings. Each port, including the CPU port, has a
1965 * membership register, represented as a bitfield, where each bit corresponds
1966 * to a port number. A set bit indicates permission to forward frames to that
1967 * port. This function iterates over all ports, updating the membership register
1968 * to reflect current forwarding permissions:
1969 *
1970 * 1. Forwards frames only to ports that are part of the same bridge group and
1971 * in the BR_STATE_FORWARDING state.
1972 * 2. Takes into account the isolation status of ports; ports in the
1973 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward
1974 * frames to each other, even if they are in the same bridge group.
1975 * 3. Ensures that the CPU port is included in the membership based on its
1976 * upstream port configuration, allowing for management and control traffic
1977 * to flow as required.
1978 */
ksz_update_port_member(struct ksz_device * dev,int port)1979 static void ksz_update_port_member(struct ksz_device *dev, int port)
1980 {
1981 struct ksz_port *p = &dev->ports[port];
1982 struct dsa_switch *ds = dev->ds;
1983 u8 port_member = 0, cpu_port;
1984 const struct dsa_port *dp;
1985 int i, j;
1986
1987 if (!dsa_is_user_port(ds, port))
1988 return;
1989
1990 dp = dsa_to_port(ds, port);
1991 cpu_port = BIT(dsa_upstream_port(ds, port));
1992
1993 for (i = 0; i < ds->num_ports; i++) {
1994 const struct dsa_port *other_dp = dsa_to_port(ds, i);
1995 struct ksz_port *other_p = &dev->ports[i];
1996 u8 val = 0;
1997
1998 if (!dsa_is_user_port(ds, i))
1999 continue;
2000 if (port == i)
2001 continue;
2002 if (!dsa_port_bridge_same(dp, other_dp))
2003 continue;
2004 if (other_p->stp_state != BR_STATE_FORWARDING)
2005 continue;
2006
2007 /* At this point we know that "port" and "other" port [i] are in
2008 * the same bridge group and that "other" port [i] is in
2009 * forwarding stp state. If "port" is also in forwarding stp
2010 * state, we can allow forwarding from port [port] to port [i].
2011 * Except if both ports are isolated.
2012 */
2013 if (p->stp_state == BR_STATE_FORWARDING &&
2014 !(p->isolated && other_p->isolated)) {
2015 val |= BIT(port);
2016 port_member |= BIT(i);
2017 }
2018
2019 /* Retain port [i]'s relationship to other ports than [port] */
2020 for (j = 0; j < ds->num_ports; j++) {
2021 const struct dsa_port *third_dp;
2022 struct ksz_port *third_p;
2023
2024 if (j == i)
2025 continue;
2026 if (j == port)
2027 continue;
2028 if (!dsa_is_user_port(ds, j))
2029 continue;
2030 third_p = &dev->ports[j];
2031 if (third_p->stp_state != BR_STATE_FORWARDING)
2032 continue;
2033
2034 third_dp = dsa_to_port(ds, j);
2035
2036 /* Now we updating relation of the "other" port [i] to
2037 * the "third" port [j]. We already know that "other"
2038 * port [i] is in forwarding stp state and that "third"
2039 * port [j] is in forwarding stp state too.
2040 * We need to check if "other" port [i] and "third" port
2041 * [j] are in the same bridge group and not isolated
2042 * before allowing forwarding from port [i] to port [j].
2043 */
2044 if (dsa_port_bridge_same(other_dp, third_dp) &&
2045 !(other_p->isolated && third_p->isolated))
2046 val |= BIT(j);
2047 }
2048
2049 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
2050 }
2051
2052 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
2053 }
2054
ksz_sw_mdio_read(struct mii_bus * bus,int addr,int regnum)2055 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
2056 {
2057 struct ksz_device *dev = bus->priv;
2058 u16 val;
2059 int ret;
2060
2061 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
2062 if (ret < 0)
2063 return ret;
2064
2065 return val;
2066 }
2067
ksz_sw_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)2068 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
2069 u16 val)
2070 {
2071 struct ksz_device *dev = bus->priv;
2072
2073 return dev->dev_ops->w_phy(dev, addr, regnum, val);
2074 }
2075
ksz_irq_phy_setup(struct ksz_device * dev)2076 static int ksz_irq_phy_setup(struct ksz_device *dev)
2077 {
2078 struct dsa_switch *ds = dev->ds;
2079 int phy;
2080 int irq;
2081 int ret;
2082
2083 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) {
2084 if (BIT(phy) & ds->phys_mii_mask) {
2085 irq = irq_find_mapping(dev->ports[phy].pirq.domain,
2086 PORT_SRC_PHY_INT);
2087 if (irq < 0) {
2088 ret = irq;
2089 goto out;
2090 }
2091 ds->user_mii_bus->irq[phy] = irq;
2092 }
2093 }
2094 return 0;
2095 out:
2096 while (phy--)
2097 if (BIT(phy) & ds->phys_mii_mask)
2098 irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
2099
2100 return ret;
2101 }
2102
ksz_irq_phy_free(struct ksz_device * dev)2103 static void ksz_irq_phy_free(struct ksz_device *dev)
2104 {
2105 struct dsa_switch *ds = dev->ds;
2106 int phy;
2107
2108 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++)
2109 if (BIT(phy) & ds->phys_mii_mask)
2110 irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
2111 }
2112
ksz_mdio_register(struct ksz_device * dev)2113 static int ksz_mdio_register(struct ksz_device *dev)
2114 {
2115 struct dsa_switch *ds = dev->ds;
2116 struct device_node *mdio_np;
2117 struct mii_bus *bus;
2118 int ret;
2119
2120 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
2121 if (!mdio_np)
2122 return 0;
2123
2124 bus = devm_mdiobus_alloc(ds->dev);
2125 if (!bus) {
2126 of_node_put(mdio_np);
2127 return -ENOMEM;
2128 }
2129
2130 bus->priv = dev;
2131 bus->read = ksz_sw_mdio_read;
2132 bus->write = ksz_sw_mdio_write;
2133 bus->name = "ksz user smi";
2134 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
2135 bus->parent = ds->dev;
2136 bus->phy_mask = ~ds->phys_mii_mask;
2137
2138 ds->user_mii_bus = bus;
2139
2140 if (dev->irq > 0) {
2141 ret = ksz_irq_phy_setup(dev);
2142 if (ret) {
2143 of_node_put(mdio_np);
2144 return ret;
2145 }
2146 }
2147
2148 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
2149 if (ret) {
2150 dev_err(ds->dev, "unable to register MDIO bus %s\n",
2151 bus->id);
2152 if (dev->irq > 0)
2153 ksz_irq_phy_free(dev);
2154 }
2155
2156 of_node_put(mdio_np);
2157
2158 return ret;
2159 }
2160
ksz_irq_mask(struct irq_data * d)2161 static void ksz_irq_mask(struct irq_data *d)
2162 {
2163 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2164
2165 kirq->masked |= BIT(d->hwirq);
2166 }
2167
ksz_irq_unmask(struct irq_data * d)2168 static void ksz_irq_unmask(struct irq_data *d)
2169 {
2170 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2171
2172 kirq->masked &= ~BIT(d->hwirq);
2173 }
2174
ksz_irq_bus_lock(struct irq_data * d)2175 static void ksz_irq_bus_lock(struct irq_data *d)
2176 {
2177 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2178
2179 mutex_lock(&kirq->dev->lock_irq);
2180 }
2181
ksz_irq_bus_sync_unlock(struct irq_data * d)2182 static void ksz_irq_bus_sync_unlock(struct irq_data *d)
2183 {
2184 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2185 struct ksz_device *dev = kirq->dev;
2186 int ret;
2187
2188 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked);
2189 if (ret)
2190 dev_err(dev->dev, "failed to change IRQ mask\n");
2191
2192 mutex_unlock(&dev->lock_irq);
2193 }
2194
2195 static const struct irq_chip ksz_irq_chip = {
2196 .name = "ksz-irq",
2197 .irq_mask = ksz_irq_mask,
2198 .irq_unmask = ksz_irq_unmask,
2199 .irq_bus_lock = ksz_irq_bus_lock,
2200 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
2201 };
2202
ksz_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)2203 static int ksz_irq_domain_map(struct irq_domain *d,
2204 unsigned int irq, irq_hw_number_t hwirq)
2205 {
2206 irq_set_chip_data(irq, d->host_data);
2207 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq);
2208 irq_set_noprobe(irq);
2209
2210 return 0;
2211 }
2212
2213 static const struct irq_domain_ops ksz_irq_domain_ops = {
2214 .map = ksz_irq_domain_map,
2215 .xlate = irq_domain_xlate_twocell,
2216 };
2217
ksz_irq_free(struct ksz_irq * kirq)2218 static void ksz_irq_free(struct ksz_irq *kirq)
2219 {
2220 int irq, virq;
2221
2222 free_irq(kirq->irq_num, kirq);
2223
2224 for (irq = 0; irq < kirq->nirqs; irq++) {
2225 virq = irq_find_mapping(kirq->domain, irq);
2226 irq_dispose_mapping(virq);
2227 }
2228
2229 irq_domain_remove(kirq->domain);
2230 }
2231
ksz_irq_thread_fn(int irq,void * dev_id)2232 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
2233 {
2234 struct ksz_irq *kirq = dev_id;
2235 unsigned int nhandled = 0;
2236 struct ksz_device *dev;
2237 unsigned int sub_irq;
2238 u8 data;
2239 int ret;
2240 u8 n;
2241
2242 dev = kirq->dev;
2243
2244 /* Read interrupt status register */
2245 ret = ksz_read8(dev, kirq->reg_status, &data);
2246 if (ret)
2247 goto out;
2248
2249 for (n = 0; n < kirq->nirqs; ++n) {
2250 if (data & BIT(n)) {
2251 sub_irq = irq_find_mapping(kirq->domain, n);
2252 handle_nested_irq(sub_irq);
2253 ++nhandled;
2254 }
2255 }
2256 out:
2257 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
2258 }
2259
ksz_irq_common_setup(struct ksz_device * dev,struct ksz_irq * kirq)2260 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
2261 {
2262 int ret, n;
2263
2264 kirq->dev = dev;
2265 kirq->masked = ~0;
2266
2267 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0,
2268 &ksz_irq_domain_ops, kirq);
2269 if (!kirq->domain)
2270 return -ENOMEM;
2271
2272 for (n = 0; n < kirq->nirqs; n++)
2273 irq_create_mapping(kirq->domain, n);
2274
2275 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn,
2276 IRQF_ONESHOT, kirq->name, kirq);
2277 if (ret)
2278 goto out;
2279
2280 return 0;
2281
2282 out:
2283 ksz_irq_free(kirq);
2284
2285 return ret;
2286 }
2287
ksz_girq_setup(struct ksz_device * dev)2288 static int ksz_girq_setup(struct ksz_device *dev)
2289 {
2290 struct ksz_irq *girq = &dev->girq;
2291
2292 girq->nirqs = dev->info->port_cnt;
2293 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2294 girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2295 snprintf(girq->name, sizeof(girq->name), "global_port_irq");
2296
2297 girq->irq_num = dev->irq;
2298
2299 return ksz_irq_common_setup(dev, girq);
2300 }
2301
ksz_pirq_setup(struct ksz_device * dev,u8 p)2302 static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2303 {
2304 struct ksz_irq *pirq = &dev->ports[p].pirq;
2305
2306 pirq->nirqs = dev->info->port_nirqs;
2307 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2308 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2309 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
2310
2311 pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
2312 if (pirq->irq_num < 0)
2313 return pirq->irq_num;
2314
2315 return ksz_irq_common_setup(dev, pirq);
2316 }
2317
2318 static int ksz_parse_drive_strength(struct ksz_device *dev);
2319
ksz_setup(struct dsa_switch * ds)2320 static int ksz_setup(struct dsa_switch *ds)
2321 {
2322 struct ksz_device *dev = ds->priv;
2323 struct dsa_port *dp;
2324 struct ksz_port *p;
2325 const u16 *regs;
2326 int ret;
2327
2328 regs = dev->info->regs;
2329
2330 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
2331 dev->info->num_vlans, GFP_KERNEL);
2332 if (!dev->vlan_cache)
2333 return -ENOMEM;
2334
2335 ret = dev->dev_ops->reset(dev);
2336 if (ret) {
2337 dev_err(ds->dev, "failed to reset switch\n");
2338 return ret;
2339 }
2340
2341 ret = ksz_parse_drive_strength(dev);
2342 if (ret)
2343 return ret;
2344
2345 /* set broadcast storm protection 10% rate */
2346 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL],
2347 BROADCAST_STORM_RATE,
2348 (BROADCAST_STORM_VALUE *
2349 BROADCAST_STORM_PROT_RATE) / 100);
2350
2351 dev->dev_ops->config_cpu_port(ds);
2352
2353 dev->dev_ops->enable_stp_addr(dev);
2354
2355 ds->num_tx_queues = dev->info->num_tx_queues;
2356
2357 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL],
2358 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
2359
2360 ksz_init_mib_timer(dev);
2361
2362 ds->configure_vlan_while_not_filtering = false;
2363 ds->dscp_prio_mapping_is_global = true;
2364
2365 if (dev->dev_ops->setup) {
2366 ret = dev->dev_ops->setup(ds);
2367 if (ret)
2368 return ret;
2369 }
2370
2371 /* Start with learning disabled on standalone user ports, and enabled
2372 * on the CPU port. In lack of other finer mechanisms, learning on the
2373 * CPU port will avoid flooding bridge local addresses on the network
2374 * in some cases.
2375 */
2376 p = &dev->ports[dev->cpu_port];
2377 p->learning = true;
2378
2379 if (dev->irq > 0) {
2380 ret = ksz_girq_setup(dev);
2381 if (ret)
2382 return ret;
2383
2384 dsa_switch_for_each_user_port(dp, dev->ds) {
2385 ret = ksz_pirq_setup(dev, dp->index);
2386 if (ret)
2387 goto out_girq;
2388
2389 ret = ksz_ptp_irq_setup(ds, dp->index);
2390 if (ret)
2391 goto out_pirq;
2392 }
2393 }
2394
2395 ret = ksz_ptp_clock_register(ds);
2396 if (ret) {
2397 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret);
2398 goto out_ptpirq;
2399 }
2400
2401 ret = ksz_mdio_register(dev);
2402 if (ret < 0) {
2403 dev_err(dev->dev, "failed to register the mdio");
2404 goto out_ptp_clock_unregister;
2405 }
2406
2407 ret = ksz_dcb_init(dev);
2408 if (ret)
2409 goto out_ptp_clock_unregister;
2410
2411 /* start switch */
2412 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL],
2413 SW_START, SW_START);
2414
2415 return 0;
2416
2417 out_ptp_clock_unregister:
2418 ksz_ptp_clock_unregister(ds);
2419 out_ptpirq:
2420 if (dev->irq > 0)
2421 dsa_switch_for_each_user_port(dp, dev->ds)
2422 ksz_ptp_irq_free(ds, dp->index);
2423 out_pirq:
2424 if (dev->irq > 0)
2425 dsa_switch_for_each_user_port(dp, dev->ds)
2426 ksz_irq_free(&dev->ports[dp->index].pirq);
2427 out_girq:
2428 if (dev->irq > 0)
2429 ksz_irq_free(&dev->girq);
2430
2431 return ret;
2432 }
2433
ksz_teardown(struct dsa_switch * ds)2434 static void ksz_teardown(struct dsa_switch *ds)
2435 {
2436 struct ksz_device *dev = ds->priv;
2437 struct dsa_port *dp;
2438
2439 ksz_ptp_clock_unregister(ds);
2440
2441 if (dev->irq > 0) {
2442 dsa_switch_for_each_user_port(dp, dev->ds) {
2443 ksz_ptp_irq_free(ds, dp->index);
2444
2445 ksz_irq_free(&dev->ports[dp->index].pirq);
2446 }
2447
2448 ksz_irq_free(&dev->girq);
2449 }
2450
2451 if (dev->dev_ops->teardown)
2452 dev->dev_ops->teardown(ds);
2453 }
2454
port_r_cnt(struct ksz_device * dev,int port)2455 static void port_r_cnt(struct ksz_device *dev, int port)
2456 {
2457 struct ksz_port_mib *mib = &dev->ports[port].mib;
2458 u64 *dropped;
2459
2460 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
2461 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
2462 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
2463 &mib->counters[mib->cnt_ptr]);
2464 ++mib->cnt_ptr;
2465 }
2466
2467 /* last one in storage */
2468 dropped = &mib->counters[dev->info->mib_cnt];
2469
2470 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
2471 while (mib->cnt_ptr < dev->info->mib_cnt) {
2472 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
2473 dropped, &mib->counters[mib->cnt_ptr]);
2474 ++mib->cnt_ptr;
2475 }
2476 mib->cnt_ptr = 0;
2477 }
2478
ksz_mib_read_work(struct work_struct * work)2479 static void ksz_mib_read_work(struct work_struct *work)
2480 {
2481 struct ksz_device *dev = container_of(work, struct ksz_device,
2482 mib_read.work);
2483 struct ksz_port_mib *mib;
2484 struct ksz_port *p;
2485 int i;
2486
2487 for (i = 0; i < dev->info->port_cnt; i++) {
2488 if (dsa_is_unused_port(dev->ds, i))
2489 continue;
2490
2491 p = &dev->ports[i];
2492 mib = &p->mib;
2493 mutex_lock(&mib->cnt_mutex);
2494
2495 /* Only read MIB counters when the port is told to do.
2496 * If not, read only dropped counters when link is not up.
2497 */
2498 if (!p->read) {
2499 const struct dsa_port *dp = dsa_to_port(dev->ds, i);
2500
2501 if (!netif_carrier_ok(dp->user))
2502 mib->cnt_ptr = dev->info->reg_mib_cnt;
2503 }
2504 port_r_cnt(dev, i);
2505 p->read = false;
2506
2507 if (dev->dev_ops->r_mib_stat64)
2508 dev->dev_ops->r_mib_stat64(dev, i);
2509
2510 mutex_unlock(&mib->cnt_mutex);
2511 }
2512
2513 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
2514 }
2515
ksz_init_mib_timer(struct ksz_device * dev)2516 void ksz_init_mib_timer(struct ksz_device *dev)
2517 {
2518 int i;
2519
2520 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
2521
2522 for (i = 0; i < dev->info->port_cnt; i++) {
2523 struct ksz_port_mib *mib = &dev->ports[i].mib;
2524
2525 dev->dev_ops->port_init_cnt(dev, i);
2526
2527 mib->cnt_ptr = 0;
2528 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
2529 }
2530 }
2531
ksz_phy_read16(struct dsa_switch * ds,int addr,int reg)2532 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
2533 {
2534 struct ksz_device *dev = ds->priv;
2535 u16 val = 0xffff;
2536 int ret;
2537
2538 ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
2539 if (ret)
2540 return ret;
2541
2542 return val;
2543 }
2544
ksz_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)2545 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
2546 {
2547 struct ksz_device *dev = ds->priv;
2548 int ret;
2549
2550 ret = dev->dev_ops->w_phy(dev, addr, reg, val);
2551 if (ret)
2552 return ret;
2553
2554 return 0;
2555 }
2556
ksz_get_phy_flags(struct dsa_switch * ds,int port)2557 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
2558 {
2559 struct ksz_device *dev = ds->priv;
2560
2561 switch (dev->chip_id) {
2562 case KSZ8830_CHIP_ID:
2563 /* Silicon Errata Sheet (DS80000830A):
2564 * Port 1 does not work with LinkMD Cable-Testing.
2565 * Port 1 does not respond to received PAUSE control frames.
2566 */
2567 if (!port)
2568 return MICREL_KSZ8_P1_ERRATA;
2569 break;
2570 case KSZ9477_CHIP_ID:
2571 /* KSZ9477 Errata DS80000754C
2572 *
2573 * Module 4: Energy Efficient Ethernet (EEE) feature select must
2574 * be manually disabled
2575 * The EEE feature is enabled by default, but it is not fully
2576 * operational. It must be manually disabled through register
2577 * controls. If not disabled, the PHY ports can auto-negotiate
2578 * to enable EEE, and this feature can cause link drops when
2579 * linked to another device supporting EEE.
2580 */
2581 return MICREL_NO_EEE;
2582 }
2583
2584 return 0;
2585 }
2586
ksz_phylink_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)2587 static void ksz_phylink_mac_link_down(struct phylink_config *config,
2588 unsigned int mode,
2589 phy_interface_t interface)
2590 {
2591 struct dsa_port *dp = dsa_phylink_to_port(config);
2592 struct ksz_device *dev = dp->ds->priv;
2593
2594 /* Read all MIB counters when the link is going down. */
2595 dev->ports[dp->index].read = true;
2596 /* timer started */
2597 if (dev->mib_read_interval)
2598 schedule_delayed_work(&dev->mib_read, 0);
2599 }
2600
ksz_sset_count(struct dsa_switch * ds,int port,int sset)2601 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
2602 {
2603 struct ksz_device *dev = ds->priv;
2604
2605 if (sset != ETH_SS_STATS)
2606 return 0;
2607
2608 return dev->info->mib_cnt;
2609 }
2610
ksz_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * buf)2611 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
2612 uint64_t *buf)
2613 {
2614 const struct dsa_port *dp = dsa_to_port(ds, port);
2615 struct ksz_device *dev = ds->priv;
2616 struct ksz_port_mib *mib;
2617
2618 mib = &dev->ports[port].mib;
2619 mutex_lock(&mib->cnt_mutex);
2620
2621 /* Only read dropped counters if no link. */
2622 if (!netif_carrier_ok(dp->user))
2623 mib->cnt_ptr = dev->info->reg_mib_cnt;
2624 port_r_cnt(dev, port);
2625 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
2626 mutex_unlock(&mib->cnt_mutex);
2627 }
2628
ksz_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)2629 static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
2630 struct dsa_bridge bridge,
2631 bool *tx_fwd_offload,
2632 struct netlink_ext_ack *extack)
2633 {
2634 /* port_stp_state_set() will be called after to put the port in
2635 * appropriate state so there is no need to do anything.
2636 */
2637
2638 return 0;
2639 }
2640
ksz_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)2641 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
2642 struct dsa_bridge bridge)
2643 {
2644 /* port_stp_state_set() will be called after to put the port in
2645 * forwarding state so there is no need to do anything.
2646 */
2647 }
2648
ksz_port_fast_age(struct dsa_switch * ds,int port)2649 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
2650 {
2651 struct ksz_device *dev = ds->priv;
2652
2653 dev->dev_ops->flush_dyn_mac_table(dev, port);
2654 }
2655
ksz_set_ageing_time(struct dsa_switch * ds,unsigned int msecs)2656 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
2657 {
2658 struct ksz_device *dev = ds->priv;
2659
2660 if (!dev->dev_ops->set_ageing_time)
2661 return -EOPNOTSUPP;
2662
2663 return dev->dev_ops->set_ageing_time(dev, msecs);
2664 }
2665
ksz_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2666 static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
2667 const unsigned char *addr, u16 vid,
2668 struct dsa_db db)
2669 {
2670 struct ksz_device *dev = ds->priv;
2671
2672 if (!dev->dev_ops->fdb_add)
2673 return -EOPNOTSUPP;
2674
2675 return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
2676 }
2677
ksz_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2678 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
2679 const unsigned char *addr,
2680 u16 vid, struct dsa_db db)
2681 {
2682 struct ksz_device *dev = ds->priv;
2683
2684 if (!dev->dev_ops->fdb_del)
2685 return -EOPNOTSUPP;
2686
2687 return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
2688 }
2689
ksz_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)2690 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
2691 dsa_fdb_dump_cb_t *cb, void *data)
2692 {
2693 struct ksz_device *dev = ds->priv;
2694
2695 if (!dev->dev_ops->fdb_dump)
2696 return -EOPNOTSUPP;
2697
2698 return dev->dev_ops->fdb_dump(dev, port, cb, data);
2699 }
2700
ksz_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)2701 static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
2702 const struct switchdev_obj_port_mdb *mdb,
2703 struct dsa_db db)
2704 {
2705 struct ksz_device *dev = ds->priv;
2706
2707 if (!dev->dev_ops->mdb_add)
2708 return -EOPNOTSUPP;
2709
2710 return dev->dev_ops->mdb_add(dev, port, mdb, db);
2711 }
2712
ksz_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)2713 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
2714 const struct switchdev_obj_port_mdb *mdb,
2715 struct dsa_db db)
2716 {
2717 struct ksz_device *dev = ds->priv;
2718
2719 if (!dev->dev_ops->mdb_del)
2720 return -EOPNOTSUPP;
2721
2722 return dev->dev_ops->mdb_del(dev, port, mdb, db);
2723 }
2724
ksz9477_set_default_prio_queue_mapping(struct ksz_device * dev,int port)2725 static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev,
2726 int port)
2727 {
2728 u32 queue_map = 0;
2729 int ipm;
2730
2731 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) {
2732 int queue;
2733
2734 /* Traffic Type (TT) is corresponding to the Internal Priority
2735 * Map (IPM) in the switch. Traffic Class (TC) is
2736 * corresponding to the queue in the switch.
2737 */
2738 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues);
2739 if (queue < 0)
2740 return queue;
2741
2742 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S);
2743 }
2744
2745 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
2746 }
2747
ksz_port_setup(struct dsa_switch * ds,int port)2748 static int ksz_port_setup(struct dsa_switch *ds, int port)
2749 {
2750 struct ksz_device *dev = ds->priv;
2751 int ret;
2752
2753 if (!dsa_is_user_port(ds, port))
2754 return 0;
2755
2756 /* setup user port */
2757 dev->dev_ops->port_setup(dev, port, false);
2758
2759 if (!is_ksz8(dev)) {
2760 ret = ksz9477_set_default_prio_queue_mapping(dev, port);
2761 if (ret)
2762 return ret;
2763 }
2764
2765 /* port_stp_state_set() will be called after to enable the port so
2766 * there is no need to do anything.
2767 */
2768
2769 return ksz_dcb_init_port(dev, port);
2770 }
2771
ksz_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)2772 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
2773 {
2774 struct ksz_device *dev = ds->priv;
2775 struct ksz_port *p;
2776 const u16 *regs;
2777 u8 data;
2778
2779 regs = dev->info->regs;
2780
2781 ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
2782 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2783
2784 p = &dev->ports[port];
2785
2786 switch (state) {
2787 case BR_STATE_DISABLED:
2788 data |= PORT_LEARN_DISABLE;
2789 break;
2790 case BR_STATE_LISTENING:
2791 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2792 break;
2793 case BR_STATE_LEARNING:
2794 data |= PORT_RX_ENABLE;
2795 if (!p->learning)
2796 data |= PORT_LEARN_DISABLE;
2797 break;
2798 case BR_STATE_FORWARDING:
2799 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2800 if (!p->learning)
2801 data |= PORT_LEARN_DISABLE;
2802 break;
2803 case BR_STATE_BLOCKING:
2804 data |= PORT_LEARN_DISABLE;
2805 break;
2806 default:
2807 dev_err(ds->dev, "invalid STP state: %d\n", state);
2808 return;
2809 }
2810
2811 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
2812
2813 p->stp_state = state;
2814
2815 ksz_update_port_member(dev, port);
2816 }
2817
ksz_port_teardown(struct dsa_switch * ds,int port)2818 static void ksz_port_teardown(struct dsa_switch *ds, int port)
2819 {
2820 struct ksz_device *dev = ds->priv;
2821
2822 switch (dev->chip_id) {
2823 case KSZ8563_CHIP_ID:
2824 case KSZ8567_CHIP_ID:
2825 case KSZ9477_CHIP_ID:
2826 case KSZ9563_CHIP_ID:
2827 case KSZ9567_CHIP_ID:
2828 case KSZ9893_CHIP_ID:
2829 case KSZ9896_CHIP_ID:
2830 case KSZ9897_CHIP_ID:
2831 if (dsa_is_user_port(ds, port))
2832 ksz9477_port_acl_free(dev, port);
2833 }
2834 }
2835
ksz_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2836 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2837 struct switchdev_brport_flags flags,
2838 struct netlink_ext_ack *extack)
2839 {
2840 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED))
2841 return -EINVAL;
2842
2843 return 0;
2844 }
2845
ksz_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2846 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
2847 struct switchdev_brport_flags flags,
2848 struct netlink_ext_ack *extack)
2849 {
2850 struct ksz_device *dev = ds->priv;
2851 struct ksz_port *p = &dev->ports[port];
2852
2853 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) {
2854 if (flags.mask & BR_LEARNING)
2855 p->learning = !!(flags.val & BR_LEARNING);
2856
2857 if (flags.mask & BR_ISOLATED)
2858 p->isolated = !!(flags.val & BR_ISOLATED);
2859
2860 /* Make the change take effect immediately */
2861 ksz_port_stp_state_set(ds, port, p->stp_state);
2862 }
2863
2864 return 0;
2865 }
2866
ksz_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)2867 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
2868 int port,
2869 enum dsa_tag_protocol mp)
2870 {
2871 struct ksz_device *dev = ds->priv;
2872 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
2873
2874 if (dev->chip_id == KSZ8795_CHIP_ID ||
2875 dev->chip_id == KSZ8794_CHIP_ID ||
2876 dev->chip_id == KSZ8765_CHIP_ID)
2877 proto = DSA_TAG_PROTO_KSZ8795;
2878
2879 if (dev->chip_id == KSZ8830_CHIP_ID ||
2880 dev->chip_id == KSZ8563_CHIP_ID ||
2881 dev->chip_id == KSZ9893_CHIP_ID ||
2882 dev->chip_id == KSZ9563_CHIP_ID)
2883 proto = DSA_TAG_PROTO_KSZ9893;
2884
2885 if (dev->chip_id == KSZ8567_CHIP_ID ||
2886 dev->chip_id == KSZ9477_CHIP_ID ||
2887 dev->chip_id == KSZ9896_CHIP_ID ||
2888 dev->chip_id == KSZ9897_CHIP_ID ||
2889 dev->chip_id == KSZ9567_CHIP_ID)
2890 proto = DSA_TAG_PROTO_KSZ9477;
2891
2892 if (is_lan937x(dev))
2893 proto = DSA_TAG_PROTO_LAN937X;
2894
2895 return proto;
2896 }
2897
ksz_connect_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)2898 static int ksz_connect_tag_protocol(struct dsa_switch *ds,
2899 enum dsa_tag_protocol proto)
2900 {
2901 struct ksz_tagger_data *tagger_data;
2902
2903 switch (proto) {
2904 case DSA_TAG_PROTO_KSZ8795:
2905 return 0;
2906 case DSA_TAG_PROTO_KSZ9893:
2907 case DSA_TAG_PROTO_KSZ9477:
2908 case DSA_TAG_PROTO_LAN937X:
2909 tagger_data = ksz_tagger_data(ds);
2910 tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
2911 return 0;
2912 default:
2913 return -EPROTONOSUPPORT;
2914 }
2915 }
2916
ksz_port_vlan_filtering(struct dsa_switch * ds,int port,bool flag,struct netlink_ext_ack * extack)2917 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
2918 bool flag, struct netlink_ext_ack *extack)
2919 {
2920 struct ksz_device *dev = ds->priv;
2921
2922 if (!dev->dev_ops->vlan_filtering)
2923 return -EOPNOTSUPP;
2924
2925 return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
2926 }
2927
ksz_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)2928 static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
2929 const struct switchdev_obj_port_vlan *vlan,
2930 struct netlink_ext_ack *extack)
2931 {
2932 struct ksz_device *dev = ds->priv;
2933
2934 if (!dev->dev_ops->vlan_add)
2935 return -EOPNOTSUPP;
2936
2937 return dev->dev_ops->vlan_add(dev, port, vlan, extack);
2938 }
2939
ksz_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2940 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
2941 const struct switchdev_obj_port_vlan *vlan)
2942 {
2943 struct ksz_device *dev = ds->priv;
2944
2945 if (!dev->dev_ops->vlan_del)
2946 return -EOPNOTSUPP;
2947
2948 return dev->dev_ops->vlan_del(dev, port, vlan);
2949 }
2950
ksz_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)2951 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
2952 struct dsa_mall_mirror_tc_entry *mirror,
2953 bool ingress, struct netlink_ext_ack *extack)
2954 {
2955 struct ksz_device *dev = ds->priv;
2956
2957 if (!dev->dev_ops->mirror_add)
2958 return -EOPNOTSUPP;
2959
2960 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
2961 }
2962
ksz_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)2963 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
2964 struct dsa_mall_mirror_tc_entry *mirror)
2965 {
2966 struct ksz_device *dev = ds->priv;
2967
2968 if (dev->dev_ops->mirror_del)
2969 dev->dev_ops->mirror_del(dev, port, mirror);
2970 }
2971
ksz_change_mtu(struct dsa_switch * ds,int port,int mtu)2972 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
2973 {
2974 struct ksz_device *dev = ds->priv;
2975
2976 if (!dev->dev_ops->change_mtu)
2977 return -EOPNOTSUPP;
2978
2979 return dev->dev_ops->change_mtu(dev, port, mtu);
2980 }
2981
ksz_max_mtu(struct dsa_switch * ds,int port)2982 static int ksz_max_mtu(struct dsa_switch *ds, int port)
2983 {
2984 struct ksz_device *dev = ds->priv;
2985
2986 switch (dev->chip_id) {
2987 case KSZ8795_CHIP_ID:
2988 case KSZ8794_CHIP_ID:
2989 case KSZ8765_CHIP_ID:
2990 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2991 case KSZ8830_CHIP_ID:
2992 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2993 case KSZ8563_CHIP_ID:
2994 case KSZ8567_CHIP_ID:
2995 case KSZ9477_CHIP_ID:
2996 case KSZ9563_CHIP_ID:
2997 case KSZ9567_CHIP_ID:
2998 case KSZ9893_CHIP_ID:
2999 case KSZ9896_CHIP_ID:
3000 case KSZ9897_CHIP_ID:
3001 case LAN9370_CHIP_ID:
3002 case LAN9371_CHIP_ID:
3003 case LAN9372_CHIP_ID:
3004 case LAN9373_CHIP_ID:
3005 case LAN9374_CHIP_ID:
3006 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3007 }
3008
3009 return -EOPNOTSUPP;
3010 }
3011
ksz_validate_eee(struct dsa_switch * ds,int port)3012 static int ksz_validate_eee(struct dsa_switch *ds, int port)
3013 {
3014 struct ksz_device *dev = ds->priv;
3015
3016 if (!dev->info->internal_phy[port])
3017 return -EOPNOTSUPP;
3018
3019 switch (dev->chip_id) {
3020 case KSZ8563_CHIP_ID:
3021 case KSZ8567_CHIP_ID:
3022 case KSZ9477_CHIP_ID:
3023 case KSZ9563_CHIP_ID:
3024 case KSZ9567_CHIP_ID:
3025 case KSZ9893_CHIP_ID:
3026 case KSZ9896_CHIP_ID:
3027 case KSZ9897_CHIP_ID:
3028 return 0;
3029 }
3030
3031 return -EOPNOTSUPP;
3032 }
3033
ksz_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_keee * e)3034 static int ksz_get_mac_eee(struct dsa_switch *ds, int port,
3035 struct ethtool_keee *e)
3036 {
3037 int ret;
3038
3039 ret = ksz_validate_eee(ds, port);
3040 if (ret)
3041 return ret;
3042
3043 /* There is no documented control of Tx LPI configuration. */
3044 e->tx_lpi_enabled = true;
3045
3046 /* There is no documented control of Tx LPI timer. According to tests
3047 * Tx LPI timer seems to be set by default to minimal value.
3048 */
3049 e->tx_lpi_timer = 0;
3050
3051 return 0;
3052 }
3053
ksz_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_keee * e)3054 static int ksz_set_mac_eee(struct dsa_switch *ds, int port,
3055 struct ethtool_keee *e)
3056 {
3057 struct ksz_device *dev = ds->priv;
3058 int ret;
3059
3060 ret = ksz_validate_eee(ds, port);
3061 if (ret)
3062 return ret;
3063
3064 if (!e->tx_lpi_enabled) {
3065 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n");
3066 return -EINVAL;
3067 }
3068
3069 if (e->tx_lpi_timer) {
3070 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n");
3071 return -EINVAL;
3072 }
3073
3074 return 0;
3075 }
3076
ksz_set_xmii(struct ksz_device * dev,int port,phy_interface_t interface)3077 static void ksz_set_xmii(struct ksz_device *dev, int port,
3078 phy_interface_t interface)
3079 {
3080 const u8 *bitval = dev->info->xmii_ctrl1;
3081 struct ksz_port *p = &dev->ports[port];
3082 const u16 *regs = dev->info->regs;
3083 u8 data8;
3084
3085 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3086
3087 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
3088 P_RGMII_ID_EG_ENABLE);
3089
3090 switch (interface) {
3091 case PHY_INTERFACE_MODE_MII:
3092 data8 |= bitval[P_MII_SEL];
3093 break;
3094 case PHY_INTERFACE_MODE_RMII:
3095 data8 |= bitval[P_RMII_SEL];
3096 break;
3097 case PHY_INTERFACE_MODE_GMII:
3098 data8 |= bitval[P_GMII_SEL];
3099 break;
3100 case PHY_INTERFACE_MODE_RGMII:
3101 case PHY_INTERFACE_MODE_RGMII_ID:
3102 case PHY_INTERFACE_MODE_RGMII_TXID:
3103 case PHY_INTERFACE_MODE_RGMII_RXID:
3104 data8 |= bitval[P_RGMII_SEL];
3105 /* On KSZ9893, disable RGMII in-band status support */
3106 if (dev->chip_id == KSZ9893_CHIP_ID ||
3107 dev->chip_id == KSZ8563_CHIP_ID ||
3108 dev->chip_id == KSZ9563_CHIP_ID)
3109 data8 &= ~P_MII_MAC_MODE;
3110 break;
3111 default:
3112 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
3113 phy_modes(interface), port);
3114 return;
3115 }
3116
3117 if (p->rgmii_tx_val)
3118 data8 |= P_RGMII_ID_EG_ENABLE;
3119
3120 if (p->rgmii_rx_val)
3121 data8 |= P_RGMII_ID_IG_ENABLE;
3122
3123 /* Write the updated value */
3124 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
3125 }
3126
ksz_get_xmii(struct ksz_device * dev,int port,bool gbit)3127 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
3128 {
3129 const u8 *bitval = dev->info->xmii_ctrl1;
3130 const u16 *regs = dev->info->regs;
3131 phy_interface_t interface;
3132 u8 data8;
3133 u8 val;
3134
3135 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3136
3137 val = FIELD_GET(P_MII_SEL_M, data8);
3138
3139 if (val == bitval[P_MII_SEL]) {
3140 if (gbit)
3141 interface = PHY_INTERFACE_MODE_GMII;
3142 else
3143 interface = PHY_INTERFACE_MODE_MII;
3144 } else if (val == bitval[P_RMII_SEL]) {
3145 interface = PHY_INTERFACE_MODE_RMII;
3146 } else {
3147 interface = PHY_INTERFACE_MODE_RGMII;
3148 if (data8 & P_RGMII_ID_EG_ENABLE)
3149 interface = PHY_INTERFACE_MODE_RGMII_TXID;
3150 if (data8 & P_RGMII_ID_IG_ENABLE) {
3151 interface = PHY_INTERFACE_MODE_RGMII_RXID;
3152 if (data8 & P_RGMII_ID_EG_ENABLE)
3153 interface = PHY_INTERFACE_MODE_RGMII_ID;
3154 }
3155 }
3156
3157 return interface;
3158 }
3159
ksz8830_phylink_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)3160 static void ksz8830_phylink_mac_config(struct phylink_config *config,
3161 unsigned int mode,
3162 const struct phylink_link_state *state)
3163 {
3164 struct dsa_port *dp = dsa_phylink_to_port(config);
3165 struct ksz_device *dev = dp->ds->priv;
3166
3167 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN);
3168 }
3169
ksz_phylink_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)3170 static void ksz_phylink_mac_config(struct phylink_config *config,
3171 unsigned int mode,
3172 const struct phylink_link_state *state)
3173 {
3174 struct dsa_port *dp = dsa_phylink_to_port(config);
3175 struct ksz_device *dev = dp->ds->priv;
3176 int port = dp->index;
3177
3178 /* Internal PHYs */
3179 if (dev->info->internal_phy[port])
3180 return;
3181
3182 if (phylink_autoneg_inband(mode)) {
3183 dev_err(dev->dev, "In-band AN not supported!\n");
3184 return;
3185 }
3186
3187 ksz_set_xmii(dev, port, state->interface);
3188
3189 if (dev->dev_ops->setup_rgmii_delay)
3190 dev->dev_ops->setup_rgmii_delay(dev, port);
3191 }
3192
ksz_get_gbit(struct ksz_device * dev,int port)3193 bool ksz_get_gbit(struct ksz_device *dev, int port)
3194 {
3195 const u8 *bitval = dev->info->xmii_ctrl1;
3196 const u16 *regs = dev->info->regs;
3197 bool gbit = false;
3198 u8 data8;
3199 bool val;
3200
3201 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3202
3203 val = FIELD_GET(P_GMII_1GBIT_M, data8);
3204
3205 if (val == bitval[P_GMII_1GBIT])
3206 gbit = true;
3207
3208 return gbit;
3209 }
3210
ksz_set_gbit(struct ksz_device * dev,int port,bool gbit)3211 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
3212 {
3213 const u8 *bitval = dev->info->xmii_ctrl1;
3214 const u16 *regs = dev->info->regs;
3215 u8 data8;
3216
3217 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3218
3219 data8 &= ~P_GMII_1GBIT_M;
3220
3221 if (gbit)
3222 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
3223 else
3224 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
3225
3226 /* Write the updated value */
3227 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
3228 }
3229
ksz_set_100_10mbit(struct ksz_device * dev,int port,int speed)3230 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
3231 {
3232 const u8 *bitval = dev->info->xmii_ctrl0;
3233 const u16 *regs = dev->info->regs;
3234 u8 data8;
3235
3236 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
3237
3238 data8 &= ~P_MII_100MBIT_M;
3239
3240 if (speed == SPEED_100)
3241 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
3242 else
3243 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
3244
3245 /* Write the updated value */
3246 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
3247 }
3248
ksz_port_set_xmii_speed(struct ksz_device * dev,int port,int speed)3249 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
3250 {
3251 if (speed == SPEED_1000)
3252 ksz_set_gbit(dev, port, true);
3253 else
3254 ksz_set_gbit(dev, port, false);
3255
3256 if (speed == SPEED_100 || speed == SPEED_10)
3257 ksz_set_100_10mbit(dev, port, speed);
3258 }
3259
ksz_duplex_flowctrl(struct ksz_device * dev,int port,int duplex,bool tx_pause,bool rx_pause)3260 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
3261 bool tx_pause, bool rx_pause)
3262 {
3263 const u8 *bitval = dev->info->xmii_ctrl0;
3264 const u32 *masks = dev->info->masks;
3265 const u16 *regs = dev->info->regs;
3266 u8 mask;
3267 u8 val;
3268
3269 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
3270 masks[P_MII_RX_FLOW_CTRL];
3271
3272 if (duplex == DUPLEX_FULL)
3273 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
3274 else
3275 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
3276
3277 if (tx_pause)
3278 val |= masks[P_MII_TX_FLOW_CTRL];
3279
3280 if (rx_pause)
3281 val |= masks[P_MII_RX_FLOW_CTRL];
3282
3283 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
3284 }
3285
ksz9477_phylink_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)3286 static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
3287 struct phy_device *phydev,
3288 unsigned int mode,
3289 phy_interface_t interface,
3290 int speed, int duplex, bool tx_pause,
3291 bool rx_pause)
3292 {
3293 struct dsa_port *dp = dsa_phylink_to_port(config);
3294 struct ksz_device *dev = dp->ds->priv;
3295 int port = dp->index;
3296 struct ksz_port *p;
3297
3298 p = &dev->ports[port];
3299
3300 /* Internal PHYs */
3301 if (dev->info->internal_phy[port])
3302 return;
3303
3304 p->phydev.speed = speed;
3305
3306 ksz_port_set_xmii_speed(dev, port, speed);
3307
3308 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
3309 }
3310
ksz_switch_detect(struct ksz_device * dev)3311 static int ksz_switch_detect(struct ksz_device *dev)
3312 {
3313 u8 id1, id2, id4;
3314 u16 id16;
3315 u32 id32;
3316 int ret;
3317
3318 /* read chip id */
3319 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
3320 if (ret)
3321 return ret;
3322
3323 id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
3324 id2 = FIELD_GET(SW_CHIP_ID_M, id16);
3325
3326 switch (id1) {
3327 case KSZ87_FAMILY_ID:
3328 if (id2 == KSZ87_CHIP_ID_95) {
3329 u8 val;
3330
3331 dev->chip_id = KSZ8795_CHIP_ID;
3332
3333 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
3334 if (val & KSZ8_PORT_FIBER_MODE)
3335 dev->chip_id = KSZ8765_CHIP_ID;
3336 } else if (id2 == KSZ87_CHIP_ID_94) {
3337 dev->chip_id = KSZ8794_CHIP_ID;
3338 } else {
3339 return -ENODEV;
3340 }
3341 break;
3342 case KSZ88_FAMILY_ID:
3343 if (id2 == KSZ88_CHIP_ID_63)
3344 dev->chip_id = KSZ8830_CHIP_ID;
3345 else
3346 return -ENODEV;
3347 break;
3348 default:
3349 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
3350 if (ret)
3351 return ret;
3352
3353 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
3354 id32 &= ~0xFF;
3355
3356 switch (id32) {
3357 case KSZ9477_CHIP_ID:
3358 case KSZ9896_CHIP_ID:
3359 case KSZ9897_CHIP_ID:
3360 case KSZ9567_CHIP_ID:
3361 case KSZ8567_CHIP_ID:
3362 case LAN9370_CHIP_ID:
3363 case LAN9371_CHIP_ID:
3364 case LAN9372_CHIP_ID:
3365 case LAN9373_CHIP_ID:
3366 case LAN9374_CHIP_ID:
3367 dev->chip_id = id32;
3368 break;
3369 case KSZ9893_CHIP_ID:
3370 ret = ksz_read8(dev, REG_CHIP_ID4,
3371 &id4);
3372 if (ret)
3373 return ret;
3374
3375 if (id4 == SKU_ID_KSZ8563)
3376 dev->chip_id = KSZ8563_CHIP_ID;
3377 else if (id4 == SKU_ID_KSZ9563)
3378 dev->chip_id = KSZ9563_CHIP_ID;
3379 else
3380 dev->chip_id = KSZ9893_CHIP_ID;
3381
3382 break;
3383 default:
3384 dev_err(dev->dev,
3385 "unsupported switch detected %x)\n", id32);
3386 return -ENODEV;
3387 }
3388 }
3389 return 0;
3390 }
3391
ksz_cls_flower_add(struct dsa_switch * ds,int port,struct flow_cls_offload * cls,bool ingress)3392 static int ksz_cls_flower_add(struct dsa_switch *ds, int port,
3393 struct flow_cls_offload *cls, bool ingress)
3394 {
3395 struct ksz_device *dev = ds->priv;
3396
3397 switch (dev->chip_id) {
3398 case KSZ8563_CHIP_ID:
3399 case KSZ8567_CHIP_ID:
3400 case KSZ9477_CHIP_ID:
3401 case KSZ9563_CHIP_ID:
3402 case KSZ9567_CHIP_ID:
3403 case KSZ9893_CHIP_ID:
3404 case KSZ9896_CHIP_ID:
3405 case KSZ9897_CHIP_ID:
3406 return ksz9477_cls_flower_add(ds, port, cls, ingress);
3407 }
3408
3409 return -EOPNOTSUPP;
3410 }
3411
ksz_cls_flower_del(struct dsa_switch * ds,int port,struct flow_cls_offload * cls,bool ingress)3412 static int ksz_cls_flower_del(struct dsa_switch *ds, int port,
3413 struct flow_cls_offload *cls, bool ingress)
3414 {
3415 struct ksz_device *dev = ds->priv;
3416
3417 switch (dev->chip_id) {
3418 case KSZ8563_CHIP_ID:
3419 case KSZ8567_CHIP_ID:
3420 case KSZ9477_CHIP_ID:
3421 case KSZ9563_CHIP_ID:
3422 case KSZ9567_CHIP_ID:
3423 case KSZ9893_CHIP_ID:
3424 case KSZ9896_CHIP_ID:
3425 case KSZ9897_CHIP_ID:
3426 return ksz9477_cls_flower_del(ds, port, cls, ingress);
3427 }
3428
3429 return -EOPNOTSUPP;
3430 }
3431
3432 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth
3433 * is converted to Hex-decimal using the successive multiplication method. On
3434 * every step, integer part is taken and decimal part is carry forwarded.
3435 */
cinc_cal(s32 idle_slope,s32 send_slope,u32 * bw)3436 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw)
3437 {
3438 u32 cinc = 0;
3439 u32 txrate;
3440 u32 rate;
3441 u8 temp;
3442 u8 i;
3443
3444 txrate = idle_slope - send_slope;
3445
3446 if (!txrate)
3447 return -EINVAL;
3448
3449 rate = idle_slope;
3450
3451 /* 24 bit register */
3452 for (i = 0; i < 6; i++) {
3453 rate = rate * 16;
3454
3455 temp = rate / txrate;
3456
3457 rate %= txrate;
3458
3459 cinc = ((cinc << 4) | temp);
3460 }
3461
3462 *bw = cinc;
3463
3464 return 0;
3465 }
3466
ksz_setup_tc_mode(struct ksz_device * dev,int port,u8 scheduler,u8 shaper)3467 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler,
3468 u8 shaper)
3469 {
3470 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
3471 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) |
3472 FIELD_PREP(MTI_SHAPING_M, shaper));
3473 }
3474
ksz_setup_tc_cbs(struct dsa_switch * ds,int port,struct tc_cbs_qopt_offload * qopt)3475 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
3476 struct tc_cbs_qopt_offload *qopt)
3477 {
3478 struct ksz_device *dev = ds->priv;
3479 int ret;
3480 u32 bw;
3481
3482 if (!dev->info->tc_cbs_supported)
3483 return -EOPNOTSUPP;
3484
3485 if (qopt->queue > dev->info->num_tx_queues)
3486 return -EINVAL;
3487
3488 /* Queue Selection */
3489 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue);
3490 if (ret)
3491 return ret;
3492
3493 if (!qopt->enable)
3494 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3495 MTI_SHAPING_OFF);
3496
3497 /* High Credit */
3498 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK,
3499 qopt->hicredit);
3500 if (ret)
3501 return ret;
3502
3503 /* Low Credit */
3504 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK,
3505 qopt->locredit);
3506 if (ret)
3507 return ret;
3508
3509 /* Credit Increment Register */
3510 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw);
3511 if (ret)
3512 return ret;
3513
3514 if (dev->dev_ops->tc_cbs_set_cinc) {
3515 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw);
3516 if (ret)
3517 return ret;
3518 }
3519
3520 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3521 MTI_SHAPING_SRP);
3522 }
3523
ksz_disable_egress_rate_limit(struct ksz_device * dev,int port)3524 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port)
3525 {
3526 int queue, ret;
3527
3528 /* Configuration will not take effect until the last Port Queue X
3529 * Egress Limit Control Register is written.
3530 */
3531 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3532 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue,
3533 KSZ9477_OUT_RATE_NO_LIMIT);
3534 if (ret)
3535 return ret;
3536 }
3537
3538 return 0;
3539 }
3540
ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params * p,int band)3541 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p,
3542 int band)
3543 {
3544 /* Compared to queues, bands prioritize packets differently. In strict
3545 * priority mode, the lowest priority is assigned to Queue 0 while the
3546 * highest priority is given to Band 0.
3547 */
3548 return p->bands - 1 - band;
3549 }
3550
ksz_queue_set_strict(struct ksz_device * dev,int port,int queue)3551 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue)
3552 {
3553 int ret;
3554
3555 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
3556 if (ret)
3557 return ret;
3558
3559 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3560 MTI_SHAPING_OFF);
3561 }
3562
ksz_queue_set_wrr(struct ksz_device * dev,int port,int queue,int weight)3563 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue,
3564 int weight)
3565 {
3566 int ret;
3567
3568 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
3569 if (ret)
3570 return ret;
3571
3572 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3573 MTI_SHAPING_OFF);
3574 if (ret)
3575 return ret;
3576
3577 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight);
3578 }
3579
ksz_tc_ets_add(struct ksz_device * dev,int port,struct tc_ets_qopt_offload_replace_params * p)3580 static int ksz_tc_ets_add(struct ksz_device *dev, int port,
3581 struct tc_ets_qopt_offload_replace_params *p)
3582 {
3583 int ret, band, tc_prio;
3584 u32 queue_map = 0;
3585
3586 /* In order to ensure proper prioritization, it is necessary to set the
3587 * rate limit for the related queue to zero. Otherwise strict priority
3588 * or WRR mode will not work. This is a hardware limitation.
3589 */
3590 ret = ksz_disable_egress_rate_limit(dev, port);
3591 if (ret)
3592 return ret;
3593
3594 /* Configure queue scheduling mode for all bands. Currently only strict
3595 * prio mode is supported.
3596 */
3597 for (band = 0; band < p->bands; band++) {
3598 int queue = ksz_ets_band_to_queue(p, band);
3599
3600 ret = ksz_queue_set_strict(dev, port, queue);
3601 if (ret)
3602 return ret;
3603 }
3604
3605 /* Configure the mapping between traffic classes and queues. Note:
3606 * priomap variable support 16 traffic classes, but the chip can handle
3607 * only 8 classes.
3608 */
3609 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) {
3610 int queue;
3611
3612 if (tc_prio >= dev->info->num_ipms)
3613 break;
3614
3615 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]);
3616 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
3617 }
3618
3619 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
3620 }
3621
ksz_tc_ets_del(struct ksz_device * dev,int port)3622 static int ksz_tc_ets_del(struct ksz_device *dev, int port)
3623 {
3624 int ret, queue;
3625
3626 /* To restore the default chip configuration, set all queues to use the
3627 * WRR scheduler with a weight of 1.
3628 */
3629 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3630 ret = ksz_queue_set_wrr(dev, port, queue,
3631 KSZ9477_DEFAULT_WRR_WEIGHT);
3632 if (ret)
3633 return ret;
3634 }
3635
3636 /* Revert the queue mapping for TC-priority to its default setting on
3637 * the chip.
3638 */
3639 return ksz9477_set_default_prio_queue_mapping(dev, port);
3640 }
3641
ksz_tc_ets_validate(struct ksz_device * dev,int port,struct tc_ets_qopt_offload_replace_params * p)3642 static int ksz_tc_ets_validate(struct ksz_device *dev, int port,
3643 struct tc_ets_qopt_offload_replace_params *p)
3644 {
3645 int band;
3646
3647 /* Since it is not feasible to share one port among multiple qdisc,
3648 * the user must configure all available queues appropriately.
3649 */
3650 if (p->bands != dev->info->num_tx_queues) {
3651 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n",
3652 dev->info->num_tx_queues);
3653 return -EOPNOTSUPP;
3654 }
3655
3656 for (band = 0; band < p->bands; ++band) {
3657 /* The KSZ switches utilize a weighted round robin configuration
3658 * where a certain number of packets can be transmitted from a
3659 * queue before the next queue is serviced. For more information
3660 * on this, refer to section 5.2.8.4 of the KSZ8565R
3661 * documentation on the Port Transmit Queue Control 1 Register.
3662 * However, the current ETS Qdisc implementation (as of February
3663 * 2023) assigns a weight to each queue based on the number of
3664 * bytes or extrapolated bandwidth in percentages. Since this
3665 * differs from the KSZ switches' method and we don't want to
3666 * fake support by converting bytes to packets, it is better to
3667 * return an error instead.
3668 */
3669 if (p->quanta[band]) {
3670 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n");
3671 return -EOPNOTSUPP;
3672 }
3673 }
3674
3675 return 0;
3676 }
3677
ksz_tc_setup_qdisc_ets(struct dsa_switch * ds,int port,struct tc_ets_qopt_offload * qopt)3678 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port,
3679 struct tc_ets_qopt_offload *qopt)
3680 {
3681 struct ksz_device *dev = ds->priv;
3682 int ret;
3683
3684 if (is_ksz8(dev))
3685 return -EOPNOTSUPP;
3686
3687 if (qopt->parent != TC_H_ROOT) {
3688 dev_err(dev->dev, "Parent should be \"root\"\n");
3689 return -EOPNOTSUPP;
3690 }
3691
3692 switch (qopt->command) {
3693 case TC_ETS_REPLACE:
3694 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params);
3695 if (ret)
3696 return ret;
3697
3698 return ksz_tc_ets_add(dev, port, &qopt->replace_params);
3699 case TC_ETS_DESTROY:
3700 return ksz_tc_ets_del(dev, port);
3701 case TC_ETS_STATS:
3702 case TC_ETS_GRAFT:
3703 return -EOPNOTSUPP;
3704 }
3705
3706 return -EOPNOTSUPP;
3707 }
3708
ksz_setup_tc(struct dsa_switch * ds,int port,enum tc_setup_type type,void * type_data)3709 static int ksz_setup_tc(struct dsa_switch *ds, int port,
3710 enum tc_setup_type type, void *type_data)
3711 {
3712 switch (type) {
3713 case TC_SETUP_QDISC_CBS:
3714 return ksz_setup_tc_cbs(ds, port, type_data);
3715 case TC_SETUP_QDISC_ETS:
3716 return ksz_tc_setup_qdisc_ets(ds, port, type_data);
3717 default:
3718 return -EOPNOTSUPP;
3719 }
3720 }
3721
ksz_get_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)3722 static void ksz_get_wol(struct dsa_switch *ds, int port,
3723 struct ethtool_wolinfo *wol)
3724 {
3725 struct ksz_device *dev = ds->priv;
3726
3727 if (dev->dev_ops->get_wol)
3728 dev->dev_ops->get_wol(dev, port, wol);
3729 }
3730
ksz_set_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)3731 static int ksz_set_wol(struct dsa_switch *ds, int port,
3732 struct ethtool_wolinfo *wol)
3733 {
3734 struct ksz_device *dev = ds->priv;
3735
3736 if (dev->dev_ops->set_wol)
3737 return dev->dev_ops->set_wol(dev, port, wol);
3738
3739 return -EOPNOTSUPP;
3740 }
3741
ksz_port_set_mac_address(struct dsa_switch * ds,int port,const unsigned char * addr)3742 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port,
3743 const unsigned char *addr)
3744 {
3745 struct dsa_port *dp = dsa_to_port(ds, port);
3746 struct ethtool_wolinfo wol;
3747
3748 if (dp->hsr_dev) {
3749 dev_err(ds->dev,
3750 "Cannot change MAC address on port %d with active HSR offload\n",
3751 port);
3752 return -EBUSY;
3753 }
3754
3755 ksz_get_wol(ds, dp->index, &wol);
3756 if (wol.wolopts & WAKE_MAGIC) {
3757 dev_err(ds->dev,
3758 "Cannot change MAC address on port %d with active Wake on Magic Packet\n",
3759 port);
3760 return -EBUSY;
3761 }
3762
3763 return 0;
3764 }
3765
3766 /**
3767 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port
3768 * can be used as a global address.
3769 * @ds: Pointer to the DSA switch structure.
3770 * @port: The port number on which the MAC address is to be checked.
3771 *
3772 * This function examines the MAC address set on the specified port and
3773 * determines if it can be used as a global address for the switch.
3774 *
3775 * Return: true if the port's MAC address can be used as a global address, false
3776 * otherwise.
3777 */
ksz_is_port_mac_global_usable(struct dsa_switch * ds,int port)3778 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port)
3779 {
3780 struct net_device *user = dsa_to_port(ds, port)->user;
3781 const unsigned char *addr = user->dev_addr;
3782 struct ksz_switch_macaddr *switch_macaddr;
3783 struct ksz_device *dev = ds->priv;
3784
3785 ASSERT_RTNL();
3786
3787 switch_macaddr = dev->switch_macaddr;
3788 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr))
3789 return false;
3790
3791 return true;
3792 }
3793
3794 /**
3795 * ksz_switch_macaddr_get - Program the switch's MAC address register.
3796 * @ds: DSA switch instance.
3797 * @port: Port number.
3798 * @extack: Netlink extended acknowledgment.
3799 *
3800 * This function programs the switch's MAC address register with the MAC address
3801 * of the requesting user port. This single address is used by the switch for
3802 * multiple features like HSR self-address filtering and WoL. Other user ports
3803 * can share ownership of this address as long as their MAC address is the same.
3804 * The MAC addresses of user ports must not change while they have ownership of
3805 * the switch MAC address.
3806 *
3807 * Return: 0 on success, or other error codes on failure.
3808 */
ksz_switch_macaddr_get(struct dsa_switch * ds,int port,struct netlink_ext_ack * extack)3809 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
3810 struct netlink_ext_ack *extack)
3811 {
3812 struct net_device *user = dsa_to_port(ds, port)->user;
3813 const unsigned char *addr = user->dev_addr;
3814 struct ksz_switch_macaddr *switch_macaddr;
3815 struct ksz_device *dev = ds->priv;
3816 const u16 *regs = dev->info->regs;
3817 int i, ret;
3818
3819 /* Make sure concurrent MAC address changes are blocked */
3820 ASSERT_RTNL();
3821
3822 switch_macaddr = dev->switch_macaddr;
3823 if (switch_macaddr) {
3824 if (!ether_addr_equal(switch_macaddr->addr, addr)) {
3825 NL_SET_ERR_MSG_FMT_MOD(extack,
3826 "Switch already configured for MAC address %pM",
3827 switch_macaddr->addr);
3828 return -EBUSY;
3829 }
3830
3831 refcount_inc(&switch_macaddr->refcount);
3832 return 0;
3833 }
3834
3835 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL);
3836 if (!switch_macaddr)
3837 return -ENOMEM;
3838
3839 ether_addr_copy(switch_macaddr->addr, addr);
3840 refcount_set(&switch_macaddr->refcount, 1);
3841 dev->switch_macaddr = switch_macaddr;
3842
3843 /* Program the switch MAC address to hardware */
3844 for (i = 0; i < ETH_ALEN; i++) {
3845 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, addr[i]);
3846 if (ret)
3847 goto macaddr_drop;
3848 }
3849
3850 return 0;
3851
3852 macaddr_drop:
3853 dev->switch_macaddr = NULL;
3854 refcount_set(&switch_macaddr->refcount, 0);
3855 kfree(switch_macaddr);
3856
3857 return ret;
3858 }
3859
ksz_switch_macaddr_put(struct dsa_switch * ds)3860 void ksz_switch_macaddr_put(struct dsa_switch *ds)
3861 {
3862 struct ksz_switch_macaddr *switch_macaddr;
3863 struct ksz_device *dev = ds->priv;
3864 const u16 *regs = dev->info->regs;
3865 int i;
3866
3867 /* Make sure concurrent MAC address changes are blocked */
3868 ASSERT_RTNL();
3869
3870 switch_macaddr = dev->switch_macaddr;
3871 if (!refcount_dec_and_test(&switch_macaddr->refcount))
3872 return;
3873
3874 for (i = 0; i < ETH_ALEN; i++)
3875 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0);
3876
3877 dev->switch_macaddr = NULL;
3878 kfree(switch_macaddr);
3879 }
3880
ksz_hsr_join(struct dsa_switch * ds,int port,struct net_device * hsr,struct netlink_ext_ack * extack)3881 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr,
3882 struct netlink_ext_ack *extack)
3883 {
3884 struct ksz_device *dev = ds->priv;
3885 enum hsr_version ver;
3886 int ret;
3887
3888 ret = hsr_get_version(hsr, &ver);
3889 if (ret)
3890 return ret;
3891
3892 if (dev->chip_id != KSZ9477_CHIP_ID) {
3893 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload");
3894 return -EOPNOTSUPP;
3895 }
3896
3897 /* KSZ9477 can support HW offloading of only 1 HSR device */
3898 if (dev->hsr_dev && hsr != dev->hsr_dev) {
3899 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR");
3900 return -EOPNOTSUPP;
3901 }
3902
3903 /* KSZ9477 only supports HSR v0 and v1 */
3904 if (!(ver == HSR_V0 || ver == HSR_V1)) {
3905 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported");
3906 return -EOPNOTSUPP;
3907 }
3908
3909 /* Self MAC address filtering, to avoid frames traversing
3910 * the HSR ring more than once.
3911 */
3912 ret = ksz_switch_macaddr_get(ds, port, extack);
3913 if (ret)
3914 return ret;
3915
3916 ksz9477_hsr_join(ds, port, hsr);
3917 dev->hsr_dev = hsr;
3918 dev->hsr_ports |= BIT(port);
3919
3920 return 0;
3921 }
3922
ksz_hsr_leave(struct dsa_switch * ds,int port,struct net_device * hsr)3923 static int ksz_hsr_leave(struct dsa_switch *ds, int port,
3924 struct net_device *hsr)
3925 {
3926 struct ksz_device *dev = ds->priv;
3927
3928 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID);
3929
3930 ksz9477_hsr_leave(ds, port, hsr);
3931 dev->hsr_ports &= ~BIT(port);
3932 if (!dev->hsr_ports)
3933 dev->hsr_dev = NULL;
3934
3935 ksz_switch_macaddr_put(ds);
3936
3937 return 0;
3938 }
3939
3940 static const struct dsa_switch_ops ksz_switch_ops = {
3941 .get_tag_protocol = ksz_get_tag_protocol,
3942 .connect_tag_protocol = ksz_connect_tag_protocol,
3943 .get_phy_flags = ksz_get_phy_flags,
3944 .setup = ksz_setup,
3945 .teardown = ksz_teardown,
3946 .phy_read = ksz_phy_read16,
3947 .phy_write = ksz_phy_write16,
3948 .phylink_get_caps = ksz_phylink_get_caps,
3949 .port_setup = ksz_port_setup,
3950 .set_ageing_time = ksz_set_ageing_time,
3951 .get_strings = ksz_get_strings,
3952 .get_ethtool_stats = ksz_get_ethtool_stats,
3953 .get_sset_count = ksz_sset_count,
3954 .port_bridge_join = ksz_port_bridge_join,
3955 .port_bridge_leave = ksz_port_bridge_leave,
3956 .port_hsr_join = ksz_hsr_join,
3957 .port_hsr_leave = ksz_hsr_leave,
3958 .port_set_mac_address = ksz_port_set_mac_address,
3959 .port_stp_state_set = ksz_port_stp_state_set,
3960 .port_teardown = ksz_port_teardown,
3961 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
3962 .port_bridge_flags = ksz_port_bridge_flags,
3963 .port_fast_age = ksz_port_fast_age,
3964 .port_vlan_filtering = ksz_port_vlan_filtering,
3965 .port_vlan_add = ksz_port_vlan_add,
3966 .port_vlan_del = ksz_port_vlan_del,
3967 .port_fdb_dump = ksz_port_fdb_dump,
3968 .port_fdb_add = ksz_port_fdb_add,
3969 .port_fdb_del = ksz_port_fdb_del,
3970 .port_mdb_add = ksz_port_mdb_add,
3971 .port_mdb_del = ksz_port_mdb_del,
3972 .port_mirror_add = ksz_port_mirror_add,
3973 .port_mirror_del = ksz_port_mirror_del,
3974 .get_stats64 = ksz_get_stats64,
3975 .get_pause_stats = ksz_get_pause_stats,
3976 .port_change_mtu = ksz_change_mtu,
3977 .port_max_mtu = ksz_max_mtu,
3978 .get_wol = ksz_get_wol,
3979 .set_wol = ksz_set_wol,
3980 .get_ts_info = ksz_get_ts_info,
3981 .port_hwtstamp_get = ksz_hwtstamp_get,
3982 .port_hwtstamp_set = ksz_hwtstamp_set,
3983 .port_txtstamp = ksz_port_txtstamp,
3984 .port_rxtstamp = ksz_port_rxtstamp,
3985 .cls_flower_add = ksz_cls_flower_add,
3986 .cls_flower_del = ksz_cls_flower_del,
3987 .port_setup_tc = ksz_setup_tc,
3988 .get_mac_eee = ksz_get_mac_eee,
3989 .set_mac_eee = ksz_set_mac_eee,
3990 .port_get_default_prio = ksz_port_get_default_prio,
3991 .port_set_default_prio = ksz_port_set_default_prio,
3992 .port_get_dscp_prio = ksz_port_get_dscp_prio,
3993 .port_add_dscp_prio = ksz_port_add_dscp_prio,
3994 .port_del_dscp_prio = ksz_port_del_dscp_prio,
3995 .port_get_apptrust = ksz_port_get_apptrust,
3996 .port_set_apptrust = ksz_port_set_apptrust,
3997 };
3998
ksz_switch_alloc(struct device * base,void * priv)3999 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
4000 {
4001 struct dsa_switch *ds;
4002 struct ksz_device *swdev;
4003
4004 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
4005 if (!ds)
4006 return NULL;
4007
4008 ds->dev = base;
4009 ds->num_ports = DSA_MAX_PORTS;
4010 ds->ops = &ksz_switch_ops;
4011
4012 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
4013 if (!swdev)
4014 return NULL;
4015
4016 ds->priv = swdev;
4017 swdev->dev = base;
4018
4019 swdev->ds = ds;
4020 swdev->priv = priv;
4021
4022 return swdev;
4023 }
4024 EXPORT_SYMBOL(ksz_switch_alloc);
4025
4026 /**
4027 * ksz_switch_shutdown - Shutdown routine for the switch device.
4028 * @dev: The switch device structure.
4029 *
4030 * This function is responsible for initiating a shutdown sequence for the
4031 * switch device. It invokes the reset operation defined in the device
4032 * operations, if available, to reset the switch. Subsequently, it calls the
4033 * DSA framework's shutdown function to ensure a proper shutdown of the DSA
4034 * switch.
4035 */
ksz_switch_shutdown(struct ksz_device * dev)4036 void ksz_switch_shutdown(struct ksz_device *dev)
4037 {
4038 bool wol_enabled = false;
4039
4040 if (dev->dev_ops->wol_pre_shutdown)
4041 dev->dev_ops->wol_pre_shutdown(dev, &wol_enabled);
4042
4043 if (dev->dev_ops->reset && !wol_enabled)
4044 dev->dev_ops->reset(dev);
4045
4046 dsa_switch_shutdown(dev->ds);
4047 }
4048 EXPORT_SYMBOL(ksz_switch_shutdown);
4049
ksz_parse_rgmii_delay(struct ksz_device * dev,int port_num,struct device_node * port_dn)4050 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
4051 struct device_node *port_dn)
4052 {
4053 phy_interface_t phy_mode = dev->ports[port_num].interface;
4054 int rx_delay = -1, tx_delay = -1;
4055
4056 if (!phy_interface_mode_is_rgmii(phy_mode))
4057 return;
4058
4059 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
4060 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
4061
4062 if (rx_delay == -1 && tx_delay == -1) {
4063 dev_warn(dev->dev,
4064 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
4065 "please update device tree to specify \"rx-internal-delay-ps\" and "
4066 "\"tx-internal-delay-ps\"",
4067 port_num);
4068
4069 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
4070 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
4071 rx_delay = 2000;
4072
4073 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
4074 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
4075 tx_delay = 2000;
4076 }
4077
4078 if (rx_delay < 0)
4079 rx_delay = 0;
4080 if (tx_delay < 0)
4081 tx_delay = 0;
4082
4083 dev->ports[port_num].rgmii_rx_val = rx_delay;
4084 dev->ports[port_num].rgmii_tx_val = tx_delay;
4085 }
4086
4087 /**
4088 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding
4089 * register value.
4090 * @array: The array of drive strength values to search.
4091 * @array_size: The size of the array.
4092 * @microamp: The drive strength value in microamp to be converted.
4093 *
4094 * This function searches the array of drive strength values for the given
4095 * microamp value and returns the corresponding register value for that drive.
4096 *
4097 * Returns: If found, the corresponding register value for that drive strength
4098 * is returned. Otherwise, -EINVAL is returned indicating an invalid value.
4099 */
ksz_drive_strength_to_reg(const struct ksz_drive_strength * array,size_t array_size,int microamp)4100 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array,
4101 size_t array_size, int microamp)
4102 {
4103 int i;
4104
4105 for (i = 0; i < array_size; i++) {
4106 if (array[i].microamp == microamp)
4107 return array[i].reg_val;
4108 }
4109
4110 return -EINVAL;
4111 }
4112
4113 /**
4114 * ksz_drive_strength_error() - Report invalid drive strength value
4115 * @dev: ksz device
4116 * @array: The array of drive strength values to search.
4117 * @array_size: The size of the array.
4118 * @microamp: Invalid drive strength value in microamp
4119 *
4120 * This function logs an error message when an unsupported drive strength value
4121 * is detected. It lists out all the supported drive strength values for
4122 * reference in the error message.
4123 */
ksz_drive_strength_error(struct ksz_device * dev,const struct ksz_drive_strength * array,size_t array_size,int microamp)4124 static void ksz_drive_strength_error(struct ksz_device *dev,
4125 const struct ksz_drive_strength *array,
4126 size_t array_size, int microamp)
4127 {
4128 char supported_values[100];
4129 size_t remaining_size;
4130 int added_len;
4131 char *ptr;
4132 int i;
4133
4134 remaining_size = sizeof(supported_values);
4135 ptr = supported_values;
4136
4137 for (i = 0; i < array_size; i++) {
4138 added_len = snprintf(ptr, remaining_size,
4139 i == 0 ? "%d" : ", %d", array[i].microamp);
4140
4141 if (added_len >= remaining_size)
4142 break;
4143
4144 ptr += added_len;
4145 remaining_size -= added_len;
4146 }
4147
4148 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n",
4149 microamp, supported_values);
4150 }
4151
4152 /**
4153 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477
4154 * chip variants.
4155 * @dev: ksz device
4156 * @props: Array of drive strength properties to be applied
4157 * @num_props: Number of properties in the array
4158 *
4159 * This function configures the drive strength for various KSZ9477 chip variants
4160 * based on the provided properties. It handles chip-specific nuances and
4161 * ensures only valid drive strengths are written to the respective chip.
4162 *
4163 * Return: 0 on successful configuration, a negative error code on failure.
4164 */
ksz9477_drive_strength_write(struct ksz_device * dev,struct ksz_driver_strength_prop * props,int num_props)4165 static int ksz9477_drive_strength_write(struct ksz_device *dev,
4166 struct ksz_driver_strength_prop *props,
4167 int num_props)
4168 {
4169 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths);
4170 int i, ret, reg;
4171 u8 mask = 0;
4172 u8 val = 0;
4173
4174 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1)
4175 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4176 props[KSZ_DRIVER_STRENGTH_IO].name);
4177
4178 if (dev->chip_id == KSZ8795_CHIP_ID ||
4179 dev->chip_id == KSZ8794_CHIP_ID ||
4180 dev->chip_id == KSZ8765_CHIP_ID)
4181 reg = KSZ8795_REG_SW_CTRL_20;
4182 else
4183 reg = KSZ9477_REG_SW_IO_STRENGTH;
4184
4185 for (i = 0; i < num_props; i++) {
4186 if (props[i].value == -1)
4187 continue;
4188
4189 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths,
4190 array_size, props[i].value);
4191 if (ret < 0) {
4192 ksz_drive_strength_error(dev, ksz9477_drive_strengths,
4193 array_size, props[i].value);
4194 return ret;
4195 }
4196
4197 mask |= SW_DRIVE_STRENGTH_M << props[i].offset;
4198 val |= ret << props[i].offset;
4199 }
4200
4201 return ksz_rmw8(dev, reg, mask, val);
4202 }
4203
4204 /**
4205 * ksz8830_drive_strength_write() - Set the drive strength configuration for
4206 * KSZ8830 compatible chip variants.
4207 * @dev: ksz device
4208 * @props: Array of drive strength properties to be set
4209 * @num_props: Number of properties in the array
4210 *
4211 * This function applies the specified drive strength settings to KSZ8830 chip
4212 * variants (KSZ8873, KSZ8863).
4213 * It ensures the configurations align with what the chip variant supports and
4214 * warns or errors out on unsupported settings.
4215 *
4216 * Return: 0 on success, error code otherwise
4217 */
ksz8830_drive_strength_write(struct ksz_device * dev,struct ksz_driver_strength_prop * props,int num_props)4218 static int ksz8830_drive_strength_write(struct ksz_device *dev,
4219 struct ksz_driver_strength_prop *props,
4220 int num_props)
4221 {
4222 size_t array_size = ARRAY_SIZE(ksz8830_drive_strengths);
4223 int microamp;
4224 int i, ret;
4225
4226 for (i = 0; i < num_props; i++) {
4227 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO)
4228 continue;
4229
4230 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4231 props[i].name);
4232 }
4233
4234 microamp = props[KSZ_DRIVER_STRENGTH_IO].value;
4235 ret = ksz_drive_strength_to_reg(ksz8830_drive_strengths, array_size,
4236 microamp);
4237 if (ret < 0) {
4238 ksz_drive_strength_error(dev, ksz8830_drive_strengths,
4239 array_size, microamp);
4240 return ret;
4241 }
4242
4243 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12,
4244 KSZ8873_DRIVE_STRENGTH_16MA, ret);
4245 }
4246
4247 /**
4248 * ksz_parse_drive_strength() - Extract and apply drive strength configurations
4249 * from device tree properties.
4250 * @dev: ksz device
4251 *
4252 * This function reads the specified drive strength properties from the
4253 * device tree, validates against the supported chip variants, and sets
4254 * them accordingly. An error should be critical here, as the drive strength
4255 * settings are crucial for EMI compliance.
4256 *
4257 * Return: 0 on success, error code otherwise
4258 */
ksz_parse_drive_strength(struct ksz_device * dev)4259 static int ksz_parse_drive_strength(struct ksz_device *dev)
4260 {
4261 struct ksz_driver_strength_prop of_props[] = {
4262 [KSZ_DRIVER_STRENGTH_HI] = {
4263 .name = "microchip,hi-drive-strength-microamp",
4264 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S,
4265 .value = -1,
4266 },
4267 [KSZ_DRIVER_STRENGTH_LO] = {
4268 .name = "microchip,lo-drive-strength-microamp",
4269 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S,
4270 .value = -1,
4271 },
4272 [KSZ_DRIVER_STRENGTH_IO] = {
4273 .name = "microchip,io-drive-strength-microamp",
4274 .offset = 0, /* don't care */
4275 .value = -1,
4276 },
4277 };
4278 struct device_node *np = dev->dev->of_node;
4279 bool have_any_prop = false;
4280 int i, ret;
4281
4282 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
4283 ret = of_property_read_u32(np, of_props[i].name,
4284 &of_props[i].value);
4285 if (ret && ret != -EINVAL)
4286 dev_warn(dev->dev, "Failed to read %s\n",
4287 of_props[i].name);
4288 if (ret)
4289 continue;
4290
4291 have_any_prop = true;
4292 }
4293
4294 if (!have_any_prop)
4295 return 0;
4296
4297 switch (dev->chip_id) {
4298 case KSZ8830_CHIP_ID:
4299 return ksz8830_drive_strength_write(dev, of_props,
4300 ARRAY_SIZE(of_props));
4301 case KSZ8795_CHIP_ID:
4302 case KSZ8794_CHIP_ID:
4303 case KSZ8765_CHIP_ID:
4304 case KSZ8563_CHIP_ID:
4305 case KSZ8567_CHIP_ID:
4306 case KSZ9477_CHIP_ID:
4307 case KSZ9563_CHIP_ID:
4308 case KSZ9567_CHIP_ID:
4309 case KSZ9893_CHIP_ID:
4310 case KSZ9896_CHIP_ID:
4311 case KSZ9897_CHIP_ID:
4312 return ksz9477_drive_strength_write(dev, of_props,
4313 ARRAY_SIZE(of_props));
4314 default:
4315 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
4316 if (of_props[i].value == -1)
4317 continue;
4318
4319 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4320 of_props[i].name);
4321 }
4322 }
4323
4324 return 0;
4325 }
4326
ksz_switch_register(struct ksz_device * dev)4327 int ksz_switch_register(struct ksz_device *dev)
4328 {
4329 const struct ksz_chip_data *info;
4330 struct device_node *port, *ports;
4331 phy_interface_t interface;
4332 unsigned int port_num;
4333 int ret;
4334 int i;
4335
4336 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
4337 GPIOD_OUT_LOW);
4338 if (IS_ERR(dev->reset_gpio))
4339 return PTR_ERR(dev->reset_gpio);
4340
4341 if (dev->reset_gpio) {
4342 gpiod_set_value_cansleep(dev->reset_gpio, 1);
4343 usleep_range(10000, 12000);
4344 gpiod_set_value_cansleep(dev->reset_gpio, 0);
4345 msleep(100);
4346 }
4347
4348 mutex_init(&dev->dev_mutex);
4349 mutex_init(&dev->regmap_mutex);
4350 mutex_init(&dev->alu_mutex);
4351 mutex_init(&dev->vlan_mutex);
4352
4353 ret = ksz_switch_detect(dev);
4354 if (ret)
4355 return ret;
4356
4357 info = ksz_lookup_info(dev->chip_id);
4358 if (!info)
4359 return -ENODEV;
4360
4361 /* Update the compatible info with the probed one */
4362 dev->info = info;
4363
4364 dev_info(dev->dev, "found switch: %s, rev %i\n",
4365 dev->info->dev_name, dev->chip_rev);
4366
4367 ret = ksz_check_device_id(dev);
4368 if (ret)
4369 return ret;
4370
4371 dev->dev_ops = dev->info->ops;
4372
4373 ret = dev->dev_ops->init(dev);
4374 if (ret)
4375 return ret;
4376
4377 dev->ports = devm_kzalloc(dev->dev,
4378 dev->info->port_cnt * sizeof(struct ksz_port),
4379 GFP_KERNEL);
4380 if (!dev->ports)
4381 return -ENOMEM;
4382
4383 for (i = 0; i < dev->info->port_cnt; i++) {
4384 spin_lock_init(&dev->ports[i].mib.stats64_lock);
4385 mutex_init(&dev->ports[i].mib.cnt_mutex);
4386 dev->ports[i].mib.counters =
4387 devm_kzalloc(dev->dev,
4388 sizeof(u64) * (dev->info->mib_cnt + 1),
4389 GFP_KERNEL);
4390 if (!dev->ports[i].mib.counters)
4391 return -ENOMEM;
4392
4393 dev->ports[i].ksz_dev = dev;
4394 dev->ports[i].num = i;
4395 }
4396
4397 /* set the real number of ports */
4398 dev->ds->num_ports = dev->info->port_cnt;
4399
4400 /* set the phylink ops */
4401 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops;
4402
4403 /* Host port interface will be self detected, or specifically set in
4404 * device tree.
4405 */
4406 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
4407 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
4408 if (dev->dev->of_node) {
4409 ret = of_get_phy_mode(dev->dev->of_node, &interface);
4410 if (ret == 0)
4411 dev->compat_interface = interface;
4412 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
4413 if (!ports)
4414 ports = of_get_child_by_name(dev->dev->of_node, "ports");
4415 if (ports) {
4416 for_each_available_child_of_node(ports, port) {
4417 if (of_property_read_u32(port, "reg",
4418 &port_num))
4419 continue;
4420 if (!(dev->port_mask & BIT(port_num))) {
4421 of_node_put(port);
4422 of_node_put(ports);
4423 return -EINVAL;
4424 }
4425 of_get_phy_mode(port,
4426 &dev->ports[port_num].interface);
4427
4428 ksz_parse_rgmii_delay(dev, port_num, port);
4429 }
4430 of_node_put(ports);
4431 }
4432 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
4433 "microchip,synclko-125");
4434 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
4435 "microchip,synclko-disable");
4436 if (dev->synclko_125 && dev->synclko_disable) {
4437 dev_err(dev->dev, "inconsistent synclko settings\n");
4438 return -EINVAL;
4439 }
4440
4441 dev->wakeup_source = of_property_read_bool(dev->dev->of_node,
4442 "wakeup-source");
4443 }
4444
4445 ret = dsa_register_switch(dev->ds);
4446 if (ret) {
4447 dev->dev_ops->exit(dev);
4448 return ret;
4449 }
4450
4451 /* Read MIB counters every 30 seconds to avoid overflow. */
4452 dev->mib_read_interval = msecs_to_jiffies(5000);
4453
4454 /* Start the MIB timer. */
4455 schedule_delayed_work(&dev->mib_read, 0);
4456
4457 return ret;
4458 }
4459 EXPORT_SYMBOL(ksz_switch_register);
4460
ksz_switch_remove(struct ksz_device * dev)4461 void ksz_switch_remove(struct ksz_device *dev)
4462 {
4463 /* timer started */
4464 if (dev->mib_read_interval) {
4465 dev->mib_read_interval = 0;
4466 cancel_delayed_work_sync(&dev->mib_read);
4467 }
4468
4469 dev->dev_ops->exit(dev);
4470 dsa_unregister_switch(dev->ds);
4471
4472 if (dev->reset_gpio)
4473 gpiod_set_value_cansleep(dev->reset_gpio, 1);
4474
4475 }
4476 EXPORT_SYMBOL(ksz_switch_remove);
4477
4478 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
4479 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
4480 MODULE_LICENSE("GPL");
4481