1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Monk.liu@amd.com
23 */
24 #ifndef AMDGPU_VIRT_H
25 #define AMDGPU_VIRT_H
26
27 #include "amdgv_sriovmsg.h"
28
29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */
31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */
32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
34 #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */
35
36 /* flags for indirect register access path supported by rlcg for sriov */
37 #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28)
38 #define AMDGPU_RLCG_GC_WRITE (0x0 << 28)
39 #define AMDGPU_RLCG_GC_READ (0x1 << 28)
40 #define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28)
41
42 /* error code for indirect register access path supported by rlcg for sriov */
43 #define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000
44 #define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000
45 #define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000
46
47 #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF
48 #define AMDGPU_RLCG_SCRATCH1_ERROR_MASK 0xF000000
49
50 /* all asic after AI use this offset */
51 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
52 /* tonga/fiji use this offset */
53 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
54
55 #define AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT 5
56
57 enum amdgpu_sriov_vf_mode {
58 SRIOV_VF_MODE_BARE_METAL = 0,
59 SRIOV_VF_MODE_ONE_VF,
60 SRIOV_VF_MODE_MULTI_VF,
61 };
62
63 struct amdgpu_mm_table {
64 struct amdgpu_bo *bo;
65 uint32_t *cpu_addr;
66 uint64_t gpu_addr;
67 };
68
69 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16
70
71 /* struct error_entry - amdgpu VF error information. */
72 struct amdgpu_vf_error_buffer {
73 struct mutex lock;
74 int read_count;
75 int write_count;
76 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
77 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
78 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
79 };
80
81 enum idh_request;
82
83 /**
84 * struct amdgpu_virt_ops - amdgpu device virt operations
85 */
86 struct amdgpu_virt_ops {
87 int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
88 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
89 int (*req_init_data)(struct amdgpu_device *adev);
90 int (*reset_gpu)(struct amdgpu_device *adev);
91 int (*wait_reset)(struct amdgpu_device *adev);
92 void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req,
93 u32 data1, u32 data2, u32 data3);
94 void (*ras_poison_handler)(struct amdgpu_device *adev,
95 enum amdgpu_ras_block block);
96 };
97
98 /*
99 * Firmware Reserve Frame buffer
100 */
101 struct amdgpu_virt_fw_reserve {
102 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
103 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
104 unsigned int checksum_key;
105 };
106
107 /*
108 * Legacy GIM header
109 *
110 * Defination between PF and VF
111 * Structures forcibly aligned to 4 to keep the same style as PF.
112 */
113 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024)
114
115 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
116 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
117
118 enum AMDGIM_FEATURE_FLAG {
119 /* GIM supports feature of Error log collecting */
120 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
121 /* GIM supports feature of loading uCodes */
122 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2,
123 /* VRAM LOST by GIM */
124 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
125 /* MM bandwidth */
126 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
127 /* PP ONE VF MODE in GIM */
128 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
129 /* Indirect Reg Access enabled */
130 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
131 /* AV1 Support MODE*/
132 AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6),
133 /* VCN RB decouple */
134 AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7),
135 /* MES info */
136 AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8),
137 };
138
139 enum AMDGIM_REG_ACCESS_FLAG {
140 /* Use PSP to program IH_RB_CNTL */
141 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
142 /* Use RLC to program MMHUB regs */
143 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1),
144 /* Use RLC to program GC regs */
145 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2),
146 };
147
148 struct amdgim_pf2vf_info_v1 {
149 /* header contains size and version */
150 struct amd_sriov_msg_pf2vf_info_header header;
151 /* max_width * max_height */
152 unsigned int uvd_enc_max_pixels_count;
153 /* 16x16 pixels/sec, codec independent */
154 unsigned int uvd_enc_max_bandwidth;
155 /* max_width * max_height */
156 unsigned int vce_enc_max_pixels_count;
157 /* 16x16 pixels/sec, codec independent */
158 unsigned int vce_enc_max_bandwidth;
159 /* MEC FW position in kb from the start of visible frame buffer */
160 unsigned int mecfw_kboffset;
161 /* The features flags of the GIM driver supports. */
162 unsigned int feature_flags;
163 /* use private key from mailbox 2 to create chueksum */
164 unsigned int checksum;
165 } __aligned(4);
166
167 struct amdgim_vf2pf_info_v1 {
168 /* header contains size and version */
169 struct amd_sriov_msg_vf2pf_info_header header;
170 /* driver version */
171 char driver_version[64];
172 /* driver certification, 1=WHQL, 0=None */
173 unsigned int driver_cert;
174 /* guest OS type and version: need a define */
175 unsigned int os_info;
176 /* in the unit of 1M */
177 unsigned int fb_usage;
178 /* guest gfx engine usage percentage */
179 unsigned int gfx_usage;
180 /* guest gfx engine health percentage */
181 unsigned int gfx_health;
182 /* guest compute engine usage percentage */
183 unsigned int compute_usage;
184 /* guest compute engine health percentage */
185 unsigned int compute_health;
186 /* guest vce engine usage percentage. 0xffff means N/A. */
187 unsigned int vce_enc_usage;
188 /* guest vce engine health percentage. 0xffff means N/A. */
189 unsigned int vce_enc_health;
190 /* guest uvd engine usage percentage. 0xffff means N/A. */
191 unsigned int uvd_enc_usage;
192 /* guest uvd engine usage percentage. 0xffff means N/A. */
193 unsigned int uvd_enc_health;
194 unsigned int checksum;
195 } __aligned(4);
196
197 struct amdgim_vf2pf_info_v2 {
198 /* header contains size and version */
199 struct amd_sriov_msg_vf2pf_info_header header;
200 uint32_t checksum;
201 /* driver version */
202 uint8_t driver_version[64];
203 /* driver certification, 1=WHQL, 0=None */
204 uint32_t driver_cert;
205 /* guest OS type and version: need a define */
206 uint32_t os_info;
207 /* in the unit of 1M */
208 uint32_t fb_usage;
209 /* guest gfx engine usage percentage */
210 uint32_t gfx_usage;
211 /* guest gfx engine health percentage */
212 uint32_t gfx_health;
213 /* guest compute engine usage percentage */
214 uint32_t compute_usage;
215 /* guest compute engine health percentage */
216 uint32_t compute_health;
217 /* guest vce engine usage percentage. 0xffff means N/A. */
218 uint32_t vce_enc_usage;
219 /* guest vce engine health percentage. 0xffff means N/A. */
220 uint32_t vce_enc_health;
221 /* guest uvd engine usage percentage. 0xffff means N/A. */
222 uint32_t uvd_enc_usage;
223 /* guest uvd engine usage percentage. 0xffff means N/A. */
224 uint32_t uvd_enc_health;
225 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
226 } __aligned(4);
227
228 struct amdgpu_virt_ras_err_handler_data {
229 /* point to bad page records array */
230 struct eeprom_table_record *bps;
231 /* point to reserved bo array */
232 struct amdgpu_bo **bps_bo;
233 /* the count of entries */
234 int count;
235 /* last reserved entry's index + 1 */
236 int last_reserved;
237 };
238
239 /* GPU virtualization */
240 struct amdgpu_virt {
241 uint32_t caps;
242 struct amdgpu_bo *csa_obj;
243 void *csa_cpu_addr;
244 bool chained_ib_support;
245 uint32_t reg_val_offs;
246 struct amdgpu_irq_src ack_irq;
247 struct amdgpu_irq_src rcv_irq;
248 struct work_struct flr_work;
249 struct amdgpu_mm_table mm_table;
250 const struct amdgpu_virt_ops *ops;
251 struct amdgpu_vf_error_buffer vf_errors;
252 struct amdgpu_virt_fw_reserve fw_reserve;
253 uint32_t gim_feature;
254 uint32_t reg_access_mode;
255 int req_init_data_ver;
256 bool tdr_debug;
257 struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
258 bool ras_init_done;
259 uint32_t reg_access;
260
261 /* vf2pf message */
262 struct delayed_work vf2pf_work;
263 uint32_t vf2pf_update_interval_ms;
264 int vf2pf_update_retry_cnt;
265
266 /* multimedia bandwidth config */
267 bool is_mm_bw_enabled;
268 uint32_t decode_max_dimension_pixels;
269 uint32_t decode_max_frame_pixels;
270 uint32_t encode_max_dimension_pixels;
271 uint32_t encode_max_frame_pixels;
272
273 /* the ucode id to signal the autoload */
274 uint32_t autoload_ucode_id;
275 };
276
277 struct amdgpu_video_codec_info;
278
279 #define amdgpu_sriov_enabled(adev) \
280 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
281
282 #define amdgpu_sriov_vf(adev) \
283 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
284
285 #define amdgpu_sriov_bios(adev) \
286 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
287
288 #define amdgpu_sriov_runtime(adev) \
289 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
290
291 #define amdgpu_sriov_fullaccess(adev) \
292 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
293
294 #define amdgpu_sriov_reg_indirect_en(adev) \
295 (amdgpu_sriov_vf((adev)) && \
296 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS)))
297
298 #define amdgpu_sriov_reg_indirect_ih(adev) \
299 (amdgpu_sriov_vf((adev)) && \
300 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN)))
301
302 #define amdgpu_sriov_reg_indirect_mmhub(adev) \
303 (amdgpu_sriov_vf((adev)) && \
304 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN)))
305
306 #define amdgpu_sriov_reg_indirect_gc(adev) \
307 (amdgpu_sriov_vf((adev)) && \
308 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))
309
310 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \
311 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
312
313 #define amdgpu_passthrough(adev) \
314 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
315
316 #define amdgpu_sriov_vf_mmio_access_protection(adev) \
317 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)
318
is_virtual_machine(void)319 static inline bool is_virtual_machine(void)
320 {
321 #if defined(CONFIG_X86)
322 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
323 #elif defined(CONFIG_ARM64)
324 return !is_kernel_in_hyp_mode();
325 #else
326 return false;
327 #endif
328 }
329
330 #define amdgpu_sriov_is_pp_one_vf(adev) \
331 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
332 #define amdgpu_sriov_is_debug(adev) \
333 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
334 #define amdgpu_sriov_is_normal(adev) \
335 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
336 #define amdgpu_sriov_is_av1_support(adev) \
337 ((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT)
338 #define amdgpu_sriov_is_vcn_rb_decouple(adev) \
339 ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE)
340 #define amdgpu_sriov_is_mes_info_enable(adev) \
341 ((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE)
342 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
343 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
344 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
345 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
346 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
347 void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
348 int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
349 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
350 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
351 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
352 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
353 void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
354 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
355 void amdgpu_detect_virtualization(struct amdgpu_device *adev);
356
357 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
358 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
359 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
360
361 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
362
363 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
364 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
365 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);
366 void amdgpu_sriov_wreg(struct amdgpu_device *adev,
367 u32 offset, u32 value,
368 u32 acc_flags, u32 hwip, u32 xcc_id);
369 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
370 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);
371 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
372 uint32_t ucode_id);
373 void amdgpu_virt_post_reset(struct amdgpu_device *adev);
374 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev);
375 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
376 u32 acc_flags, u32 hwip,
377 bool write, u32 *rlcg_flag);
378 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id);
379 #endif
380