1 /* $OpenBSD: if_iwm.c,v 1.39 2015/03/23 00:35:19 jsg Exp $ */
2
3 /*
4 * Copyright (c) 2014 genua mbh <info@genua.de>
5 * Copyright (c) 2014 Fixup Software Ltd.
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 /*-
21 * Based on BSD-licensed source modules in the Linux iwlwifi driver,
22 * which were used as the reference documentation for this implementation.
23 *
24 * Driver version we are currently based off of is
25 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd)
26 *
27 ***********************************************************************
28 *
29 * This file is provided under a dual BSD/GPLv2 license. When using or
30 * redistributing this file, you may do so under either license.
31 *
32 * GPL LICENSE SUMMARY
33 *
34 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
35 *
36 * This program is free software; you can redistribute it and/or modify
37 * it under the terms of version 2 of the GNU General Public License as
38 * published by the Free Software Foundation.
39 *
40 * This program is distributed in the hope that it will be useful, but
41 * WITHOUT ANY WARRANTY; without even the implied warranty of
42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
43 * General Public License for more details.
44 *
45 * You should have received a copy of the GNU General Public License
46 * along with this program; if not, write to the Free Software
47 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
48 * USA
49 *
50 * The full GNU General Public License is included in this distribution
51 * in the file called COPYING.
52 *
53 * Contact Information:
54 * Intel Linux Wireless <ilw@linux.intel.com>
55 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
56 *
57 *
58 * BSD LICENSE
59 *
60 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
61 * All rights reserved.
62 *
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
65 * are met:
66 *
67 * * Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * * Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in
71 * the documentation and/or other materials provided with the
72 * distribution.
73 * * Neither the name Intel Corporation nor the names of its
74 * contributors may be used to endorse or promote products derived
75 * from this software without specific prior written permission.
76 *
77 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
78 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
79 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
80 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
81 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
82 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
83 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
84 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
85 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
86 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
88 */
89
90 /*-
91 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
92 *
93 * Permission to use, copy, modify, and distribute this software for any
94 * purpose with or without fee is hereby granted, provided that the above
95 * copyright notice and this permission notice appear in all copies.
96 *
97 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
98 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
99 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
100 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
101 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
102 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
103 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
104 */
105 #include <sys/param.h>
106 #include <sys/bus.h>
107 #include <sys/conf.h>
108 #include <sys/endian.h>
109 #include <sys/firmware.h>
110 #include <sys/kernel.h>
111 #include <sys/malloc.h>
112 #include <sys/mbuf.h>
113 #include <sys/rman.h>
114 #include <sys/sysctl.h>
115 #include <sys/linker.h>
116
117 #include <machine/endian.h>
118
119 #include <bus/pci/pcivar.h>
120 #include <bus/pci/pcireg.h>
121
122 #include <net/bpf.h>
123
124 #include <net/if.h>
125 #include <net/if_var.h>
126 #include <net/if_arp.h>
127 #include <net/if_dl.h>
128 #include <net/if_media.h>
129 #include <net/if_types.h>
130
131 #include <netinet/in.h>
132 #include <netinet/in_systm.h>
133 #include <netinet/if_ether.h>
134 #include <netinet/ip.h>
135
136 #include <netproto/802_11/ieee80211_var.h>
137 #include <netproto/802_11/ieee80211_regdomain.h>
138 #include <netproto/802_11/ieee80211_ratectl.h>
139 #include <netproto/802_11/ieee80211_radiotap.h>
140
141 #include "if_iwmreg.h"
142 #include "if_iwmvar.h"
143 #include "if_iwm_config.h"
144 #include "if_iwm_debug.h"
145 #include "if_iwm_pcie_trans.h"
146
147 /*
148 * This is a subset of what's in linux iwlwifi/pcie/trans.c.
149 * The rest can be migrated out into here once they're no longer in
150 * if_iwm.c.
151 */
152
153 /*
154 * basic device access
155 */
156
157 uint32_t
iwm_read_prph(struct iwm_softc * sc,uint32_t addr)158 iwm_read_prph(struct iwm_softc *sc, uint32_t addr)
159 {
160 IWM_WRITE(sc,
161 IWM_HBUS_TARG_PRPH_RADDR, ((addr & 0x000fffff) | (3 << 24)));
162 IWM_BARRIER_READ_WRITE(sc);
163 return IWM_READ(sc, IWM_HBUS_TARG_PRPH_RDAT);
164 }
165
166 void
iwm_write_prph(struct iwm_softc * sc,uint32_t addr,uint32_t val)167 iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val)
168 {
169 IWM_WRITE(sc,
170 IWM_HBUS_TARG_PRPH_WADDR, ((addr & 0x000fffff) | (3 << 24)));
171 IWM_BARRIER_WRITE(sc);
172 IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val);
173 }
174
175 void
iwm_write_prph64(struct iwm_softc * sc,uint64_t addr,uint64_t val)176 iwm_write_prph64(struct iwm_softc *sc, uint64_t addr, uint64_t val)
177 {
178 iwm_write_prph(sc, (uint32_t)addr, val & 0xffffffff);
179 iwm_write_prph(sc, (uint32_t)addr + 4, val >> 32);
180 }
181
182 int
iwm_poll_prph(struct iwm_softc * sc,uint32_t addr,uint32_t bits,uint32_t mask,int timeout)183 iwm_poll_prph(struct iwm_softc *sc, uint32_t addr, uint32_t bits, uint32_t mask,
184 int timeout)
185 {
186 do {
187 if ((iwm_read_prph(sc, addr) & mask) == (bits & mask))
188 return (0);
189 DELAY(10);
190 timeout -= 10;
191 } while (timeout > 0);
192
193 return (ETIMEDOUT);
194 }
195
196 #ifdef IWM_DEBUG
197 /* iwlwifi: pcie/trans.c */
198 int
iwm_read_mem(struct iwm_softc * sc,uint32_t addr,void * buf,int dwords)199 iwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords)
200 {
201 int offs, ret = 0;
202 uint32_t *vals = buf;
203
204 if (iwm_nic_lock(sc)) {
205 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_RADDR, addr);
206 for (offs = 0; offs < dwords; offs++)
207 vals[offs] = IWM_READ(sc, IWM_HBUS_TARG_MEM_RDAT);
208 iwm_nic_unlock(sc);
209 } else {
210 ret = EBUSY;
211 }
212 return ret;
213 }
214 #endif
215
216 /* iwlwifi: pcie/trans.c */
217 int
iwm_write_mem(struct iwm_softc * sc,uint32_t addr,const void * buf,int dwords)218 iwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords)
219 {
220 int offs;
221 const uint32_t *vals = buf;
222
223 if (iwm_nic_lock(sc)) {
224 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WADDR, addr);
225 /* WADDR auto-increments */
226 for (offs = 0; offs < dwords; offs++) {
227 uint32_t val = vals ? vals[offs] : 0;
228 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val);
229 }
230 iwm_nic_unlock(sc);
231 } else {
232 IWM_DPRINTF(sc, IWM_DEBUG_TRANS,
233 "%s: write_mem failed\n", __func__);
234 return EBUSY;
235 }
236 return 0;
237 }
238
239 int
iwm_write_mem32(struct iwm_softc * sc,uint32_t addr,uint32_t val)240 iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val)
241 {
242 return iwm_write_mem(sc, addr, &val, 1);
243 }
244
245 int
iwm_poll_bit(struct iwm_softc * sc,int reg,uint32_t bits,uint32_t mask,int timo)246 iwm_poll_bit(struct iwm_softc *sc, int reg,
247 uint32_t bits, uint32_t mask, int timo)
248 {
249 for (;;) {
250 if ((IWM_READ(sc, reg) & mask) == (bits & mask)) {
251 return 1;
252 }
253 if (timo < 10) {
254 return 0;
255 }
256 timo -= 10;
257 DELAY(10);
258 }
259 }
260
261 int
iwm_nic_lock(struct iwm_softc * sc)262 iwm_nic_lock(struct iwm_softc *sc)
263 {
264 int rv = 0;
265
266 if (sc->cmd_hold_nic_awake)
267 return 1;
268
269 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL,
270 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
271
272 if (sc->cfg->device_family >= IWM_DEVICE_FAMILY_8000)
273 DELAY(2);
274
275 if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL,
276 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
277 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
278 | IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) {
279 rv = 1;
280 } else {
281 /* jolt */
282 IWM_DPRINTF(sc, IWM_DEBUG_RESET,
283 "%s: resetting device via NMI\n", __func__);
284 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI);
285 }
286
287 return rv;
288 }
289
290 void
iwm_nic_unlock(struct iwm_softc * sc)291 iwm_nic_unlock(struct iwm_softc *sc)
292 {
293 if (sc->cmd_hold_nic_awake)
294 return;
295
296 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
297 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
298 }
299
300 void
iwm_set_bits_mask_prph(struct iwm_softc * sc,uint32_t reg,uint32_t bits,uint32_t mask)301 iwm_set_bits_mask_prph(struct iwm_softc *sc,
302 uint32_t reg, uint32_t bits, uint32_t mask)
303 {
304 uint32_t val;
305
306 /* XXX: no error path? */
307 if (iwm_nic_lock(sc)) {
308 val = iwm_read_prph(sc, reg) & mask;
309 val |= bits;
310 iwm_write_prph(sc, reg, val);
311 iwm_nic_unlock(sc);
312 }
313 }
314
315 void
iwm_set_bits_prph(struct iwm_softc * sc,uint32_t reg,uint32_t bits)316 iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)
317 {
318 iwm_set_bits_mask_prph(sc, reg, bits, ~0);
319 }
320
321 void
iwm_clear_bits_prph(struct iwm_softc * sc,uint32_t reg,uint32_t bits)322 iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)
323 {
324 iwm_set_bits_mask_prph(sc, reg, 0, ~bits);
325 }
326
327 /*
328 * High-level hardware frobbing routines
329 */
330
331 void
iwm_enable_rfkill_int(struct iwm_softc * sc)332 iwm_enable_rfkill_int(struct iwm_softc *sc)
333 {
334 sc->sc_intmask = IWM_CSR_INT_BIT_RF_KILL;
335 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask);
336 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL,
337 IWM_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);
338 }
339
340 int
iwm_check_rfkill(struct iwm_softc * sc)341 iwm_check_rfkill(struct iwm_softc *sc)
342 {
343 uint32_t v;
344 int rv;
345
346 /*
347 * "documentation" is not really helpful here:
348 * 27: HW_RF_KILL_SW
349 * Indicates state of (platform's) hardware RF-Kill switch
350 *
351 * But apparently when it's off, it's on ...
352 */
353 v = IWM_READ(sc, IWM_CSR_GP_CNTRL);
354 rv = (v & IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) == 0;
355 if (rv) {
356 sc->sc_flags |= IWM_FLAG_RFKILL;
357 } else {
358 sc->sc_flags &= ~IWM_FLAG_RFKILL;
359 }
360
361 return rv;
362 }
363
364
365 #define IWM_HW_READY_TIMEOUT 50
366 int
iwm_set_hw_ready(struct iwm_softc * sc)367 iwm_set_hw_ready(struct iwm_softc *sc)
368 {
369 int ready;
370
371 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG,
372 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
373
374 ready = iwm_poll_bit(sc, IWM_CSR_HW_IF_CONFIG_REG,
375 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
376 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
377 IWM_HW_READY_TIMEOUT);
378 if (ready) {
379 IWM_SETBITS(sc, IWM_CSR_MBOX_SET_REG,
380 IWM_CSR_MBOX_SET_REG_OS_ALIVE);
381 }
382 return ready;
383 }
384 #undef IWM_HW_READY_TIMEOUT
385
386 int
iwm_prepare_card_hw(struct iwm_softc * sc)387 iwm_prepare_card_hw(struct iwm_softc *sc)
388 {
389 int rv = 0;
390 int t = 0;
391
392 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "->%s\n", __func__);
393 if (iwm_set_hw_ready(sc))
394 goto out;
395
396 IWM_SETBITS(sc, IWM_CSR_DBG_LINK_PWR_MGMT_REG,
397 IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED);
398 DELAY(1000);
399
400 /* If HW is not ready, prepare the conditions to check again */
401 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG,
402 IWM_CSR_HW_IF_CONFIG_REG_PREPARE);
403
404 do {
405 if (iwm_set_hw_ready(sc))
406 goto out;
407 DELAY(200);
408 t += 200;
409 } while (t < 150000);
410
411 rv = ETIMEDOUT;
412
413 out:
414 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "<-%s\n", __func__);
415 return rv;
416 }
417
418 void
iwm_apm_config(struct iwm_softc * sc)419 iwm_apm_config(struct iwm_softc *sc)
420 {
421 uint16_t lctl, cap;
422 int pcie_ptr;
423
424 /*
425 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
426 * Check if BIOS (or OS) enabled L1-ASPM on this device.
427 * If so (likely), disable L0S, so device moves directly L0->L1;
428 * costs negligible amount of power savings.
429 * If not (unlikely), enable L0S, so there is at least some
430 * power savings, even without L1.
431 */
432 #if !defined(__DragonFly__)
433 int error;
434
435 error = pci_find_cap(sc->sc_dev, PCIY_EXPRESS, &pcie_ptr);
436 if (error != 0)
437 return;
438 lctl = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_LINK_CTL,
439 sizeof(lctl));
440 if (lctl & PCIEM_LINK_CTL_ASPMC_L1) {
441 #else
442 pcie_ptr = pci_get_pciecap_ptr(sc->sc_dev);
443 if (pcie_ptr == 0)
444 return;
445 lctl = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_LINKCTRL,
446 sizeof(lctl));
447 if (lctl & PCIEM_LNKCTL_ASPM_L1) {
448 #endif
449 IWM_SETBITS(sc, IWM_CSR_GIO_REG,
450 IWM_CSR_GIO_REG_VAL_L0S_ENABLED);
451 } else {
452 IWM_CLRBITS(sc, IWM_CSR_GIO_REG,
453 IWM_CSR_GIO_REG_VAL_L0S_ENABLED);
454 }
455
456 #if !defined(__DragonFly__)
457 cap = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_DEVICE_CTL2,
458 sizeof(cap));
459 sc->sc_ltr_enabled = (cap & PCIEM_CTL2_LTR_ENABLE) ? 1 : 0;
460 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_PWRSAVE,
461 "L1 %sabled - LTR %sabled\n",
462 (lctl & PCIEM_LINK_CTL_ASPMC_L1) ? "En" : "Dis",
463 sc->sc_ltr_enabled ? "En" : "Dis");
464 #else
465 cap = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_DEVCTRL2,
466 sizeof(cap));
467 sc->sc_ltr_enabled = (cap & PCIEM_DEVCTL2_LTR_ENABLE) ? 1 : 0;
468 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_PWRSAVE,
469 "L1 %sabled - LTR %sabled\n",
470 (lctl & PCIEM_LNKCTL_ASPM_L1) ? "En" : "Dis",
471 sc->sc_ltr_enabled ? "En" : "Dis");
472 #endif
473 }
474
475 /*
476 * Start up NIC's basic functionality after it has been reset
477 * (e.g. after platform boot, or shutdown via iwm_pcie_apm_stop())
478 * NOTE: This does not load uCode nor start the embedded processor
479 */
480 int
481 iwm_apm_init(struct iwm_softc *sc)
482 {
483 int error = 0;
484
485 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "iwm apm start\n");
486
487 /* Disable L0S exit timer (platform NMI Work/Around) */
488 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) {
489 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS,
490 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
491 }
492
493 /*
494 * Disable L0s without affecting L1;
495 * don't wait for ICH L0s (ICH bug W/A)
496 */
497 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS,
498 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
499
500 /* Set FH wait threshold to maximum (HW error during stress W/A) */
501 IWM_SETBITS(sc, IWM_CSR_DBG_HPET_MEM_REG, IWM_CSR_DBG_HPET_MEM_REG_VAL);
502
503 /*
504 * Enable HAP INTA (interrupt from management bus) to
505 * wake device's PCI Express link L1a -> L0s
506 */
507 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG,
508 IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
509
510 iwm_apm_config(sc);
511
512 #if 0 /* not for 7k/8k */
513 /* Configure analog phase-lock-loop before activating to D0A */
514 if (trans->cfg->base_params->pll_cfg_val)
515 IWM_SETBITS(trans, IWM_CSR_ANA_PLL_CFG,
516 trans->cfg->base_params->pll_cfg_val);
517 #endif
518
519 /*
520 * Set "initialization complete" bit to move adapter from
521 * D0U* --> D0A* (powered-up active) state.
522 */
523 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
524
525 /*
526 * Wait for clock stabilization; once stabilized, access to
527 * device-internal resources is supported, e.g. iwm_write_prph()
528 * and accesses to uCode SRAM.
529 */
530 if (!iwm_poll_bit(sc, IWM_CSR_GP_CNTRL,
531 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
532 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000)) {
533 device_printf(sc->sc_dev,
534 "timeout waiting for clock stabilization\n");
535 error = ETIMEDOUT;
536 goto out;
537 }
538
539 if (sc->cfg->host_interrupt_operation_mode) {
540 /*
541 * This is a bit of an abuse - This is needed for 7260 / 3160
542 * only check host_interrupt_operation_mode even if this is
543 * not related to host_interrupt_operation_mode.
544 *
545 * Enable the oscillator to count wake up time for L1 exit. This
546 * consumes slightly more power (100uA) - but allows to be sure
547 * that we wake up from L1 on time.
548 *
549 * This looks weird: read twice the same register, discard the
550 * value, set a bit, and yet again, read that same register
551 * just to discard the value. But that's the way the hardware
552 * seems to like it.
553 */
554 if (iwm_nic_lock(sc)) {
555 iwm_read_prph(sc, IWM_OSC_CLK);
556 iwm_read_prph(sc, IWM_OSC_CLK);
557 iwm_nic_unlock(sc);
558 }
559 iwm_set_bits_prph(sc, IWM_OSC_CLK, IWM_OSC_CLK_FORCE_CONTROL);
560 if (iwm_nic_lock(sc)) {
561 iwm_read_prph(sc, IWM_OSC_CLK);
562 iwm_read_prph(sc, IWM_OSC_CLK);
563 iwm_nic_unlock(sc);
564 }
565 }
566
567 /*
568 * Enable DMA clock and wait for it to stabilize.
569 *
570 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
571 * do not disable clocks. This preserves any hardware bits already
572 * set by default in "CLK_CTRL_REG" after reset.
573 */
574 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) {
575 if (iwm_nic_lock(sc)) {
576 iwm_write_prph(sc, IWM_APMG_CLK_EN_REG,
577 IWM_APMG_CLK_VAL_DMA_CLK_RQT);
578 iwm_nic_unlock(sc);
579 }
580 DELAY(20);
581
582 /* Disable L1-Active */
583 iwm_set_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG,
584 IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
585
586 /* Clear the interrupt in APMG if the NIC is in RFKILL */
587 if (iwm_nic_lock(sc)) {
588 iwm_write_prph(sc, IWM_APMG_RTC_INT_STT_REG,
589 IWM_APMG_RTC_INT_STT_RFKILL);
590 iwm_nic_unlock(sc);
591 }
592 }
593 out:
594 if (error)
595 device_printf(sc->sc_dev, "apm init error %d\n", error);
596 return error;
597 }
598
599 /* iwlwifi/pcie/trans.c */
600 void
601 iwm_apm_stop(struct iwm_softc *sc)
602 {
603 IWM_SETBITS(sc, IWM_CSR_DBG_LINK_PWR_MGMT_REG,
604 IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED);
605 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG,
606 IWM_CSR_HW_IF_CONFIG_REG_PREPARE |
607 IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME);
608 DELAY(1000);
609 IWM_CLRBITS(sc, IWM_CSR_DBG_LINK_PWR_MGMT_REG,
610 IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED);
611 DELAY(5000);
612
613 /* stop device's busmaster DMA activity */
614 IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_STOP_MASTER);
615
616 if (!iwm_poll_bit(sc, IWM_CSR_RESET,
617 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED,
618 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 100))
619 device_printf(sc->sc_dev, "timeout waiting for master\n");
620
621 /*
622 * Clear "initialization complete" bit to move adapter from
623 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
624 */
625 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
626 IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
627
628 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, "%s: iwm apm stop\n", __func__);
629 }
630
631 /* iwlwifi pcie/trans.c */
632 int
633 iwm_start_hw(struct iwm_softc *sc)
634 {
635 int error;
636
637 if ((error = iwm_prepare_card_hw(sc)) != 0)
638 return error;
639
640 /* Reset the entire device */
641 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET);
642 DELAY(5000);
643
644 if ((error = iwm_apm_init(sc)) != 0)
645 return error;
646
647 /* On newer chipsets MSI is disabled by default. */
648 if (sc->cfg->mqrx_supported)
649 iwm_write_prph(sc, IWM_UREG_CHICK, IWM_UREG_CHICK_MSI_ENABLE);
650
651 iwm_enable_rfkill_int(sc);
652 iwm_check_rfkill(sc);
653
654 return 0;
655 }
656
657 /* iwlwifi pcie/trans.c (always main power) */
658 void
659 iwm_set_pwr(struct iwm_softc *sc)
660 {
661 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG,
662 IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, ~IWM_APMG_PS_CTRL_MSK_PWR_SRC);
663 }
664
665 /* iwlwifi pcie/rx.c */
666 int
667 iwm_pcie_rx_stop(struct iwm_softc *sc)
668 {
669 int ret;
670
671 ret = 0;
672 if (iwm_nic_lock(sc)) {
673 if (sc->cfg->mqrx_supported) {
674 iwm_write_prph(sc, IWM_RFH_RXF_DMA_CFG, 0);
675 ret = iwm_poll_prph(sc, IWM_RFH_GEN_STATUS,
676 IWM_RXF_DMA_IDLE, IWM_RXF_DMA_IDLE, 1000);
677 } else {
678 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
679 ret = iwm_poll_bit(sc, IWM_FH_MEM_RSSR_RX_STATUS_REG,
680 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
681 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
682 1000);
683 }
684 iwm_nic_unlock(sc);
685 }
686 return ret;
687 }
688
689 void
690 iwm_pcie_clear_cmd_in_flight(struct iwm_softc *sc)
691 {
692 if (!sc->cfg->apmg_wake_up_wa)
693 return;
694
695 if (!sc->cmd_hold_nic_awake) {
696 device_printf(sc->sc_dev,
697 "%s: cmd_hold_nic_awake not set\n", __func__);
698 return;
699 }
700
701 sc->cmd_hold_nic_awake = 0;
702 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
703 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
704 }
705
706 int
707 iwm_pcie_set_cmd_in_flight(struct iwm_softc *sc)
708 {
709 int ret;
710
711 /*
712 * wake up the NIC to make sure that the firmware will see the host
713 * command - we will let the NIC sleep once all the host commands
714 * returned. This needs to be done only on NICs that have
715 * apmg_wake_up_wa set.
716 */
717 if (sc->cfg->apmg_wake_up_wa &&
718 !sc->cmd_hold_nic_awake) {
719
720 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL,
721 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
722
723 ret = iwm_poll_bit(sc, IWM_CSR_GP_CNTRL,
724 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
725 (IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
726 IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
727 15000);
728 if (ret == 0) {
729 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
730 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
731 device_printf(sc->sc_dev,
732 "%s: Failed to wake NIC for hcmd\n", __func__);
733 return EIO;
734 }
735 sc->cmd_hold_nic_awake = 1;
736 }
737
738 return 0;
739 }
740