1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #include "mpc.h" 37 #include "dwb.h" 38 #include "mcif_wb.h" 39 #include "panel_cntl.h" 40 #include "dmub/inc/dmub_cmd.h" 41 #include "pg_cntl.h" 42 43 #define MAX_CLOCK_SOURCES 7 44 #define MAX_SVP_PHANTOM_STREAMS 2 45 #define MAX_SVP_PHANTOM_PLANES 2 46 47 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 48 uint32_t controller_id); 49 50 #include "grph_object_id.h" 51 #include "link_encoder.h" 52 #include "stream_encoder.h" 53 #include "clock_source.h" 54 #include "audio.h" 55 #include "dm_pp_smu.h" 56 #include "dm_cp_psp.h" 57 #include "link_hwss.h" 58 59 /********** DAL Core*********************/ 60 #include "transform.h" 61 #include "dpp.h" 62 63 struct resource_pool; 64 struct dc_state; 65 struct resource_context; 66 struct clk_bw_params; 67 68 struct resource_funcs { 69 enum engine_id (*get_preferred_eng_id_dpia)(unsigned int dpia_index); 70 void (*destroy)(struct resource_pool **pool); 71 void (*link_init)(struct dc_link *link); 72 struct panel_cntl*(*panel_cntl_create)( 73 const struct panel_cntl_init_data *panel_cntl_init_data); 74 struct link_encoder *(*link_enc_create)( 75 struct dc_context *ctx, 76 const struct encoder_init_data *init); 77 /* Create a minimal link encoder object with no dc_link object 78 * associated with it. */ 79 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 80 81 bool (*validate_bandwidth)( 82 struct dc *dc, 83 struct dc_state *context, 84 bool fast_validate); 85 void (*calculate_wm_and_dlg)( 86 struct dc *dc, struct dc_state *context, 87 display_e2e_pipe_params_st *pipes, 88 int pipe_cnt, 89 int vlevel); 90 void (*update_soc_for_wm_a)( 91 struct dc *dc, struct dc_state *context); 92 93 unsigned int (*calculate_mall_ways_from_bytes)( 94 const struct dc *dc, 95 unsigned int total_size_in_mall_bytes); 96 /** 97 * @populate_dml_pipes - Populate pipe data struct 98 * 99 * Returns: 100 * Total of pipes available in the specific ASIC. 101 */ 102 int (*populate_dml_pipes)( 103 struct dc *dc, 104 struct dc_state *context, 105 display_e2e_pipe_params_st *pipes, 106 bool fast_validate); 107 108 /* 109 * Algorithm for assigning available link encoders to links. 110 * 111 * Update link_enc_assignments table and link_enc_avail list accordingly in 112 * struct resource_context. 113 */ 114 void (*link_encs_assign)( 115 struct dc *dc, 116 struct dc_state *state, 117 struct dc_stream_state *streams[], 118 uint8_t stream_count); 119 /* 120 * Unassign a link encoder from a stream. 121 * 122 * Update link_enc_assignments table and link_enc_avail list accordingly in 123 * struct resource_context. 124 */ 125 void (*link_enc_unassign)( 126 struct dc_state *state, 127 struct dc_stream_state *stream); 128 129 enum dc_status (*validate_global)( 130 struct dc *dc, 131 struct dc_state *context); 132 133 struct pipe_ctx *(*acquire_free_pipe_as_secondary_dpp_pipe)( 134 const struct dc_state *cur_ctx, 135 struct dc_state *new_ctx, 136 const struct resource_pool *pool, 137 const struct pipe_ctx *opp_head_pipe); 138 139 struct pipe_ctx *(*acquire_free_pipe_as_secondary_opp_head)( 140 const struct dc_state *cur_ctx, 141 struct dc_state *new_ctx, 142 const struct resource_pool *pool, 143 const struct pipe_ctx *otg_master); 144 145 void (*release_pipe)(struct dc_state *context, 146 struct pipe_ctx *pipe, 147 const struct resource_pool *pool); 148 149 enum dc_status (*validate_plane)( 150 const struct dc_plane_state *plane_state, 151 struct dc_caps *caps); 152 153 enum dc_status (*add_stream_to_ctx)( 154 struct dc *dc, 155 struct dc_state *new_ctx, 156 struct dc_stream_state *dc_stream); 157 158 enum dc_status (*remove_stream_from_ctx)( 159 struct dc *dc, 160 struct dc_state *new_ctx, 161 struct dc_stream_state *stream); 162 enum dc_status (*patch_unknown_plane_state)( 163 struct dc_plane_state *plane_state); 164 165 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 166 struct resource_context *res_ctx, 167 const struct resource_pool *pool, 168 struct dc_stream_state *stream); 169 void (*populate_dml_writeback_from_context)( 170 struct dc *dc, 171 struct resource_context *res_ctx, 172 display_e2e_pipe_params_st *pipes); 173 174 void (*set_mcif_arb_params)( 175 struct dc *dc, 176 struct dc_state *context, 177 display_e2e_pipe_params_st *pipes, 178 int pipe_cnt); 179 void (*update_bw_bounding_box)( 180 struct dc *dc, 181 struct clk_bw_params *bw_params); 182 bool (*acquire_post_bldn_3dlut)( 183 struct resource_context *res_ctx, 184 const struct resource_pool *pool, 185 int mpcc_id, 186 struct dc_3dlut **lut, 187 struct dc_transfer_func **shaper); 188 189 bool (*release_post_bldn_3dlut)( 190 struct resource_context *res_ctx, 191 const struct resource_pool *pool, 192 struct dc_3dlut **lut, 193 struct dc_transfer_func **shaper); 194 195 enum dc_status (*add_dsc_to_stream_resource)( 196 struct dc *dc, struct dc_state *state, 197 struct dc_stream_state *stream); 198 199 void (*add_phantom_pipes)( 200 struct dc *dc, 201 struct dc_state *context, 202 display_e2e_pipe_params_st *pipes, 203 unsigned int pipe_cnt, 204 unsigned int index); 205 206 void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); 207 void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx); 208 }; 209 210 struct audio_support{ 211 bool dp_audio; 212 bool hdmi_audio_on_dongle; 213 bool hdmi_audio_native; 214 }; 215 216 #define NO_UNDERLAY_PIPE -1 217 218 struct resource_pool { 219 struct mem_input *mis[MAX_PIPES]; 220 struct hubp *hubps[MAX_PIPES]; 221 struct input_pixel_processor *ipps[MAX_PIPES]; 222 struct transform *transforms[MAX_PIPES]; 223 struct dpp *dpps[MAX_PIPES]; 224 struct output_pixel_processor *opps[MAX_PIPES]; 225 struct timing_generator *timing_generators[MAX_PIPES]; 226 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 227 struct hubbub *hubbub; 228 struct mpc *mpc; 229 struct pp_smu_funcs *pp_smu; 230 struct dce_aux *engines[MAX_PIPES]; 231 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 232 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 233 bool i2c_hw_buffer_in_use; 234 235 struct dwbc *dwbc[MAX_DWB_PIPES]; 236 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 237 struct { 238 unsigned int gsl_0:1; 239 unsigned int gsl_1:1; 240 unsigned int gsl_2:1; 241 } gsl_groups; 242 243 struct display_stream_compressor *dscs[MAX_PIPES]; 244 245 unsigned int pipe_count; 246 unsigned int underlay_pipe_index; 247 unsigned int stream_enc_count; 248 249 /* An array for accessing the link encoder objects that have been created. 250 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 251 */ 252 struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 253 /* Number of DIG link encoder objects created - i.e. number of valid 254 * entries in link_encoders array. 255 */ 256 unsigned int dig_link_enc_count; 257 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 258 unsigned int usb4_dpia_count; 259 260 unsigned int hpo_dp_stream_enc_count; 261 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 262 unsigned int hpo_dp_link_enc_count; 263 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 264 struct dc_3dlut *mpc_lut[MAX_PIPES]; 265 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 266 267 struct { 268 unsigned int xtalin_clock_inKhz; 269 unsigned int dccg_ref_clock_inKhz; 270 unsigned int dchub_ref_clock_inKhz; 271 } ref_clocks; 272 unsigned int timing_generator_count; 273 unsigned int mpcc_count; 274 275 unsigned int writeback_pipe_count; 276 /* 277 * reserved clock source for DP 278 */ 279 struct clock_source *dp_clock_source; 280 281 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 282 unsigned int clk_src_count; 283 284 struct audio *audios[MAX_AUDIOS]; 285 unsigned int audio_count; 286 struct audio_support audio_support; 287 288 struct dccg *dccg; 289 struct pg_cntl *pg_cntl; 290 struct irq_service *irqs; 291 292 struct abm *abm; 293 struct dmcu *dmcu; 294 struct dmub_psr *psr; 295 296 struct dmub_replay *replay; 297 298 struct abm *multiple_abms[MAX_PIPES]; 299 300 const struct resource_funcs *funcs; 301 const struct resource_caps *res_cap; 302 303 struct ddc_service *oem_device; 304 }; 305 306 struct dcn_fe_bandwidth { 307 int dppclk_khz; 308 309 }; 310 311 /* Parameters needed to call set_disp_pattern_generator */ 312 struct test_pattern_params { 313 enum controller_dp_test_pattern test_pattern; 314 enum controller_dp_color_space color_space; 315 enum dc_color_depth color_depth; 316 int width; 317 int height; 318 int offset; 319 }; 320 321 struct stream_resource { 322 struct output_pixel_processor *opp; 323 struct display_stream_compressor *dsc; 324 struct timing_generator *tg; 325 struct stream_encoder *stream_enc; 326 struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 327 struct audio *audio; 328 329 struct pixel_clk_params pix_clk_params; 330 struct encoder_info_frame encoder_info_frame; 331 332 struct abm *abm; 333 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 334 * otherwise it's using group number 'gsl_group-1' 335 */ 336 uint8_t gsl_group; 337 338 struct test_pattern_params test_pattern_params; 339 }; 340 341 struct plane_resource { 342 /* scl_data is scratch space required to program a plane */ 343 struct scaler_data scl_data; 344 /* Below pointers to hw objects are required to enable the plane */ 345 struct hubp *hubp; 346 struct mem_input *mi; 347 struct input_pixel_processor *ipp; 348 struct transform *xfm; 349 struct dpp *dpp; 350 uint8_t mpcc_inst; 351 352 struct dcn_fe_bandwidth bw; 353 }; 354 355 #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 356 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 357 358 /* all mappable hardware resources used to enable a link */ 359 struct link_resource { 360 struct hpo_dp_link_encoder *hpo_dp_link_enc; 361 }; 362 363 struct link_config { 364 struct dc_link_settings dp_link_settings; 365 }; 366 union pipe_update_flags { 367 struct { 368 uint32_t enable : 1; 369 uint32_t disable : 1; 370 uint32_t odm : 1; 371 uint32_t global_sync : 1; 372 uint32_t opp_changed : 1; 373 uint32_t tg_changed : 1; 374 uint32_t mpcc : 1; 375 uint32_t dppclk : 1; 376 uint32_t hubp_interdependent : 1; 377 uint32_t hubp_rq_dlg_ttu : 1; 378 uint32_t gamut_remap : 1; 379 uint32_t scaler : 1; 380 uint32_t viewport : 1; 381 uint32_t plane_changed : 1; 382 uint32_t det_size : 1; 383 uint32_t unbounded_req : 1; 384 uint32_t test_pattern_changed : 1; 385 } bits; 386 uint32_t raw; 387 }; 388 389 enum p_state_switch_method { 390 P_STATE_UNKNOWN = 0, 391 P_STATE_V_BLANK = 1, 392 P_STATE_FPO, 393 P_STATE_V_ACTIVE, 394 P_STATE_SUB_VP, 395 P_STATE_DRR_SUB_VP, 396 P_STATE_V_BLANK_SUB_VP 397 }; 398 399 struct pipe_ctx { 400 struct dc_plane_state *plane_state; 401 struct dc_stream_state *stream; 402 403 struct plane_resource plane_res; 404 405 /** 406 * @stream_res: Reference to DCN resource components such OPP and DSC. 407 */ 408 struct stream_resource stream_res; 409 struct link_resource link_res; 410 411 struct clock_source *clock_source; 412 413 struct pll_settings pll_settings; 414 415 /** 416 * @link_config: 417 * 418 * link config records software decision for what link config should be 419 * enabled given current link capability and stream during hw resource 420 * mapping. This is to decouple the dependency on link capability during 421 * dc commit or update. 422 */ 423 struct link_config link_config; 424 425 uint8_t pipe_idx; 426 uint8_t pipe_idx_syncd; 427 428 struct pipe_ctx *top_pipe; 429 struct pipe_ctx *bottom_pipe; 430 struct pipe_ctx *next_odm_pipe; 431 struct pipe_ctx *prev_odm_pipe; 432 433 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 434 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 435 struct _vcs_dpi_display_rq_regs_st rq_regs; 436 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 437 struct _vcs_dpi_display_rq_params_st dml_rq_param; 438 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 439 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 440 int det_buffer_size_kb; 441 bool unbounded_req; 442 unsigned int surface_size_in_mall_bytes; 443 444 struct dwbc *dwbc; 445 struct mcif_wb *mcif_wb; 446 union pipe_update_flags update_flags; 447 enum p_state_switch_method p_state_type; 448 struct tg_color visual_confirm_color; 449 bool has_vactive_margin; 450 /* subvp_index: only valid if the pipe is a SUBVP_MAIN*/ 451 uint8_t subvp_index; 452 }; 453 454 /* Data used for dynamic link encoder assignment. 455 * Tracks current and future assignments; available link encoders; 456 * and mode of operation (whether to use current or future assignments). 457 */ 458 struct link_enc_cfg_context { 459 enum link_enc_cfg_mode mode; 460 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 461 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 462 struct link_enc_assignment transient_assignments[MAX_PIPES]; 463 }; 464 465 struct resource_context { 466 struct pipe_ctx pipe_ctx[MAX_PIPES]; 467 bool is_stream_enc_acquired[MAX_PIPES * 2]; 468 bool is_audio_acquired[MAX_PIPES]; 469 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 470 uint8_t dp_clock_source_ref_count; 471 bool is_dsc_acquired[MAX_PIPES]; 472 struct link_enc_cfg_context link_enc_cfg_ctx; 473 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 474 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 475 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 476 bool is_mpc_3dlut_acquired[MAX_PIPES]; 477 /* solely used for build scalar data in dml2 */ 478 struct pipe_ctx temp_pipe; 479 }; 480 481 struct dce_bw_output { 482 bool cpuc_state_change_enable; 483 bool cpup_state_change_enable; 484 bool stutter_mode_enable; 485 bool nbp_state_change_enable; 486 bool all_displays_in_sync; 487 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 488 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 489 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 490 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 491 int sclk_khz; 492 int sclk_deep_sleep_khz; 493 int yclk_khz; 494 int dispclk_khz; 495 int blackout_recovery_time_us; 496 }; 497 498 struct dcn_bw_writeback { 499 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 500 }; 501 502 struct dcn_bw_output { 503 struct dc_clocks clk; 504 union dcn_watermark_set watermarks; 505 struct dcn_bw_writeback bw_writeback; 506 int compbuf_size_kb; 507 unsigned int mall_ss_size_bytes; 508 unsigned int mall_ss_psr_active_size_bytes; 509 unsigned int mall_subvp_size_bytes; 510 unsigned int legacy_svp_drr_stream_index; 511 bool legacy_svp_drr_stream_index_valid; 512 }; 513 514 union bw_output { 515 struct dcn_bw_output dcn; 516 struct dce_bw_output dce; 517 }; 518 519 struct bw_context { 520 union bw_output bw; 521 struct display_mode_lib dml; 522 struct dml2_context *dml2; 523 struct dml2_context *dml2_dc_power_source; 524 }; 525 526 struct dc_dmub_cmd { 527 union dmub_rb_cmd dmub_cmd; 528 enum dm_dmub_wait_type wait_type; 529 }; 530 531 /** 532 * struct dc_state - The full description of a state requested by users 533 */ 534 struct dc_state { 535 /** 536 * @streams: Stream state properties 537 */ 538 struct dc_stream_state *streams[MAX_PIPES]; 539 540 /** 541 * @stream_status: Planes status on a given stream 542 */ 543 struct dc_stream_status stream_status[MAX_PIPES]; 544 /** 545 * @phantom_streams: Stream state properties for phantoms 546 */ 547 struct dc_stream_state *phantom_streams[MAX_PHANTOM_PIPES]; 548 /** 549 * @phantom_planes: Planes state properties for phantoms 550 */ 551 struct dc_plane_state *phantom_planes[MAX_PHANTOM_PIPES]; 552 553 /** 554 * @stream_count: Total of streams in use 555 */ 556 uint8_t stream_count; 557 uint8_t stream_mask; 558 559 /** 560 * @stream_count: Total phantom streams in use 561 */ 562 uint8_t phantom_stream_count; 563 /** 564 * @stream_count: Total phantom planes in use 565 */ 566 uint8_t phantom_plane_count; 567 /** 568 * @res_ctx: Persistent state of resources 569 */ 570 struct resource_context res_ctx; 571 572 /** 573 * @pp_display_cfg: PowerPlay clocks and settings 574 * Note: this is a big struct, do *not* put on stack! 575 */ 576 struct dm_pp_display_configuration pp_display_cfg; 577 578 /** 579 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 580 * Note: this is a big struct, do *not* put on stack! 581 */ 582 struct dcn_bw_internal_vars dcn_bw_vars; 583 584 struct clk_mgr *clk_mgr; 585 586 /** 587 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 588 * 589 * Each context must have its own instance of VBA, and in order to 590 * initialize and obtain IP and SOC, the base DML instance from DC is 591 * initially copied into every context. 592 */ 593 struct bw_context bw_ctx; 594 595 struct block_sequence block_sequence[50]; 596 unsigned int block_sequence_steps; 597 struct dc_dmub_cmd dc_dmub_cmd[10]; 598 unsigned int dmub_cmd_count; 599 600 /** 601 * @refcount: refcount reference 602 * 603 * Notice that dc_state is used around the code to capture the current 604 * context, so we need to pass it everywhere. That's why we want to use 605 * kref in this struct. 606 */ 607 struct kref refcount; 608 609 struct { 610 unsigned int stutter_period_us; 611 } perf_params; 612 613 enum dc_power_source_type power_source; 614 }; 615 616 struct replay_context { 617 /* ddc line */ 618 enum channel_id aux_inst; 619 /* Transmitter id */ 620 enum transmitter digbe_inst; 621 /* Engine Id is used for Dig Be source select */ 622 enum engine_id digfe_inst; 623 /* Controller Id used for Dig Fe source select */ 624 enum controller_id controllerId; 625 unsigned int line_time_in_ns; 626 }; 627 628 enum dc_replay_enable { 629 DC_REPLAY_DISABLE = 0, 630 DC_REPLAY_ENABLE = 1, 631 }; 632 633 struct dc_bounding_box_max_clk { 634 int max_dcfclk_mhz; 635 int max_dispclk_mhz; 636 int max_dppclk_mhz; 637 int max_phyclk_mhz; 638 }; 639 640 #endif /* _CORE_TYPES_H_ */ 641