1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "PPCInstrInfo.h"
14 #include "MCTargetDesc/PPCPredicates.h"
15 #include "PPC.h"
16 #include "PPCHazardRecognizers.h"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveIntervals.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/PseudoSourceValue.h"
31 #include "llvm/CodeGen/RegisterClassInfo.h"
32 #include "llvm/CodeGen/RegisterPressure.h"
33 #include "llvm/CodeGen/ScheduleDAG.h"
34 #include "llvm/CodeGen/SlotIndexes.h"
35 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Support/raw_ostream.h"
43
44 using namespace llvm;
45
46 #define DEBUG_TYPE "ppc-instr-info"
47
48 #define GET_INSTRMAP_INFO
49 #define GET_INSTRINFO_CTOR_DTOR
50 #include "PPCGenInstrInfo.inc"
51
52 STATISTIC(NumStoreSPILLVSRRCAsVec,
53 "Number of spillvsrrc spilled to stack as vec");
54 STATISTIC(NumStoreSPILLVSRRCAsGpr,
55 "Number of spillvsrrc spilled to stack as gpr");
56 STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc");
57 STATISTIC(CmpIselsConverted,
58 "Number of ISELs that depend on comparison of constants converted");
59 STATISTIC(MissedConvertibleImmediateInstrs,
60 "Number of compare-immediate instructions fed by constants");
61 STATISTIC(NumRcRotatesConvertedToRcAnd,
62 "Number of record-form rotates converted to record-form andi");
63
64 static cl::
65 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
66 cl::desc("Disable analysis for CTR loops"));
67
68 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
69 cl::desc("Disable compare instruction optimization"), cl::Hidden);
70
71 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
72 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
73 cl::Hidden);
74
75 static cl::opt<bool>
76 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
77 cl::desc("Use the old (incorrect) instruction latency calculation"));
78
79 static cl::opt<float>
80 FMARPFactor("ppc-fma-rp-factor", cl::Hidden, cl::init(1.5),
81 cl::desc("register pressure factor for the transformations."));
82
83 static cl::opt<bool> EnableFMARegPressureReduction(
84 "ppc-fma-rp-reduction", cl::Hidden, cl::init(true),
85 cl::desc("enable register pressure reduce in machine combiner pass."));
86
87 // Pin the vtable to this file.
anchor()88 void PPCInstrInfo::anchor() {}
89
PPCInstrInfo(PPCSubtarget & STI)90 PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
91 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
92 /* CatchRetOpcode */ -1,
93 STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
94 Subtarget(STI), RI(STI.getTargetMachine()) {}
95
96 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
97 /// this target when scheduling the DAG.
98 ScheduleHazardRecognizer *
CreateTargetHazardRecognizer(const TargetSubtargetInfo * STI,const ScheduleDAG * DAG) const99 PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
100 const ScheduleDAG *DAG) const {
101 unsigned Directive =
102 static_cast<const PPCSubtarget *>(STI)->getCPUDirective();
103 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
104 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
105 const InstrItineraryData *II =
106 static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
107 return new ScoreboardHazardRecognizer(II, DAG);
108 }
109
110 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
111 }
112
113 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
114 /// to use for this target when scheduling the DAG.
115 ScheduleHazardRecognizer *
CreateTargetPostRAHazardRecognizer(const InstrItineraryData * II,const ScheduleDAG * DAG) const116 PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
117 const ScheduleDAG *DAG) const {
118 unsigned Directive =
119 DAG->MF.getSubtarget<PPCSubtarget>().getCPUDirective();
120
121 // FIXME: Leaving this as-is until we have POWER9 scheduling info
122 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
123 return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
124
125 // Most subtargets use a PPC970 recognizer.
126 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
127 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
128 assert(DAG->TII && "No InstrInfo?");
129
130 return new PPCHazardRecognizer970(*DAG);
131 }
132
133 return new ScoreboardHazardRecognizer(II, DAG);
134 }
135
getInstrLatency(const InstrItineraryData * ItinData,const MachineInstr & MI,unsigned * PredCost) const136 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
137 const MachineInstr &MI,
138 unsigned *PredCost) const {
139 if (!ItinData || UseOldLatencyCalc)
140 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
141
142 // The default implementation of getInstrLatency calls getStageLatency, but
143 // getStageLatency does not do the right thing for us. While we have
144 // itinerary, most cores are fully pipelined, and so the itineraries only
145 // express the first part of the pipeline, not every stage. Instead, we need
146 // to use the listed output operand cycle number (using operand 0 here, which
147 // is an output).
148
149 unsigned Latency = 1;
150 unsigned DefClass = MI.getDesc().getSchedClass();
151 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
152 const MachineOperand &MO = MI.getOperand(i);
153 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
154 continue;
155
156 int Cycle = ItinData->getOperandCycle(DefClass, i);
157 if (Cycle < 0)
158 continue;
159
160 Latency = std::max(Latency, (unsigned) Cycle);
161 }
162
163 return Latency;
164 }
165
getOperandLatency(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const166 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
167 const MachineInstr &DefMI, unsigned DefIdx,
168 const MachineInstr &UseMI,
169 unsigned UseIdx) const {
170 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
171 UseMI, UseIdx);
172
173 if (!DefMI.getParent())
174 return Latency;
175
176 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
177 Register Reg = DefMO.getReg();
178
179 bool IsRegCR;
180 if (Register::isVirtualRegister(Reg)) {
181 const MachineRegisterInfo *MRI =
182 &DefMI.getParent()->getParent()->getRegInfo();
183 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
184 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
185 } else {
186 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
187 PPC::CRBITRCRegClass.contains(Reg);
188 }
189
190 if (UseMI.isBranch() && IsRegCR) {
191 if (Latency < 0)
192 Latency = getInstrLatency(ItinData, DefMI);
193
194 // On some cores, there is an additional delay between writing to a condition
195 // register, and using it from a branch.
196 unsigned Directive = Subtarget.getCPUDirective();
197 switch (Directive) {
198 default: break;
199 case PPC::DIR_7400:
200 case PPC::DIR_750:
201 case PPC::DIR_970:
202 case PPC::DIR_E5500:
203 case PPC::DIR_PWR4:
204 case PPC::DIR_PWR5:
205 case PPC::DIR_PWR5X:
206 case PPC::DIR_PWR6:
207 case PPC::DIR_PWR6X:
208 case PPC::DIR_PWR7:
209 case PPC::DIR_PWR8:
210 // FIXME: Is this needed for POWER9?
211 Latency += 2;
212 break;
213 }
214 }
215
216 return Latency;
217 }
218
219 /// This is an architecture-specific helper function of reassociateOps.
220 /// Set special operand attributes for new instructions after reassociation.
setSpecialOperandAttr(MachineInstr & OldMI1,MachineInstr & OldMI2,MachineInstr & NewMI1,MachineInstr & NewMI2) const221 void PPCInstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
222 MachineInstr &OldMI2,
223 MachineInstr &NewMI1,
224 MachineInstr &NewMI2) const {
225 // Propagate FP flags from the original instructions.
226 // But clear poison-generating flags because those may not be valid now.
227 uint16_t IntersectedFlags = OldMI1.getFlags() & OldMI2.getFlags();
228 NewMI1.setFlags(IntersectedFlags);
229 NewMI1.clearFlag(MachineInstr::MIFlag::NoSWrap);
230 NewMI1.clearFlag(MachineInstr::MIFlag::NoUWrap);
231 NewMI1.clearFlag(MachineInstr::MIFlag::IsExact);
232
233 NewMI2.setFlags(IntersectedFlags);
234 NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
235 NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
236 NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
237 }
238
setSpecialOperandAttr(MachineInstr & MI,uint16_t Flags) const239 void PPCInstrInfo::setSpecialOperandAttr(MachineInstr &MI,
240 uint16_t Flags) const {
241 MI.setFlags(Flags);
242 MI.clearFlag(MachineInstr::MIFlag::NoSWrap);
243 MI.clearFlag(MachineInstr::MIFlag::NoUWrap);
244 MI.clearFlag(MachineInstr::MIFlag::IsExact);
245 }
246
247 // This function does not list all associative and commutative operations, but
248 // only those worth feeding through the machine combiner in an attempt to
249 // reduce the critical path. Mostly, this means floating-point operations,
250 // because they have high latencies(>=5) (compared to other operations, such as
251 // and/or, which are also associative and commutative, but have low latencies).
isAssociativeAndCommutative(const MachineInstr & Inst) const252 bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
253 switch (Inst.getOpcode()) {
254 // Floating point:
255 // FP Add:
256 case PPC::FADD:
257 case PPC::FADDS:
258 // FP Multiply:
259 case PPC::FMUL:
260 case PPC::FMULS:
261 // Altivec Add:
262 case PPC::VADDFP:
263 // VSX Add:
264 case PPC::XSADDDP:
265 case PPC::XVADDDP:
266 case PPC::XVADDSP:
267 case PPC::XSADDSP:
268 // VSX Multiply:
269 case PPC::XSMULDP:
270 case PPC::XVMULDP:
271 case PPC::XVMULSP:
272 case PPC::XSMULSP:
273 return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
274 Inst.getFlag(MachineInstr::MIFlag::FmNsz);
275 // Fixed point:
276 // Multiply:
277 case PPC::MULHD:
278 case PPC::MULLD:
279 case PPC::MULHW:
280 case PPC::MULLW:
281 return true;
282 default:
283 return false;
284 }
285 }
286
287 #define InfoArrayIdxFMAInst 0
288 #define InfoArrayIdxFAddInst 1
289 #define InfoArrayIdxFMULInst 2
290 #define InfoArrayIdxAddOpIdx 3
291 #define InfoArrayIdxMULOpIdx 4
292 #define InfoArrayIdxFSubInst 5
293 // Array keeps info for FMA instructions:
294 // Index 0(InfoArrayIdxFMAInst): FMA instruction;
295 // Index 1(InfoArrayIdxFAddInst): ADD instruction associated with FMA;
296 // Index 2(InfoArrayIdxFMULInst): MUL instruction associated with FMA;
297 // Index 3(InfoArrayIdxAddOpIdx): ADD operand index in FMA operands;
298 // Index 4(InfoArrayIdxMULOpIdx): first MUL operand index in FMA operands;
299 // second MUL operand index is plus 1;
300 // Index 5(InfoArrayIdxFSubInst): SUB instruction associated with FMA.
301 static const uint16_t FMAOpIdxInfo[][6] = {
302 // FIXME: Add more FMA instructions like XSNMADDADP and so on.
303 {PPC::XSMADDADP, PPC::XSADDDP, PPC::XSMULDP, 1, 2, PPC::XSSUBDP},
304 {PPC::XSMADDASP, PPC::XSADDSP, PPC::XSMULSP, 1, 2, PPC::XSSUBSP},
305 {PPC::XVMADDADP, PPC::XVADDDP, PPC::XVMULDP, 1, 2, PPC::XVSUBDP},
306 {PPC::XVMADDASP, PPC::XVADDSP, PPC::XVMULSP, 1, 2, PPC::XVSUBSP},
307 {PPC::FMADD, PPC::FADD, PPC::FMUL, 3, 1, PPC::FSUB},
308 {PPC::FMADDS, PPC::FADDS, PPC::FMULS, 3, 1, PPC::FSUBS}};
309
310 // Check if an opcode is a FMA instruction. If it is, return the index in array
311 // FMAOpIdxInfo. Otherwise, return -1.
getFMAOpIdxInfo(unsigned Opcode) const312 int16_t PPCInstrInfo::getFMAOpIdxInfo(unsigned Opcode) const {
313 for (unsigned I = 0; I < array_lengthof(FMAOpIdxInfo); I++)
314 if (FMAOpIdxInfo[I][InfoArrayIdxFMAInst] == Opcode)
315 return I;
316 return -1;
317 }
318
319 // On PowerPC target, we have two kinds of patterns related to FMA:
320 // 1: Improve ILP.
321 // Try to reassociate FMA chains like below:
322 //
323 // Pattern 1:
324 // A = FADD X, Y (Leaf)
325 // B = FMA A, M21, M22 (Prev)
326 // C = FMA B, M31, M32 (Root)
327 // -->
328 // A = FMA X, M21, M22
329 // B = FMA Y, M31, M32
330 // C = FADD A, B
331 //
332 // Pattern 2:
333 // A = FMA X, M11, M12 (Leaf)
334 // B = FMA A, M21, M22 (Prev)
335 // C = FMA B, M31, M32 (Root)
336 // -->
337 // A = FMUL M11, M12
338 // B = FMA X, M21, M22
339 // D = FMA A, M31, M32
340 // C = FADD B, D
341 //
342 // breaking the dependency between A and B, allowing FMA to be executed in
343 // parallel (or back-to-back in a pipeline) instead of depending on each other.
344 //
345 // 2: Reduce register pressure.
346 // Try to reassociate FMA with FSUB and a constant like below:
347 // C is a floating point const.
348 //
349 // Pattern 1:
350 // A = FSUB X, Y (Leaf)
351 // D = FMA B, C, A (Root)
352 // -->
353 // A = FMA B, Y, -C
354 // D = FMA A, X, C
355 //
356 // Pattern 2:
357 // A = FSUB X, Y (Leaf)
358 // D = FMA B, A, C (Root)
359 // -->
360 // A = FMA B, Y, -C
361 // D = FMA A, X, C
362 //
363 // Before the transformation, A must be assigned with different hardware
364 // register with D. After the transformation, A and D must be assigned with
365 // same hardware register due to TIE attribute of FMA instructions.
366 //
getFMAPatterns(MachineInstr & Root,SmallVectorImpl<MachineCombinerPattern> & Patterns,bool DoRegPressureReduce) const367 bool PPCInstrInfo::getFMAPatterns(
368 MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns,
369 bool DoRegPressureReduce) const {
370 MachineBasicBlock *MBB = Root.getParent();
371 const MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo();
372 const TargetRegisterInfo *TRI = &getRegisterInfo();
373
374 auto IsAllOpsVirtualReg = [](const MachineInstr &Instr) {
375 for (const auto &MO : Instr.explicit_operands())
376 if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
377 return false;
378 return true;
379 };
380
381 auto IsReassociableAddOrSub = [&](const MachineInstr &Instr,
382 unsigned OpType) {
383 if (Instr.getOpcode() !=
384 FMAOpIdxInfo[getFMAOpIdxInfo(Root.getOpcode())][OpType])
385 return false;
386
387 // Instruction can be reassociated.
388 // fast math flags may prohibit reassociation.
389 if (!(Instr.getFlag(MachineInstr::MIFlag::FmReassoc) &&
390 Instr.getFlag(MachineInstr::MIFlag::FmNsz)))
391 return false;
392
393 // Instruction operands are virtual registers for reassociation.
394 if (!IsAllOpsVirtualReg(Instr))
395 return false;
396
397 // For register pressure reassociation, the FSub must have only one use as
398 // we want to delete the sub to save its def.
399 if (OpType == InfoArrayIdxFSubInst &&
400 !MRI->hasOneNonDBGUse(Instr.getOperand(0).getReg()))
401 return false;
402
403 return true;
404 };
405
406 auto IsReassociableFMA = [&](const MachineInstr &Instr, int16_t &AddOpIdx,
407 int16_t &MulOpIdx, bool IsLeaf) {
408 int16_t Idx = getFMAOpIdxInfo(Instr.getOpcode());
409 if (Idx < 0)
410 return false;
411
412 // Instruction can be reassociated.
413 // fast math flags may prohibit reassociation.
414 if (!(Instr.getFlag(MachineInstr::MIFlag::FmReassoc) &&
415 Instr.getFlag(MachineInstr::MIFlag::FmNsz)))
416 return false;
417
418 // Instruction operands are virtual registers for reassociation.
419 if (!IsAllOpsVirtualReg(Instr))
420 return false;
421
422 MulOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxMULOpIdx];
423 if (IsLeaf)
424 return true;
425
426 AddOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxAddOpIdx];
427
428 const MachineOperand &OpAdd = Instr.getOperand(AddOpIdx);
429 MachineInstr *MIAdd = MRI->getUniqueVRegDef(OpAdd.getReg());
430 // If 'add' operand's def is not in current block, don't do ILP related opt.
431 if (!MIAdd || MIAdd->getParent() != MBB)
432 return false;
433
434 // If this is not Leaf FMA Instr, its 'add' operand should only have one use
435 // as this fma will be changed later.
436 return IsLeaf ? true : MRI->hasOneNonDBGUse(OpAdd.getReg());
437 };
438
439 int16_t AddOpIdx = -1;
440 int16_t MulOpIdx = -1;
441
442 bool IsUsedOnceL = false;
443 bool IsUsedOnceR = false;
444 MachineInstr *MULInstrL = nullptr;
445 MachineInstr *MULInstrR = nullptr;
446
447 auto IsRPReductionCandidate = [&]() {
448 // Currently, we only support float and double.
449 // FIXME: add support for other types.
450 unsigned Opcode = Root.getOpcode();
451 if (Opcode != PPC::XSMADDASP && Opcode != PPC::XSMADDADP)
452 return false;
453
454 // Root must be a valid FMA like instruction.
455 // Treat it as leaf as we don't care its add operand.
456 if (IsReassociableFMA(Root, AddOpIdx, MulOpIdx, true)) {
457 assert((MulOpIdx >= 0) && "mul operand index not right!");
458 Register MULRegL = TRI->lookThruSingleUseCopyChain(
459 Root.getOperand(MulOpIdx).getReg(), MRI);
460 Register MULRegR = TRI->lookThruSingleUseCopyChain(
461 Root.getOperand(MulOpIdx + 1).getReg(), MRI);
462 if (!MULRegL && !MULRegR)
463 return false;
464
465 if (MULRegL && !MULRegR) {
466 MULRegR =
467 TRI->lookThruCopyLike(Root.getOperand(MulOpIdx + 1).getReg(), MRI);
468 IsUsedOnceL = true;
469 } else if (!MULRegL && MULRegR) {
470 MULRegL =
471 TRI->lookThruCopyLike(Root.getOperand(MulOpIdx).getReg(), MRI);
472 IsUsedOnceR = true;
473 } else {
474 IsUsedOnceL = true;
475 IsUsedOnceR = true;
476 }
477
478 if (!Register::isVirtualRegister(MULRegL) ||
479 !Register::isVirtualRegister(MULRegR))
480 return false;
481
482 MULInstrL = MRI->getVRegDef(MULRegL);
483 MULInstrR = MRI->getVRegDef(MULRegR);
484 return true;
485 }
486 return false;
487 };
488
489 // Register pressure fma reassociation patterns.
490 if (DoRegPressureReduce && IsRPReductionCandidate()) {
491 assert((MULInstrL && MULInstrR) && "wrong register preduction candidate!");
492 // Register pressure pattern 1
493 if (isLoadFromConstantPool(MULInstrL) && IsUsedOnceR &&
494 IsReassociableAddOrSub(*MULInstrR, InfoArrayIdxFSubInst)) {
495 LLVM_DEBUG(dbgs() << "add pattern REASSOC_XY_BCA\n");
496 Patterns.push_back(MachineCombinerPattern::REASSOC_XY_BCA);
497 return true;
498 }
499
500 // Register pressure pattern 2
501 if ((isLoadFromConstantPool(MULInstrR) && IsUsedOnceL &&
502 IsReassociableAddOrSub(*MULInstrL, InfoArrayIdxFSubInst))) {
503 LLVM_DEBUG(dbgs() << "add pattern REASSOC_XY_BAC\n");
504 Patterns.push_back(MachineCombinerPattern::REASSOC_XY_BAC);
505 return true;
506 }
507 }
508
509 // ILP fma reassociation patterns.
510 // Root must be a valid FMA like instruction.
511 AddOpIdx = -1;
512 if (!IsReassociableFMA(Root, AddOpIdx, MulOpIdx, false))
513 return false;
514
515 assert((AddOpIdx >= 0) && "add operand index not right!");
516
517 Register RegB = Root.getOperand(AddOpIdx).getReg();
518 MachineInstr *Prev = MRI->getUniqueVRegDef(RegB);
519
520 // Prev must be a valid FMA like instruction.
521 AddOpIdx = -1;
522 if (!IsReassociableFMA(*Prev, AddOpIdx, MulOpIdx, false))
523 return false;
524
525 assert((AddOpIdx >= 0) && "add operand index not right!");
526
527 Register RegA = Prev->getOperand(AddOpIdx).getReg();
528 MachineInstr *Leaf = MRI->getUniqueVRegDef(RegA);
529 AddOpIdx = -1;
530 if (IsReassociableFMA(*Leaf, AddOpIdx, MulOpIdx, true)) {
531 Patterns.push_back(MachineCombinerPattern::REASSOC_XMM_AMM_BMM);
532 LLVM_DEBUG(dbgs() << "add pattern REASSOC_XMM_AMM_BMM\n");
533 return true;
534 }
535 if (IsReassociableAddOrSub(*Leaf, InfoArrayIdxFAddInst)) {
536 Patterns.push_back(MachineCombinerPattern::REASSOC_XY_AMM_BMM);
537 LLVM_DEBUG(dbgs() << "add pattern REASSOC_XY_AMM_BMM\n");
538 return true;
539 }
540 return false;
541 }
542
finalizeInsInstrs(MachineInstr & Root,MachineCombinerPattern & P,SmallVectorImpl<MachineInstr * > & InsInstrs) const543 void PPCInstrInfo::finalizeInsInstrs(
544 MachineInstr &Root, MachineCombinerPattern &P,
545 SmallVectorImpl<MachineInstr *> &InsInstrs) const {
546 assert(!InsInstrs.empty() && "Instructions set to be inserted is empty!");
547
548 MachineFunction *MF = Root.getMF();
549 MachineRegisterInfo *MRI = &MF->getRegInfo();
550 const TargetRegisterInfo *TRI = &getRegisterInfo();
551 MachineConstantPool *MCP = MF->getConstantPool();
552
553 int16_t Idx = getFMAOpIdxInfo(Root.getOpcode());
554 if (Idx < 0)
555 return;
556
557 uint16_t FirstMulOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxMULOpIdx];
558
559 // For now we only need to fix up placeholder for register pressure reduce
560 // patterns.
561 Register ConstReg = 0;
562 switch (P) {
563 case MachineCombinerPattern::REASSOC_XY_BCA:
564 ConstReg =
565 TRI->lookThruCopyLike(Root.getOperand(FirstMulOpIdx).getReg(), MRI);
566 break;
567 case MachineCombinerPattern::REASSOC_XY_BAC:
568 ConstReg =
569 TRI->lookThruCopyLike(Root.getOperand(FirstMulOpIdx + 1).getReg(), MRI);
570 break;
571 default:
572 // Not register pressure reduce patterns.
573 return;
574 }
575
576 MachineInstr *ConstDefInstr = MRI->getVRegDef(ConstReg);
577 // Get const value from const pool.
578 const Constant *C = getConstantFromConstantPool(ConstDefInstr);
579 assert(isa<llvm::ConstantFP>(C) && "not a valid constant!");
580
581 // Get negative fp const.
582 APFloat F1((dyn_cast<ConstantFP>(C))->getValueAPF());
583 F1.changeSign();
584 Constant *NegC = ConstantFP::get(dyn_cast<ConstantFP>(C)->getContext(), F1);
585 Align Alignment = MF->getDataLayout().getPrefTypeAlign(C->getType());
586
587 // Put negative fp const into constant pool.
588 unsigned ConstPoolIdx = MCP->getConstantPoolIndex(NegC, Alignment);
589
590 MachineOperand *Placeholder = nullptr;
591 // Record the placeholder PPC::ZERO8 we add in reassociateFMA.
592 for (auto *Inst : InsInstrs) {
593 for (MachineOperand &Operand : Inst->explicit_operands()) {
594 assert(Operand.isReg() && "Invalid instruction in InsInstrs!");
595 if (Operand.getReg() == PPC::ZERO8) {
596 Placeholder = &Operand;
597 break;
598 }
599 }
600 }
601
602 assert(Placeholder && "Placeholder does not exist!");
603
604 // Generate instructions to load the const fp from constant pool.
605 // We only support PPC64 and medium code model.
606 Register LoadNewConst =
607 generateLoadForNewConst(ConstPoolIdx, &Root, C->getType(), InsInstrs);
608
609 // Fill the placeholder with the new load from constant pool.
610 Placeholder->setReg(LoadNewConst);
611 }
612
shouldReduceRegisterPressure(MachineBasicBlock * MBB,RegisterClassInfo * RegClassInfo) const613 bool PPCInstrInfo::shouldReduceRegisterPressure(
614 MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) const {
615
616 if (!EnableFMARegPressureReduction)
617 return false;
618
619 // Currently, we only enable register pressure reducing in machine combiner
620 // for: 1: PPC64; 2: Code Model is Medium; 3: Power9 which also has vector
621 // support.
622 //
623 // So we need following instructions to access a TOC entry:
624 //
625 // %6:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, %const.0
626 // %7:vssrc = DFLOADf32 target-flags(ppc-toc-lo) %const.0,
627 // killed %6:g8rc_and_g8rc_nox0, implicit $x2 :: (load 4 from constant-pool)
628 //
629 // FIXME: add more supported targets, like Small and Large code model, PPC32,
630 // AIX.
631 if (!(Subtarget.isPPC64() && Subtarget.hasP9Vector() &&
632 Subtarget.getTargetMachine().getCodeModel() == CodeModel::Medium))
633 return false;
634
635 const TargetRegisterInfo *TRI = &getRegisterInfo();
636 MachineFunction *MF = MBB->getParent();
637 MachineRegisterInfo *MRI = &MF->getRegInfo();
638
639 auto GetMBBPressure = [&](MachineBasicBlock *MBB) -> std::vector<unsigned> {
640 RegionPressure Pressure;
641 RegPressureTracker RPTracker(Pressure);
642
643 // Initialize the register pressure tracker.
644 RPTracker.init(MBB->getParent(), RegClassInfo, nullptr, MBB, MBB->end(),
645 /*TrackLaneMasks*/ false, /*TrackUntiedDefs=*/true);
646
647 for (MachineBasicBlock::iterator MII = MBB->instr_end(),
648 MIE = MBB->instr_begin();
649 MII != MIE; --MII) {
650 MachineInstr &MI = *std::prev(MII);
651 if (MI.isDebugValue() || MI.isDebugLabel())
652 continue;
653 RegisterOperands RegOpers;
654 RegOpers.collect(MI, *TRI, *MRI, false, false);
655 RPTracker.recedeSkipDebugValues();
656 assert(&*RPTracker.getPos() == &MI && "RPTracker sync error!");
657 RPTracker.recede(RegOpers);
658 }
659
660 // Close the RPTracker to finalize live ins.
661 RPTracker.closeRegion();
662
663 return RPTracker.getPressure().MaxSetPressure;
664 };
665
666 // For now we only care about float and double type fma.
667 unsigned VSSRCLimit = TRI->getRegPressureSetLimit(
668 *MBB->getParent(), PPC::RegisterPressureSets::VSSRC);
669
670 // Only reduce register pressure when pressure is high.
671 return GetMBBPressure(MBB)[PPC::RegisterPressureSets::VSSRC] >
672 (float)VSSRCLimit * FMARPFactor;
673 }
674
isLoadFromConstantPool(MachineInstr * I) const675 bool PPCInstrInfo::isLoadFromConstantPool(MachineInstr *I) const {
676 // I has only one memory operand which is load from constant pool.
677 if (!I->hasOneMemOperand())
678 return false;
679
680 MachineMemOperand *Op = I->memoperands()[0];
681 return Op->isLoad() && Op->getPseudoValue() &&
682 Op->getPseudoValue()->kind() == PseudoSourceValue::ConstantPool;
683 }
684
generateLoadForNewConst(unsigned Idx,MachineInstr * MI,Type * Ty,SmallVectorImpl<MachineInstr * > & InsInstrs) const685 Register PPCInstrInfo::generateLoadForNewConst(
686 unsigned Idx, MachineInstr *MI, Type *Ty,
687 SmallVectorImpl<MachineInstr *> &InsInstrs) const {
688 // Now we only support PPC64, Medium code model and P9 with vector.
689 // We have immutable pattern to access const pool. See function
690 // shouldReduceRegisterPressure.
691 assert((Subtarget.isPPC64() && Subtarget.hasP9Vector() &&
692 Subtarget.getTargetMachine().getCodeModel() == CodeModel::Medium) &&
693 "Target not supported!\n");
694
695 MachineFunction *MF = MI->getMF();
696 MachineRegisterInfo *MRI = &MF->getRegInfo();
697
698 // Generate ADDIStocHA8
699 Register VReg1 = MRI->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass);
700 MachineInstrBuilder TOCOffset =
701 BuildMI(*MF, MI->getDebugLoc(), get(PPC::ADDIStocHA8), VReg1)
702 .addReg(PPC::X2)
703 .addConstantPoolIndex(Idx);
704
705 assert((Ty->isFloatTy() || Ty->isDoubleTy()) &&
706 "Only float and double are supported!");
707
708 unsigned LoadOpcode;
709 // Should be float type or double type.
710 if (Ty->isFloatTy())
711 LoadOpcode = PPC::DFLOADf32;
712 else
713 LoadOpcode = PPC::DFLOADf64;
714
715 const TargetRegisterClass *RC = MRI->getRegClass(MI->getOperand(0).getReg());
716 Register VReg2 = MRI->createVirtualRegister(RC);
717 MachineMemOperand *MMO = MF->getMachineMemOperand(
718 MachinePointerInfo::getConstantPool(*MF), MachineMemOperand::MOLoad,
719 Ty->getScalarSizeInBits() / 8, MF->getDataLayout().getPrefTypeAlign(Ty));
720
721 // Generate Load from constant pool.
722 MachineInstrBuilder Load =
723 BuildMI(*MF, MI->getDebugLoc(), get(LoadOpcode), VReg2)
724 .addConstantPoolIndex(Idx)
725 .addReg(VReg1, getKillRegState(true))
726 .addMemOperand(MMO);
727
728 Load->getOperand(1).setTargetFlags(PPCII::MO_TOC_LO);
729
730 // Insert the toc load instructions into InsInstrs.
731 InsInstrs.insert(InsInstrs.begin(), Load);
732 InsInstrs.insert(InsInstrs.begin(), TOCOffset);
733 return VReg2;
734 }
735
736 // This function returns the const value in constant pool if the \p I is a load
737 // from constant pool.
738 const Constant *
getConstantFromConstantPool(MachineInstr * I) const739 PPCInstrInfo::getConstantFromConstantPool(MachineInstr *I) const {
740 MachineFunction *MF = I->getMF();
741 MachineRegisterInfo *MRI = &MF->getRegInfo();
742 MachineConstantPool *MCP = MF->getConstantPool();
743 assert(I->mayLoad() && "Should be a load instruction.\n");
744 for (auto MO : I->uses()) {
745 if (!MO.isReg())
746 continue;
747 Register Reg = MO.getReg();
748 if (Reg == 0 || !Register::isVirtualRegister(Reg))
749 continue;
750 // Find the toc address.
751 MachineInstr *DefMI = MRI->getVRegDef(Reg);
752 for (auto MO2 : DefMI->uses())
753 if (MO2.isCPI())
754 return (MCP->getConstants())[MO2.getIndex()].Val.ConstVal;
755 }
756 return nullptr;
757 }
758
getMachineCombinerPatterns(MachineInstr & Root,SmallVectorImpl<MachineCombinerPattern> & Patterns,bool DoRegPressureReduce) const759 bool PPCInstrInfo::getMachineCombinerPatterns(
760 MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns,
761 bool DoRegPressureReduce) const {
762 // Using the machine combiner in this way is potentially expensive, so
763 // restrict to when aggressive optimizations are desired.
764 if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive)
765 return false;
766
767 if (getFMAPatterns(Root, Patterns, DoRegPressureReduce))
768 return true;
769
770 return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns,
771 DoRegPressureReduce);
772 }
773
genAlternativeCodeSequence(MachineInstr & Root,MachineCombinerPattern Pattern,SmallVectorImpl<MachineInstr * > & InsInstrs,SmallVectorImpl<MachineInstr * > & DelInstrs,DenseMap<unsigned,unsigned> & InstrIdxForVirtReg) const774 void PPCInstrInfo::genAlternativeCodeSequence(
775 MachineInstr &Root, MachineCombinerPattern Pattern,
776 SmallVectorImpl<MachineInstr *> &InsInstrs,
777 SmallVectorImpl<MachineInstr *> &DelInstrs,
778 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
779 switch (Pattern) {
780 case MachineCombinerPattern::REASSOC_XY_AMM_BMM:
781 case MachineCombinerPattern::REASSOC_XMM_AMM_BMM:
782 case MachineCombinerPattern::REASSOC_XY_BCA:
783 case MachineCombinerPattern::REASSOC_XY_BAC:
784 reassociateFMA(Root, Pattern, InsInstrs, DelInstrs, InstrIdxForVirtReg);
785 break;
786 default:
787 // Reassociate default patterns.
788 TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs,
789 DelInstrs, InstrIdxForVirtReg);
790 break;
791 }
792 }
793
reassociateFMA(MachineInstr & Root,MachineCombinerPattern Pattern,SmallVectorImpl<MachineInstr * > & InsInstrs,SmallVectorImpl<MachineInstr * > & DelInstrs,DenseMap<unsigned,unsigned> & InstrIdxForVirtReg) const794 void PPCInstrInfo::reassociateFMA(
795 MachineInstr &Root, MachineCombinerPattern Pattern,
796 SmallVectorImpl<MachineInstr *> &InsInstrs,
797 SmallVectorImpl<MachineInstr *> &DelInstrs,
798 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
799 MachineFunction *MF = Root.getMF();
800 MachineRegisterInfo &MRI = MF->getRegInfo();
801 const TargetRegisterInfo *TRI = &getRegisterInfo();
802 MachineOperand &OpC = Root.getOperand(0);
803 Register RegC = OpC.getReg();
804 const TargetRegisterClass *RC = MRI.getRegClass(RegC);
805 MRI.constrainRegClass(RegC, RC);
806
807 unsigned FmaOp = Root.getOpcode();
808 int16_t Idx = getFMAOpIdxInfo(FmaOp);
809 assert(Idx >= 0 && "Root must be a FMA instruction");
810
811 bool IsILPReassociate =
812 (Pattern == MachineCombinerPattern::REASSOC_XY_AMM_BMM) ||
813 (Pattern == MachineCombinerPattern::REASSOC_XMM_AMM_BMM);
814
815 uint16_t AddOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxAddOpIdx];
816 uint16_t FirstMulOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxMULOpIdx];
817
818 MachineInstr *Prev = nullptr;
819 MachineInstr *Leaf = nullptr;
820 switch (Pattern) {
821 default:
822 llvm_unreachable("not recognized pattern!");
823 case MachineCombinerPattern::REASSOC_XY_AMM_BMM:
824 case MachineCombinerPattern::REASSOC_XMM_AMM_BMM:
825 Prev = MRI.getUniqueVRegDef(Root.getOperand(AddOpIdx).getReg());
826 Leaf = MRI.getUniqueVRegDef(Prev->getOperand(AddOpIdx).getReg());
827 break;
828 case MachineCombinerPattern::REASSOC_XY_BAC: {
829 Register MULReg =
830 TRI->lookThruCopyLike(Root.getOperand(FirstMulOpIdx).getReg(), &MRI);
831 Leaf = MRI.getVRegDef(MULReg);
832 break;
833 }
834 case MachineCombinerPattern::REASSOC_XY_BCA: {
835 Register MULReg = TRI->lookThruCopyLike(
836 Root.getOperand(FirstMulOpIdx + 1).getReg(), &MRI);
837 Leaf = MRI.getVRegDef(MULReg);
838 break;
839 }
840 }
841
842 uint16_t IntersectedFlags = 0;
843 if (IsILPReassociate)
844 IntersectedFlags = Root.getFlags() & Prev->getFlags() & Leaf->getFlags();
845 else
846 IntersectedFlags = Root.getFlags() & Leaf->getFlags();
847
848 auto GetOperandInfo = [&](const MachineOperand &Operand, Register &Reg,
849 bool &KillFlag) {
850 Reg = Operand.getReg();
851 MRI.constrainRegClass(Reg, RC);
852 KillFlag = Operand.isKill();
853 };
854
855 auto GetFMAInstrInfo = [&](const MachineInstr &Instr, Register &MulOp1,
856 Register &MulOp2, Register &AddOp,
857 bool &MulOp1KillFlag, bool &MulOp2KillFlag,
858 bool &AddOpKillFlag) {
859 GetOperandInfo(Instr.getOperand(FirstMulOpIdx), MulOp1, MulOp1KillFlag);
860 GetOperandInfo(Instr.getOperand(FirstMulOpIdx + 1), MulOp2, MulOp2KillFlag);
861 GetOperandInfo(Instr.getOperand(AddOpIdx), AddOp, AddOpKillFlag);
862 };
863
864 Register RegM11, RegM12, RegX, RegY, RegM21, RegM22, RegM31, RegM32, RegA11,
865 RegA21, RegB;
866 bool KillX = false, KillY = false, KillM11 = false, KillM12 = false,
867 KillM21 = false, KillM22 = false, KillM31 = false, KillM32 = false,
868 KillA11 = false, KillA21 = false, KillB = false;
869
870 GetFMAInstrInfo(Root, RegM31, RegM32, RegB, KillM31, KillM32, KillB);
871
872 if (IsILPReassociate)
873 GetFMAInstrInfo(*Prev, RegM21, RegM22, RegA21, KillM21, KillM22, KillA21);
874
875 if (Pattern == MachineCombinerPattern::REASSOC_XMM_AMM_BMM) {
876 GetFMAInstrInfo(*Leaf, RegM11, RegM12, RegA11, KillM11, KillM12, KillA11);
877 GetOperandInfo(Leaf->getOperand(AddOpIdx), RegX, KillX);
878 } else if (Pattern == MachineCombinerPattern::REASSOC_XY_AMM_BMM) {
879 GetOperandInfo(Leaf->getOperand(1), RegX, KillX);
880 GetOperandInfo(Leaf->getOperand(2), RegY, KillY);
881 } else {
882 // Get FSUB instruction info.
883 GetOperandInfo(Leaf->getOperand(1), RegX, KillX);
884 GetOperandInfo(Leaf->getOperand(2), RegY, KillY);
885 }
886
887 // Create new virtual registers for the new results instead of
888 // recycling legacy ones because the MachineCombiner's computation of the
889 // critical path requires a new register definition rather than an existing
890 // one.
891 // For register pressure reassociation, we only need create one virtual
892 // register for the new fma.
893 Register NewVRA = MRI.createVirtualRegister(RC);
894 InstrIdxForVirtReg.insert(std::make_pair(NewVRA, 0));
895
896 Register NewVRB = 0;
897 if (IsILPReassociate) {
898 NewVRB = MRI.createVirtualRegister(RC);
899 InstrIdxForVirtReg.insert(std::make_pair(NewVRB, 1));
900 }
901
902 Register NewVRD = 0;
903 if (Pattern == MachineCombinerPattern::REASSOC_XMM_AMM_BMM) {
904 NewVRD = MRI.createVirtualRegister(RC);
905 InstrIdxForVirtReg.insert(std::make_pair(NewVRD, 2));
906 }
907
908 auto AdjustOperandOrder = [&](MachineInstr *MI, Register RegAdd, bool KillAdd,
909 Register RegMul1, bool KillRegMul1,
910 Register RegMul2, bool KillRegMul2) {
911 MI->getOperand(AddOpIdx).setReg(RegAdd);
912 MI->getOperand(AddOpIdx).setIsKill(KillAdd);
913 MI->getOperand(FirstMulOpIdx).setReg(RegMul1);
914 MI->getOperand(FirstMulOpIdx).setIsKill(KillRegMul1);
915 MI->getOperand(FirstMulOpIdx + 1).setReg(RegMul2);
916 MI->getOperand(FirstMulOpIdx + 1).setIsKill(KillRegMul2);
917 };
918
919 MachineInstrBuilder NewARegPressure, NewCRegPressure;
920 switch (Pattern) {
921 default:
922 llvm_unreachable("not recognized pattern!");
923 case MachineCombinerPattern::REASSOC_XY_AMM_BMM: {
924 // Create new instructions for insertion.
925 MachineInstrBuilder MINewB =
926 BuildMI(*MF, Prev->getDebugLoc(), get(FmaOp), NewVRB)
927 .addReg(RegX, getKillRegState(KillX))
928 .addReg(RegM21, getKillRegState(KillM21))
929 .addReg(RegM22, getKillRegState(KillM22));
930 MachineInstrBuilder MINewA =
931 BuildMI(*MF, Root.getDebugLoc(), get(FmaOp), NewVRA)
932 .addReg(RegY, getKillRegState(KillY))
933 .addReg(RegM31, getKillRegState(KillM31))
934 .addReg(RegM32, getKillRegState(KillM32));
935 // If AddOpIdx is not 1, adjust the order.
936 if (AddOpIdx != 1) {
937 AdjustOperandOrder(MINewB, RegX, KillX, RegM21, KillM21, RegM22, KillM22);
938 AdjustOperandOrder(MINewA, RegY, KillY, RegM31, KillM31, RegM32, KillM32);
939 }
940
941 MachineInstrBuilder MINewC =
942 BuildMI(*MF, Root.getDebugLoc(),
943 get(FMAOpIdxInfo[Idx][InfoArrayIdxFAddInst]), RegC)
944 .addReg(NewVRB, getKillRegState(true))
945 .addReg(NewVRA, getKillRegState(true));
946
947 // Update flags for newly created instructions.
948 setSpecialOperandAttr(*MINewA, IntersectedFlags);
949 setSpecialOperandAttr(*MINewB, IntersectedFlags);
950 setSpecialOperandAttr(*MINewC, IntersectedFlags);
951
952 // Record new instructions for insertion.
953 InsInstrs.push_back(MINewA);
954 InsInstrs.push_back(MINewB);
955 InsInstrs.push_back(MINewC);
956 break;
957 }
958 case MachineCombinerPattern::REASSOC_XMM_AMM_BMM: {
959 assert(NewVRD && "new FMA register not created!");
960 // Create new instructions for insertion.
961 MachineInstrBuilder MINewA =
962 BuildMI(*MF, Leaf->getDebugLoc(),
963 get(FMAOpIdxInfo[Idx][InfoArrayIdxFMULInst]), NewVRA)
964 .addReg(RegM11, getKillRegState(KillM11))
965 .addReg(RegM12, getKillRegState(KillM12));
966 MachineInstrBuilder MINewB =
967 BuildMI(*MF, Prev->getDebugLoc(), get(FmaOp), NewVRB)
968 .addReg(RegX, getKillRegState(KillX))
969 .addReg(RegM21, getKillRegState(KillM21))
970 .addReg(RegM22, getKillRegState(KillM22));
971 MachineInstrBuilder MINewD =
972 BuildMI(*MF, Root.getDebugLoc(), get(FmaOp), NewVRD)
973 .addReg(NewVRA, getKillRegState(true))
974 .addReg(RegM31, getKillRegState(KillM31))
975 .addReg(RegM32, getKillRegState(KillM32));
976 // If AddOpIdx is not 1, adjust the order.
977 if (AddOpIdx != 1) {
978 AdjustOperandOrder(MINewB, RegX, KillX, RegM21, KillM21, RegM22, KillM22);
979 AdjustOperandOrder(MINewD, NewVRA, true, RegM31, KillM31, RegM32,
980 KillM32);
981 }
982
983 MachineInstrBuilder MINewC =
984 BuildMI(*MF, Root.getDebugLoc(),
985 get(FMAOpIdxInfo[Idx][InfoArrayIdxFAddInst]), RegC)
986 .addReg(NewVRB, getKillRegState(true))
987 .addReg(NewVRD, getKillRegState(true));
988
989 // Update flags for newly created instructions.
990 setSpecialOperandAttr(*MINewA, IntersectedFlags);
991 setSpecialOperandAttr(*MINewB, IntersectedFlags);
992 setSpecialOperandAttr(*MINewD, IntersectedFlags);
993 setSpecialOperandAttr(*MINewC, IntersectedFlags);
994
995 // Record new instructions for insertion.
996 InsInstrs.push_back(MINewA);
997 InsInstrs.push_back(MINewB);
998 InsInstrs.push_back(MINewD);
999 InsInstrs.push_back(MINewC);
1000 break;
1001 }
1002 case MachineCombinerPattern::REASSOC_XY_BAC:
1003 case MachineCombinerPattern::REASSOC_XY_BCA: {
1004 Register VarReg;
1005 bool KillVarReg = false;
1006 if (Pattern == MachineCombinerPattern::REASSOC_XY_BCA) {
1007 VarReg = RegM31;
1008 KillVarReg = KillM31;
1009 } else {
1010 VarReg = RegM32;
1011 KillVarReg = KillM32;
1012 }
1013 // We don't want to get negative const from memory pool too early, as the
1014 // created entry will not be deleted even if it has no users. Since all
1015 // operand of Leaf and Root are virtual register, we use zero register
1016 // here as a placeholder. When the InsInstrs is selected in
1017 // MachineCombiner, we call finalizeInsInstrs to replace the zero register
1018 // with a virtual register which is a load from constant pool.
1019 NewARegPressure = BuildMI(*MF, Root.getDebugLoc(), get(FmaOp), NewVRA)
1020 .addReg(RegB, getKillRegState(RegB))
1021 .addReg(RegY, getKillRegState(KillY))
1022 .addReg(PPC::ZERO8);
1023 NewCRegPressure = BuildMI(*MF, Root.getDebugLoc(), get(FmaOp), RegC)
1024 .addReg(NewVRA, getKillRegState(true))
1025 .addReg(RegX, getKillRegState(KillX))
1026 .addReg(VarReg, getKillRegState(KillVarReg));
1027 // For now, we only support xsmaddadp/xsmaddasp, their add operand are
1028 // both at index 1, no need to adjust.
1029 // FIXME: when add more fma instructions support, like fma/fmas, adjust
1030 // the operand index here.
1031 break;
1032 }
1033 }
1034
1035 if (!IsILPReassociate) {
1036 setSpecialOperandAttr(*NewARegPressure, IntersectedFlags);
1037 setSpecialOperandAttr(*NewCRegPressure, IntersectedFlags);
1038
1039 InsInstrs.push_back(NewARegPressure);
1040 InsInstrs.push_back(NewCRegPressure);
1041 }
1042
1043 assert(!InsInstrs.empty() &&
1044 "Insertion instructions set should not be empty!");
1045
1046 // Record old instructions for deletion.
1047 DelInstrs.push_back(Leaf);
1048 if (IsILPReassociate)
1049 DelInstrs.push_back(Prev);
1050 DelInstrs.push_back(&Root);
1051 }
1052
1053 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
isCoalescableExtInstr(const MachineInstr & MI,Register & SrcReg,Register & DstReg,unsigned & SubIdx) const1054 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1055 Register &SrcReg, Register &DstReg,
1056 unsigned &SubIdx) const {
1057 switch (MI.getOpcode()) {
1058 default: return false;
1059 case PPC::EXTSW:
1060 case PPC::EXTSW_32:
1061 case PPC::EXTSW_32_64:
1062 SrcReg = MI.getOperand(1).getReg();
1063 DstReg = MI.getOperand(0).getReg();
1064 SubIdx = PPC::sub_32;
1065 return true;
1066 }
1067 }
1068
isLoadFromStackSlot(const MachineInstr & MI,int & FrameIndex) const1069 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
1070 int &FrameIndex) const {
1071 unsigned Opcode = MI.getOpcode();
1072 const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1073 const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
1074
1075 if (End != std::find(OpcodesForSpill, End, Opcode)) {
1076 // Check for the operands added by addFrameReference (the immediate is the
1077 // offset which defaults to 0).
1078 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
1079 MI.getOperand(2).isFI()) {
1080 FrameIndex = MI.getOperand(2).getIndex();
1081 return MI.getOperand(0).getReg();
1082 }
1083 }
1084 return 0;
1085 }
1086
1087 // For opcodes with the ReMaterializable flag set, this function is called to
1088 // verify the instruction is really rematable.
isReallyTriviallyReMaterializable(const MachineInstr & MI,AliasAnalysis * AA) const1089 bool PPCInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
1090 AliasAnalysis *AA) const {
1091 switch (MI.getOpcode()) {
1092 default:
1093 // This function should only be called for opcodes with the ReMaterializable
1094 // flag set.
1095 llvm_unreachable("Unknown rematerializable operation!");
1096 break;
1097 case PPC::LI:
1098 case PPC::LI8:
1099 case PPC::PLI:
1100 case PPC::PLI8:
1101 case PPC::LIS:
1102 case PPC::LIS8:
1103 case PPC::ADDIStocHA:
1104 case PPC::ADDIStocHA8:
1105 case PPC::ADDItocL:
1106 case PPC::LOAD_STACK_GUARD:
1107 case PPC::XXLXORz:
1108 case PPC::XXLXORspz:
1109 case PPC::XXLXORdpz:
1110 case PPC::XXLEQVOnes:
1111 case PPC::XXSPLTI32DX:
1112 case PPC::V_SET0B:
1113 case PPC::V_SET0H:
1114 case PPC::V_SET0:
1115 case PPC::V_SETALLONESB:
1116 case PPC::V_SETALLONESH:
1117 case PPC::V_SETALLONES:
1118 case PPC::CRSET:
1119 case PPC::CRUNSET:
1120 case PPC::XXSETACCZ:
1121 return true;
1122 }
1123 return false;
1124 }
1125
isStoreToStackSlot(const MachineInstr & MI,int & FrameIndex) const1126 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
1127 int &FrameIndex) const {
1128 unsigned Opcode = MI.getOpcode();
1129 const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1130 const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
1131
1132 if (End != std::find(OpcodesForSpill, End, Opcode)) {
1133 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
1134 MI.getOperand(2).isFI()) {
1135 FrameIndex = MI.getOperand(2).getIndex();
1136 return MI.getOperand(0).getReg();
1137 }
1138 }
1139 return 0;
1140 }
1141
commuteInstructionImpl(MachineInstr & MI,bool NewMI,unsigned OpIdx1,unsigned OpIdx2) const1142 MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
1143 unsigned OpIdx1,
1144 unsigned OpIdx2) const {
1145 MachineFunction &MF = *MI.getParent()->getParent();
1146
1147 // Normal instructions can be commuted the obvious way.
1148 if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMI_rec)
1149 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1150 // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
1151 // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
1152 // changing the relative order of the mask operands might change what happens
1153 // to the high-bits of the mask (and, thus, the result).
1154
1155 // Cannot commute if it has a non-zero rotate count.
1156 if (MI.getOperand(3).getImm() != 0)
1157 return nullptr;
1158
1159 // If we have a zero rotate count, we have:
1160 // M = mask(MB,ME)
1161 // Op0 = (Op1 & ~M) | (Op2 & M)
1162 // Change this to:
1163 // M = mask((ME+1)&31, (MB-1)&31)
1164 // Op0 = (Op2 & ~M) | (Op1 & M)
1165
1166 // Swap op1/op2
1167 assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
1168 "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMI_rec.");
1169 Register Reg0 = MI.getOperand(0).getReg();
1170 Register Reg1 = MI.getOperand(1).getReg();
1171 Register Reg2 = MI.getOperand(2).getReg();
1172 unsigned SubReg1 = MI.getOperand(1).getSubReg();
1173 unsigned SubReg2 = MI.getOperand(2).getSubReg();
1174 bool Reg1IsKill = MI.getOperand(1).isKill();
1175 bool Reg2IsKill = MI.getOperand(2).isKill();
1176 bool ChangeReg0 = false;
1177 // If machine instrs are no longer in two-address forms, update
1178 // destination register as well.
1179 if (Reg0 == Reg1) {
1180 // Must be two address instruction!
1181 assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
1182 "Expecting a two-address instruction!");
1183 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
1184 Reg2IsKill = false;
1185 ChangeReg0 = true;
1186 }
1187
1188 // Masks.
1189 unsigned MB = MI.getOperand(4).getImm();
1190 unsigned ME = MI.getOperand(5).getImm();
1191
1192 // We can't commute a trivial mask (there is no way to represent an all-zero
1193 // mask).
1194 if (MB == 0 && ME == 31)
1195 return nullptr;
1196
1197 if (NewMI) {
1198 // Create a new instruction.
1199 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
1200 bool Reg0IsDead = MI.getOperand(0).isDead();
1201 return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
1202 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
1203 .addReg(Reg2, getKillRegState(Reg2IsKill))
1204 .addReg(Reg1, getKillRegState(Reg1IsKill))
1205 .addImm((ME + 1) & 31)
1206 .addImm((MB - 1) & 31);
1207 }
1208
1209 if (ChangeReg0) {
1210 MI.getOperand(0).setReg(Reg2);
1211 MI.getOperand(0).setSubReg(SubReg2);
1212 }
1213 MI.getOperand(2).setReg(Reg1);
1214 MI.getOperand(1).setReg(Reg2);
1215 MI.getOperand(2).setSubReg(SubReg1);
1216 MI.getOperand(1).setSubReg(SubReg2);
1217 MI.getOperand(2).setIsKill(Reg1IsKill);
1218 MI.getOperand(1).setIsKill(Reg2IsKill);
1219
1220 // Swap the mask around.
1221 MI.getOperand(4).setImm((ME + 1) & 31);
1222 MI.getOperand(5).setImm((MB - 1) & 31);
1223 return &MI;
1224 }
1225
findCommutedOpIndices(const MachineInstr & MI,unsigned & SrcOpIdx1,unsigned & SrcOpIdx2) const1226 bool PPCInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
1227 unsigned &SrcOpIdx1,
1228 unsigned &SrcOpIdx2) const {
1229 // For VSX A-Type FMA instructions, it is the first two operands that can be
1230 // commuted, however, because the non-encoded tied input operand is listed
1231 // first, the operands to swap are actually the second and third.
1232
1233 int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
1234 if (AltOpc == -1)
1235 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1236
1237 // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
1238 // and SrcOpIdx2.
1239 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
1240 }
1241
insertNoop(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI) const1242 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
1243 MachineBasicBlock::iterator MI) const {
1244 // This function is used for scheduling, and the nop wanted here is the type
1245 // that terminates dispatch groups on the POWER cores.
1246 unsigned Directive = Subtarget.getCPUDirective();
1247 unsigned Opcode;
1248 switch (Directive) {
1249 default: Opcode = PPC::NOP; break;
1250 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
1251 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
1252 case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
1253 // FIXME: Update when POWER9 scheduling model is ready.
1254 case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
1255 }
1256
1257 DebugLoc DL;
1258 BuildMI(MBB, MI, DL, get(Opcode));
1259 }
1260
1261 /// Return the noop instruction to use for a noop.
getNop() const1262 MCInst PPCInstrInfo::getNop() const {
1263 MCInst Nop;
1264 Nop.setOpcode(PPC::NOP);
1265 return Nop;
1266 }
1267
1268 // Branch analysis.
1269 // Note: If the condition register is set to CTR or CTR8 then this is a
1270 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
analyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const1271 bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
1272 MachineBasicBlock *&TBB,
1273 MachineBasicBlock *&FBB,
1274 SmallVectorImpl<MachineOperand> &Cond,
1275 bool AllowModify) const {
1276 bool isPPC64 = Subtarget.isPPC64();
1277
1278 // If the block has no terminators, it just falls into the block after it.
1279 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
1280 if (I == MBB.end())
1281 return false;
1282
1283 if (!isUnpredicatedTerminator(*I))
1284 return false;
1285
1286 if (AllowModify) {
1287 // If the BB ends with an unconditional branch to the fallthrough BB,
1288 // we eliminate the branch instruction.
1289 if (I->getOpcode() == PPC::B &&
1290 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1291 I->eraseFromParent();
1292
1293 // We update iterator after deleting the last branch.
1294 I = MBB.getLastNonDebugInstr();
1295 if (I == MBB.end() || !isUnpredicatedTerminator(*I))
1296 return false;
1297 }
1298 }
1299
1300 // Get the last instruction in the block.
1301 MachineInstr &LastInst = *I;
1302
1303 // If there is only one terminator instruction, process it.
1304 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
1305 if (LastInst.getOpcode() == PPC::B) {
1306 if (!LastInst.getOperand(0).isMBB())
1307 return true;
1308 TBB = LastInst.getOperand(0).getMBB();
1309 return false;
1310 } else if (LastInst.getOpcode() == PPC::BCC) {
1311 if (!LastInst.getOperand(2).isMBB())
1312 return true;
1313 // Block ends with fall-through condbranch.
1314 TBB = LastInst.getOperand(2).getMBB();
1315 Cond.push_back(LastInst.getOperand(0));
1316 Cond.push_back(LastInst.getOperand(1));
1317 return false;
1318 } else if (LastInst.getOpcode() == PPC::BC) {
1319 if (!LastInst.getOperand(1).isMBB())
1320 return true;
1321 // Block ends with fall-through condbranch.
1322 TBB = LastInst.getOperand(1).getMBB();
1323 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
1324 Cond.push_back(LastInst.getOperand(0));
1325 return false;
1326 } else if (LastInst.getOpcode() == PPC::BCn) {
1327 if (!LastInst.getOperand(1).isMBB())
1328 return true;
1329 // Block ends with fall-through condbranch.
1330 TBB = LastInst.getOperand(1).getMBB();
1331 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
1332 Cond.push_back(LastInst.getOperand(0));
1333 return false;
1334 } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
1335 LastInst.getOpcode() == PPC::BDNZ) {
1336 if (!LastInst.getOperand(0).isMBB())
1337 return true;
1338 if (DisableCTRLoopAnal)
1339 return true;
1340 TBB = LastInst.getOperand(0).getMBB();
1341 Cond.push_back(MachineOperand::CreateImm(1));
1342 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
1343 true));
1344 return false;
1345 } else if (LastInst.getOpcode() == PPC::BDZ8 ||
1346 LastInst.getOpcode() == PPC::BDZ) {
1347 if (!LastInst.getOperand(0).isMBB())
1348 return true;
1349 if (DisableCTRLoopAnal)
1350 return true;
1351 TBB = LastInst.getOperand(0).getMBB();
1352 Cond.push_back(MachineOperand::CreateImm(0));
1353 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
1354 true));
1355 return false;
1356 }
1357
1358 // Otherwise, don't know what this is.
1359 return true;
1360 }
1361
1362 // Get the instruction before it if it's a terminator.
1363 MachineInstr &SecondLastInst = *I;
1364
1365 // If there are three terminators, we don't know what sort of block this is.
1366 if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
1367 return true;
1368
1369 // If the block ends with PPC::B and PPC:BCC, handle it.
1370 if (SecondLastInst.getOpcode() == PPC::BCC &&
1371 LastInst.getOpcode() == PPC::B) {
1372 if (!SecondLastInst.getOperand(2).isMBB() ||
1373 !LastInst.getOperand(0).isMBB())
1374 return true;
1375 TBB = SecondLastInst.getOperand(2).getMBB();
1376 Cond.push_back(SecondLastInst.getOperand(0));
1377 Cond.push_back(SecondLastInst.getOperand(1));
1378 FBB = LastInst.getOperand(0).getMBB();
1379 return false;
1380 } else if (SecondLastInst.getOpcode() == PPC::BC &&
1381 LastInst.getOpcode() == PPC::B) {
1382 if (!SecondLastInst.getOperand(1).isMBB() ||
1383 !LastInst.getOperand(0).isMBB())
1384 return true;
1385 TBB = SecondLastInst.getOperand(1).getMBB();
1386 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
1387 Cond.push_back(SecondLastInst.getOperand(0));
1388 FBB = LastInst.getOperand(0).getMBB();
1389 return false;
1390 } else if (SecondLastInst.getOpcode() == PPC::BCn &&
1391 LastInst.getOpcode() == PPC::B) {
1392 if (!SecondLastInst.getOperand(1).isMBB() ||
1393 !LastInst.getOperand(0).isMBB())
1394 return true;
1395 TBB = SecondLastInst.getOperand(1).getMBB();
1396 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
1397 Cond.push_back(SecondLastInst.getOperand(0));
1398 FBB = LastInst.getOperand(0).getMBB();
1399 return false;
1400 } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
1401 SecondLastInst.getOpcode() == PPC::BDNZ) &&
1402 LastInst.getOpcode() == PPC::B) {
1403 if (!SecondLastInst.getOperand(0).isMBB() ||
1404 !LastInst.getOperand(0).isMBB())
1405 return true;
1406 if (DisableCTRLoopAnal)
1407 return true;
1408 TBB = SecondLastInst.getOperand(0).getMBB();
1409 Cond.push_back(MachineOperand::CreateImm(1));
1410 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
1411 true));
1412 FBB = LastInst.getOperand(0).getMBB();
1413 return false;
1414 } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
1415 SecondLastInst.getOpcode() == PPC::BDZ) &&
1416 LastInst.getOpcode() == PPC::B) {
1417 if (!SecondLastInst.getOperand(0).isMBB() ||
1418 !LastInst.getOperand(0).isMBB())
1419 return true;
1420 if (DisableCTRLoopAnal)
1421 return true;
1422 TBB = SecondLastInst.getOperand(0).getMBB();
1423 Cond.push_back(MachineOperand::CreateImm(0));
1424 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
1425 true));
1426 FBB = LastInst.getOperand(0).getMBB();
1427 return false;
1428 }
1429
1430 // If the block ends with two PPC:Bs, handle it. The second one is not
1431 // executed, so remove it.
1432 if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
1433 if (!SecondLastInst.getOperand(0).isMBB())
1434 return true;
1435 TBB = SecondLastInst.getOperand(0).getMBB();
1436 I = LastInst;
1437 if (AllowModify)
1438 I->eraseFromParent();
1439 return false;
1440 }
1441
1442 // Otherwise, can't handle this.
1443 return true;
1444 }
1445
removeBranch(MachineBasicBlock & MBB,int * BytesRemoved) const1446 unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB,
1447 int *BytesRemoved) const {
1448 assert(!BytesRemoved && "code size not handled");
1449
1450 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
1451 if (I == MBB.end())
1452 return 0;
1453
1454 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
1455 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
1456 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
1457 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
1458 return 0;
1459
1460 // Remove the branch.
1461 I->eraseFromParent();
1462
1463 I = MBB.end();
1464
1465 if (I == MBB.begin()) return 1;
1466 --I;
1467 if (I->getOpcode() != PPC::BCC &&
1468 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
1469 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
1470 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
1471 return 1;
1472
1473 // Remove the branch.
1474 I->eraseFromParent();
1475 return 2;
1476 }
1477
insertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,ArrayRef<MachineOperand> Cond,const DebugLoc & DL,int * BytesAdded) const1478 unsigned PPCInstrInfo::insertBranch(MachineBasicBlock &MBB,
1479 MachineBasicBlock *TBB,
1480 MachineBasicBlock *FBB,
1481 ArrayRef<MachineOperand> Cond,
1482 const DebugLoc &DL,
1483 int *BytesAdded) const {
1484 // Shouldn't be a fall through.
1485 assert(TBB && "insertBranch must not be told to insert a fallthrough");
1486 assert((Cond.size() == 2 || Cond.size() == 0) &&
1487 "PPC branch conditions have two components!");
1488 assert(!BytesAdded && "code size not handled");
1489
1490 bool isPPC64 = Subtarget.isPPC64();
1491
1492 // One-way branch.
1493 if (!FBB) {
1494 if (Cond.empty()) // Unconditional branch
1495 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
1496 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
1497 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
1498 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1499 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
1500 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
1501 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
1502 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
1503 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
1504 else // Conditional branch
1505 BuildMI(&MBB, DL, get(PPC::BCC))
1506 .addImm(Cond[0].getImm())
1507 .add(Cond[1])
1508 .addMBB(TBB);
1509 return 1;
1510 }
1511
1512 // Two-way Conditional Branch.
1513 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
1514 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
1515 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1516 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
1517 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
1518 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
1519 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
1520 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
1521 else
1522 BuildMI(&MBB, DL, get(PPC::BCC))
1523 .addImm(Cond[0].getImm())
1524 .add(Cond[1])
1525 .addMBB(TBB);
1526 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
1527 return 2;
1528 }
1529
1530 // Select analysis.
canInsertSelect(const MachineBasicBlock & MBB,ArrayRef<MachineOperand> Cond,Register DstReg,Register TrueReg,Register FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles) const1531 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
1532 ArrayRef<MachineOperand> Cond,
1533 Register DstReg, Register TrueReg,
1534 Register FalseReg, int &CondCycles,
1535 int &TrueCycles, int &FalseCycles) const {
1536 if (Cond.size() != 2)
1537 return false;
1538
1539 // If this is really a bdnz-like condition, then it cannot be turned into a
1540 // select.
1541 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
1542 return false;
1543
1544 // Check register classes.
1545 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1546 const TargetRegisterClass *RC =
1547 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
1548 if (!RC)
1549 return false;
1550
1551 // isel is for regular integer GPRs only.
1552 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
1553 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
1554 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
1555 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
1556 return false;
1557
1558 // FIXME: These numbers are for the A2, how well they work for other cores is
1559 // an open question. On the A2, the isel instruction has a 2-cycle latency
1560 // but single-cycle throughput. These numbers are used in combination with
1561 // the MispredictPenalty setting from the active SchedMachineModel.
1562 CondCycles = 1;
1563 TrueCycles = 1;
1564 FalseCycles = 1;
1565
1566 return true;
1567 }
1568
insertSelect(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const DebugLoc & dl,Register DestReg,ArrayRef<MachineOperand> Cond,Register TrueReg,Register FalseReg) const1569 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
1570 MachineBasicBlock::iterator MI,
1571 const DebugLoc &dl, Register DestReg,
1572 ArrayRef<MachineOperand> Cond, Register TrueReg,
1573 Register FalseReg) const {
1574 assert(Cond.size() == 2 &&
1575 "PPC branch conditions have two components!");
1576
1577 // Get the register classes.
1578 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1579 const TargetRegisterClass *RC =
1580 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
1581 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
1582
1583 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
1584 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
1585 assert((Is64Bit ||
1586 PPC::GPRCRegClass.hasSubClassEq(RC) ||
1587 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
1588 "isel is for regular integer GPRs only");
1589
1590 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
1591 auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
1592
1593 unsigned SubIdx = 0;
1594 bool SwapOps = false;
1595 switch (SelectPred) {
1596 case PPC::PRED_EQ:
1597 case PPC::PRED_EQ_MINUS:
1598 case PPC::PRED_EQ_PLUS:
1599 SubIdx = PPC::sub_eq; SwapOps = false; break;
1600 case PPC::PRED_NE:
1601 case PPC::PRED_NE_MINUS:
1602 case PPC::PRED_NE_PLUS:
1603 SubIdx = PPC::sub_eq; SwapOps = true; break;
1604 case PPC::PRED_LT:
1605 case PPC::PRED_LT_MINUS:
1606 case PPC::PRED_LT_PLUS:
1607 SubIdx = PPC::sub_lt; SwapOps = false; break;
1608 case PPC::PRED_GE:
1609 case PPC::PRED_GE_MINUS:
1610 case PPC::PRED_GE_PLUS:
1611 SubIdx = PPC::sub_lt; SwapOps = true; break;
1612 case PPC::PRED_GT:
1613 case PPC::PRED_GT_MINUS:
1614 case PPC::PRED_GT_PLUS:
1615 SubIdx = PPC::sub_gt; SwapOps = false; break;
1616 case PPC::PRED_LE:
1617 case PPC::PRED_LE_MINUS:
1618 case PPC::PRED_LE_PLUS:
1619 SubIdx = PPC::sub_gt; SwapOps = true; break;
1620 case PPC::PRED_UN:
1621 case PPC::PRED_UN_MINUS:
1622 case PPC::PRED_UN_PLUS:
1623 SubIdx = PPC::sub_un; SwapOps = false; break;
1624 case PPC::PRED_NU:
1625 case PPC::PRED_NU_MINUS:
1626 case PPC::PRED_NU_PLUS:
1627 SubIdx = PPC::sub_un; SwapOps = true; break;
1628 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
1629 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
1630 }
1631
1632 Register FirstReg = SwapOps ? FalseReg : TrueReg,
1633 SecondReg = SwapOps ? TrueReg : FalseReg;
1634
1635 // The first input register of isel cannot be r0. If it is a member
1636 // of a register class that can be r0, then copy it first (the
1637 // register allocator should eliminate the copy).
1638 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
1639 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
1640 const TargetRegisterClass *FirstRC =
1641 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
1642 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
1643 Register OldFirstReg = FirstReg;
1644 FirstReg = MRI.createVirtualRegister(FirstRC);
1645 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
1646 .addReg(OldFirstReg);
1647 }
1648
1649 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
1650 .addReg(FirstReg).addReg(SecondReg)
1651 .addReg(Cond[1].getReg(), 0, SubIdx);
1652 }
1653
getCRBitValue(unsigned CRBit)1654 static unsigned getCRBitValue(unsigned CRBit) {
1655 unsigned Ret = 4;
1656 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
1657 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
1658 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
1659 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
1660 Ret = 3;
1661 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
1662 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
1663 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
1664 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
1665 Ret = 2;
1666 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
1667 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
1668 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
1669 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
1670 Ret = 1;
1671 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
1672 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
1673 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
1674 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
1675 Ret = 0;
1676
1677 assert(Ret != 4 && "Invalid CR bit register");
1678 return Ret;
1679 }
1680
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,MCRegister DestReg,MCRegister SrcReg,bool KillSrc) const1681 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1682 MachineBasicBlock::iterator I,
1683 const DebugLoc &DL, MCRegister DestReg,
1684 MCRegister SrcReg, bool KillSrc) const {
1685 // We can end up with self copies and similar things as a result of VSX copy
1686 // legalization. Promote them here.
1687 const TargetRegisterInfo *TRI = &getRegisterInfo();
1688 if (PPC::F8RCRegClass.contains(DestReg) &&
1689 PPC::VSRCRegClass.contains(SrcReg)) {
1690 MCRegister SuperReg =
1691 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
1692
1693 if (VSXSelfCopyCrash && SrcReg == SuperReg)
1694 llvm_unreachable("nop VSX copy");
1695
1696 DestReg = SuperReg;
1697 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
1698 PPC::VSRCRegClass.contains(DestReg)) {
1699 MCRegister SuperReg =
1700 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
1701
1702 if (VSXSelfCopyCrash && DestReg == SuperReg)
1703 llvm_unreachable("nop VSX copy");
1704
1705 SrcReg = SuperReg;
1706 }
1707
1708 // Different class register copy
1709 if (PPC::CRBITRCRegClass.contains(SrcReg) &&
1710 PPC::GPRCRegClass.contains(DestReg)) {
1711 MCRegister CRReg = getCRFromCRBit(SrcReg);
1712 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
1713 getKillRegState(KillSrc);
1714 // Rotate the CR bit in the CR fields to be the least significant bit and
1715 // then mask with 0x1 (MB = ME = 31).
1716 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
1717 .addReg(DestReg, RegState::Kill)
1718 .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
1719 .addImm(31)
1720 .addImm(31);
1721 return;
1722 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
1723 (PPC::G8RCRegClass.contains(DestReg) ||
1724 PPC::GPRCRegClass.contains(DestReg))) {
1725 bool Is64Bit = PPC::G8RCRegClass.contains(DestReg);
1726 unsigned MvCode = Is64Bit ? PPC::MFOCRF8 : PPC::MFOCRF;
1727 unsigned ShCode = Is64Bit ? PPC::RLWINM8 : PPC::RLWINM;
1728 unsigned CRNum = TRI->getEncodingValue(SrcReg);
1729 BuildMI(MBB, I, DL, get(MvCode), DestReg).addReg(SrcReg);
1730 getKillRegState(KillSrc);
1731 if (CRNum == 7)
1732 return;
1733 // Shift the CR bits to make the CR field in the lowest 4 bits of GRC.
1734 BuildMI(MBB, I, DL, get(ShCode), DestReg)
1735 .addReg(DestReg, RegState::Kill)
1736 .addImm(CRNum * 4 + 4)
1737 .addImm(28)
1738 .addImm(31);
1739 return;
1740 } else if (PPC::G8RCRegClass.contains(SrcReg) &&
1741 PPC::VSFRCRegClass.contains(DestReg)) {
1742 assert(Subtarget.hasDirectMove() &&
1743 "Subtarget doesn't support directmove, don't know how to copy.");
1744 BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
1745 NumGPRtoVSRSpill++;
1746 getKillRegState(KillSrc);
1747 return;
1748 } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
1749 PPC::G8RCRegClass.contains(DestReg)) {
1750 assert(Subtarget.hasDirectMove() &&
1751 "Subtarget doesn't support directmove, don't know how to copy.");
1752 BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
1753 getKillRegState(KillSrc);
1754 return;
1755 } else if (PPC::SPERCRegClass.contains(SrcReg) &&
1756 PPC::GPRCRegClass.contains(DestReg)) {
1757 BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
1758 getKillRegState(KillSrc);
1759 return;
1760 } else if (PPC::GPRCRegClass.contains(SrcReg) &&
1761 PPC::SPERCRegClass.contains(DestReg)) {
1762 BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
1763 getKillRegState(KillSrc);
1764 return;
1765 }
1766
1767 unsigned Opc;
1768 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
1769 Opc = PPC::OR;
1770 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
1771 Opc = PPC::OR8;
1772 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
1773 Opc = PPC::FMR;
1774 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
1775 Opc = PPC::MCRF;
1776 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
1777 Opc = PPC::VOR;
1778 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
1779 // There are two different ways this can be done:
1780 // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
1781 // issue in VSU pipeline 0.
1782 // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
1783 // can go to either pipeline.
1784 // We'll always use xxlor here, because in practically all cases where
1785 // copies are generated, they are close enough to some use that the
1786 // lower-latency form is preferable.
1787 Opc = PPC::XXLOR;
1788 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
1789 PPC::VSSRCRegClass.contains(DestReg, SrcReg))
1790 Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
1791 else if (Subtarget.pairedVectorMemops() &&
1792 PPC::VSRpRCRegClass.contains(DestReg, SrcReg)) {
1793 if (SrcReg > PPC::VSRp15)
1794 SrcReg = PPC::V0 + (SrcReg - PPC::VSRp16) * 2;
1795 else
1796 SrcReg = PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2;
1797 if (DestReg > PPC::VSRp15)
1798 DestReg = PPC::V0 + (DestReg - PPC::VSRp16) * 2;
1799 else
1800 DestReg = PPC::VSL0 + (DestReg - PPC::VSRp0) * 2;
1801 BuildMI(MBB, I, DL, get(PPC::XXLOR), DestReg).
1802 addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1803 BuildMI(MBB, I, DL, get(PPC::XXLOR), DestReg + 1).
1804 addReg(SrcReg + 1).addReg(SrcReg + 1, getKillRegState(KillSrc));
1805 return;
1806 }
1807 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
1808 Opc = PPC::CROR;
1809 else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
1810 Opc = PPC::EVOR;
1811 else if ((PPC::ACCRCRegClass.contains(DestReg) ||
1812 PPC::UACCRCRegClass.contains(DestReg)) &&
1813 (PPC::ACCRCRegClass.contains(SrcReg) ||
1814 PPC::UACCRCRegClass.contains(SrcReg))) {
1815 // If primed, de-prime the source register, copy the individual registers
1816 // and prime the destination if needed. The vector subregisters are
1817 // vs[(u)acc * 4] - vs[(u)acc * 4 + 3]. If the copy is not a kill and the
1818 // source is primed, we need to re-prime it after the copy as well.
1819 PPCRegisterInfo::emitAccCopyInfo(MBB, DestReg, SrcReg);
1820 bool DestPrimed = PPC::ACCRCRegClass.contains(DestReg);
1821 bool SrcPrimed = PPC::ACCRCRegClass.contains(SrcReg);
1822 MCRegister VSLSrcReg =
1823 PPC::VSL0 + (SrcReg - (SrcPrimed ? PPC::ACC0 : PPC::UACC0)) * 4;
1824 MCRegister VSLDestReg =
1825 PPC::VSL0 + (DestReg - (DestPrimed ? PPC::ACC0 : PPC::UACC0)) * 4;
1826 if (SrcPrimed)
1827 BuildMI(MBB, I, DL, get(PPC::XXMFACC), SrcReg).addReg(SrcReg);
1828 for (unsigned Idx = 0; Idx < 4; Idx++)
1829 BuildMI(MBB, I, DL, get(PPC::XXLOR), VSLDestReg + Idx)
1830 .addReg(VSLSrcReg + Idx)
1831 .addReg(VSLSrcReg + Idx, getKillRegState(KillSrc));
1832 if (DestPrimed)
1833 BuildMI(MBB, I, DL, get(PPC::XXMTACC), DestReg).addReg(DestReg);
1834 if (SrcPrimed && !KillSrc)
1835 BuildMI(MBB, I, DL, get(PPC::XXMTACC), SrcReg).addReg(SrcReg);
1836 return;
1837 } else
1838 llvm_unreachable("Impossible reg-to-reg copy");
1839
1840 const MCInstrDesc &MCID = get(Opc);
1841 if (MCID.getNumOperands() == 3)
1842 BuildMI(MBB, I, DL, MCID, DestReg)
1843 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1844 else
1845 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1846 }
1847
getSpillIndex(const TargetRegisterClass * RC) const1848 unsigned PPCInstrInfo::getSpillIndex(const TargetRegisterClass *RC) const {
1849 int OpcodeIndex = 0;
1850
1851 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1852 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1853 OpcodeIndex = SOK_Int4Spill;
1854 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1855 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1856 OpcodeIndex = SOK_Int8Spill;
1857 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1858 OpcodeIndex = SOK_Float8Spill;
1859 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1860 OpcodeIndex = SOK_Float4Spill;
1861 } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1862 OpcodeIndex = SOK_SPESpill;
1863 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1864 OpcodeIndex = SOK_CRSpill;
1865 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1866 OpcodeIndex = SOK_CRBitSpill;
1867 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1868 OpcodeIndex = SOK_VRVectorSpill;
1869 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1870 OpcodeIndex = SOK_VSXVectorSpill;
1871 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1872 OpcodeIndex = SOK_VectorFloat8Spill;
1873 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1874 OpcodeIndex = SOK_VectorFloat4Spill;
1875 } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1876 OpcodeIndex = SOK_SpillToVSR;
1877 } else if (PPC::ACCRCRegClass.hasSubClassEq(RC)) {
1878 assert(Subtarget.pairedVectorMemops() &&
1879 "Register unexpected when paired memops are disabled.");
1880 OpcodeIndex = SOK_AccumulatorSpill;
1881 } else if (PPC::UACCRCRegClass.hasSubClassEq(RC)) {
1882 assert(Subtarget.pairedVectorMemops() &&
1883 "Register unexpected when paired memops are disabled.");
1884 OpcodeIndex = SOK_UAccumulatorSpill;
1885 } else if (PPC::VSRpRCRegClass.hasSubClassEq(RC)) {
1886 assert(Subtarget.pairedVectorMemops() &&
1887 "Register unexpected when paired memops are disabled.");
1888 OpcodeIndex = SOK_PairedVecSpill;
1889 } else {
1890 llvm_unreachable("Unknown regclass!");
1891 }
1892 return OpcodeIndex;
1893 }
1894
1895 unsigned
getStoreOpcodeForSpill(const TargetRegisterClass * RC) const1896 PPCInstrInfo::getStoreOpcodeForSpill(const TargetRegisterClass *RC) const {
1897 const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1898 return OpcodesForSpill[getSpillIndex(RC)];
1899 }
1900
1901 unsigned
getLoadOpcodeForSpill(const TargetRegisterClass * RC) const1902 PPCInstrInfo::getLoadOpcodeForSpill(const TargetRegisterClass *RC) const {
1903 const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1904 return OpcodesForSpill[getSpillIndex(RC)];
1905 }
1906
StoreRegToStackSlot(MachineFunction & MF,unsigned SrcReg,bool isKill,int FrameIdx,const TargetRegisterClass * RC,SmallVectorImpl<MachineInstr * > & NewMIs) const1907 void PPCInstrInfo::StoreRegToStackSlot(
1908 MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
1909 const TargetRegisterClass *RC,
1910 SmallVectorImpl<MachineInstr *> &NewMIs) const {
1911 unsigned Opcode = getStoreOpcodeForSpill(RC);
1912 DebugLoc DL;
1913
1914 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1915 FuncInfo->setHasSpills();
1916
1917 NewMIs.push_back(addFrameReference(
1918 BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1919 FrameIdx));
1920
1921 if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1922 PPC::CRBITRCRegClass.hasSubClassEq(RC))
1923 FuncInfo->setSpillsCR();
1924
1925 if (isXFormMemOp(Opcode))
1926 FuncInfo->setHasNonRISpills();
1927 }
1928
storeRegToStackSlotNoUpd(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned SrcReg,bool isKill,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const1929 void PPCInstrInfo::storeRegToStackSlotNoUpd(
1930 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg,
1931 bool isKill, int FrameIdx, const TargetRegisterClass *RC,
1932 const TargetRegisterInfo *TRI) const {
1933 MachineFunction &MF = *MBB.getParent();
1934 SmallVector<MachineInstr *, 4> NewMIs;
1935
1936 StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1937
1938 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1939 MBB.insert(MI, NewMIs[i]);
1940
1941 const MachineFrameInfo &MFI = MF.getFrameInfo();
1942 MachineMemOperand *MMO = MF.getMachineMemOperand(
1943 MachinePointerInfo::getFixedStack(MF, FrameIdx),
1944 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
1945 MFI.getObjectAlign(FrameIdx));
1946 NewMIs.back()->addMemOperand(MF, MMO);
1947 }
1948
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,Register SrcReg,bool isKill,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const1949 void PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1950 MachineBasicBlock::iterator MI,
1951 Register SrcReg, bool isKill,
1952 int FrameIdx,
1953 const TargetRegisterClass *RC,
1954 const TargetRegisterInfo *TRI) const {
1955 // We need to avoid a situation in which the value from a VRRC register is
1956 // spilled using an Altivec instruction and reloaded into a VSRC register
1957 // using a VSX instruction. The issue with this is that the VSX
1958 // load/store instructions swap the doublewords in the vector and the Altivec
1959 // ones don't. The register classes on the spill/reload may be different if
1960 // the register is defined using an Altivec instruction and is then used by a
1961 // VSX instruction.
1962 RC = updatedRC(RC);
1963 storeRegToStackSlotNoUpd(MBB, MI, SrcReg, isKill, FrameIdx, RC, TRI);
1964 }
1965
LoadRegFromStackSlot(MachineFunction & MF,const DebugLoc & DL,unsigned DestReg,int FrameIdx,const TargetRegisterClass * RC,SmallVectorImpl<MachineInstr * > & NewMIs) const1966 void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1967 unsigned DestReg, int FrameIdx,
1968 const TargetRegisterClass *RC,
1969 SmallVectorImpl<MachineInstr *> &NewMIs)
1970 const {
1971 unsigned Opcode = getLoadOpcodeForSpill(RC);
1972 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1973 FrameIdx));
1974 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1975
1976 if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1977 PPC::CRBITRCRegClass.hasSubClassEq(RC))
1978 FuncInfo->setSpillsCR();
1979
1980 if (isXFormMemOp(Opcode))
1981 FuncInfo->setHasNonRISpills();
1982 }
1983
loadRegFromStackSlotNoUpd(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned DestReg,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const1984 void PPCInstrInfo::loadRegFromStackSlotNoUpd(
1985 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg,
1986 int FrameIdx, const TargetRegisterClass *RC,
1987 const TargetRegisterInfo *TRI) const {
1988 MachineFunction &MF = *MBB.getParent();
1989 SmallVector<MachineInstr*, 4> NewMIs;
1990 DebugLoc DL;
1991 if (MI != MBB.end()) DL = MI->getDebugLoc();
1992
1993 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1994 FuncInfo->setHasSpills();
1995
1996 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
1997
1998 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1999 MBB.insert(MI, NewMIs[i]);
2000
2001 const MachineFrameInfo &MFI = MF.getFrameInfo();
2002 MachineMemOperand *MMO = MF.getMachineMemOperand(
2003 MachinePointerInfo::getFixedStack(MF, FrameIdx),
2004 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
2005 MFI.getObjectAlign(FrameIdx));
2006 NewMIs.back()->addMemOperand(MF, MMO);
2007 }
2008
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,Register DestReg,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const2009 void PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2010 MachineBasicBlock::iterator MI,
2011 Register DestReg, int FrameIdx,
2012 const TargetRegisterClass *RC,
2013 const TargetRegisterInfo *TRI) const {
2014 // We need to avoid a situation in which the value from a VRRC register is
2015 // spilled using an Altivec instruction and reloaded into a VSRC register
2016 // using a VSX instruction. The issue with this is that the VSX
2017 // load/store instructions swap the doublewords in the vector and the Altivec
2018 // ones don't. The register classes on the spill/reload may be different if
2019 // the register is defined using an Altivec instruction and is then used by a
2020 // VSX instruction.
2021 RC = updatedRC(RC);
2022
2023 loadRegFromStackSlotNoUpd(MBB, MI, DestReg, FrameIdx, RC, TRI);
2024 }
2025
2026 bool PPCInstrInfo::
reverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const2027 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2028 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
2029 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
2030 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
2031 else
2032 // Leave the CR# the same, but invert the condition.
2033 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
2034 return false;
2035 }
2036
2037 // For some instructions, it is legal to fold ZERO into the RA register field.
2038 // This function performs that fold by replacing the operand with PPC::ZERO,
2039 // it does not consider whether the load immediate zero is no longer in use.
onlyFoldImmediate(MachineInstr & UseMI,MachineInstr & DefMI,Register Reg) const2040 bool PPCInstrInfo::onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
2041 Register Reg) const {
2042 // A zero immediate should always be loaded with a single li.
2043 unsigned DefOpc = DefMI.getOpcode();
2044 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
2045 return false;
2046 if (!DefMI.getOperand(1).isImm())
2047 return false;
2048 if (DefMI.getOperand(1).getImm() != 0)
2049 return false;
2050
2051 // Note that we cannot here invert the arguments of an isel in order to fold
2052 // a ZERO into what is presented as the second argument. All we have here
2053 // is the condition bit, and that might come from a CR-logical bit operation.
2054
2055 const MCInstrDesc &UseMCID = UseMI.getDesc();
2056
2057 // Only fold into real machine instructions.
2058 if (UseMCID.isPseudo())
2059 return false;
2060
2061 // We need to find which of the User's operands is to be folded, that will be
2062 // the operand that matches the given register ID.
2063 unsigned UseIdx;
2064 for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
2065 if (UseMI.getOperand(UseIdx).isReg() &&
2066 UseMI.getOperand(UseIdx).getReg() == Reg)
2067 break;
2068
2069 assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
2070 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
2071
2072 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
2073
2074 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
2075 // register (which might also be specified as a pointer class kind).
2076 if (UseInfo->isLookupPtrRegClass()) {
2077 if (UseInfo->RegClass /* Kind */ != 1)
2078 return false;
2079 } else {
2080 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
2081 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
2082 return false;
2083 }
2084
2085 // Make sure this is not tied to an output register (or otherwise
2086 // constrained). This is true for ST?UX registers, for example, which
2087 // are tied to their output registers.
2088 if (UseInfo->Constraints != 0)
2089 return false;
2090
2091 MCRegister ZeroReg;
2092 if (UseInfo->isLookupPtrRegClass()) {
2093 bool isPPC64 = Subtarget.isPPC64();
2094 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
2095 } else {
2096 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
2097 PPC::ZERO8 : PPC::ZERO;
2098 }
2099
2100 UseMI.getOperand(UseIdx).setReg(ZeroReg);
2101 return true;
2102 }
2103
2104 // Folds zero into instructions which have a load immediate zero as an operand
2105 // but also recognize zero as immediate zero. If the definition of the load
2106 // has no more users it is deleted.
FoldImmediate(MachineInstr & UseMI,MachineInstr & DefMI,Register Reg,MachineRegisterInfo * MRI) const2107 bool PPCInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
2108 Register Reg, MachineRegisterInfo *MRI) const {
2109 bool Changed = onlyFoldImmediate(UseMI, DefMI, Reg);
2110 if (MRI->use_nodbg_empty(Reg))
2111 DefMI.eraseFromParent();
2112 return Changed;
2113 }
2114
MBBDefinesCTR(MachineBasicBlock & MBB)2115 static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
2116 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
2117 I != IE; ++I)
2118 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
2119 return true;
2120 return false;
2121 }
2122
2123 // We should make sure that, if we're going to predicate both sides of a
2124 // condition (a diamond), that both sides don't define the counter register. We
2125 // can predicate counter-decrement-based branches, but while that predicates
2126 // the branching, it does not predicate the counter decrement. If we tried to
2127 // merge the triangle into one predicated block, we'd decrement the counter
2128 // twice.
isProfitableToIfCvt(MachineBasicBlock & TMBB,unsigned NumT,unsigned ExtraT,MachineBasicBlock & FMBB,unsigned NumF,unsigned ExtraF,BranchProbability Probability) const2129 bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
2130 unsigned NumT, unsigned ExtraT,
2131 MachineBasicBlock &FMBB,
2132 unsigned NumF, unsigned ExtraF,
2133 BranchProbability Probability) const {
2134 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
2135 }
2136
2137
isPredicated(const MachineInstr & MI) const2138 bool PPCInstrInfo::isPredicated(const MachineInstr &MI) const {
2139 // The predicated branches are identified by their type, not really by the
2140 // explicit presence of a predicate. Furthermore, some of them can be
2141 // predicated more than once. Because if conversion won't try to predicate
2142 // any instruction which already claims to be predicated (by returning true
2143 // here), always return false. In doing so, we let isPredicable() be the
2144 // final word on whether not the instruction can be (further) predicated.
2145
2146 return false;
2147 }
2148
isSchedulingBoundary(const MachineInstr & MI,const MachineBasicBlock * MBB,const MachineFunction & MF) const2149 bool PPCInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
2150 const MachineBasicBlock *MBB,
2151 const MachineFunction &MF) const {
2152 // Set MFFS and MTFSF as scheduling boundary to avoid unexpected code motion
2153 // across them, since some FP operations may change content of FPSCR.
2154 // TODO: Model FPSCR in PPC instruction definitions and remove the workaround
2155 if (MI.getOpcode() == PPC::MFFS || MI.getOpcode() == PPC::MTFSF)
2156 return true;
2157 return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
2158 }
2159
PredicateInstruction(MachineInstr & MI,ArrayRef<MachineOperand> Pred) const2160 bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI,
2161 ArrayRef<MachineOperand> Pred) const {
2162 unsigned OpC = MI.getOpcode();
2163 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
2164 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
2165 bool isPPC64 = Subtarget.isPPC64();
2166 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
2167 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
2168 // Need add Def and Use for CTR implicit operand.
2169 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2170 .addReg(Pred[1].getReg(), RegState::Implicit)
2171 .addReg(Pred[1].getReg(), RegState::ImplicitDefine);
2172 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
2173 MI.setDesc(get(PPC::BCLR));
2174 MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
2175 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
2176 MI.setDesc(get(PPC::BCLRn));
2177 MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
2178 } else {
2179 MI.setDesc(get(PPC::BCCLR));
2180 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2181 .addImm(Pred[0].getImm())
2182 .add(Pred[1]);
2183 }
2184
2185 return true;
2186 } else if (OpC == PPC::B) {
2187 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
2188 bool isPPC64 = Subtarget.isPPC64();
2189 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
2190 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
2191 // Need add Def and Use for CTR implicit operand.
2192 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2193 .addReg(Pred[1].getReg(), RegState::Implicit)
2194 .addReg(Pred[1].getReg(), RegState::ImplicitDefine);
2195 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
2196 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
2197 MI.RemoveOperand(0);
2198
2199 MI.setDesc(get(PPC::BC));
2200 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2201 .add(Pred[1])
2202 .addMBB(MBB);
2203 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
2204 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
2205 MI.RemoveOperand(0);
2206
2207 MI.setDesc(get(PPC::BCn));
2208 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2209 .add(Pred[1])
2210 .addMBB(MBB);
2211 } else {
2212 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
2213 MI.RemoveOperand(0);
2214
2215 MI.setDesc(get(PPC::BCC));
2216 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2217 .addImm(Pred[0].getImm())
2218 .add(Pred[1])
2219 .addMBB(MBB);
2220 }
2221
2222 return true;
2223 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL ||
2224 OpC == PPC::BCTRL8) {
2225 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
2226 llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
2227
2228 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
2229 bool isPPC64 = Subtarget.isPPC64();
2230
2231 if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
2232 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
2233 : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
2234 MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
2235 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
2236 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
2237 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
2238 MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
2239 } else {
2240 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
2241 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
2242 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2243 .addImm(Pred[0].getImm())
2244 .add(Pred[1]);
2245 }
2246
2247 // Need add Def and Use for LR implicit operand.
2248 if (setLR)
2249 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2250 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::Implicit)
2251 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::ImplicitDefine);
2252
2253 return true;
2254 }
2255
2256 return false;
2257 }
2258
SubsumesPredicate(ArrayRef<MachineOperand> Pred1,ArrayRef<MachineOperand> Pred2) const2259 bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
2260 ArrayRef<MachineOperand> Pred2) const {
2261 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
2262 assert(Pred2.size() == 2 && "Invalid PPC second predicate");
2263
2264 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
2265 return false;
2266 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
2267 return false;
2268
2269 // P1 can only subsume P2 if they test the same condition register.
2270 if (Pred1[1].getReg() != Pred2[1].getReg())
2271 return false;
2272
2273 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
2274 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
2275
2276 if (P1 == P2)
2277 return true;
2278
2279 // Does P1 subsume P2, e.g. GE subsumes GT.
2280 if (P1 == PPC::PRED_LE &&
2281 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
2282 return true;
2283 if (P1 == PPC::PRED_GE &&
2284 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
2285 return true;
2286
2287 return false;
2288 }
2289
ClobbersPredicate(MachineInstr & MI,std::vector<MachineOperand> & Pred,bool SkipDead) const2290 bool PPCInstrInfo::ClobbersPredicate(MachineInstr &MI,
2291 std::vector<MachineOperand> &Pred,
2292 bool SkipDead) const {
2293 // Note: At the present time, the contents of Pred from this function is
2294 // unused by IfConversion. This implementation follows ARM by pushing the
2295 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
2296 // predicate, instructions defining CTR or CTR8 are also included as
2297 // predicate-defining instructions.
2298
2299 const TargetRegisterClass *RCs[] =
2300 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
2301 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
2302
2303 bool Found = false;
2304 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2305 const MachineOperand &MO = MI.getOperand(i);
2306 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
2307 const TargetRegisterClass *RC = RCs[c];
2308 if (MO.isReg()) {
2309 if (MO.isDef() && RC->contains(MO.getReg())) {
2310 Pred.push_back(MO);
2311 Found = true;
2312 }
2313 } else if (MO.isRegMask()) {
2314 for (TargetRegisterClass::iterator I = RC->begin(),
2315 IE = RC->end(); I != IE; ++I)
2316 if (MO.clobbersPhysReg(*I)) {
2317 Pred.push_back(MO);
2318 Found = true;
2319 }
2320 }
2321 }
2322 }
2323
2324 return Found;
2325 }
2326
analyzeCompare(const MachineInstr & MI,Register & SrcReg,Register & SrcReg2,int & Mask,int & Value) const2327 bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
2328 Register &SrcReg2, int &Mask,
2329 int &Value) const {
2330 unsigned Opc = MI.getOpcode();
2331
2332 switch (Opc) {
2333 default: return false;
2334 case PPC::CMPWI:
2335 case PPC::CMPLWI:
2336 case PPC::CMPDI:
2337 case PPC::CMPLDI:
2338 SrcReg = MI.getOperand(1).getReg();
2339 SrcReg2 = 0;
2340 Value = MI.getOperand(2).getImm();
2341 Mask = 0xFFFF;
2342 return true;
2343 case PPC::CMPW:
2344 case PPC::CMPLW:
2345 case PPC::CMPD:
2346 case PPC::CMPLD:
2347 case PPC::FCMPUS:
2348 case PPC::FCMPUD:
2349 SrcReg = MI.getOperand(1).getReg();
2350 SrcReg2 = MI.getOperand(2).getReg();
2351 Value = 0;
2352 Mask = 0;
2353 return true;
2354 }
2355 }
2356
optimizeCompareInstr(MachineInstr & CmpInstr,Register SrcReg,Register SrcReg2,int Mask,int Value,const MachineRegisterInfo * MRI) const2357 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
2358 Register SrcReg2, int Mask, int Value,
2359 const MachineRegisterInfo *MRI) const {
2360 if (DisableCmpOpt)
2361 return false;
2362
2363 int OpC = CmpInstr.getOpcode();
2364 Register CRReg = CmpInstr.getOperand(0).getReg();
2365
2366 // FP record forms set CR1 based on the exception status bits, not a
2367 // comparison with zero.
2368 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
2369 return false;
2370
2371 const TargetRegisterInfo *TRI = &getRegisterInfo();
2372 // The record forms set the condition register based on a signed comparison
2373 // with zero (so says the ISA manual). This is not as straightforward as it
2374 // seems, however, because this is always a 64-bit comparison on PPC64, even
2375 // for instructions that are 32-bit in nature (like slw for example).
2376 // So, on PPC32, for unsigned comparisons, we can use the record forms only
2377 // for equality checks (as those don't depend on the sign). On PPC64,
2378 // we are restricted to equality for unsigned 64-bit comparisons and for
2379 // signed 32-bit comparisons the applicability is more restricted.
2380 bool isPPC64 = Subtarget.isPPC64();
2381 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
2382 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
2383 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
2384
2385 // Look through copies unless that gets us to a physical register.
2386 Register ActualSrc = TRI->lookThruCopyLike(SrcReg, MRI);
2387 if (ActualSrc.isVirtual())
2388 SrcReg = ActualSrc;
2389
2390 // Get the unique definition of SrcReg.
2391 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2392 if (!MI) return false;
2393
2394 bool equalityOnly = false;
2395 bool noSub = false;
2396 if (isPPC64) {
2397 if (is32BitSignedCompare) {
2398 // We can perform this optimization only if MI is sign-extending.
2399 if (isSignExtended(*MI))
2400 noSub = true;
2401 else
2402 return false;
2403 } else if (is32BitUnsignedCompare) {
2404 // We can perform this optimization, equality only, if MI is
2405 // zero-extending.
2406 if (isZeroExtended(*MI)) {
2407 noSub = true;
2408 equalityOnly = true;
2409 } else
2410 return false;
2411 } else
2412 equalityOnly = is64BitUnsignedCompare;
2413 } else
2414 equalityOnly = is32BitUnsignedCompare;
2415
2416 if (equalityOnly) {
2417 // We need to check the uses of the condition register in order to reject
2418 // non-equality comparisons.
2419 for (MachineRegisterInfo::use_instr_iterator
2420 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
2421 I != IE; ++I) {
2422 MachineInstr *UseMI = &*I;
2423 if (UseMI->getOpcode() == PPC::BCC) {
2424 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
2425 unsigned PredCond = PPC::getPredicateCondition(Pred);
2426 // We ignore hint bits when checking for non-equality comparisons.
2427 if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
2428 return false;
2429 } else if (UseMI->getOpcode() == PPC::ISEL ||
2430 UseMI->getOpcode() == PPC::ISEL8) {
2431 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
2432 if (SubIdx != PPC::sub_eq)
2433 return false;
2434 } else
2435 return false;
2436 }
2437 }
2438
2439 MachineBasicBlock::iterator I = CmpInstr;
2440
2441 // Scan forward to find the first use of the compare.
2442 for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
2443 ++I) {
2444 bool FoundUse = false;
2445 for (MachineRegisterInfo::use_instr_iterator
2446 J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
2447 J != JE; ++J)
2448 if (&*J == &*I) {
2449 FoundUse = true;
2450 break;
2451 }
2452
2453 if (FoundUse)
2454 break;
2455 }
2456
2457 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
2458 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
2459
2460 // There are two possible candidates which can be changed to set CR[01].
2461 // One is MI, the other is a SUB instruction.
2462 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2463 MachineInstr *Sub = nullptr;
2464 if (SrcReg2 != 0)
2465 // MI is not a candidate for CMPrr.
2466 MI = nullptr;
2467 // FIXME: Conservatively refuse to convert an instruction which isn't in the
2468 // same BB as the comparison. This is to allow the check below to avoid calls
2469 // (and other explicit clobbers); instead we should really check for these
2470 // more explicitly (in at least a few predecessors).
2471 else if (MI->getParent() != CmpInstr.getParent())
2472 return false;
2473 else if (Value != 0) {
2474 // The record-form instructions set CR bit based on signed comparison
2475 // against 0. We try to convert a compare against 1 or -1 into a compare
2476 // against 0 to exploit record-form instructions. For example, we change
2477 // the condition "greater than -1" into "greater than or equal to 0"
2478 // and "less than 1" into "less than or equal to 0".
2479
2480 // Since we optimize comparison based on a specific branch condition,
2481 // we don't optimize if condition code is used by more than once.
2482 if (equalityOnly || !MRI->hasOneUse(CRReg))
2483 return false;
2484
2485 MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
2486 if (UseMI->getOpcode() != PPC::BCC)
2487 return false;
2488
2489 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
2490 unsigned PredCond = PPC::getPredicateCondition(Pred);
2491 unsigned PredHint = PPC::getPredicateHint(Pred);
2492 int16_t Immed = (int16_t)Value;
2493
2494 // When modifying the condition in the predicate, we propagate hint bits
2495 // from the original predicate to the new one.
2496 if (Immed == -1 && PredCond == PPC::PRED_GT)
2497 // We convert "greater than -1" into "greater than or equal to 0",
2498 // since we are assuming signed comparison by !equalityOnly
2499 Pred = PPC::getPredicate(PPC::PRED_GE, PredHint);
2500 else if (Immed == -1 && PredCond == PPC::PRED_LE)
2501 // We convert "less than or equal to -1" into "less than 0".
2502 Pred = PPC::getPredicate(PPC::PRED_LT, PredHint);
2503 else if (Immed == 1 && PredCond == PPC::PRED_LT)
2504 // We convert "less than 1" into "less than or equal to 0".
2505 Pred = PPC::getPredicate(PPC::PRED_LE, PredHint);
2506 else if (Immed == 1 && PredCond == PPC::PRED_GE)
2507 // We convert "greater than or equal to 1" into "greater than 0".
2508 Pred = PPC::getPredicate(PPC::PRED_GT, PredHint);
2509 else
2510 return false;
2511
2512 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)), Pred));
2513 }
2514
2515 // Search for Sub.
2516 --I;
2517
2518 // Get ready to iterate backward from CmpInstr.
2519 MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
2520
2521 for (; I != E && !noSub; --I) {
2522 const MachineInstr &Instr = *I;
2523 unsigned IOpC = Instr.getOpcode();
2524
2525 if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
2526 Instr.readsRegister(PPC::CR0, TRI)))
2527 // This instruction modifies or uses the record condition register after
2528 // the one we want to change. While we could do this transformation, it
2529 // would likely not be profitable. This transformation removes one
2530 // instruction, and so even forcing RA to generate one move probably
2531 // makes it unprofitable.
2532 return false;
2533
2534 // Check whether CmpInstr can be made redundant by the current instruction.
2535 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
2536 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
2537 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
2538 ((Instr.getOperand(1).getReg() == SrcReg &&
2539 Instr.getOperand(2).getReg() == SrcReg2) ||
2540 (Instr.getOperand(1).getReg() == SrcReg2 &&
2541 Instr.getOperand(2).getReg() == SrcReg))) {
2542 Sub = &*I;
2543 break;
2544 }
2545
2546 if (I == B)
2547 // The 'and' is below the comparison instruction.
2548 return false;
2549 }
2550
2551 // Return false if no candidates exist.
2552 if (!MI && !Sub)
2553 return false;
2554
2555 // The single candidate is called MI.
2556 if (!MI) MI = Sub;
2557
2558 int NewOpC = -1;
2559 int MIOpC = MI->getOpcode();
2560 if (MIOpC == PPC::ANDI_rec || MIOpC == PPC::ANDI8_rec ||
2561 MIOpC == PPC::ANDIS_rec || MIOpC == PPC::ANDIS8_rec)
2562 NewOpC = MIOpC;
2563 else {
2564 NewOpC = PPC::getRecordFormOpcode(MIOpC);
2565 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
2566 NewOpC = MIOpC;
2567 }
2568
2569 // FIXME: On the non-embedded POWER architectures, only some of the record
2570 // forms are fast, and we should use only the fast ones.
2571
2572 // The defining instruction has a record form (or is already a record
2573 // form). It is possible, however, that we'll need to reverse the condition
2574 // code of the users.
2575 if (NewOpC == -1)
2576 return false;
2577
2578 // This transformation should not be performed if `nsw` is missing and is not
2579 // `equalityOnly` comparison. Since if there is overflow, sub_lt, sub_gt in
2580 // CRReg do not reflect correct order. If `equalityOnly` is true, sub_eq in
2581 // CRReg can reflect if compared values are equal, this optz is still valid.
2582 if (!equalityOnly && (NewOpC == PPC::SUBF_rec || NewOpC == PPC::SUBF8_rec) &&
2583 Sub && !Sub->getFlag(MachineInstr::NoSWrap))
2584 return false;
2585
2586 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
2587 // needs to be updated to be based on SUB. Push the condition code
2588 // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
2589 // condition code of these operands will be modified.
2590 // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
2591 // comparison against 0, which may modify predicate.
2592 bool ShouldSwap = false;
2593 if (Sub && Value == 0) {
2594 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2595 Sub->getOperand(2).getReg() == SrcReg;
2596
2597 // The operands to subf are the opposite of sub, so only in the fixed-point
2598 // case, invert the order.
2599 ShouldSwap = !ShouldSwap;
2600 }
2601
2602 if (ShouldSwap)
2603 for (MachineRegisterInfo::use_instr_iterator
2604 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
2605 I != IE; ++I) {
2606 MachineInstr *UseMI = &*I;
2607 if (UseMI->getOpcode() == PPC::BCC) {
2608 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
2609 unsigned PredCond = PPC::getPredicateCondition(Pred);
2610 assert((!equalityOnly ||
2611 PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&
2612 "Invalid predicate for equality-only optimization");
2613 (void)PredCond; // To suppress warning in release build.
2614 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
2615 PPC::getSwappedPredicate(Pred)));
2616 } else if (UseMI->getOpcode() == PPC::ISEL ||
2617 UseMI->getOpcode() == PPC::ISEL8) {
2618 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
2619 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
2620 "Invalid CR bit for equality-only optimization");
2621
2622 if (NewSubReg == PPC::sub_lt)
2623 NewSubReg = PPC::sub_gt;
2624 else if (NewSubReg == PPC::sub_gt)
2625 NewSubReg = PPC::sub_lt;
2626
2627 SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
2628 NewSubReg));
2629 } else // We need to abort on a user we don't understand.
2630 return false;
2631 }
2632 assert(!(Value != 0 && ShouldSwap) &&
2633 "Non-zero immediate support and ShouldSwap"
2634 "may conflict in updating predicate");
2635
2636 // Create a new virtual register to hold the value of the CR set by the
2637 // record-form instruction. If the instruction was not previously in
2638 // record form, then set the kill flag on the CR.
2639 CmpInstr.eraseFromParent();
2640
2641 MachineBasicBlock::iterator MII = MI;
2642 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
2643 get(TargetOpcode::COPY), CRReg)
2644 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
2645
2646 // Even if CR0 register were dead before, it is alive now since the
2647 // instruction we just built uses it.
2648 MI->clearRegisterDeads(PPC::CR0);
2649
2650 if (MIOpC != NewOpC) {
2651 // We need to be careful here: we're replacing one instruction with
2652 // another, and we need to make sure that we get all of the right
2653 // implicit uses and defs. On the other hand, the caller may be holding
2654 // an iterator to this instruction, and so we can't delete it (this is
2655 // specifically the case if this is the instruction directly after the
2656 // compare).
2657
2658 // Rotates are expensive instructions. If we're emitting a record-form
2659 // rotate that can just be an andi/andis, we should just emit that.
2660 if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
2661 Register GPRRes = MI->getOperand(0).getReg();
2662 int64_t SH = MI->getOperand(2).getImm();
2663 int64_t MB = MI->getOperand(3).getImm();
2664 int64_t ME = MI->getOperand(4).getImm();
2665 // We can only do this if both the start and end of the mask are in the
2666 // same halfword.
2667 bool MBInLoHWord = MB >= 16;
2668 bool MEInLoHWord = ME >= 16;
2669 uint64_t Mask = ~0LLU;
2670
2671 if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
2672 Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2673 // The mask value needs to shift right 16 if we're emitting andis.
2674 Mask >>= MBInLoHWord ? 0 : 16;
2675 NewOpC = MIOpC == PPC::RLWINM
2676 ? (MBInLoHWord ? PPC::ANDI_rec : PPC::ANDIS_rec)
2677 : (MBInLoHWord ? PPC::ANDI8_rec : PPC::ANDIS8_rec);
2678 } else if (MRI->use_empty(GPRRes) && (ME == 31) &&
2679 (ME - MB + 1 == SH) && (MB >= 16)) {
2680 // If we are rotating by the exact number of bits as are in the mask
2681 // and the mask is in the least significant bits of the register,
2682 // that's just an andis. (as long as the GPR result has no uses).
2683 Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
2684 Mask >>= 16;
2685 NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDIS_rec : PPC::ANDIS8_rec;
2686 }
2687 // If we've set the mask, we can transform.
2688 if (Mask != ~0LLU) {
2689 MI->RemoveOperand(4);
2690 MI->RemoveOperand(3);
2691 MI->getOperand(2).setImm(Mask);
2692 NumRcRotatesConvertedToRcAnd++;
2693 }
2694 } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
2695 int64_t MB = MI->getOperand(3).getImm();
2696 if (MB >= 48) {
2697 uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2698 NewOpC = PPC::ANDI8_rec;
2699 MI->RemoveOperand(3);
2700 MI->getOperand(2).setImm(Mask);
2701 NumRcRotatesConvertedToRcAnd++;
2702 }
2703 }
2704
2705 const MCInstrDesc &NewDesc = get(NewOpC);
2706 MI->setDesc(NewDesc);
2707
2708 if (NewDesc.ImplicitDefs)
2709 for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
2710 *ImpDefs; ++ImpDefs)
2711 if (!MI->definesRegister(*ImpDefs))
2712 MI->addOperand(*MI->getParent()->getParent(),
2713 MachineOperand::CreateReg(*ImpDefs, true, true));
2714 if (NewDesc.ImplicitUses)
2715 for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
2716 *ImpUses; ++ImpUses)
2717 if (!MI->readsRegister(*ImpUses))
2718 MI->addOperand(*MI->getParent()->getParent(),
2719 MachineOperand::CreateReg(*ImpUses, false, true));
2720 }
2721 assert(MI->definesRegister(PPC::CR0) &&
2722 "Record-form instruction does not define cr0?");
2723
2724 // Modify the condition code of operands in OperandsToUpdate.
2725 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2726 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2727 for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
2728 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
2729
2730 for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
2731 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
2732
2733 return true;
2734 }
2735
getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,unsigned & Width,const TargetRegisterInfo * TRI) const2736 bool PPCInstrInfo::getMemOperandsWithOffsetWidth(
2737 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
2738 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
2739 const TargetRegisterInfo *TRI) const {
2740 const MachineOperand *BaseOp;
2741 OffsetIsScalable = false;
2742 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI))
2743 return false;
2744 BaseOps.push_back(BaseOp);
2745 return true;
2746 }
2747
isLdStSafeToCluster(const MachineInstr & LdSt,const TargetRegisterInfo * TRI)2748 static bool isLdStSafeToCluster(const MachineInstr &LdSt,
2749 const TargetRegisterInfo *TRI) {
2750 // If this is a volatile load/store, don't mess with it.
2751 if (LdSt.hasOrderedMemoryRef() || LdSt.getNumExplicitOperands() != 3)
2752 return false;
2753
2754 if (LdSt.getOperand(2).isFI())
2755 return true;
2756
2757 assert(LdSt.getOperand(2).isReg() && "Expected a reg operand.");
2758 // Can't cluster if the instruction modifies the base register
2759 // or it is update form. e.g. ld r2,3(r2)
2760 if (LdSt.modifiesRegister(LdSt.getOperand(2).getReg(), TRI))
2761 return false;
2762
2763 return true;
2764 }
2765
2766 // Only cluster instruction pair that have the same opcode, and they are
2767 // clusterable according to PowerPC specification.
isClusterableLdStOpcPair(unsigned FirstOpc,unsigned SecondOpc,const PPCSubtarget & Subtarget)2768 static bool isClusterableLdStOpcPair(unsigned FirstOpc, unsigned SecondOpc,
2769 const PPCSubtarget &Subtarget) {
2770 switch (FirstOpc) {
2771 default:
2772 return false;
2773 case PPC::STD:
2774 case PPC::STFD:
2775 case PPC::STXSD:
2776 case PPC::DFSTOREf64:
2777 return FirstOpc == SecondOpc;
2778 // PowerPC backend has opcode STW/STW8 for instruction "stw" to deal with
2779 // 32bit and 64bit instruction selection. They are clusterable pair though
2780 // they are different opcode.
2781 case PPC::STW:
2782 case PPC::STW8:
2783 return SecondOpc == PPC::STW || SecondOpc == PPC::STW8;
2784 }
2785 }
2786
shouldClusterMemOps(ArrayRef<const MachineOperand * > BaseOps1,ArrayRef<const MachineOperand * > BaseOps2,unsigned NumLoads,unsigned NumBytes) const2787 bool PPCInstrInfo::shouldClusterMemOps(
2788 ArrayRef<const MachineOperand *> BaseOps1,
2789 ArrayRef<const MachineOperand *> BaseOps2, unsigned NumLoads,
2790 unsigned NumBytes) const {
2791
2792 assert(BaseOps1.size() == 1 && BaseOps2.size() == 1);
2793 const MachineOperand &BaseOp1 = *BaseOps1.front();
2794 const MachineOperand &BaseOp2 = *BaseOps2.front();
2795 assert((BaseOp1.isReg() || BaseOp1.isFI()) &&
2796 "Only base registers and frame indices are supported.");
2797
2798 // The NumLoads means the number of loads that has been clustered.
2799 // Don't cluster memory op if there are already two ops clustered at least.
2800 if (NumLoads > 2)
2801 return false;
2802
2803 // Cluster the load/store only when they have the same base
2804 // register or FI.
2805 if ((BaseOp1.isReg() != BaseOp2.isReg()) ||
2806 (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) ||
2807 (BaseOp1.isFI() && BaseOp1.getIndex() != BaseOp2.getIndex()))
2808 return false;
2809
2810 // Check if the load/store are clusterable according to the PowerPC
2811 // specification.
2812 const MachineInstr &FirstLdSt = *BaseOp1.getParent();
2813 const MachineInstr &SecondLdSt = *BaseOp2.getParent();
2814 unsigned FirstOpc = FirstLdSt.getOpcode();
2815 unsigned SecondOpc = SecondLdSt.getOpcode();
2816 const TargetRegisterInfo *TRI = &getRegisterInfo();
2817 // Cluster the load/store only when they have the same opcode, and they are
2818 // clusterable opcode according to PowerPC specification.
2819 if (!isClusterableLdStOpcPair(FirstOpc, SecondOpc, Subtarget))
2820 return false;
2821
2822 // Can't cluster load/store that have ordered or volatile memory reference.
2823 if (!isLdStSafeToCluster(FirstLdSt, TRI) ||
2824 !isLdStSafeToCluster(SecondLdSt, TRI))
2825 return false;
2826
2827 int64_t Offset1 = 0, Offset2 = 0;
2828 unsigned Width1 = 0, Width2 = 0;
2829 const MachineOperand *Base1 = nullptr, *Base2 = nullptr;
2830 if (!getMemOperandWithOffsetWidth(FirstLdSt, Base1, Offset1, Width1, TRI) ||
2831 !getMemOperandWithOffsetWidth(SecondLdSt, Base2, Offset2, Width2, TRI) ||
2832 Width1 != Width2)
2833 return false;
2834
2835 assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 &&
2836 "getMemOperandWithOffsetWidth return incorrect base op");
2837 // The caller should already have ordered FirstMemOp/SecondMemOp by offset.
2838 assert(Offset1 <= Offset2 && "Caller should have ordered offsets.");
2839 return Offset1 + Width1 == Offset2;
2840 }
2841
2842 /// GetInstSize - Return the number of bytes of code the specified
2843 /// instruction may be. This returns the maximum number of bytes.
2844 ///
getInstSizeInBytes(const MachineInstr & MI) const2845 unsigned PPCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
2846 unsigned Opcode = MI.getOpcode();
2847
2848 if (Opcode == PPC::INLINEASM || Opcode == PPC::INLINEASM_BR) {
2849 const MachineFunction *MF = MI.getParent()->getParent();
2850 const char *AsmStr = MI.getOperand(0).getSymbolName();
2851 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
2852 } else if (Opcode == TargetOpcode::STACKMAP) {
2853 StackMapOpers Opers(&MI);
2854 return Opers.getNumPatchBytes();
2855 } else if (Opcode == TargetOpcode::PATCHPOINT) {
2856 PatchPointOpers Opers(&MI);
2857 return Opers.getNumPatchBytes();
2858 } else {
2859 return get(Opcode).getSize();
2860 }
2861 }
2862
2863 std::pair<unsigned, unsigned>
decomposeMachineOperandsTargetFlags(unsigned TF) const2864 PPCInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
2865 const unsigned Mask = PPCII::MO_ACCESS_MASK;
2866 return std::make_pair(TF & Mask, TF & ~Mask);
2867 }
2868
2869 ArrayRef<std::pair<unsigned, const char *>>
getSerializableDirectMachineOperandTargetFlags() const2870 PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
2871 using namespace PPCII;
2872 static const std::pair<unsigned, const char *> TargetFlags[] = {
2873 {MO_LO, "ppc-lo"},
2874 {MO_HA, "ppc-ha"},
2875 {MO_TPREL_LO, "ppc-tprel-lo"},
2876 {MO_TPREL_HA, "ppc-tprel-ha"},
2877 {MO_DTPREL_LO, "ppc-dtprel-lo"},
2878 {MO_TLSLD_LO, "ppc-tlsld-lo"},
2879 {MO_TOC_LO, "ppc-toc-lo"},
2880 {MO_TLS, "ppc-tls"}};
2881 return makeArrayRef(TargetFlags);
2882 }
2883
2884 ArrayRef<std::pair<unsigned, const char *>>
getSerializableBitmaskMachineOperandTargetFlags() const2885 PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
2886 using namespace PPCII;
2887 static const std::pair<unsigned, const char *> TargetFlags[] = {
2888 {MO_PLT, "ppc-plt"},
2889 {MO_PIC_FLAG, "ppc-pic"},
2890 {MO_PCREL_FLAG, "ppc-pcrel"},
2891 {MO_GOT_FLAG, "ppc-got"},
2892 {MO_PCREL_OPT_FLAG, "ppc-opt-pcrel"},
2893 {MO_TLSGD_FLAG, "ppc-tlsgd"},
2894 {MO_TLSLD_FLAG, "ppc-tlsld"},
2895 {MO_TPREL_FLAG, "ppc-tprel"},
2896 {MO_TLSGDM_FLAG, "ppc-tlsgdm"},
2897 {MO_GOT_TLSGD_PCREL_FLAG, "ppc-got-tlsgd-pcrel"},
2898 {MO_GOT_TLSLD_PCREL_FLAG, "ppc-got-tlsld-pcrel"},
2899 {MO_GOT_TPREL_PCREL_FLAG, "ppc-got-tprel-pcrel"}};
2900 return makeArrayRef(TargetFlags);
2901 }
2902
2903 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
2904 // The VSX versions have the advantage of a full 64-register target whereas
2905 // the FP ones have the advantage of lower latency and higher throughput. So
2906 // what we are after is using the faster instructions in low register pressure
2907 // situations and using the larger register file in high register pressure
2908 // situations.
expandVSXMemPseudo(MachineInstr & MI) const2909 bool PPCInstrInfo::expandVSXMemPseudo(MachineInstr &MI) const {
2910 unsigned UpperOpcode, LowerOpcode;
2911 switch (MI.getOpcode()) {
2912 case PPC::DFLOADf32:
2913 UpperOpcode = PPC::LXSSP;
2914 LowerOpcode = PPC::LFS;
2915 break;
2916 case PPC::DFLOADf64:
2917 UpperOpcode = PPC::LXSD;
2918 LowerOpcode = PPC::LFD;
2919 break;
2920 case PPC::DFSTOREf32:
2921 UpperOpcode = PPC::STXSSP;
2922 LowerOpcode = PPC::STFS;
2923 break;
2924 case PPC::DFSTOREf64:
2925 UpperOpcode = PPC::STXSD;
2926 LowerOpcode = PPC::STFD;
2927 break;
2928 case PPC::XFLOADf32:
2929 UpperOpcode = PPC::LXSSPX;
2930 LowerOpcode = PPC::LFSX;
2931 break;
2932 case PPC::XFLOADf64:
2933 UpperOpcode = PPC::LXSDX;
2934 LowerOpcode = PPC::LFDX;
2935 break;
2936 case PPC::XFSTOREf32:
2937 UpperOpcode = PPC::STXSSPX;
2938 LowerOpcode = PPC::STFSX;
2939 break;
2940 case PPC::XFSTOREf64:
2941 UpperOpcode = PPC::STXSDX;
2942 LowerOpcode = PPC::STFDX;
2943 break;
2944 case PPC::LIWAX:
2945 UpperOpcode = PPC::LXSIWAX;
2946 LowerOpcode = PPC::LFIWAX;
2947 break;
2948 case PPC::LIWZX:
2949 UpperOpcode = PPC::LXSIWZX;
2950 LowerOpcode = PPC::LFIWZX;
2951 break;
2952 case PPC::STIWX:
2953 UpperOpcode = PPC::STXSIWX;
2954 LowerOpcode = PPC::STFIWX;
2955 break;
2956 default:
2957 llvm_unreachable("Unknown Operation!");
2958 }
2959
2960 Register TargetReg = MI.getOperand(0).getReg();
2961 unsigned Opcode;
2962 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2963 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2964 Opcode = LowerOpcode;
2965 else
2966 Opcode = UpperOpcode;
2967 MI.setDesc(get(Opcode));
2968 return true;
2969 }
2970
isAnImmediateOperand(const MachineOperand & MO)2971 static bool isAnImmediateOperand(const MachineOperand &MO) {
2972 return MO.isCPI() || MO.isGlobal() || MO.isImm();
2973 }
2974
expandPostRAPseudo(MachineInstr & MI) const2975 bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
2976 auto &MBB = *MI.getParent();
2977 auto DL = MI.getDebugLoc();
2978
2979 switch (MI.getOpcode()) {
2980 case PPC::BUILD_UACC: {
2981 MCRegister ACC = MI.getOperand(0).getReg();
2982 MCRegister UACC = MI.getOperand(1).getReg();
2983 if (ACC - PPC::ACC0 != UACC - PPC::UACC0) {
2984 MCRegister SrcVSR = PPC::VSL0 + (UACC - PPC::UACC0) * 4;
2985 MCRegister DstVSR = PPC::VSL0 + (ACC - PPC::ACC0) * 4;
2986 // FIXME: This can easily be improved to look up to the top of the MBB
2987 // to see if the inputs are XXLOR's. If they are and SrcReg is killed,
2988 // we can just re-target any such XXLOR's to DstVSR + offset.
2989 for (int VecNo = 0; VecNo < 4; VecNo++)
2990 BuildMI(MBB, MI, DL, get(PPC::XXLOR), DstVSR + VecNo)
2991 .addReg(SrcVSR + VecNo)
2992 .addReg(SrcVSR + VecNo);
2993 }
2994 // BUILD_UACC is expanded to 4 copies of the underlying vsx regisers.
2995 // So after building the 4 copies, we can replace the BUILD_UACC instruction
2996 // with a NOP.
2997 LLVM_FALLTHROUGH;
2998 }
2999 case PPC::KILL_PAIR: {
3000 MI.setDesc(get(PPC::UNENCODED_NOP));
3001 MI.RemoveOperand(1);
3002 MI.RemoveOperand(0);
3003 return true;
3004 }
3005 case TargetOpcode::LOAD_STACK_GUARD: {
3006 assert(Subtarget.isTargetLinux() &&
3007 "Only Linux target is expected to contain LOAD_STACK_GUARD");
3008 const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
3009 const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
3010 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
3011 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
3012 .addImm(Offset)
3013 .addReg(Reg);
3014 return true;
3015 }
3016 case PPC::DFLOADf32:
3017 case PPC::DFLOADf64:
3018 case PPC::DFSTOREf32:
3019 case PPC::DFSTOREf64: {
3020 assert(Subtarget.hasP9Vector() &&
3021 "Invalid D-Form Pseudo-ops on Pre-P9 target.");
3022 assert(MI.getOperand(2).isReg() &&
3023 isAnImmediateOperand(MI.getOperand(1)) &&
3024 "D-form op must have register and immediate operands");
3025 return expandVSXMemPseudo(MI);
3026 }
3027 case PPC::XFLOADf32:
3028 case PPC::XFSTOREf32:
3029 case PPC::LIWAX:
3030 case PPC::LIWZX:
3031 case PPC::STIWX: {
3032 assert(Subtarget.hasP8Vector() &&
3033 "Invalid X-Form Pseudo-ops on Pre-P8 target.");
3034 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
3035 "X-form op must have register and register operands");
3036 return expandVSXMemPseudo(MI);
3037 }
3038 case PPC::XFLOADf64:
3039 case PPC::XFSTOREf64: {
3040 assert(Subtarget.hasVSX() &&
3041 "Invalid X-Form Pseudo-ops on target that has no VSX.");
3042 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
3043 "X-form op must have register and register operands");
3044 return expandVSXMemPseudo(MI);
3045 }
3046 case PPC::SPILLTOVSR_LD: {
3047 Register TargetReg = MI.getOperand(0).getReg();
3048 if (PPC::VSFRCRegClass.contains(TargetReg)) {
3049 MI.setDesc(get(PPC::DFLOADf64));
3050 return expandPostRAPseudo(MI);
3051 }
3052 else
3053 MI.setDesc(get(PPC::LD));
3054 return true;
3055 }
3056 case PPC::SPILLTOVSR_ST: {
3057 Register SrcReg = MI.getOperand(0).getReg();
3058 if (PPC::VSFRCRegClass.contains(SrcReg)) {
3059 NumStoreSPILLVSRRCAsVec++;
3060 MI.setDesc(get(PPC::DFSTOREf64));
3061 return expandPostRAPseudo(MI);
3062 } else {
3063 NumStoreSPILLVSRRCAsGpr++;
3064 MI.setDesc(get(PPC::STD));
3065 }
3066 return true;
3067 }
3068 case PPC::SPILLTOVSR_LDX: {
3069 Register TargetReg = MI.getOperand(0).getReg();
3070 if (PPC::VSFRCRegClass.contains(TargetReg))
3071 MI.setDesc(get(PPC::LXSDX));
3072 else
3073 MI.setDesc(get(PPC::LDX));
3074 return true;
3075 }
3076 case PPC::SPILLTOVSR_STX: {
3077 Register SrcReg = MI.getOperand(0).getReg();
3078 if (PPC::VSFRCRegClass.contains(SrcReg)) {
3079 NumStoreSPILLVSRRCAsVec++;
3080 MI.setDesc(get(PPC::STXSDX));
3081 } else {
3082 NumStoreSPILLVSRRCAsGpr++;
3083 MI.setDesc(get(PPC::STDX));
3084 }
3085 return true;
3086 }
3087
3088 case PPC::CFENCE8: {
3089 auto Val = MI.getOperand(0).getReg();
3090 BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
3091 BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
3092 .addImm(PPC::PRED_NE_MINUS)
3093 .addReg(PPC::CR7)
3094 .addImm(1);
3095 MI.setDesc(get(PPC::ISYNC));
3096 MI.RemoveOperand(0);
3097 return true;
3098 }
3099 }
3100 return false;
3101 }
3102
3103 // Essentially a compile-time implementation of a compare->isel sequence.
3104 // It takes two constants to compare, along with the true/false registers
3105 // and the comparison type (as a subreg to a CR field) and returns one
3106 // of the true/false registers, depending on the comparison results.
selectReg(int64_t Imm1,int64_t Imm2,unsigned CompareOpc,unsigned TrueReg,unsigned FalseReg,unsigned CRSubReg)3107 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
3108 unsigned TrueReg, unsigned FalseReg,
3109 unsigned CRSubReg) {
3110 // Signed comparisons. The immediates are assumed to be sign-extended.
3111 if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
3112 switch (CRSubReg) {
3113 default: llvm_unreachable("Unknown integer comparison type.");
3114 case PPC::sub_lt:
3115 return Imm1 < Imm2 ? TrueReg : FalseReg;
3116 case PPC::sub_gt:
3117 return Imm1 > Imm2 ? TrueReg : FalseReg;
3118 case PPC::sub_eq:
3119 return Imm1 == Imm2 ? TrueReg : FalseReg;
3120 }
3121 }
3122 // Unsigned comparisons.
3123 else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
3124 switch (CRSubReg) {
3125 default: llvm_unreachable("Unknown integer comparison type.");
3126 case PPC::sub_lt:
3127 return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
3128 case PPC::sub_gt:
3129 return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
3130 case PPC::sub_eq:
3131 return Imm1 == Imm2 ? TrueReg : FalseReg;
3132 }
3133 }
3134 return PPC::NoRegister;
3135 }
3136
replaceInstrOperandWithImm(MachineInstr & MI,unsigned OpNo,int64_t Imm) const3137 void PPCInstrInfo::replaceInstrOperandWithImm(MachineInstr &MI,
3138 unsigned OpNo,
3139 int64_t Imm) const {
3140 assert(MI.getOperand(OpNo).isReg() && "Operand must be a REG");
3141 // Replace the REG with the Immediate.
3142 Register InUseReg = MI.getOperand(OpNo).getReg();
3143 MI.getOperand(OpNo).ChangeToImmediate(Imm);
3144
3145 if (MI.implicit_operands().empty())
3146 return;
3147
3148 // We need to make sure that the MI didn't have any implicit use
3149 // of this REG any more.
3150 const TargetRegisterInfo *TRI = &getRegisterInfo();
3151 int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, false, TRI);
3152 if (UseOpIdx >= 0) {
3153 MachineOperand &MO = MI.getOperand(UseOpIdx);
3154 if (MO.isImplicit())
3155 // The operands must always be in the following order:
3156 // - explicit reg defs,
3157 // - other explicit operands (reg uses, immediates, etc.),
3158 // - implicit reg defs
3159 // - implicit reg uses
3160 // Therefore, removing the implicit operand won't change the explicit
3161 // operands layout.
3162 MI.RemoveOperand(UseOpIdx);
3163 }
3164 }
3165
3166 // Replace an instruction with one that materializes a constant (and sets
3167 // CR0 if the original instruction was a record-form instruction).
replaceInstrWithLI(MachineInstr & MI,const LoadImmediateInfo & LII) const3168 void PPCInstrInfo::replaceInstrWithLI(MachineInstr &MI,
3169 const LoadImmediateInfo &LII) const {
3170 // Remove existing operands.
3171 int OperandToKeep = LII.SetCR ? 1 : 0;
3172 for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
3173 MI.RemoveOperand(i);
3174
3175 // Replace the instruction.
3176 if (LII.SetCR) {
3177 MI.setDesc(get(LII.Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec));
3178 // Set the immediate.
3179 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
3180 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
3181 return;
3182 }
3183 else
3184 MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
3185
3186 // Set the immediate.
3187 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
3188 .addImm(LII.Imm);
3189 }
3190
getDefMIPostRA(unsigned Reg,MachineInstr & MI,bool & SeenIntermediateUse) const3191 MachineInstr *PPCInstrInfo::getDefMIPostRA(unsigned Reg, MachineInstr &MI,
3192 bool &SeenIntermediateUse) const {
3193 assert(!MI.getParent()->getParent()->getRegInfo().isSSA() &&
3194 "Should be called after register allocation.");
3195 const TargetRegisterInfo *TRI = &getRegisterInfo();
3196 MachineBasicBlock::reverse_iterator E = MI.getParent()->rend(), It = MI;
3197 It++;
3198 SeenIntermediateUse = false;
3199 for (; It != E; ++It) {
3200 if (It->modifiesRegister(Reg, TRI))
3201 return &*It;
3202 if (It->readsRegister(Reg, TRI))
3203 SeenIntermediateUse = true;
3204 }
3205 return nullptr;
3206 }
3207
getForwardingDefMI(MachineInstr & MI,unsigned & OpNoForForwarding,bool & SeenIntermediateUse) const3208 MachineInstr *PPCInstrInfo::getForwardingDefMI(
3209 MachineInstr &MI,
3210 unsigned &OpNoForForwarding,
3211 bool &SeenIntermediateUse) const {
3212 OpNoForForwarding = ~0U;
3213 MachineInstr *DefMI = nullptr;
3214 MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
3215 const TargetRegisterInfo *TRI = &getRegisterInfo();
3216 // If we're in SSA, get the defs through the MRI. Otherwise, only look
3217 // within the basic block to see if the register is defined using an
3218 // LI/LI8/ADDI/ADDI8.
3219 if (MRI->isSSA()) {
3220 for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
3221 if (!MI.getOperand(i).isReg())
3222 continue;
3223 Register Reg = MI.getOperand(i).getReg();
3224 if (!Register::isVirtualRegister(Reg))
3225 continue;
3226 unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
3227 if (Register::isVirtualRegister(TrueReg)) {
3228 DefMI = MRI->getVRegDef(TrueReg);
3229 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8 ||
3230 DefMI->getOpcode() == PPC::ADDI ||
3231 DefMI->getOpcode() == PPC::ADDI8) {
3232 OpNoForForwarding = i;
3233 // The ADDI and LI operand maybe exist in one instruction at same
3234 // time. we prefer to fold LI operand as LI only has one Imm operand
3235 // and is more possible to be converted. So if current DefMI is
3236 // ADDI/ADDI8, we continue to find possible LI/LI8.
3237 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8)
3238 break;
3239 }
3240 }
3241 }
3242 } else {
3243 // Looking back through the definition for each operand could be expensive,
3244 // so exit early if this isn't an instruction that either has an immediate
3245 // form or is already an immediate form that we can handle.
3246 ImmInstrInfo III;
3247 unsigned Opc = MI.getOpcode();
3248 bool ConvertibleImmForm =
3249 Opc == PPC::CMPWI || Opc == PPC::CMPLWI || Opc == PPC::CMPDI ||
3250 Opc == PPC::CMPLDI || Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
3251 Opc == PPC::ORI || Opc == PPC::ORI8 || Opc == PPC::XORI ||
3252 Opc == PPC::XORI8 || Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec ||
3253 Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
3254 Opc == PPC::RLWINM || Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8 ||
3255 Opc == PPC::RLWINM8_rec;
3256 bool IsVFReg = (MI.getNumOperands() && MI.getOperand(0).isReg())
3257 ? isVFRegister(MI.getOperand(0).getReg())
3258 : false;
3259 if (!ConvertibleImmForm && !instrHasImmForm(Opc, IsVFReg, III, true))
3260 return nullptr;
3261
3262 // Don't convert or %X, %Y, %Y since that's just a register move.
3263 if ((Opc == PPC::OR || Opc == PPC::OR8) &&
3264 MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
3265 return nullptr;
3266 for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
3267 MachineOperand &MO = MI.getOperand(i);
3268 SeenIntermediateUse = false;
3269 if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
3270 Register Reg = MI.getOperand(i).getReg();
3271 // If we see another use of this reg between the def and the MI,
3272 // we want to flat it so the def isn't deleted.
3273 MachineInstr *DefMI = getDefMIPostRA(Reg, MI, SeenIntermediateUse);
3274 if (DefMI) {
3275 // Is this register defined by some form of add-immediate (including
3276 // load-immediate) within this basic block?
3277 switch (DefMI->getOpcode()) {
3278 default:
3279 break;
3280 case PPC::LI:
3281 case PPC::LI8:
3282 case PPC::ADDItocL:
3283 case PPC::ADDI:
3284 case PPC::ADDI8:
3285 OpNoForForwarding = i;
3286 return DefMI;
3287 }
3288 }
3289 }
3290 }
3291 }
3292 return OpNoForForwarding == ~0U ? nullptr : DefMI;
3293 }
3294
getSpillTarget() const3295 unsigned PPCInstrInfo::getSpillTarget() const {
3296 // With P10, we may need to spill paired vector registers or accumulator
3297 // registers. MMA implies paired vectors, so we can just check that.
3298 bool IsP10Variant = Subtarget.isISA3_1() || Subtarget.pairedVectorMemops();
3299 return IsP10Variant ? 2 : Subtarget.hasP9Vector() ? 1 : 0;
3300 }
3301
getStoreOpcodesForSpillArray() const3302 const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
3303 return StoreSpillOpcodesArray[getSpillTarget()];
3304 }
3305
getLoadOpcodesForSpillArray() const3306 const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
3307 return LoadSpillOpcodesArray[getSpillTarget()];
3308 }
3309
fixupIsDeadOrKill(MachineInstr * StartMI,MachineInstr * EndMI,unsigned RegNo) const3310 void PPCInstrInfo::fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI,
3311 unsigned RegNo) const {
3312 // Conservatively clear kill flag for the register if the instructions are in
3313 // different basic blocks and in SSA form, because the kill flag may no longer
3314 // be right. There is no need to bother with dead flags since defs with no
3315 // uses will be handled by DCE.
3316 MachineRegisterInfo &MRI = StartMI->getParent()->getParent()->getRegInfo();
3317 if (MRI.isSSA() && (StartMI->getParent() != EndMI->getParent())) {
3318 MRI.clearKillFlags(RegNo);
3319 return;
3320 }
3321
3322 // Instructions between [StartMI, EndMI] should be in same basic block.
3323 assert((StartMI->getParent() == EndMI->getParent()) &&
3324 "Instructions are not in same basic block");
3325
3326 // If before RA, StartMI may be def through COPY, we need to adjust it to the
3327 // real def. See function getForwardingDefMI.
3328 if (MRI.isSSA()) {
3329 bool Reads, Writes;
3330 std::tie(Reads, Writes) = StartMI->readsWritesVirtualRegister(RegNo);
3331 if (!Reads && !Writes) {
3332 assert(Register::isVirtualRegister(RegNo) &&
3333 "Must be a virtual register");
3334 // Get real def and ignore copies.
3335 StartMI = MRI.getVRegDef(RegNo);
3336 }
3337 }
3338
3339 bool IsKillSet = false;
3340
3341 auto clearOperandKillInfo = [=] (MachineInstr &MI, unsigned Index) {
3342 MachineOperand &MO = MI.getOperand(Index);
3343 if (MO.isReg() && MO.isUse() && MO.isKill() &&
3344 getRegisterInfo().regsOverlap(MO.getReg(), RegNo))
3345 MO.setIsKill(false);
3346 };
3347
3348 // Set killed flag for EndMI.
3349 // No need to do anything if EndMI defines RegNo.
3350 int UseIndex =
3351 EndMI->findRegisterUseOperandIdx(RegNo, false, &getRegisterInfo());
3352 if (UseIndex != -1) {
3353 EndMI->getOperand(UseIndex).setIsKill(true);
3354 IsKillSet = true;
3355 // Clear killed flag for other EndMI operands related to RegNo. In some
3356 // upexpected cases, killed may be set multiple times for same register
3357 // operand in same MI.
3358 for (int i = 0, e = EndMI->getNumOperands(); i != e; ++i)
3359 if (i != UseIndex)
3360 clearOperandKillInfo(*EndMI, i);
3361 }
3362
3363 // Walking the inst in reverse order (EndMI -> StartMI].
3364 MachineBasicBlock::reverse_iterator It = *EndMI;
3365 MachineBasicBlock::reverse_iterator E = EndMI->getParent()->rend();
3366 // EndMI has been handled above, skip it here.
3367 It++;
3368 MachineOperand *MO = nullptr;
3369 for (; It != E; ++It) {
3370 // Skip insturctions which could not be a def/use of RegNo.
3371 if (It->isDebugInstr() || It->isPosition())
3372 continue;
3373
3374 // Clear killed flag for all It operands related to RegNo. In some
3375 // upexpected cases, killed may be set multiple times for same register
3376 // operand in same MI.
3377 for (int i = 0, e = It->getNumOperands(); i != e; ++i)
3378 clearOperandKillInfo(*It, i);
3379
3380 // If killed is not set, set killed for its last use or set dead for its def
3381 // if no use found.
3382 if (!IsKillSet) {
3383 if ((MO = It->findRegisterUseOperand(RegNo, false, &getRegisterInfo()))) {
3384 // Use found, set it killed.
3385 IsKillSet = true;
3386 MO->setIsKill(true);
3387 continue;
3388 } else if ((MO = It->findRegisterDefOperand(RegNo, false, true,
3389 &getRegisterInfo()))) {
3390 // No use found, set dead for its def.
3391 assert(&*It == StartMI && "No new def between StartMI and EndMI.");
3392 MO->setIsDead(true);
3393 break;
3394 }
3395 }
3396
3397 if ((&*It) == StartMI)
3398 break;
3399 }
3400 // Ensure RegMo liveness is killed after EndMI.
3401 assert((IsKillSet || (MO && MO->isDead())) &&
3402 "RegNo should be killed or dead");
3403 }
3404
3405 // This opt tries to convert the following imm form to an index form to save an
3406 // add for stack variables.
3407 // Return false if no such pattern found.
3408 //
3409 // ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, OffsetAddi
3410 // ADD instr: ToBeDeletedReg = ADD ToBeChangedReg(killed), ScaleReg
3411 // Imm instr: Reg = op OffsetImm, ToBeDeletedReg(killed)
3412 //
3413 // can be converted to:
3414 //
3415 // new ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, (OffsetAddi + OffsetImm)
3416 // Index instr: Reg = opx ScaleReg, ToBeChangedReg(killed)
3417 //
3418 // In order to eliminate ADD instr, make sure that:
3419 // 1: (OffsetAddi + OffsetImm) must be int16 since this offset will be used in
3420 // new ADDI instr and ADDI can only take int16 Imm.
3421 // 2: ToBeChangedReg must be killed in ADD instr and there is no other use
3422 // between ADDI and ADD instr since its original def in ADDI will be changed
3423 // in new ADDI instr. And also there should be no new def for it between
3424 // ADD and Imm instr as ToBeChangedReg will be used in Index instr.
3425 // 3: ToBeDeletedReg must be killed in Imm instr and there is no other use
3426 // between ADD and Imm instr since ADD instr will be eliminated.
3427 // 4: ScaleReg must not be redefined between ADD and Imm instr since it will be
3428 // moved to Index instr.
foldFrameOffset(MachineInstr & MI) const3429 bool PPCInstrInfo::foldFrameOffset(MachineInstr &MI) const {
3430 MachineFunction *MF = MI.getParent()->getParent();
3431 MachineRegisterInfo *MRI = &MF->getRegInfo();
3432 bool PostRA = !MRI->isSSA();
3433 // Do this opt after PEI which is after RA. The reason is stack slot expansion
3434 // in PEI may expose such opportunities since in PEI, stack slot offsets to
3435 // frame base(OffsetAddi) are determined.
3436 if (!PostRA)
3437 return false;
3438 unsigned ToBeDeletedReg = 0;
3439 int64_t OffsetImm = 0;
3440 unsigned XFormOpcode = 0;
3441 ImmInstrInfo III;
3442
3443 // Check if Imm instr meets requirement.
3444 if (!isImmInstrEligibleForFolding(MI, ToBeDeletedReg, XFormOpcode, OffsetImm,
3445 III))
3446 return false;
3447
3448 bool OtherIntermediateUse = false;
3449 MachineInstr *ADDMI = getDefMIPostRA(ToBeDeletedReg, MI, OtherIntermediateUse);
3450
3451 // Exit if there is other use between ADD and Imm instr or no def found.
3452 if (OtherIntermediateUse || !ADDMI)
3453 return false;
3454
3455 // Check if ADD instr meets requirement.
3456 if (!isADDInstrEligibleForFolding(*ADDMI))
3457 return false;
3458
3459 unsigned ScaleRegIdx = 0;
3460 int64_t OffsetAddi = 0;
3461 MachineInstr *ADDIMI = nullptr;
3462
3463 // Check if there is a valid ToBeChangedReg in ADDMI.
3464 // 1: It must be killed.
3465 // 2: Its definition must be a valid ADDIMI.
3466 // 3: It must satify int16 offset requirement.
3467 if (isValidToBeChangedReg(ADDMI, 1, ADDIMI, OffsetAddi, OffsetImm))
3468 ScaleRegIdx = 2;
3469 else if (isValidToBeChangedReg(ADDMI, 2, ADDIMI, OffsetAddi, OffsetImm))
3470 ScaleRegIdx = 1;
3471 else
3472 return false;
3473
3474 assert(ADDIMI && "There should be ADDIMI for valid ToBeChangedReg.");
3475 unsigned ToBeChangedReg = ADDIMI->getOperand(0).getReg();
3476 unsigned ScaleReg = ADDMI->getOperand(ScaleRegIdx).getReg();
3477 auto NewDefFor = [&](unsigned Reg, MachineBasicBlock::iterator Start,
3478 MachineBasicBlock::iterator End) {
3479 for (auto It = ++Start; It != End; It++)
3480 if (It->modifiesRegister(Reg, &getRegisterInfo()))
3481 return true;
3482 return false;
3483 };
3484
3485 // We are trying to replace the ImmOpNo with ScaleReg. Give up if it is
3486 // treated as special zero when ScaleReg is R0/X0 register.
3487 if (III.ZeroIsSpecialOrig == III.ImmOpNo &&
3488 (ScaleReg == PPC::R0 || ScaleReg == PPC::X0))
3489 return false;
3490
3491 // Make sure no other def for ToBeChangedReg and ScaleReg between ADD Instr
3492 // and Imm Instr.
3493 if (NewDefFor(ToBeChangedReg, *ADDMI, MI) || NewDefFor(ScaleReg, *ADDMI, MI))
3494 return false;
3495
3496 // Now start to do the transformation.
3497 LLVM_DEBUG(dbgs() << "Replace instruction: "
3498 << "\n");
3499 LLVM_DEBUG(ADDIMI->dump());
3500 LLVM_DEBUG(ADDMI->dump());
3501 LLVM_DEBUG(MI.dump());
3502 LLVM_DEBUG(dbgs() << "with: "
3503 << "\n");
3504
3505 // Update ADDI instr.
3506 ADDIMI->getOperand(2).setImm(OffsetAddi + OffsetImm);
3507
3508 // Update Imm instr.
3509 MI.setDesc(get(XFormOpcode));
3510 MI.getOperand(III.ImmOpNo)
3511 .ChangeToRegister(ScaleReg, false, false,
3512 ADDMI->getOperand(ScaleRegIdx).isKill());
3513
3514 MI.getOperand(III.OpNoForForwarding)
3515 .ChangeToRegister(ToBeChangedReg, false, false, true);
3516
3517 // Eliminate ADD instr.
3518 ADDMI->eraseFromParent();
3519
3520 LLVM_DEBUG(ADDIMI->dump());
3521 LLVM_DEBUG(MI.dump());
3522
3523 return true;
3524 }
3525
isADDIInstrEligibleForFolding(MachineInstr & ADDIMI,int64_t & Imm) const3526 bool PPCInstrInfo::isADDIInstrEligibleForFolding(MachineInstr &ADDIMI,
3527 int64_t &Imm) const {
3528 unsigned Opc = ADDIMI.getOpcode();
3529
3530 // Exit if the instruction is not ADDI.
3531 if (Opc != PPC::ADDI && Opc != PPC::ADDI8)
3532 return false;
3533
3534 // The operand may not necessarily be an immediate - it could be a relocation.
3535 if (!ADDIMI.getOperand(2).isImm())
3536 return false;
3537
3538 Imm = ADDIMI.getOperand(2).getImm();
3539
3540 return true;
3541 }
3542
isADDInstrEligibleForFolding(MachineInstr & ADDMI) const3543 bool PPCInstrInfo::isADDInstrEligibleForFolding(MachineInstr &ADDMI) const {
3544 unsigned Opc = ADDMI.getOpcode();
3545
3546 // Exit if the instruction is not ADD.
3547 return Opc == PPC::ADD4 || Opc == PPC::ADD8;
3548 }
3549
isImmInstrEligibleForFolding(MachineInstr & MI,unsigned & ToBeDeletedReg,unsigned & XFormOpcode,int64_t & OffsetImm,ImmInstrInfo & III) const3550 bool PPCInstrInfo::isImmInstrEligibleForFolding(MachineInstr &MI,
3551 unsigned &ToBeDeletedReg,
3552 unsigned &XFormOpcode,
3553 int64_t &OffsetImm,
3554 ImmInstrInfo &III) const {
3555 // Only handle load/store.
3556 if (!MI.mayLoadOrStore())
3557 return false;
3558
3559 unsigned Opc = MI.getOpcode();
3560
3561 XFormOpcode = RI.getMappedIdxOpcForImmOpc(Opc);
3562
3563 // Exit if instruction has no index form.
3564 if (XFormOpcode == PPC::INSTRUCTION_LIST_END)
3565 return false;
3566
3567 // TODO: sync the logic between instrHasImmForm() and ImmToIdxMap.
3568 if (!instrHasImmForm(XFormOpcode, isVFRegister(MI.getOperand(0).getReg()),
3569 III, true))
3570 return false;
3571
3572 if (!III.IsSummingOperands)
3573 return false;
3574
3575 MachineOperand ImmOperand = MI.getOperand(III.ImmOpNo);
3576 MachineOperand RegOperand = MI.getOperand(III.OpNoForForwarding);
3577 // Only support imm operands, not relocation slots or others.
3578 if (!ImmOperand.isImm())
3579 return false;
3580
3581 assert(RegOperand.isReg() && "Instruction format is not right");
3582
3583 // There are other use for ToBeDeletedReg after Imm instr, can not delete it.
3584 if (!RegOperand.isKill())
3585 return false;
3586
3587 ToBeDeletedReg = RegOperand.getReg();
3588 OffsetImm = ImmOperand.getImm();
3589
3590 return true;
3591 }
3592
isValidToBeChangedReg(MachineInstr * ADDMI,unsigned Index,MachineInstr * & ADDIMI,int64_t & OffsetAddi,int64_t OffsetImm) const3593 bool PPCInstrInfo::isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
3594 MachineInstr *&ADDIMI,
3595 int64_t &OffsetAddi,
3596 int64_t OffsetImm) const {
3597 assert((Index == 1 || Index == 2) && "Invalid operand index for add.");
3598 MachineOperand &MO = ADDMI->getOperand(Index);
3599
3600 if (!MO.isKill())
3601 return false;
3602
3603 bool OtherIntermediateUse = false;
3604
3605 ADDIMI = getDefMIPostRA(MO.getReg(), *ADDMI, OtherIntermediateUse);
3606 // Currently handle only one "add + Imminstr" pair case, exit if other
3607 // intermediate use for ToBeChangedReg found.
3608 // TODO: handle the cases where there are other "add + Imminstr" pairs
3609 // with same offset in Imminstr which is like:
3610 //
3611 // ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, OffsetAddi
3612 // ADD instr1: ToBeDeletedReg1 = ADD ToBeChangedReg, ScaleReg1
3613 // Imm instr1: Reg1 = op1 OffsetImm, ToBeDeletedReg1(killed)
3614 // ADD instr2: ToBeDeletedReg2 = ADD ToBeChangedReg(killed), ScaleReg2
3615 // Imm instr2: Reg2 = op2 OffsetImm, ToBeDeletedReg2(killed)
3616 //
3617 // can be converted to:
3618 //
3619 // new ADDI instr: ToBeChangedReg = ADDI FrameBaseReg,
3620 // (OffsetAddi + OffsetImm)
3621 // Index instr1: Reg1 = opx1 ScaleReg1, ToBeChangedReg
3622 // Index instr2: Reg2 = opx2 ScaleReg2, ToBeChangedReg(killed)
3623
3624 if (OtherIntermediateUse || !ADDIMI)
3625 return false;
3626 // Check if ADDI instr meets requirement.
3627 if (!isADDIInstrEligibleForFolding(*ADDIMI, OffsetAddi))
3628 return false;
3629
3630 if (isInt<16>(OffsetAddi + OffsetImm))
3631 return true;
3632 return false;
3633 }
3634
3635 // If this instruction has an immediate form and one of its operands is a
3636 // result of a load-immediate or an add-immediate, convert it to
3637 // the immediate form if the constant is in range.
convertToImmediateForm(MachineInstr & MI,MachineInstr ** KilledDef) const3638 bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
3639 MachineInstr **KilledDef) const {
3640 MachineFunction *MF = MI.getParent()->getParent();
3641 MachineRegisterInfo *MRI = &MF->getRegInfo();
3642 bool PostRA = !MRI->isSSA();
3643 bool SeenIntermediateUse = true;
3644 unsigned ForwardingOperand = ~0U;
3645 MachineInstr *DefMI = getForwardingDefMI(MI, ForwardingOperand,
3646 SeenIntermediateUse);
3647 if (!DefMI)
3648 return false;
3649 assert(ForwardingOperand < MI.getNumOperands() &&
3650 "The forwarding operand needs to be valid at this point");
3651 bool IsForwardingOperandKilled = MI.getOperand(ForwardingOperand).isKill();
3652 bool KillFwdDefMI = !SeenIntermediateUse && IsForwardingOperandKilled;
3653 if (KilledDef && KillFwdDefMI)
3654 *KilledDef = DefMI;
3655
3656 // If this is a imm instruction and its register operands is produced by ADDI,
3657 // put the imm into imm inst directly.
3658 if (RI.getMappedIdxOpcForImmOpc(MI.getOpcode()) !=
3659 PPC::INSTRUCTION_LIST_END &&
3660 transformToNewImmFormFedByAdd(MI, *DefMI, ForwardingOperand))
3661 return true;
3662
3663 ImmInstrInfo III;
3664 bool IsVFReg = MI.getOperand(0).isReg()
3665 ? isVFRegister(MI.getOperand(0).getReg())
3666 : false;
3667 bool HasImmForm = instrHasImmForm(MI.getOpcode(), IsVFReg, III, PostRA);
3668 // If this is a reg+reg instruction that has a reg+imm form,
3669 // and one of the operands is produced by an add-immediate,
3670 // try to convert it.
3671 if (HasImmForm &&
3672 transformToImmFormFedByAdd(MI, III, ForwardingOperand, *DefMI,
3673 KillFwdDefMI))
3674 return true;
3675
3676 // If this is a reg+reg instruction that has a reg+imm form,
3677 // and one of the operands is produced by LI, convert it now.
3678 if (HasImmForm &&
3679 transformToImmFormFedByLI(MI, III, ForwardingOperand, *DefMI))
3680 return true;
3681
3682 // If this is not a reg+reg, but the DefMI is LI/LI8, check if its user MI
3683 // can be simpified to LI.
3684 if (!HasImmForm && simplifyToLI(MI, *DefMI, ForwardingOperand, KilledDef))
3685 return true;
3686
3687 return false;
3688 }
3689
combineRLWINM(MachineInstr & MI,MachineInstr ** ToErase) const3690 bool PPCInstrInfo::combineRLWINM(MachineInstr &MI,
3691 MachineInstr **ToErase) const {
3692 MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
3693 unsigned FoldingReg = MI.getOperand(1).getReg();
3694 if (!Register::isVirtualRegister(FoldingReg))
3695 return false;
3696 MachineInstr *SrcMI = MRI->getVRegDef(FoldingReg);
3697 if (SrcMI->getOpcode() != PPC::RLWINM &&
3698 SrcMI->getOpcode() != PPC::RLWINM_rec &&
3699 SrcMI->getOpcode() != PPC::RLWINM8 &&
3700 SrcMI->getOpcode() != PPC::RLWINM8_rec)
3701 return false;
3702 assert((MI.getOperand(2).isImm() && MI.getOperand(3).isImm() &&
3703 MI.getOperand(4).isImm() && SrcMI->getOperand(2).isImm() &&
3704 SrcMI->getOperand(3).isImm() && SrcMI->getOperand(4).isImm()) &&
3705 "Invalid PPC::RLWINM Instruction!");
3706 uint64_t SHSrc = SrcMI->getOperand(2).getImm();
3707 uint64_t SHMI = MI.getOperand(2).getImm();
3708 uint64_t MBSrc = SrcMI->getOperand(3).getImm();
3709 uint64_t MBMI = MI.getOperand(3).getImm();
3710 uint64_t MESrc = SrcMI->getOperand(4).getImm();
3711 uint64_t MEMI = MI.getOperand(4).getImm();
3712
3713 assert((MEMI < 32 && MESrc < 32 && MBMI < 32 && MBSrc < 32) &&
3714 "Invalid PPC::RLWINM Instruction!");
3715 // If MBMI is bigger than MEMI, we always can not get run of ones.
3716 // RotatedSrcMask non-wrap:
3717 // 0........31|32........63
3718 // RotatedSrcMask: B---E B---E
3719 // MaskMI: -----------|--E B------
3720 // Result: ----- --- (Bad candidate)
3721 //
3722 // RotatedSrcMask wrap:
3723 // 0........31|32........63
3724 // RotatedSrcMask: --E B----|--E B----
3725 // MaskMI: -----------|--E B------
3726 // Result: --- -----|--- ----- (Bad candidate)
3727 //
3728 // One special case is RotatedSrcMask is a full set mask.
3729 // RotatedSrcMask full:
3730 // 0........31|32........63
3731 // RotatedSrcMask: ------EB---|-------EB---
3732 // MaskMI: -----------|--E B------
3733 // Result: -----------|--- ------- (Good candidate)
3734
3735 // Mark special case.
3736 bool SrcMaskFull = (MBSrc - MESrc == 1) || (MBSrc == 0 && MESrc == 31);
3737
3738 // For other MBMI > MEMI cases, just return.
3739 if ((MBMI > MEMI) && !SrcMaskFull)
3740 return false;
3741
3742 // Handle MBMI <= MEMI cases.
3743 APInt MaskMI = APInt::getBitsSetWithWrap(32, 32 - MEMI - 1, 32 - MBMI);
3744 // In MI, we only need low 32 bits of SrcMI, just consider about low 32
3745 // bit of SrcMI mask. Note that in APInt, lowerest bit is at index 0,
3746 // while in PowerPC ISA, lowerest bit is at index 63.
3747 APInt MaskSrc = APInt::getBitsSetWithWrap(32, 32 - MESrc - 1, 32 - MBSrc);
3748
3749 APInt RotatedSrcMask = MaskSrc.rotl(SHMI);
3750 APInt FinalMask = RotatedSrcMask & MaskMI;
3751 uint32_t NewMB, NewME;
3752 bool Simplified = false;
3753
3754 // If final mask is 0, MI result should be 0 too.
3755 if (FinalMask.isNullValue()) {
3756 bool Is64Bit =
3757 (MI.getOpcode() == PPC::RLWINM8 || MI.getOpcode() == PPC::RLWINM8_rec);
3758 Simplified = true;
3759 LLVM_DEBUG(dbgs() << "Replace Instr: ");
3760 LLVM_DEBUG(MI.dump());
3761
3762 if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8) {
3763 // Replace MI with "LI 0"
3764 MI.RemoveOperand(4);
3765 MI.RemoveOperand(3);
3766 MI.RemoveOperand(2);
3767 MI.getOperand(1).ChangeToImmediate(0);
3768 MI.setDesc(get(Is64Bit ? PPC::LI8 : PPC::LI));
3769 } else {
3770 // Replace MI with "ANDI_rec reg, 0"
3771 MI.RemoveOperand(4);
3772 MI.RemoveOperand(3);
3773 MI.getOperand(2).setImm(0);
3774 MI.setDesc(get(Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec));
3775 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
3776 if (SrcMI->getOperand(1).isKill()) {
3777 MI.getOperand(1).setIsKill(true);
3778 SrcMI->getOperand(1).setIsKill(false);
3779 } else
3780 // About to replace MI.getOperand(1), clear its kill flag.
3781 MI.getOperand(1).setIsKill(false);
3782 }
3783
3784 LLVM_DEBUG(dbgs() << "With: ");
3785 LLVM_DEBUG(MI.dump());
3786
3787 } else if ((isRunOfOnes((unsigned)(FinalMask.getZExtValue()), NewMB, NewME) &&
3788 NewMB <= NewME) ||
3789 SrcMaskFull) {
3790 // Here we only handle MBMI <= MEMI case, so NewMB must be no bigger
3791 // than NewME. Otherwise we get a 64 bit value after folding, but MI
3792 // return a 32 bit value.
3793 Simplified = true;
3794 LLVM_DEBUG(dbgs() << "Converting Instr: ");
3795 LLVM_DEBUG(MI.dump());
3796
3797 uint16_t NewSH = (SHSrc + SHMI) % 32;
3798 MI.getOperand(2).setImm(NewSH);
3799 // If SrcMI mask is full, no need to update MBMI and MEMI.
3800 if (!SrcMaskFull) {
3801 MI.getOperand(3).setImm(NewMB);
3802 MI.getOperand(4).setImm(NewME);
3803 }
3804 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
3805 if (SrcMI->getOperand(1).isKill()) {
3806 MI.getOperand(1).setIsKill(true);
3807 SrcMI->getOperand(1).setIsKill(false);
3808 } else
3809 // About to replace MI.getOperand(1), clear its kill flag.
3810 MI.getOperand(1).setIsKill(false);
3811
3812 LLVM_DEBUG(dbgs() << "To: ");
3813 LLVM_DEBUG(MI.dump());
3814 }
3815 if (Simplified & MRI->use_nodbg_empty(FoldingReg) &&
3816 !SrcMI->hasImplicitDef()) {
3817 // If FoldingReg has no non-debug use and it has no implicit def (it
3818 // is not RLWINMO or RLWINM8o), it's safe to delete its def SrcMI.
3819 // Otherwise keep it.
3820 *ToErase = SrcMI;
3821 LLVM_DEBUG(dbgs() << "Delete dead instruction: ");
3822 LLVM_DEBUG(SrcMI->dump());
3823 }
3824 return Simplified;
3825 }
3826
instrHasImmForm(unsigned Opc,bool IsVFReg,ImmInstrInfo & III,bool PostRA) const3827 bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg,
3828 ImmInstrInfo &III, bool PostRA) const {
3829 // The vast majority of the instructions would need their operand 2 replaced
3830 // with an immediate when switching to the reg+imm form. A marked exception
3831 // are the update form loads/stores for which a constant operand 2 would need
3832 // to turn into a displacement and move operand 1 to the operand 2 position.
3833 III.ImmOpNo = 2;
3834 III.OpNoForForwarding = 2;
3835 III.ImmWidth = 16;
3836 III.ImmMustBeMultipleOf = 1;
3837 III.TruncateImmTo = 0;
3838 III.IsSummingOperands = false;
3839 switch (Opc) {
3840 default: return false;
3841 case PPC::ADD4:
3842 case PPC::ADD8:
3843 III.SignedImm = true;
3844 III.ZeroIsSpecialOrig = 0;
3845 III.ZeroIsSpecialNew = 1;
3846 III.IsCommutative = true;
3847 III.IsSummingOperands = true;
3848 III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
3849 break;
3850 case PPC::ADDC:
3851 case PPC::ADDC8:
3852 III.SignedImm = true;
3853 III.ZeroIsSpecialOrig = 0;
3854 III.ZeroIsSpecialNew = 0;
3855 III.IsCommutative = true;
3856 III.IsSummingOperands = true;
3857 III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
3858 break;
3859 case PPC::ADDC_rec:
3860 III.SignedImm = true;
3861 III.ZeroIsSpecialOrig = 0;
3862 III.ZeroIsSpecialNew = 0;
3863 III.IsCommutative = true;
3864 III.IsSummingOperands = true;
3865 III.ImmOpcode = PPC::ADDIC_rec;
3866 break;
3867 case PPC::SUBFC:
3868 case PPC::SUBFC8:
3869 III.SignedImm = true;
3870 III.ZeroIsSpecialOrig = 0;
3871 III.ZeroIsSpecialNew = 0;
3872 III.IsCommutative = false;
3873 III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
3874 break;
3875 case PPC::CMPW:
3876 case PPC::CMPD:
3877 III.SignedImm = true;
3878 III.ZeroIsSpecialOrig = 0;
3879 III.ZeroIsSpecialNew = 0;
3880 III.IsCommutative = false;
3881 III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
3882 break;
3883 case PPC::CMPLW:
3884 case PPC::CMPLD:
3885 III.SignedImm = false;
3886 III.ZeroIsSpecialOrig = 0;
3887 III.ZeroIsSpecialNew = 0;
3888 III.IsCommutative = false;
3889 III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
3890 break;
3891 case PPC::AND_rec:
3892 case PPC::AND8_rec:
3893 case PPC::OR:
3894 case PPC::OR8:
3895 case PPC::XOR:
3896 case PPC::XOR8:
3897 III.SignedImm = false;
3898 III.ZeroIsSpecialOrig = 0;
3899 III.ZeroIsSpecialNew = 0;
3900 III.IsCommutative = true;
3901 switch(Opc) {
3902 default: llvm_unreachable("Unknown opcode");
3903 case PPC::AND_rec:
3904 III.ImmOpcode = PPC::ANDI_rec;
3905 break;
3906 case PPC::AND8_rec:
3907 III.ImmOpcode = PPC::ANDI8_rec;
3908 break;
3909 case PPC::OR: III.ImmOpcode = PPC::ORI; break;
3910 case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
3911 case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
3912 case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
3913 }
3914 break;
3915 case PPC::RLWNM:
3916 case PPC::RLWNM8:
3917 case PPC::RLWNM_rec:
3918 case PPC::RLWNM8_rec:
3919 case PPC::SLW:
3920 case PPC::SLW8:
3921 case PPC::SLW_rec:
3922 case PPC::SLW8_rec:
3923 case PPC::SRW:
3924 case PPC::SRW8:
3925 case PPC::SRW_rec:
3926 case PPC::SRW8_rec:
3927 case PPC::SRAW:
3928 case PPC::SRAW_rec:
3929 III.SignedImm = false;
3930 III.ZeroIsSpecialOrig = 0;
3931 III.ZeroIsSpecialNew = 0;
3932 III.IsCommutative = false;
3933 // This isn't actually true, but the instructions ignore any of the
3934 // upper bits, so any immediate loaded with an LI is acceptable.
3935 // This does not apply to shift right algebraic because a value
3936 // out of range will produce a -1/0.
3937 III.ImmWidth = 16;
3938 if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 || Opc == PPC::RLWNM_rec ||
3939 Opc == PPC::RLWNM8_rec)
3940 III.TruncateImmTo = 5;
3941 else
3942 III.TruncateImmTo = 6;
3943 switch(Opc) {
3944 default: llvm_unreachable("Unknown opcode");
3945 case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
3946 case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
3947 case PPC::RLWNM_rec:
3948 III.ImmOpcode = PPC::RLWINM_rec;
3949 break;
3950 case PPC::RLWNM8_rec:
3951 III.ImmOpcode = PPC::RLWINM8_rec;
3952 break;
3953 case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
3954 case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
3955 case PPC::SLW_rec:
3956 III.ImmOpcode = PPC::RLWINM_rec;
3957 break;
3958 case PPC::SLW8_rec:
3959 III.ImmOpcode = PPC::RLWINM8_rec;
3960 break;
3961 case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
3962 case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
3963 case PPC::SRW_rec:
3964 III.ImmOpcode = PPC::RLWINM_rec;
3965 break;
3966 case PPC::SRW8_rec:
3967 III.ImmOpcode = PPC::RLWINM8_rec;
3968 break;
3969 case PPC::SRAW:
3970 III.ImmWidth = 5;
3971 III.TruncateImmTo = 0;
3972 III.ImmOpcode = PPC::SRAWI;
3973 break;
3974 case PPC::SRAW_rec:
3975 III.ImmWidth = 5;
3976 III.TruncateImmTo = 0;
3977 III.ImmOpcode = PPC::SRAWI_rec;
3978 break;
3979 }
3980 break;
3981 case PPC::RLDCL:
3982 case PPC::RLDCL_rec:
3983 case PPC::RLDCR:
3984 case PPC::RLDCR_rec:
3985 case PPC::SLD:
3986 case PPC::SLD_rec:
3987 case PPC::SRD:
3988 case PPC::SRD_rec:
3989 case PPC::SRAD:
3990 case PPC::SRAD_rec:
3991 III.SignedImm = false;
3992 III.ZeroIsSpecialOrig = 0;
3993 III.ZeroIsSpecialNew = 0;
3994 III.IsCommutative = false;
3995 // This isn't actually true, but the instructions ignore any of the
3996 // upper bits, so any immediate loaded with an LI is acceptable.
3997 // This does not apply to shift right algebraic because a value
3998 // out of range will produce a -1/0.
3999 III.ImmWidth = 16;
4000 if (Opc == PPC::RLDCL || Opc == PPC::RLDCL_rec || Opc == PPC::RLDCR ||
4001 Opc == PPC::RLDCR_rec)
4002 III.TruncateImmTo = 6;
4003 else
4004 III.TruncateImmTo = 7;
4005 switch(Opc) {
4006 default: llvm_unreachable("Unknown opcode");
4007 case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
4008 case PPC::RLDCL_rec:
4009 III.ImmOpcode = PPC::RLDICL_rec;
4010 break;
4011 case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
4012 case PPC::RLDCR_rec:
4013 III.ImmOpcode = PPC::RLDICR_rec;
4014 break;
4015 case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
4016 case PPC::SLD_rec:
4017 III.ImmOpcode = PPC::RLDICR_rec;
4018 break;
4019 case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
4020 case PPC::SRD_rec:
4021 III.ImmOpcode = PPC::RLDICL_rec;
4022 break;
4023 case PPC::SRAD:
4024 III.ImmWidth = 6;
4025 III.TruncateImmTo = 0;
4026 III.ImmOpcode = PPC::SRADI;
4027 break;
4028 case PPC::SRAD_rec:
4029 III.ImmWidth = 6;
4030 III.TruncateImmTo = 0;
4031 III.ImmOpcode = PPC::SRADI_rec;
4032 break;
4033 }
4034 break;
4035 // Loads and stores:
4036 case PPC::LBZX:
4037 case PPC::LBZX8:
4038 case PPC::LHZX:
4039 case PPC::LHZX8:
4040 case PPC::LHAX:
4041 case PPC::LHAX8:
4042 case PPC::LWZX:
4043 case PPC::LWZX8:
4044 case PPC::LWAX:
4045 case PPC::LDX:
4046 case PPC::LFSX:
4047 case PPC::LFDX:
4048 case PPC::STBX:
4049 case PPC::STBX8:
4050 case PPC::STHX:
4051 case PPC::STHX8:
4052 case PPC::STWX:
4053 case PPC::STWX8:
4054 case PPC::STDX:
4055 case PPC::STFSX:
4056 case PPC::STFDX:
4057 III.SignedImm = true;
4058 III.ZeroIsSpecialOrig = 1;
4059 III.ZeroIsSpecialNew = 2;
4060 III.IsCommutative = true;
4061 III.IsSummingOperands = true;
4062 III.ImmOpNo = 1;
4063 III.OpNoForForwarding = 2;
4064 switch(Opc) {
4065 default: llvm_unreachable("Unknown opcode");
4066 case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
4067 case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
4068 case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
4069 case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
4070 case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
4071 case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
4072 case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
4073 case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
4074 case PPC::LWAX:
4075 III.ImmOpcode = PPC::LWA;
4076 III.ImmMustBeMultipleOf = 4;
4077 break;
4078 case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
4079 case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
4080 case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
4081 case PPC::STBX: III.ImmOpcode = PPC::STB; break;
4082 case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
4083 case PPC::STHX: III.ImmOpcode = PPC::STH; break;
4084 case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
4085 case PPC::STWX: III.ImmOpcode = PPC::STW; break;
4086 case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
4087 case PPC::STDX:
4088 III.ImmOpcode = PPC::STD;
4089 III.ImmMustBeMultipleOf = 4;
4090 break;
4091 case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
4092 case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
4093 }
4094 break;
4095 case PPC::LBZUX:
4096 case PPC::LBZUX8:
4097 case PPC::LHZUX:
4098 case PPC::LHZUX8:
4099 case PPC::LHAUX:
4100 case PPC::LHAUX8:
4101 case PPC::LWZUX:
4102 case PPC::LWZUX8:
4103 case PPC::LDUX:
4104 case PPC::LFSUX:
4105 case PPC::LFDUX:
4106 case PPC::STBUX:
4107 case PPC::STBUX8:
4108 case PPC::STHUX:
4109 case PPC::STHUX8:
4110 case PPC::STWUX:
4111 case PPC::STWUX8:
4112 case PPC::STDUX:
4113 case PPC::STFSUX:
4114 case PPC::STFDUX:
4115 III.SignedImm = true;
4116 III.ZeroIsSpecialOrig = 2;
4117 III.ZeroIsSpecialNew = 3;
4118 III.IsCommutative = false;
4119 III.IsSummingOperands = true;
4120 III.ImmOpNo = 2;
4121 III.OpNoForForwarding = 3;
4122 switch(Opc) {
4123 default: llvm_unreachable("Unknown opcode");
4124 case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
4125 case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
4126 case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
4127 case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
4128 case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
4129 case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
4130 case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
4131 case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
4132 case PPC::LDUX:
4133 III.ImmOpcode = PPC::LDU;
4134 III.ImmMustBeMultipleOf = 4;
4135 break;
4136 case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
4137 case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
4138 case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
4139 case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
4140 case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
4141 case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
4142 case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
4143 case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
4144 case PPC::STDUX:
4145 III.ImmOpcode = PPC::STDU;
4146 III.ImmMustBeMultipleOf = 4;
4147 break;
4148 case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
4149 case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
4150 }
4151 break;
4152 // Power9 and up only. For some of these, the X-Form version has access to all
4153 // 64 VSR's whereas the D-Form only has access to the VR's. We replace those
4154 // with pseudo-ops pre-ra and for post-ra, we check that the register loaded
4155 // into or stored from is one of the VR registers.
4156 case PPC::LXVX:
4157 case PPC::LXSSPX:
4158 case PPC::LXSDX:
4159 case PPC::STXVX:
4160 case PPC::STXSSPX:
4161 case PPC::STXSDX:
4162 case PPC::XFLOADf32:
4163 case PPC::XFLOADf64:
4164 case PPC::XFSTOREf32:
4165 case PPC::XFSTOREf64:
4166 if (!Subtarget.hasP9Vector())
4167 return false;
4168 III.SignedImm = true;
4169 III.ZeroIsSpecialOrig = 1;
4170 III.ZeroIsSpecialNew = 2;
4171 III.IsCommutative = true;
4172 III.IsSummingOperands = true;
4173 III.ImmOpNo = 1;
4174 III.OpNoForForwarding = 2;
4175 III.ImmMustBeMultipleOf = 4;
4176 switch(Opc) {
4177 default: llvm_unreachable("Unknown opcode");
4178 case PPC::LXVX:
4179 III.ImmOpcode = PPC::LXV;
4180 III.ImmMustBeMultipleOf = 16;
4181 break;
4182 case PPC::LXSSPX:
4183 if (PostRA) {
4184 if (IsVFReg)
4185 III.ImmOpcode = PPC::LXSSP;
4186 else {
4187 III.ImmOpcode = PPC::LFS;
4188 III.ImmMustBeMultipleOf = 1;
4189 }
4190 break;
4191 }
4192 LLVM_FALLTHROUGH;
4193 case PPC::XFLOADf32:
4194 III.ImmOpcode = PPC::DFLOADf32;
4195 break;
4196 case PPC::LXSDX:
4197 if (PostRA) {
4198 if (IsVFReg)
4199 III.ImmOpcode = PPC::LXSD;
4200 else {
4201 III.ImmOpcode = PPC::LFD;
4202 III.ImmMustBeMultipleOf = 1;
4203 }
4204 break;
4205 }
4206 LLVM_FALLTHROUGH;
4207 case PPC::XFLOADf64:
4208 III.ImmOpcode = PPC::DFLOADf64;
4209 break;
4210 case PPC::STXVX:
4211 III.ImmOpcode = PPC::STXV;
4212 III.ImmMustBeMultipleOf = 16;
4213 break;
4214 case PPC::STXSSPX:
4215 if (PostRA) {
4216 if (IsVFReg)
4217 III.ImmOpcode = PPC::STXSSP;
4218 else {
4219 III.ImmOpcode = PPC::STFS;
4220 III.ImmMustBeMultipleOf = 1;
4221 }
4222 break;
4223 }
4224 LLVM_FALLTHROUGH;
4225 case PPC::XFSTOREf32:
4226 III.ImmOpcode = PPC::DFSTOREf32;
4227 break;
4228 case PPC::STXSDX:
4229 if (PostRA) {
4230 if (IsVFReg)
4231 III.ImmOpcode = PPC::STXSD;
4232 else {
4233 III.ImmOpcode = PPC::STFD;
4234 III.ImmMustBeMultipleOf = 1;
4235 }
4236 break;
4237 }
4238 LLVM_FALLTHROUGH;
4239 case PPC::XFSTOREf64:
4240 III.ImmOpcode = PPC::DFSTOREf64;
4241 break;
4242 }
4243 break;
4244 }
4245 return true;
4246 }
4247
4248 // Utility function for swaping two arbitrary operands of an instruction.
swapMIOperands(MachineInstr & MI,unsigned Op1,unsigned Op2)4249 static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
4250 assert(Op1 != Op2 && "Cannot swap operand with itself.");
4251
4252 unsigned MaxOp = std::max(Op1, Op2);
4253 unsigned MinOp = std::min(Op1, Op2);
4254 MachineOperand MOp1 = MI.getOperand(MinOp);
4255 MachineOperand MOp2 = MI.getOperand(MaxOp);
4256 MI.RemoveOperand(std::max(Op1, Op2));
4257 MI.RemoveOperand(std::min(Op1, Op2));
4258
4259 // If the operands we are swapping are the two at the end (the common case)
4260 // we can just remove both and add them in the opposite order.
4261 if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
4262 MI.addOperand(MOp2);
4263 MI.addOperand(MOp1);
4264 } else {
4265 // Store all operands in a temporary vector, remove them and re-add in the
4266 // right order.
4267 SmallVector<MachineOperand, 2> MOps;
4268 unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
4269 for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
4270 MOps.push_back(MI.getOperand(i));
4271 MI.RemoveOperand(i);
4272 }
4273 // MOp2 needs to be added next.
4274 MI.addOperand(MOp2);
4275 // Now add the rest.
4276 for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
4277 if (i == MaxOp)
4278 MI.addOperand(MOp1);
4279 else {
4280 MI.addOperand(MOps.back());
4281 MOps.pop_back();
4282 }
4283 }
4284 }
4285 }
4286
4287 // Check if the 'MI' that has the index OpNoForForwarding
4288 // meets the requirement described in the ImmInstrInfo.
isUseMIElgibleForForwarding(MachineInstr & MI,const ImmInstrInfo & III,unsigned OpNoForForwarding) const4289 bool PPCInstrInfo::isUseMIElgibleForForwarding(MachineInstr &MI,
4290 const ImmInstrInfo &III,
4291 unsigned OpNoForForwarding
4292 ) const {
4293 // As the algorithm of checking for PPC::ZERO/PPC::ZERO8
4294 // would not work pre-RA, we can only do the check post RA.
4295 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4296 if (MRI.isSSA())
4297 return false;
4298
4299 // Cannot do the transform if MI isn't summing the operands.
4300 if (!III.IsSummingOperands)
4301 return false;
4302
4303 // The instruction we are trying to replace must have the ZeroIsSpecialOrig set.
4304 if (!III.ZeroIsSpecialOrig)
4305 return false;
4306
4307 // We cannot do the transform if the operand we are trying to replace
4308 // isn't the same as the operand the instruction allows.
4309 if (OpNoForForwarding != III.OpNoForForwarding)
4310 return false;
4311
4312 // Check if the instruction we are trying to transform really has
4313 // the special zero register as its operand.
4314 if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
4315 MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
4316 return false;
4317
4318 // This machine instruction is convertible if it is,
4319 // 1. summing the operands.
4320 // 2. one of the operands is special zero register.
4321 // 3. the operand we are trying to replace is allowed by the MI.
4322 return true;
4323 }
4324
4325 // Check if the DefMI is the add inst and set the ImmMO and RegMO
4326 // accordingly.
isDefMIElgibleForForwarding(MachineInstr & DefMI,const ImmInstrInfo & III,MachineOperand * & ImmMO,MachineOperand * & RegMO) const4327 bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI,
4328 const ImmInstrInfo &III,
4329 MachineOperand *&ImmMO,
4330 MachineOperand *&RegMO) const {
4331 unsigned Opc = DefMI.getOpcode();
4332 if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
4333 return false;
4334
4335 assert(DefMI.getNumOperands() >= 3 &&
4336 "Add inst must have at least three operands");
4337 RegMO = &DefMI.getOperand(1);
4338 ImmMO = &DefMI.getOperand(2);
4339
4340 // Before RA, ADDI first operand could be a frame index.
4341 if (!RegMO->isReg())
4342 return false;
4343
4344 // This DefMI is elgible for forwarding if it is:
4345 // 1. add inst
4346 // 2. one of the operands is Imm/CPI/Global.
4347 return isAnImmediateOperand(*ImmMO);
4348 }
4349
isRegElgibleForForwarding(const MachineOperand & RegMO,const MachineInstr & DefMI,const MachineInstr & MI,bool KillDefMI,bool & IsFwdFeederRegKilled) const4350 bool PPCInstrInfo::isRegElgibleForForwarding(
4351 const MachineOperand &RegMO, const MachineInstr &DefMI,
4352 const MachineInstr &MI, bool KillDefMI,
4353 bool &IsFwdFeederRegKilled) const {
4354 // x = addi y, imm
4355 // ...
4356 // z = lfdx 0, x -> z = lfd imm(y)
4357 // The Reg "y" can be forwarded to the MI(z) only when there is no DEF
4358 // of "y" between the DEF of "x" and "z".
4359 // The query is only valid post RA.
4360 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4361 if (MRI.isSSA())
4362 return false;
4363
4364 Register Reg = RegMO.getReg();
4365
4366 // Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg.
4367 MachineBasicBlock::const_reverse_iterator It = MI;
4368 MachineBasicBlock::const_reverse_iterator E = MI.getParent()->rend();
4369 It++;
4370 for (; It != E; ++It) {
4371 if (It->modifiesRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
4372 return false;
4373 else if (It->killsRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
4374 IsFwdFeederRegKilled = true;
4375 // Made it to DefMI without encountering a clobber.
4376 if ((&*It) == &DefMI)
4377 break;
4378 }
4379 assert((&*It) == &DefMI && "DefMI is missing");
4380
4381 // If DefMI also defines the register to be forwarded, we can only forward it
4382 // if DefMI is being erased.
4383 if (DefMI.modifiesRegister(Reg, &getRegisterInfo()))
4384 return KillDefMI;
4385
4386 return true;
4387 }
4388
isImmElgibleForForwarding(const MachineOperand & ImmMO,const MachineInstr & DefMI,const ImmInstrInfo & III,int64_t & Imm,int64_t BaseImm) const4389 bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
4390 const MachineInstr &DefMI,
4391 const ImmInstrInfo &III,
4392 int64_t &Imm,
4393 int64_t BaseImm) const {
4394 assert(isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate");
4395 if (DefMI.getOpcode() == PPC::ADDItocL) {
4396 // The operand for ADDItocL is CPI, which isn't imm at compiling time,
4397 // However, we know that, it is 16-bit width, and has the alignment of 4.
4398 // Check if the instruction met the requirement.
4399 if (III.ImmMustBeMultipleOf > 4 ||
4400 III.TruncateImmTo || III.ImmWidth != 16)
4401 return false;
4402
4403 // Going from XForm to DForm loads means that the displacement needs to be
4404 // not just an immediate but also a multiple of 4, or 16 depending on the
4405 // load. A DForm load cannot be represented if it is a multiple of say 2.
4406 // XForm loads do not have this restriction.
4407 if (ImmMO.isGlobal()) {
4408 const DataLayout &DL = ImmMO.getGlobal()->getParent()->getDataLayout();
4409 if (ImmMO.getGlobal()->getPointerAlignment(DL) < III.ImmMustBeMultipleOf)
4410 return false;
4411 }
4412
4413 return true;
4414 }
4415
4416 if (ImmMO.isImm()) {
4417 // It is Imm, we need to check if the Imm fit the range.
4418 // Sign-extend to 64-bits.
4419 // DefMI may be folded with another imm form instruction, the result Imm is
4420 // the sum of Imm of DefMI and BaseImm which is from imm form instruction.
4421 APInt ActualValue(64, ImmMO.getImm() + BaseImm, true);
4422 if (III.SignedImm && !ActualValue.isSignedIntN(III.ImmWidth))
4423 return false;
4424 if (!III.SignedImm && !ActualValue.isIntN(III.ImmWidth))
4425 return false;
4426 Imm = SignExtend64<16>(ImmMO.getImm() + BaseImm);
4427
4428 if (Imm % III.ImmMustBeMultipleOf)
4429 return false;
4430 if (III.TruncateImmTo)
4431 Imm &= ((1 << III.TruncateImmTo) - 1);
4432 }
4433 else
4434 return false;
4435
4436 // This ImmMO is forwarded if it meets the requriement describle
4437 // in ImmInstrInfo
4438 return true;
4439 }
4440
simplifyToLI(MachineInstr & MI,MachineInstr & DefMI,unsigned OpNoForForwarding,MachineInstr ** KilledDef) const4441 bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
4442 unsigned OpNoForForwarding,
4443 MachineInstr **KilledDef) const {
4444 if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) ||
4445 !DefMI.getOperand(1).isImm())
4446 return false;
4447
4448 MachineFunction *MF = MI.getParent()->getParent();
4449 MachineRegisterInfo *MRI = &MF->getRegInfo();
4450 bool PostRA = !MRI->isSSA();
4451
4452 int64_t Immediate = DefMI.getOperand(1).getImm();
4453 // Sign-extend to 64-bits.
4454 int64_t SExtImm = SignExtend64<16>(Immediate);
4455
4456 bool IsForwardingOperandKilled = MI.getOperand(OpNoForForwarding).isKill();
4457 Register ForwardingOperandReg = MI.getOperand(OpNoForForwarding).getReg();
4458
4459 bool ReplaceWithLI = false;
4460 bool Is64BitLI = false;
4461 int64_t NewImm = 0;
4462 bool SetCR = false;
4463 unsigned Opc = MI.getOpcode();
4464 switch (Opc) {
4465 default:
4466 return false;
4467
4468 // FIXME: Any branches conditional on such a comparison can be made
4469 // unconditional. At this time, this happens too infrequently to be worth
4470 // the implementation effort, but if that ever changes, we could convert
4471 // such a pattern here.
4472 case PPC::CMPWI:
4473 case PPC::CMPLWI:
4474 case PPC::CMPDI:
4475 case PPC::CMPLDI: {
4476 // Doing this post-RA would require dataflow analysis to reliably find uses
4477 // of the CR register set by the compare.
4478 // No need to fixup killed/dead flag since this transformation is only valid
4479 // before RA.
4480 if (PostRA)
4481 return false;
4482 // If a compare-immediate is fed by an immediate and is itself an input of
4483 // an ISEL (the most common case) into a COPY of the correct register.
4484 bool Changed = false;
4485 Register DefReg = MI.getOperand(0).getReg();
4486 int64_t Comparand = MI.getOperand(2).getImm();
4487 int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0
4488 ? (Comparand | 0xFFFFFFFFFFFF0000)
4489 : Comparand;
4490
4491 for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
4492 unsigned UseOpc = CompareUseMI.getOpcode();
4493 if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
4494 continue;
4495 unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
4496 Register TrueReg = CompareUseMI.getOperand(1).getReg();
4497 Register FalseReg = CompareUseMI.getOperand(2).getReg();
4498 unsigned RegToCopy =
4499 selectReg(SExtImm, SExtComparand, Opc, TrueReg, FalseReg, CRSubReg);
4500 if (RegToCopy == PPC::NoRegister)
4501 continue;
4502 // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
4503 if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
4504 CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
4505 replaceInstrOperandWithImm(CompareUseMI, 1, 0);
4506 CompareUseMI.RemoveOperand(3);
4507 CompareUseMI.RemoveOperand(2);
4508 continue;
4509 }
4510 LLVM_DEBUG(
4511 dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n");
4512 LLVM_DEBUG(DefMI.dump(); MI.dump(); CompareUseMI.dump());
4513 LLVM_DEBUG(dbgs() << "Is converted to:\n");
4514 // Convert to copy and remove unneeded operands.
4515 CompareUseMI.setDesc(get(PPC::COPY));
4516 CompareUseMI.RemoveOperand(3);
4517 CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
4518 CmpIselsConverted++;
4519 Changed = true;
4520 LLVM_DEBUG(CompareUseMI.dump());
4521 }
4522 if (Changed)
4523 return true;
4524 // This may end up incremented multiple times since this function is called
4525 // during a fixed-point transformation, but it is only meant to indicate the
4526 // presence of this opportunity.
4527 MissedConvertibleImmediateInstrs++;
4528 return false;
4529 }
4530
4531 // Immediate forms - may simply be convertable to an LI.
4532 case PPC::ADDI:
4533 case PPC::ADDI8: {
4534 // Does the sum fit in a 16-bit signed field?
4535 int64_t Addend = MI.getOperand(2).getImm();
4536 if (isInt<16>(Addend + SExtImm)) {
4537 ReplaceWithLI = true;
4538 Is64BitLI = Opc == PPC::ADDI8;
4539 NewImm = Addend + SExtImm;
4540 break;
4541 }
4542 return false;
4543 }
4544 case PPC::SUBFIC:
4545 case PPC::SUBFIC8: {
4546 // Only transform this if the CARRY implicit operand is dead.
4547 if (MI.getNumOperands() > 3 && !MI.getOperand(3).isDead())
4548 return false;
4549 int64_t Minuend = MI.getOperand(2).getImm();
4550 if (isInt<16>(Minuend - SExtImm)) {
4551 ReplaceWithLI = true;
4552 Is64BitLI = Opc == PPC::SUBFIC8;
4553 NewImm = Minuend - SExtImm;
4554 break;
4555 }
4556 return false;
4557 }
4558 case PPC::RLDICL:
4559 case PPC::RLDICL_rec:
4560 case PPC::RLDICL_32:
4561 case PPC::RLDICL_32_64: {
4562 // Use APInt's rotate function.
4563 int64_t SH = MI.getOperand(2).getImm();
4564 int64_t MB = MI.getOperand(3).getImm();
4565 APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec) ? 64 : 32,
4566 SExtImm, true);
4567 InVal = InVal.rotl(SH);
4568 uint64_t Mask = MB == 0 ? -1LLU : (1LLU << (63 - MB + 1)) - 1;
4569 InVal &= Mask;
4570 // Can't replace negative values with an LI as that will sign-extend
4571 // and not clear the left bits. If we're setting the CR bit, we will use
4572 // ANDI_rec which won't sign extend, so that's safe.
4573 if (isUInt<15>(InVal.getSExtValue()) ||
4574 (Opc == PPC::RLDICL_rec && isUInt<16>(InVal.getSExtValue()))) {
4575 ReplaceWithLI = true;
4576 Is64BitLI = Opc != PPC::RLDICL_32;
4577 NewImm = InVal.getSExtValue();
4578 SetCR = Opc == PPC::RLDICL_rec;
4579 break;
4580 }
4581 return false;
4582 }
4583 case PPC::RLWINM:
4584 case PPC::RLWINM8:
4585 case PPC::RLWINM_rec:
4586 case PPC::RLWINM8_rec: {
4587 int64_t SH = MI.getOperand(2).getImm();
4588 int64_t MB = MI.getOperand(3).getImm();
4589 int64_t ME = MI.getOperand(4).getImm();
4590 APInt InVal(32, SExtImm, true);
4591 InVal = InVal.rotl(SH);
4592 APInt Mask = APInt::getBitsSetWithWrap(32, 32 - ME - 1, 32 - MB);
4593 InVal &= Mask;
4594 // Can't replace negative values with an LI as that will sign-extend
4595 // and not clear the left bits. If we're setting the CR bit, we will use
4596 // ANDI_rec which won't sign extend, so that's safe.
4597 bool ValueFits = isUInt<15>(InVal.getSExtValue());
4598 ValueFits |= ((Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec) &&
4599 isUInt<16>(InVal.getSExtValue()));
4600 if (ValueFits) {
4601 ReplaceWithLI = true;
4602 Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8_rec;
4603 NewImm = InVal.getSExtValue();
4604 SetCR = Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec;
4605 break;
4606 }
4607 return false;
4608 }
4609 case PPC::ORI:
4610 case PPC::ORI8:
4611 case PPC::XORI:
4612 case PPC::XORI8: {
4613 int64_t LogicalImm = MI.getOperand(2).getImm();
4614 int64_t Result = 0;
4615 if (Opc == PPC::ORI || Opc == PPC::ORI8)
4616 Result = LogicalImm | SExtImm;
4617 else
4618 Result = LogicalImm ^ SExtImm;
4619 if (isInt<16>(Result)) {
4620 ReplaceWithLI = true;
4621 Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
4622 NewImm = Result;
4623 break;
4624 }
4625 return false;
4626 }
4627 }
4628
4629 if (ReplaceWithLI) {
4630 // We need to be careful with CR-setting instructions we're replacing.
4631 if (SetCR) {
4632 // We don't know anything about uses when we're out of SSA, so only
4633 // replace if the new immediate will be reproduced.
4634 bool ImmChanged = (SExtImm & NewImm) != NewImm;
4635 if (PostRA && ImmChanged)
4636 return false;
4637
4638 if (!PostRA) {
4639 // If the defining load-immediate has no other uses, we can just replace
4640 // the immediate with the new immediate.
4641 if (MRI->hasOneUse(DefMI.getOperand(0).getReg()))
4642 DefMI.getOperand(1).setImm(NewImm);
4643
4644 // If we're not using the GPR result of the CR-setting instruction, we
4645 // just need to and with zero/non-zero depending on the new immediate.
4646 else if (MRI->use_empty(MI.getOperand(0).getReg())) {
4647 if (NewImm) {
4648 assert(Immediate && "Transformation converted zero to non-zero?");
4649 NewImm = Immediate;
4650 }
4651 } else if (ImmChanged)
4652 return false;
4653 }
4654 }
4655
4656 LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
4657 LLVM_DEBUG(MI.dump());
4658 LLVM_DEBUG(dbgs() << "Fed by:\n");
4659 LLVM_DEBUG(DefMI.dump());
4660 LoadImmediateInfo LII;
4661 LII.Imm = NewImm;
4662 LII.Is64Bit = Is64BitLI;
4663 LII.SetCR = SetCR;
4664 // If we're setting the CR, the original load-immediate must be kept (as an
4665 // operand to ANDI_rec/ANDI8_rec).
4666 if (KilledDef && SetCR)
4667 *KilledDef = nullptr;
4668 replaceInstrWithLI(MI, LII);
4669
4670 // Fixup killed/dead flag after transformation.
4671 // Pattern:
4672 // ForwardingOperandReg = LI imm1
4673 // y = op2 imm2, ForwardingOperandReg(killed)
4674 if (IsForwardingOperandKilled)
4675 fixupIsDeadOrKill(&DefMI, &MI, ForwardingOperandReg);
4676
4677 LLVM_DEBUG(dbgs() << "With:\n");
4678 LLVM_DEBUG(MI.dump());
4679 return true;
4680 }
4681 return false;
4682 }
4683
transformToNewImmFormFedByAdd(MachineInstr & MI,MachineInstr & DefMI,unsigned OpNoForForwarding) const4684 bool PPCInstrInfo::transformToNewImmFormFedByAdd(
4685 MachineInstr &MI, MachineInstr &DefMI, unsigned OpNoForForwarding) const {
4686 MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
4687 bool PostRA = !MRI->isSSA();
4688 // FIXME: extend this to post-ra. Need to do some change in getForwardingDefMI
4689 // for post-ra.
4690 if (PostRA)
4691 return false;
4692
4693 // Only handle load/store.
4694 if (!MI.mayLoadOrStore())
4695 return false;
4696
4697 unsigned XFormOpcode = RI.getMappedIdxOpcForImmOpc(MI.getOpcode());
4698
4699 assert((XFormOpcode != PPC::INSTRUCTION_LIST_END) &&
4700 "MI must have x-form opcode");
4701
4702 // get Imm Form info.
4703 ImmInstrInfo III;
4704 bool IsVFReg = MI.getOperand(0).isReg()
4705 ? isVFRegister(MI.getOperand(0).getReg())
4706 : false;
4707
4708 if (!instrHasImmForm(XFormOpcode, IsVFReg, III, PostRA))
4709 return false;
4710
4711 if (!III.IsSummingOperands)
4712 return false;
4713
4714 if (OpNoForForwarding != III.OpNoForForwarding)
4715 return false;
4716
4717 MachineOperand ImmOperandMI = MI.getOperand(III.ImmOpNo);
4718 if (!ImmOperandMI.isImm())
4719 return false;
4720
4721 // Check DefMI.
4722 MachineOperand *ImmMO = nullptr;
4723 MachineOperand *RegMO = nullptr;
4724 if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
4725 return false;
4726 assert(ImmMO && RegMO && "Imm and Reg operand must have been set");
4727
4728 // Check Imm.
4729 // Set ImmBase from imm instruction as base and get new Imm inside
4730 // isImmElgibleForForwarding.
4731 int64_t ImmBase = ImmOperandMI.getImm();
4732 int64_t Imm = 0;
4733 if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm, ImmBase))
4734 return false;
4735
4736 // Get killed info in case fixup needed after transformation.
4737 unsigned ForwardKilledOperandReg = ~0U;
4738 if (MI.getOperand(III.OpNoForForwarding).isKill())
4739 ForwardKilledOperandReg = MI.getOperand(III.OpNoForForwarding).getReg();
4740
4741 // Do the transform
4742 LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
4743 LLVM_DEBUG(MI.dump());
4744 LLVM_DEBUG(dbgs() << "Fed by:\n");
4745 LLVM_DEBUG(DefMI.dump());
4746
4747 MI.getOperand(III.OpNoForForwarding).setReg(RegMO->getReg());
4748 if (RegMO->isKill()) {
4749 MI.getOperand(III.OpNoForForwarding).setIsKill(true);
4750 // Clear the killed flag in RegMO. Doing this here can handle some cases
4751 // that DefMI and MI are not in same basic block.
4752 RegMO->setIsKill(false);
4753 }
4754 MI.getOperand(III.ImmOpNo).setImm(Imm);
4755
4756 // FIXME: fix kill/dead flag if MI and DefMI are not in same basic block.
4757 if (DefMI.getParent() == MI.getParent()) {
4758 // Check if reg is killed between MI and DefMI.
4759 auto IsKilledFor = [&](unsigned Reg) {
4760 MachineBasicBlock::const_reverse_iterator It = MI;
4761 MachineBasicBlock::const_reverse_iterator E = DefMI;
4762 It++;
4763 for (; It != E; ++It) {
4764 if (It->killsRegister(Reg))
4765 return true;
4766 }
4767 return false;
4768 };
4769
4770 // Update kill flag
4771 if (RegMO->isKill() || IsKilledFor(RegMO->getReg()))
4772 fixupIsDeadOrKill(&DefMI, &MI, RegMO->getReg());
4773 if (ForwardKilledOperandReg != ~0U)
4774 fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
4775 }
4776
4777 LLVM_DEBUG(dbgs() << "With:\n");
4778 LLVM_DEBUG(MI.dump());
4779 return true;
4780 }
4781
4782 // If an X-Form instruction is fed by an add-immediate and one of its operands
4783 // is the literal zero, attempt to forward the source of the add-immediate to
4784 // the corresponding D-Form instruction with the displacement coming from
4785 // the immediate being added.
transformToImmFormFedByAdd(MachineInstr & MI,const ImmInstrInfo & III,unsigned OpNoForForwarding,MachineInstr & DefMI,bool KillDefMI) const4786 bool PPCInstrInfo::transformToImmFormFedByAdd(
4787 MachineInstr &MI, const ImmInstrInfo &III, unsigned OpNoForForwarding,
4788 MachineInstr &DefMI, bool KillDefMI) const {
4789 // RegMO ImmMO
4790 // | |
4791 // x = addi reg, imm <----- DefMI
4792 // y = op 0 , x <----- MI
4793 // |
4794 // OpNoForForwarding
4795 // Check if the MI meet the requirement described in the III.
4796 if (!isUseMIElgibleForForwarding(MI, III, OpNoForForwarding))
4797 return false;
4798
4799 // Check if the DefMI meet the requirement
4800 // described in the III. If yes, set the ImmMO and RegMO accordingly.
4801 MachineOperand *ImmMO = nullptr;
4802 MachineOperand *RegMO = nullptr;
4803 if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
4804 return false;
4805 assert(ImmMO && RegMO && "Imm and Reg operand must have been set");
4806
4807 // As we get the Imm operand now, we need to check if the ImmMO meet
4808 // the requirement described in the III. If yes set the Imm.
4809 int64_t Imm = 0;
4810 if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm))
4811 return false;
4812
4813 bool IsFwdFeederRegKilled = false;
4814 // Check if the RegMO can be forwarded to MI.
4815 if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI,
4816 IsFwdFeederRegKilled))
4817 return false;
4818
4819 // Get killed info in case fixup needed after transformation.
4820 unsigned ForwardKilledOperandReg = ~0U;
4821 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4822 bool PostRA = !MRI.isSSA();
4823 if (PostRA && MI.getOperand(OpNoForForwarding).isKill())
4824 ForwardKilledOperandReg = MI.getOperand(OpNoForForwarding).getReg();
4825
4826 // We know that, the MI and DefMI both meet the pattern, and
4827 // the Imm also meet the requirement with the new Imm-form.
4828 // It is safe to do the transformation now.
4829 LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
4830 LLVM_DEBUG(MI.dump());
4831 LLVM_DEBUG(dbgs() << "Fed by:\n");
4832 LLVM_DEBUG(DefMI.dump());
4833
4834 // Update the base reg first.
4835 MI.getOperand(III.OpNoForForwarding).ChangeToRegister(RegMO->getReg(),
4836 false, false,
4837 RegMO->isKill());
4838
4839 // Then, update the imm.
4840 if (ImmMO->isImm()) {
4841 // If the ImmMO is Imm, change the operand that has ZERO to that Imm
4842 // directly.
4843 replaceInstrOperandWithImm(MI, III.ZeroIsSpecialOrig, Imm);
4844 }
4845 else {
4846 // Otherwise, it is Constant Pool Index(CPI) or Global,
4847 // which is relocation in fact. We need to replace the special zero
4848 // register with ImmMO.
4849 // Before that, we need to fixup the target flags for imm.
4850 // For some reason, we miss to set the flag for the ImmMO if it is CPI.
4851 if (DefMI.getOpcode() == PPC::ADDItocL)
4852 ImmMO->setTargetFlags(PPCII::MO_TOC_LO);
4853
4854 // MI didn't have the interface such as MI.setOperand(i) though
4855 // it has MI.getOperand(i). To repalce the ZERO MachineOperand with
4856 // ImmMO, we need to remove ZERO operand and all the operands behind it,
4857 // and, add the ImmMO, then, move back all the operands behind ZERO.
4858 SmallVector<MachineOperand, 2> MOps;
4859 for (unsigned i = MI.getNumOperands() - 1; i >= III.ZeroIsSpecialOrig; i--) {
4860 MOps.push_back(MI.getOperand(i));
4861 MI.RemoveOperand(i);
4862 }
4863
4864 // Remove the last MO in the list, which is ZERO operand in fact.
4865 MOps.pop_back();
4866 // Add the imm operand.
4867 MI.addOperand(*ImmMO);
4868 // Now add the rest back.
4869 for (auto &MO : MOps)
4870 MI.addOperand(MO);
4871 }
4872
4873 // Update the opcode.
4874 MI.setDesc(get(III.ImmOpcode));
4875
4876 // Fix up killed/dead flag after transformation.
4877 // Pattern 1:
4878 // x = ADD KilledFwdFeederReg, imm
4879 // n = opn KilledFwdFeederReg(killed), regn
4880 // y = XOP 0, x
4881 // Pattern 2:
4882 // x = ADD reg(killed), imm
4883 // y = XOP 0, x
4884 if (IsFwdFeederRegKilled || RegMO->isKill())
4885 fixupIsDeadOrKill(&DefMI, &MI, RegMO->getReg());
4886 // Pattern 3:
4887 // ForwardKilledOperandReg = ADD reg, imm
4888 // y = XOP 0, ForwardKilledOperandReg(killed)
4889 if (ForwardKilledOperandReg != ~0U)
4890 fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
4891
4892 LLVM_DEBUG(dbgs() << "With:\n");
4893 LLVM_DEBUG(MI.dump());
4894
4895 return true;
4896 }
4897
transformToImmFormFedByLI(MachineInstr & MI,const ImmInstrInfo & III,unsigned ConstantOpNo,MachineInstr & DefMI) const4898 bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
4899 const ImmInstrInfo &III,
4900 unsigned ConstantOpNo,
4901 MachineInstr &DefMI) const {
4902 // DefMI must be LI or LI8.
4903 if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) ||
4904 !DefMI.getOperand(1).isImm())
4905 return false;
4906
4907 // Get Imm operand and Sign-extend to 64-bits.
4908 int64_t Imm = SignExtend64<16>(DefMI.getOperand(1).getImm());
4909
4910 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4911 bool PostRA = !MRI.isSSA();
4912 // Exit early if we can't convert this.
4913 if ((ConstantOpNo != III.OpNoForForwarding) && !III.IsCommutative)
4914 return false;
4915 if (Imm % III.ImmMustBeMultipleOf)
4916 return false;
4917 if (III.TruncateImmTo)
4918 Imm &= ((1 << III.TruncateImmTo) - 1);
4919 if (III.SignedImm) {
4920 APInt ActualValue(64, Imm, true);
4921 if (!ActualValue.isSignedIntN(III.ImmWidth))
4922 return false;
4923 } else {
4924 uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
4925 if ((uint64_t)Imm > UnsignedMax)
4926 return false;
4927 }
4928
4929 // If we're post-RA, the instructions don't agree on whether register zero is
4930 // special, we can transform this as long as the register operand that will
4931 // end up in the location where zero is special isn't R0.
4932 if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
4933 unsigned PosForOrigZero = III.ZeroIsSpecialOrig ? III.ZeroIsSpecialOrig :
4934 III.ZeroIsSpecialNew + 1;
4935 Register OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
4936 Register NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
4937 // If R0 is in the operand where zero is special for the new instruction,
4938 // it is unsafe to transform if the constant operand isn't that operand.
4939 if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
4940 ConstantOpNo != III.ZeroIsSpecialNew)
4941 return false;
4942 if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
4943 ConstantOpNo != PosForOrigZero)
4944 return false;
4945 }
4946
4947 // Get killed info in case fixup needed after transformation.
4948 unsigned ForwardKilledOperandReg = ~0U;
4949 if (PostRA && MI.getOperand(ConstantOpNo).isKill())
4950 ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg();
4951
4952 unsigned Opc = MI.getOpcode();
4953 bool SpecialShift32 = Opc == PPC::SLW || Opc == PPC::SLW_rec ||
4954 Opc == PPC::SRW || Opc == PPC::SRW_rec ||
4955 Opc == PPC::SLW8 || Opc == PPC::SLW8_rec ||
4956 Opc == PPC::SRW8 || Opc == PPC::SRW8_rec;
4957 bool SpecialShift64 = Opc == PPC::SLD || Opc == PPC::SLD_rec ||
4958 Opc == PPC::SRD || Opc == PPC::SRD_rec;
4959 bool SetCR = Opc == PPC::SLW_rec || Opc == PPC::SRW_rec ||
4960 Opc == PPC::SLD_rec || Opc == PPC::SRD_rec;
4961 bool RightShift = Opc == PPC::SRW || Opc == PPC::SRW_rec || Opc == PPC::SRD ||
4962 Opc == PPC::SRD_rec;
4963
4964 MI.setDesc(get(III.ImmOpcode));
4965 if (ConstantOpNo == III.OpNoForForwarding) {
4966 // Converting shifts to immediate form is a bit tricky since they may do
4967 // one of three things:
4968 // 1. If the shift amount is between OpSize and 2*OpSize, the result is zero
4969 // 2. If the shift amount is zero, the result is unchanged (save for maybe
4970 // setting CR0)
4971 // 3. If the shift amount is in [1, OpSize), it's just a shift
4972 if (SpecialShift32 || SpecialShift64) {
4973 LoadImmediateInfo LII;
4974 LII.Imm = 0;
4975 LII.SetCR = SetCR;
4976 LII.Is64Bit = SpecialShift64;
4977 uint64_t ShAmt = Imm & (SpecialShift32 ? 0x1F : 0x3F);
4978 if (Imm & (SpecialShift32 ? 0x20 : 0x40))
4979 replaceInstrWithLI(MI, LII);
4980 // Shifts by zero don't change the value. If we don't need to set CR0,
4981 // just convert this to a COPY. Can't do this post-RA since we've already
4982 // cleaned up the copies.
4983 else if (!SetCR && ShAmt == 0 && !PostRA) {
4984 MI.RemoveOperand(2);
4985 MI.setDesc(get(PPC::COPY));
4986 } else {
4987 // The 32 bit and 64 bit instructions are quite different.
4988 if (SpecialShift32) {
4989 // Left shifts use (N, 0, 31-N).
4990 // Right shifts use (32-N, N, 31) if 0 < N < 32.
4991 // use (0, 0, 31) if N == 0.
4992 uint64_t SH = ShAmt == 0 ? 0 : RightShift ? 32 - ShAmt : ShAmt;
4993 uint64_t MB = RightShift ? ShAmt : 0;
4994 uint64_t ME = RightShift ? 31 : 31 - ShAmt;
4995 replaceInstrOperandWithImm(MI, III.OpNoForForwarding, SH);
4996 MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
4997 .addImm(ME);
4998 } else {
4999 // Left shifts use (N, 63-N).
5000 // Right shifts use (64-N, N) if 0 < N < 64.
5001 // use (0, 0) if N == 0.
5002 uint64_t SH = ShAmt == 0 ? 0 : RightShift ? 64 - ShAmt : ShAmt;
5003 uint64_t ME = RightShift ? ShAmt : 63 - ShAmt;
5004 replaceInstrOperandWithImm(MI, III.OpNoForForwarding, SH);
5005 MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
5006 }
5007 }
5008 } else
5009 replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
5010 }
5011 // Convert commutative instructions (switch the operands and convert the
5012 // desired one to an immediate.
5013 else if (III.IsCommutative) {
5014 replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
5015 swapMIOperands(MI, ConstantOpNo, III.OpNoForForwarding);
5016 } else
5017 llvm_unreachable("Should have exited early!");
5018
5019 // For instructions for which the constant register replaces a different
5020 // operand than where the immediate goes, we need to swap them.
5021 if (III.OpNoForForwarding != III.ImmOpNo)
5022 swapMIOperands(MI, III.OpNoForForwarding, III.ImmOpNo);
5023
5024 // If the special R0/X0 register index are different for original instruction
5025 // and new instruction, we need to fix up the register class in new
5026 // instruction.
5027 if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
5028 if (III.ZeroIsSpecialNew) {
5029 // If operand at III.ZeroIsSpecialNew is physical reg(eg: ZERO/ZERO8), no
5030 // need to fix up register class.
5031 Register RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
5032 if (Register::isVirtualRegister(RegToModify)) {
5033 const TargetRegisterClass *NewRC =
5034 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
5035 &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
5036 MRI.setRegClass(RegToModify, NewRC);
5037 }
5038 }
5039 }
5040
5041 // Fix up killed/dead flag after transformation.
5042 // Pattern:
5043 // ForwardKilledOperandReg = LI imm
5044 // y = XOP reg, ForwardKilledOperandReg(killed)
5045 if (ForwardKilledOperandReg != ~0U)
5046 fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
5047 return true;
5048 }
5049
5050 const TargetRegisterClass *
updatedRC(const TargetRegisterClass * RC) const5051 PPCInstrInfo::updatedRC(const TargetRegisterClass *RC) const {
5052 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
5053 return &PPC::VSRCRegClass;
5054 return RC;
5055 }
5056
getRecordFormOpcode(unsigned Opcode)5057 int PPCInstrInfo::getRecordFormOpcode(unsigned Opcode) {
5058 return PPC::getRecordFormOpcode(Opcode);
5059 }
5060
5061 // This function returns true if the machine instruction
5062 // always outputs a value by sign-extending a 32 bit value,
5063 // i.e. 0 to 31-th bits are same as 32-th bit.
isSignExtendingOp(const MachineInstr & MI)5064 static bool isSignExtendingOp(const MachineInstr &MI) {
5065 int Opcode = MI.getOpcode();
5066 if (Opcode == PPC::LI || Opcode == PPC::LI8 || Opcode == PPC::LIS ||
5067 Opcode == PPC::LIS8 || Opcode == PPC::SRAW || Opcode == PPC::SRAW_rec ||
5068 Opcode == PPC::SRAWI || Opcode == PPC::SRAWI_rec || Opcode == PPC::LWA ||
5069 Opcode == PPC::LWAX || Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
5070 Opcode == PPC::LHA || Opcode == PPC::LHAX || Opcode == PPC::LHA8 ||
5071 Opcode == PPC::LHAX8 || Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
5072 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || Opcode == PPC::LBZU ||
5073 Opcode == PPC::LBZUX || Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
5074 Opcode == PPC::LHZ || Opcode == PPC::LHZX || Opcode == PPC::LHZ8 ||
5075 Opcode == PPC::LHZX8 || Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
5076 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 || Opcode == PPC::EXTSB ||
5077 Opcode == PPC::EXTSB_rec || Opcode == PPC::EXTSH ||
5078 Opcode == PPC::EXTSH_rec || Opcode == PPC::EXTSB8 ||
5079 Opcode == PPC::EXTSH8 || Opcode == PPC::EXTSW ||
5080 Opcode == PPC::EXTSW_rec || Opcode == PPC::SETB || Opcode == PPC::SETB8 ||
5081 Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
5082 Opcode == PPC::EXTSB8_32_64)
5083 return true;
5084
5085 if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
5086 return true;
5087
5088 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
5089 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec) &&
5090 MI.getOperand(3).getImm() > 0 &&
5091 MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
5092 return true;
5093
5094 return false;
5095 }
5096
5097 // This function returns true if the machine instruction
5098 // always outputs zeros in higher 32 bits.
isZeroExtendingOp(const MachineInstr & MI)5099 static bool isZeroExtendingOp(const MachineInstr &MI) {
5100 int Opcode = MI.getOpcode();
5101 // The 16-bit immediate is sign-extended in li/lis.
5102 // If the most significant bit is zero, all higher bits are zero.
5103 if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
5104 Opcode == PPC::LIS || Opcode == PPC::LIS8) {
5105 int64_t Imm = MI.getOperand(1).getImm();
5106 if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
5107 return true;
5108 }
5109
5110 // We have some variations of rotate-and-mask instructions
5111 // that clear higher 32-bits.
5112 if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec ||
5113 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec ||
5114 Opcode == PPC::RLDICL_32_64) &&
5115 MI.getOperand(3).getImm() >= 32)
5116 return true;
5117
5118 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) &&
5119 MI.getOperand(3).getImm() >= 32 &&
5120 MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
5121 return true;
5122
5123 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
5124 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec ||
5125 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
5126 MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
5127 return true;
5128
5129 // There are other instructions that clear higher 32-bits.
5130 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec ||
5131 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec ||
5132 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
5133 Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec ||
5134 Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec ||
5135 Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW || Opcode == PPC::SLW ||
5136 Opcode == PPC::SLW_rec || Opcode == PPC::SRW || Opcode == PPC::SRW_rec ||
5137 Opcode == PPC::SLW8 || Opcode == PPC::SRW8 || Opcode == PPC::SLWI ||
5138 Opcode == PPC::SLWI_rec || Opcode == PPC::SRWI ||
5139 Opcode == PPC::SRWI_rec || Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
5140 Opcode == PPC::LWZU || Opcode == PPC::LWZUX || Opcode == PPC::LWBRX ||
5141 Opcode == PPC::LHBRX || Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
5142 Opcode == PPC::LHZU || Opcode == PPC::LHZUX || Opcode == PPC::LBZ ||
5143 Opcode == PPC::LBZX || Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
5144 Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 || Opcode == PPC::LWZU8 ||
5145 Opcode == PPC::LWZUX8 || Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
5146 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || Opcode == PPC::LHZU8 ||
5147 Opcode == PPC::LHZUX8 || Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
5148 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
5149 Opcode == PPC::ANDI_rec || Opcode == PPC::ANDIS_rec ||
5150 Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWI_rec ||
5151 Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWI_rec ||
5152 Opcode == PPC::MFVSRWZ)
5153 return true;
5154
5155 return false;
5156 }
5157
5158 // This function returns true if the input MachineInstr is a TOC save
5159 // instruction.
isTOCSaveMI(const MachineInstr & MI) const5160 bool PPCInstrInfo::isTOCSaveMI(const MachineInstr &MI) const {
5161 if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
5162 return false;
5163 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5164 unsigned StackOffset = MI.getOperand(1).getImm();
5165 Register StackReg = MI.getOperand(2).getReg();
5166 Register SPReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
5167 if (StackReg == SPReg && StackOffset == TOCSaveOffset)
5168 return true;
5169
5170 return false;
5171 }
5172
5173 // We limit the max depth to track incoming values of PHIs or binary ops
5174 // (e.g. AND) to avoid excessive cost.
5175 const unsigned MAX_DEPTH = 1;
5176
5177 bool
isSignOrZeroExtended(const MachineInstr & MI,bool SignExt,const unsigned Depth) const5178 PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
5179 const unsigned Depth) const {
5180 const MachineFunction *MF = MI.getParent()->getParent();
5181 const MachineRegisterInfo *MRI = &MF->getRegInfo();
5182
5183 // If we know this instruction returns sign- or zero-extended result,
5184 // return true.
5185 if (SignExt ? isSignExtendingOp(MI):
5186 isZeroExtendingOp(MI))
5187 return true;
5188
5189 switch (MI.getOpcode()) {
5190 case PPC::COPY: {
5191 Register SrcReg = MI.getOperand(1).getReg();
5192
5193 // In both ELFv1 and v2 ABI, method parameters and the return value
5194 // are sign- or zero-extended.
5195 if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
5196 const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
5197 // We check the ZExt/SExt flags for a method parameter.
5198 if (MI.getParent()->getBasicBlock() ==
5199 &MF->getFunction().getEntryBlock()) {
5200 Register VReg = MI.getOperand(0).getReg();
5201 if (MF->getRegInfo().isLiveIn(VReg))
5202 return SignExt ? FuncInfo->isLiveInSExt(VReg) :
5203 FuncInfo->isLiveInZExt(VReg);
5204 }
5205
5206 // For a method return value, we check the ZExt/SExt flags in attribute.
5207 // We assume the following code sequence for method call.
5208 // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
5209 // BL8_NOP @func,...
5210 // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
5211 // %5 = COPY %x3; G8RC:%5
5212 if (SrcReg == PPC::X3) {
5213 const MachineBasicBlock *MBB = MI.getParent();
5214 MachineBasicBlock::const_instr_iterator II =
5215 MachineBasicBlock::const_instr_iterator(&MI);
5216 if (II != MBB->instr_begin() &&
5217 (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
5218 const MachineInstr &CallMI = *(--II);
5219 if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
5220 const Function *CalleeFn =
5221 dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
5222 if (!CalleeFn)
5223 return false;
5224 const IntegerType *IntTy =
5225 dyn_cast<IntegerType>(CalleeFn->getReturnType());
5226 const AttributeSet &Attrs =
5227 CalleeFn->getAttributes().getRetAttributes();
5228 if (IntTy && IntTy->getBitWidth() <= 32)
5229 return Attrs.hasAttribute(SignExt ? Attribute::SExt :
5230 Attribute::ZExt);
5231 }
5232 }
5233 }
5234 }
5235
5236 // If this is a copy from another register, we recursively check source.
5237 if (!Register::isVirtualRegister(SrcReg))
5238 return false;
5239 const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
5240 if (SrcMI != NULL)
5241 return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
5242
5243 return false;
5244 }
5245
5246 case PPC::ANDI_rec:
5247 case PPC::ANDIS_rec:
5248 case PPC::ORI:
5249 case PPC::ORIS:
5250 case PPC::XORI:
5251 case PPC::XORIS:
5252 case PPC::ANDI8_rec:
5253 case PPC::ANDIS8_rec:
5254 case PPC::ORI8:
5255 case PPC::ORIS8:
5256 case PPC::XORI8:
5257 case PPC::XORIS8: {
5258 // logical operation with 16-bit immediate does not change the upper bits.
5259 // So, we track the operand register as we do for register copy.
5260 Register SrcReg = MI.getOperand(1).getReg();
5261 if (!Register::isVirtualRegister(SrcReg))
5262 return false;
5263 const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
5264 if (SrcMI != NULL)
5265 return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
5266
5267 return false;
5268 }
5269
5270 // If all incoming values are sign-/zero-extended,
5271 // the output of OR, ISEL or PHI is also sign-/zero-extended.
5272 case PPC::OR:
5273 case PPC::OR8:
5274 case PPC::ISEL:
5275 case PPC::PHI: {
5276 if (Depth >= MAX_DEPTH)
5277 return false;
5278
5279 // The input registers for PHI are operand 1, 3, ...
5280 // The input registers for others are operand 1 and 2.
5281 unsigned E = 3, D = 1;
5282 if (MI.getOpcode() == PPC::PHI) {
5283 E = MI.getNumOperands();
5284 D = 2;
5285 }
5286
5287 for (unsigned I = 1; I != E; I += D) {
5288 if (MI.getOperand(I).isReg()) {
5289 Register SrcReg = MI.getOperand(I).getReg();
5290 if (!Register::isVirtualRegister(SrcReg))
5291 return false;
5292 const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
5293 if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
5294 return false;
5295 }
5296 else
5297 return false;
5298 }
5299 return true;
5300 }
5301
5302 // If at least one of the incoming values of an AND is zero extended
5303 // then the output is also zero-extended. If both of the incoming values
5304 // are sign-extended then the output is also sign extended.
5305 case PPC::AND:
5306 case PPC::AND8: {
5307 if (Depth >= MAX_DEPTH)
5308 return false;
5309
5310 assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
5311
5312 Register SrcReg1 = MI.getOperand(1).getReg();
5313 Register SrcReg2 = MI.getOperand(2).getReg();
5314
5315 if (!Register::isVirtualRegister(SrcReg1) ||
5316 !Register::isVirtualRegister(SrcReg2))
5317 return false;
5318
5319 const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
5320 const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
5321 if (!MISrc1 || !MISrc2)
5322 return false;
5323
5324 if(SignExt)
5325 return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
5326 isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
5327 else
5328 return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
5329 isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
5330 }
5331
5332 default:
5333 break;
5334 }
5335 return false;
5336 }
5337
isBDNZ(unsigned Opcode) const5338 bool PPCInstrInfo::isBDNZ(unsigned Opcode) const {
5339 return (Opcode == (Subtarget.isPPC64() ? PPC::BDNZ8 : PPC::BDNZ));
5340 }
5341
5342 namespace {
5343 class PPCPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
5344 MachineInstr *Loop, *EndLoop, *LoopCount;
5345 MachineFunction *MF;
5346 const TargetInstrInfo *TII;
5347 int64_t TripCount;
5348
5349 public:
PPCPipelinerLoopInfo(MachineInstr * Loop,MachineInstr * EndLoop,MachineInstr * LoopCount)5350 PPCPipelinerLoopInfo(MachineInstr *Loop, MachineInstr *EndLoop,
5351 MachineInstr *LoopCount)
5352 : Loop(Loop), EndLoop(EndLoop), LoopCount(LoopCount),
5353 MF(Loop->getParent()->getParent()),
5354 TII(MF->getSubtarget().getInstrInfo()) {
5355 // Inspect the Loop instruction up-front, as it may be deleted when we call
5356 // createTripCountGreaterCondition.
5357 if (LoopCount->getOpcode() == PPC::LI8 || LoopCount->getOpcode() == PPC::LI)
5358 TripCount = LoopCount->getOperand(1).getImm();
5359 else
5360 TripCount = -1;
5361 }
5362
shouldIgnoreForPipelining(const MachineInstr * MI) const5363 bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
5364 // Only ignore the terminator.
5365 return MI == EndLoop;
5366 }
5367
5368 Optional<bool>
createTripCountGreaterCondition(int TC,MachineBasicBlock & MBB,SmallVectorImpl<MachineOperand> & Cond)5369 createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
5370 SmallVectorImpl<MachineOperand> &Cond) override {
5371 if (TripCount == -1) {
5372 // Since BDZ/BDZ8 that we will insert will also decrease the ctr by 1,
5373 // so we don't need to generate any thing here.
5374 Cond.push_back(MachineOperand::CreateImm(0));
5375 Cond.push_back(MachineOperand::CreateReg(
5376 MF->getSubtarget<PPCSubtarget>().isPPC64() ? PPC::CTR8 : PPC::CTR,
5377 true));
5378 return {};
5379 }
5380
5381 return TripCount > TC;
5382 }
5383
setPreheader(MachineBasicBlock * NewPreheader)5384 void setPreheader(MachineBasicBlock *NewPreheader) override {
5385 // Do nothing. We want the LOOP setup instruction to stay in the *old*
5386 // preheader, so we can use BDZ in the prologs to adapt the loop trip count.
5387 }
5388
adjustTripCount(int TripCountAdjust)5389 void adjustTripCount(int TripCountAdjust) override {
5390 // If the loop trip count is a compile-time value, then just change the
5391 // value.
5392 if (LoopCount->getOpcode() == PPC::LI8 ||
5393 LoopCount->getOpcode() == PPC::LI) {
5394 int64_t TripCount = LoopCount->getOperand(1).getImm() + TripCountAdjust;
5395 LoopCount->getOperand(1).setImm(TripCount);
5396 return;
5397 }
5398
5399 // Since BDZ/BDZ8 that we will insert will also decrease the ctr by 1,
5400 // so we don't need to generate any thing here.
5401 }
5402
disposed()5403 void disposed() override {
5404 Loop->eraseFromParent();
5405 // Ensure the loop setup instruction is deleted too.
5406 LoopCount->eraseFromParent();
5407 }
5408 };
5409 } // namespace
5410
5411 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
analyzeLoopForPipelining(MachineBasicBlock * LoopBB) const5412 PPCInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
5413 // We really "analyze" only hardware loops right now.
5414 MachineBasicBlock::iterator I = LoopBB->getFirstTerminator();
5415 MachineBasicBlock *Preheader = *LoopBB->pred_begin();
5416 if (Preheader == LoopBB)
5417 Preheader = *std::next(LoopBB->pred_begin());
5418 MachineFunction *MF = Preheader->getParent();
5419
5420 if (I != LoopBB->end() && isBDNZ(I->getOpcode())) {
5421 SmallPtrSet<MachineBasicBlock *, 8> Visited;
5422 if (MachineInstr *LoopInst = findLoopInstr(*Preheader, Visited)) {
5423 Register LoopCountReg = LoopInst->getOperand(0).getReg();
5424 MachineRegisterInfo &MRI = MF->getRegInfo();
5425 MachineInstr *LoopCount = MRI.getUniqueVRegDef(LoopCountReg);
5426 return std::make_unique<PPCPipelinerLoopInfo>(LoopInst, &*I, LoopCount);
5427 }
5428 }
5429 return nullptr;
5430 }
5431
findLoopInstr(MachineBasicBlock & PreHeader,SmallPtrSet<MachineBasicBlock *,8> & Visited) const5432 MachineInstr *PPCInstrInfo::findLoopInstr(
5433 MachineBasicBlock &PreHeader,
5434 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
5435
5436 unsigned LOOPi = (Subtarget.isPPC64() ? PPC::MTCTR8loop : PPC::MTCTRloop);
5437
5438 // The loop set-up instruction should be in preheader
5439 for (auto &I : PreHeader.instrs())
5440 if (I.getOpcode() == LOOPi)
5441 return &I;
5442 return nullptr;
5443 }
5444
5445 // Return true if get the base operand, byte offset of an instruction and the
5446 // memory width. Width is the size of memory that is being loaded/stored.
getMemOperandWithOffsetWidth(const MachineInstr & LdSt,const MachineOperand * & BaseReg,int64_t & Offset,unsigned & Width,const TargetRegisterInfo * TRI) const5447 bool PPCInstrInfo::getMemOperandWithOffsetWidth(
5448 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset,
5449 unsigned &Width, const TargetRegisterInfo *TRI) const {
5450 if (!LdSt.mayLoadOrStore() || LdSt.getNumExplicitOperands() != 3)
5451 return false;
5452
5453 // Handle only loads/stores with base register followed by immediate offset.
5454 if (!LdSt.getOperand(1).isImm() ||
5455 (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()))
5456 return false;
5457 if (!LdSt.getOperand(1).isImm() ||
5458 (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()))
5459 return false;
5460
5461 if (!LdSt.hasOneMemOperand())
5462 return false;
5463
5464 Width = (*LdSt.memoperands_begin())->getSize();
5465 Offset = LdSt.getOperand(1).getImm();
5466 BaseReg = &LdSt.getOperand(2);
5467 return true;
5468 }
5469
areMemAccessesTriviallyDisjoint(const MachineInstr & MIa,const MachineInstr & MIb) const5470 bool PPCInstrInfo::areMemAccessesTriviallyDisjoint(
5471 const MachineInstr &MIa, const MachineInstr &MIb) const {
5472 assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
5473 assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
5474
5475 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
5476 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
5477 return false;
5478
5479 // Retrieve the base register, offset from the base register and width. Width
5480 // is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If
5481 // base registers are identical, and the offset of a lower memory access +
5482 // the width doesn't overlap the offset of a higher memory access,
5483 // then the memory accesses are different.
5484 const TargetRegisterInfo *TRI = &getRegisterInfo();
5485 const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
5486 int64_t OffsetA = 0, OffsetB = 0;
5487 unsigned int WidthA = 0, WidthB = 0;
5488 if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
5489 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
5490 if (BaseOpA->isIdenticalTo(*BaseOpB)) {
5491 int LowOffset = std::min(OffsetA, OffsetB);
5492 int HighOffset = std::max(OffsetA, OffsetB);
5493 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
5494 if (LowOffset + LowWidth <= HighOffset)
5495 return true;
5496 }
5497 }
5498 return false;
5499 }
5500