1 /* ESAME.C (c) Copyright Jan Jaeger, 2000-2013 */
2 /* ESAME (z/Architecture) instructions */
3
4 /*-------------------------------------------------------------------*/
5 /* This module implements the instructions which exist in ESAME */
6 /* mode but not in ESA/390 mode, as described in the manual */
7 /* SA22-7832-00 z/Architecture Principles of Operation */
8 /*-------------------------------------------------------------------*/
9
10 /*-------------------------------------------------------------------*/
11 /* Additional credits: */
12 /* EPSW/EREGG/LMD instructions - Roger Bowler */
13 /* PKA/PKU/UNPKA/UNPKU instructions - Roger Bowler */
14 /* Multiply/Divide Logical instructions - Vic Cross Feb2001*/
15 /* Long displacement facility - Roger Bowler June2003*/
16 /* DAT enhancement facility - Roger Bowler July2004*/
17 /* Extended immediate facility - Roger Bowler Aug2005*/
18 /*-------------------------------------------------------------------*/
19
20 #include "hstdinc.h"
21
22 #if !defined(_HENGINE_DLL_)
23 #define _HENGINE_DLL_
24 #endif
25
26 #if !defined(_ESAME_C_)
27 #define _ESAME_C_
28
29 BYTE * get_stfl_data(int, int *);
30
31 #endif
32
33 #include "hercules.h"
34 #include "opcode.h"
35 #include "inline.h"
36
37 #define CRYPTO_EXTERN extern
38 #include "crypto.h"
39
40 #include "clock.h"
41
42
43 #if defined(FEATURE_BINARY_FLOATING_POINT)
44 /*-------------------------------------------------------------------*/
45 /* B29C STFPC - Store FPC [S] */
46 /*-------------------------------------------------------------------*/
DEF_INST(store_fpc)47 DEF_INST(store_fpc)
48 {
49 int b2; /* Base of effective addr */
50 VADR effective_addr2; /* Effective address */
51
52 S(inst, regs, b2, effective_addr2);
53
54 BFPINST_CHECK(regs);
55
56 /* Store register contents at operand address */
57 ARCH_DEP(vstore4) ( regs->fpc, effective_addr2, b2, regs );
58
59 } /* end DEF_INST(store_fpc) */
60 #endif /*defined(FEATURE_BINARY_FLOATING_POINT)*/
61
62
63 #if defined(FEATURE_BINARY_FLOATING_POINT)
64 /*-------------------------------------------------------------------*/
65 /* B29D LFPC - Load FPC [S] */
66 /*-------------------------------------------------------------------*/
DEF_INST(load_fpc)67 DEF_INST(load_fpc)
68 {
69 int b2; /* Base of effective addr */
70 VADR effective_addr2; /* Effective address */
71 U32 tmp_fpc;
72
73 S(inst, regs, b2, effective_addr2);
74
75 BFPINST_CHECK(regs);
76
77 /* Load FPC register from operand address */
78 tmp_fpc = ARCH_DEP(vfetch4) (effective_addr2, b2, regs);
79
80 /* Program check if reserved bits are non-zero */
81 FPC_CHECK(tmp_fpc, regs);
82
83 /* Update FPC register */
84 regs->fpc = tmp_fpc;
85
86 } /* end DEF_INST(load_fpc) */
87 #endif /*defined(FEATURE_BINARY_FLOATING_POINT)*/
88
89
90 #if defined(FEATURE_BINARY_FLOATING_POINT)
91 /*-------------------------------------------------------------------*/
92 /* B384 SFPC - Set FPC [RRE] */
93 /*-------------------------------------------------------------------*/
DEF_INST(set_fpc)94 DEF_INST(set_fpc)
95 {
96 int r1, unused; /* Values of R fields */
97
98 RRE(inst, regs, r1, unused);
99
100 BFPINST_CHECK(regs);
101
102 /* Program check if reserved bits are non-zero */
103 FPC_CHECK(regs->GR_L(r1), regs);
104
105 /* Load FPC register from R1 register bits 32-63 */
106 regs->fpc = regs->GR_L(r1);
107
108 } /* end DEF_INST(set_fpc) */
109 #endif /*defined(FEATURE_BINARY_FLOATING_POINT)*/
110
111
112 #if defined(FEATURE_BINARY_FLOATING_POINT)
113 /*-------------------------------------------------------------------*/
114 /* B38C EFPC - Extract FPC [RRE] */
115 /*-------------------------------------------------------------------*/
DEF_INST(extract_fpc)116 DEF_INST(extract_fpc)
117 {
118 int r1, unused; /* Values of R fields */
119
120 RRE(inst, regs, r1, unused);
121
122 BFPINST_CHECK(regs);
123
124 /* Load R1 register bits 32-63 from FPC register */
125 regs->GR_L(r1) = regs->fpc;
126
127 } /* end DEF_INST(extract_fpc) */
128 #endif /*defined(FEATURE_BINARY_FLOATING_POINT)*/
129
130
131 #if defined(FEATURE_BINARY_FLOATING_POINT)
132 /*-------------------------------------------------------------------*/
133 /* B299 SRNM - Set BFP Rounding Mode (2-bit) [S] */
134 /*-------------------------------------------------------------------*/
DEF_INST(set_bfp_rounding_mode_2bit)135 DEF_INST(set_bfp_rounding_mode_2bit)
136 {
137 int b2; /* Base of effective addr */
138 VADR effective_addr2; /* Effective address */
139
140 S(inst, regs, b2, effective_addr2);
141
142 BFPINST_CHECK(regs);
143
144 /* Set FPC register BFP rounding mode bits from operand address */
145 regs->fpc &= ~(FPC_BRM_2BIT);
146 regs->fpc |= (effective_addr2 & FPC_BRM_2BIT);
147
148 #if defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY) /*810*/
149 /* Zeroize FPC bit 29 if FP Extension Facility is installed */
150 regs->fpc &= ~(FPC_BIT29);
151 #endif /*defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY)*/ /*810*/
152
153 } /* end DEF_INST(set_bfp_rounding_mode_2bit) */
154 #endif /*defined(FEATURE_BINARY_FLOATING_POINT)*/
155
156
157 #if defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY) /*810*/
158 /*-------------------------------------------------------------------*/
159 /* B2B8 SRNMB - Set BFP Rounding Mode (3-bit) [S] */
160 /*-------------------------------------------------------------------*/
DEF_INST(set_bfp_rounding_mode_3bit)161 DEF_INST(set_bfp_rounding_mode_3bit) /*810*/
162 {
163 int b2; /* Base of effective addr */
164 VADR effective_addr2; /* Effective address */
165
166 S(inst, regs, b2, effective_addr2);
167
168 BFPINST_CHECK(regs);
169
170 /* Program check if operand address bits 56-60 are non-zero */
171 if ((effective_addr2 & 0xFF) & ~(FPC_BRM_3BIT))
172 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
173
174 /* Program check if operand address bits 61-63 not a valid BRM */
175 if ((effective_addr2 & FPC_BRM_3BIT) == BRM_RESV4
176 || (effective_addr2 & FPC_BRM_3BIT) == BRM_RESV5
177 || (effective_addr2 & FPC_BRM_3BIT) == BRM_RESV6)
178 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
179
180 /* Set FPC 3-bit BFP rounding mode bits from operand address */
181 regs->fpc &= ~(FPC_BRM_3BIT);
182 regs->fpc |= (effective_addr2 & FPC_BRM_3BIT);
183
184 } /* end DEF_INST(set_bfp_rounding_mode_3bit) */
185 #endif /*defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY)*/ /*810*/
186
187
188 #if defined(FEATURE_LINKAGE_STACK)
189 /*-------------------------------------------------------------------*/
190 /* 01FF TRAP2 - Trap [E] */
191 /*-------------------------------------------------------------------*/
DEF_INST(trap2)192 DEF_INST(trap2)
193 {
194 E(inst, regs);
195
196 ARCH_DEP(trap_x) (0, regs, 0);
197
198 } /* end DEF_INST(trap2) */
199 #endif /*defined(FEATURE_LINKAGE_STACK)*/
200
201
202 #if defined(FEATURE_LINKAGE_STACK)
203 /*-------------------------------------------------------------------*/
204 /* B2FF TRAP4 - Trap [S] */
205 /*-------------------------------------------------------------------*/
DEF_INST(trap4)206 DEF_INST(trap4)
207 {
208 int b2; /* Base of effective addr */
209 VADR effective_addr2; /* Effective address */
210
211 S(inst, regs, b2, effective_addr2);
212
213 ARCH_DEP(trap_x) (1, regs, effective_addr2);
214
215 } /* end DEF_INST(trap4) */
216 #endif /*defined(FEATURE_LINKAGE_STACK)*/
217
218
219 #if defined(FEATURE_RESUME_PROGRAM)
220 /*-------------------------------------------------------------------*/
221 /* B277 RP - Resume Program [S] */
222 /*-------------------------------------------------------------------*/
DEF_INST(resume_program)223 DEF_INST(resume_program)
224 {
225 int b2; /* Base of effective addr */
226 VADR effective_addr2; /* Effective address */
227 VADR pl_addr; /* Address of parmlist */
228 U16 flags; /* Flags in parmfield */
229 U16 psw_offset; /* Offset to new PSW */
230 U16 ar_offset; /* Offset to new AR */
231 U16 gr_offset; /* Offset to new GR */
232 U32 ar; /* Copy of new AR */
233 U32 gr = 0; /* Copy of new GR */
234 #if defined(FEATURE_ESAME)
235 U16 grd_offset = 0; /* Offset of disjoint GR_H */
236 BYTE psw[16]; /* Copy of new PSW */
237 U64 gr8 = 0; /* Copy of new GR - 8 bytes */
238 U32 grd = 0; /* Copy of new GR - disjoint */
239 U64 ia; /* ia for trace */
240 BYTE amode64; /* save for amod64 */
241 #else /*!defined(FEATURE_ESAME)*/
242 BYTE psw[8]; /* Copy of new PSW */
243 U32 ia; /* ia for trace */
244 #endif /*!defined(FEATURE_ESAME)*/
245 BYTE amode; /* amode for trace */
246 PSW save_psw; /* Saved copy of current PSW */
247 BYTE *mn; /* Mainstor address of parm */
248 #ifdef FEATURE_TRACING
249 CREG newcr12 = 0; /* CR12 upon completion */
250 #endif /*FEATURE_TRACING*/
251
252 S(inst, regs, b2, effective_addr2);
253
254 /* Determine the address of the parameter list */
255 pl_addr = !regs->execflag ? PSW_IA(regs, 0) :
256 regs->exrl ? (regs->ET + 6) : (regs->ET + 4);
257
258 /* Fetch flags from the instruction address space */
259 mn = MADDR (pl_addr, USE_INST_SPACE, regs, ACCTYPE_INSTFETCH, regs->psw.pkey);
260 FETCH_HW(flags, mn);
261
262 #if defined(FEATURE_ESAME)
263 /* Bits 0-12 must be zero */
264 if(flags & 0xFFF8)
265 #else /*!defined(FEATURE_ESAME)*/
266 /* All flag bits must be zero in ESA/390 mode */
267 if(flags)
268 #endif /*!defined(FEATURE_ESAME)*/
269 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
270
271 /* Fetch the offset to the new psw */
272 mn = MADDR (pl_addr + 2, USE_INST_SPACE, regs, ACCTYPE_INSTFETCH, regs->psw.pkey);
273 FETCH_HW(psw_offset, mn);
274
275 /* Fetch the offset to the new ar */
276 mn = MADDR (pl_addr + 4, USE_INST_SPACE, regs, ACCTYPE_INSTFETCH, regs->psw.pkey);
277 FETCH_HW(ar_offset, mn);
278
279 /* Fetch the offset to the new gr */
280 mn = MADDR (pl_addr + 6, USE_INST_SPACE, regs, ACCTYPE_INSTFETCH, regs->psw.pkey);
281 FETCH_HW(gr_offset, mn);
282
283 #if defined(FEATURE_ESAME)
284 /* Fetch the offset to the new disjoint gr_h */
285 if((flags & 0x0003) == 0x0003)
286 {
287 mn = MADDR (pl_addr + 8, USE_INST_SPACE, regs, ACCTYPE_INSTFETCH, regs->psw.pkey);
288 FETCH_HW(grd_offset, mn);
289 }
290 #endif /*defined(FEATURE_ESAME)*/
291
292
293 /* Fetch the PSW from the operand address + psw offset */
294 #if defined(FEATURE_ESAME)
295 if(flags & 0x0004)
296 ARCH_DEP(vfetchc) (psw, 15, (effective_addr2 + psw_offset)
297 & ADDRESS_MAXWRAP(regs), b2, regs);
298 else
299 #endif /*defined(FEATURE_ESAME)*/
300 ARCH_DEP(vfetchc) (psw, 7, (effective_addr2 + psw_offset)
301 & ADDRESS_MAXWRAP(regs), b2, regs);
302
303
304 /* Fetch new AR (B2) from operand address + AR offset */
305 ar = ARCH_DEP(vfetch4) ((effective_addr2 + ar_offset)
306 & ADDRESS_MAXWRAP(regs), b2, regs);
307
308
309 /* Fetch the new gr from operand address + GPR offset */
310 #if defined(FEATURE_ESAME)
311 /* General Register Field 1 is eight bytes */
312 if((flags & 0x0003) == 0x0002)
313 {
314 gr8 = ARCH_DEP(vfetch8) ((effective_addr2 + gr_offset)
315 & ADDRESS_MAXWRAP(regs), b2, regs);
316 }
317 /* General Register Field 1 and 2 are four bytes - disjoint */
318 else if((flags & 0x0003) == 0x0003)
319 {
320 gr = ARCH_DEP(vfetch4) ((effective_addr2 + gr_offset)
321 & ADDRESS_MAXWRAP(regs), b2, regs);
322 grd = ARCH_DEP(vfetch4) ((effective_addr2 + grd_offset)
323 & ADDRESS_MAXWRAP(regs), b2, regs);
324 }
325 else
326 #endif /*defined(FEATURE_ESAME)*/
327 gr = ARCH_DEP(vfetch4) ((effective_addr2 + gr_offset)
328 & ADDRESS_MAXWRAP(regs), b2, regs);
329
330 #if defined(FEATURE_TRACING)
331 #if defined(FEATURE_ESAME)
332 /* fetch 8 or 4 byte IA depending on psw operand size */
333 if (flags & 0x0004)
334 FETCH_DW(ia, psw + 8);
335 else
336 FETCH_FW(ia, psw + 4);
337 amode64 = psw[3] & 0x01;
338 #else /*!defined(FEATURE_ESAME)*/
339 FETCH_FW(ia, psw + 4);
340 ia &= 0x7FFFFFFF;
341 #endif /*!defined(FEATURE_ESAME)*/
342 amode = psw[4] & 0x80;
343
344 #if defined(FEATURE_ESAME)
345 /* Add a mode trace entry when switching in/out of 64 bit mode */
346 if((regs->CR(12) & CR12_MTRACE) && (regs->psw.amode64 != amode64))
347 newcr12 = ARCH_DEP(trace_ms) (regs->CR(12) & CR12_BRTRACE ? 1 : 0, ia, regs);
348 else
349 #endif /*defined(FEATURE_ESAME)*/
350 if (regs->CR(12) & CR12_BRTRACE)
351 newcr12 = ARCH_DEP(trace_br) (amode, ia, regs);
352 #endif /*defined(FEATURE_TRACING)*/
353
354 INVALIDATE_AIA(regs);
355
356 /* Save current PSW */
357 save_psw = regs->psw;
358
359
360 /* Use bytes 0 and 1 of old psw and byte 2 from operand */
361 psw[0] = save_psw.sysmask;
362 psw[1] = save_psw.pkey | save_psw.states;
363 /* ignore bits 24-30 */
364 psw[3] = 0x01 & psw[3];
365
366
367 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
368 if(SIE_STATB(regs, MX, XC)
369 && (psw[2] & 0x80))
370 regs->program_interrupt (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
371 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
372
373 /* Special operation exception when setting AR space mode
374 and ASF is off */
375 if(!REAL_MODE(®s->psw)
376 && ((psw[2] & 0xC0) == 0x40)
377 && !ASF_ENABLED(regs) )
378 regs->program_interrupt (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
379
380 /* Privileged Operation exception when setting home
381 space mode in problem state */
382 if(!REAL_MODE(®s->psw)
383 && PROBSTATE(®s->psw)
384 && ((psw[2] & 0xC0) == 0xC0) )
385 regs->program_interrupt (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
386
387 #if defined(FEATURE_ESAME)
388 /* Handle 16 byte psw operand */
389 if(flags & 0x0004)
390 {
391 psw[1] &= ~0x08; /* force bit 12 off */
392 if( ARCH_DEP(load_psw) (regs, psw) )/* only check invalid IA not odd */
393 {
394 /* restore the psw */
395 regs->psw = save_psw;
396 /* And generate a program interrupt */
397 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
398 }
399 }
400 /* Handle 8 byte psw operand */
401 else
402 {
403 /* Save amode64, do not check amode64 bit (force to zero) */
404 /* This is so s390_load_psw will work. */
405 /* Checks for amode64 will be done a few lines later */
406 amode64 = psw[3] & 01;
407 psw[3] &= ~0x01;
408 #endif /*defined(FEATURE_ESAME)*/
409 psw[1] |= 0x08; /* force bit 12 on */
410 if( s390_load_psw(regs, psw) )
411 {
412 /* restore the psw */
413 regs->psw = save_psw;
414 /* And generate a program interrupt */
415 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
416 }
417 #if defined(FEATURE_ESAME)
418 regs->psw.states &= ~BIT(PSW_NOTESAME_BIT);
419 /* clear high word of IA since operand was 8-byte psw */
420 regs->psw.IA_H = 0;
421 /* Check original amode64 and restore and do checks */
422 if (amode64)
423 {
424 /* if amode64 (31) on, then amode (32) must be on too */
425 if (!regs->psw.amode)
426 {
427 /* restore the psw */
428 regs->psw = save_psw;
429 /* And generate a program interrupt */
430 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
431 }
432 regs->psw.amode64 = 1;
433 regs->psw.AMASK = AMASK64;
434 }
435 else
436 {
437 regs->psw.amode64 = 0;
438 regs->psw.AMASK_H = 0;
439 }
440 }
441 #endif /*defined(FEATURE_ESAME)*/
442
443 /* Check for odd IA in psw */
444 if(regs->psw.IA & 0x01)
445 {
446 /* restore the psw */
447 regs->psw = save_psw;
448 /* And generate a program interrupt */
449 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
450 }
451
452 /* Update access register b2 */
453 regs->AR(b2) = ar;
454
455 /* Update general register b2 */
456 #if defined(FEATURE_ESAME)
457 if((flags & 0x0003) == 0x0002)
458 regs->GR_G(b2) = gr8;
459 else if((flags & 0x0003) == 0x0003)
460 {
461 regs->GR_L(b2) = gr;
462 regs->GR_H(b2) = grd;
463 }
464 else
465 #endif /*defined(FEATURE_ESAME)*/
466 regs->GR_L(b2) = gr;
467
468 #ifdef FEATURE_TRACING
469 /* Update trace table address if branch tracing is on */
470 if (newcr12)
471 regs->CR(12) = newcr12;
472 #endif /*FEATURE_TRACING*/
473
474 SET_BEAR_REG(regs, regs->ip - 4);
475 SET_IC_ECMODE_MASK(regs);
476 SET_AEA_MODE(regs);
477 PER_SB(regs, regs->psw.IA);
478
479 /* Space switch event when switching into or
480 out of home space mode AND space-switch-event on in CR1 or CR13 */
481 if((HOME_SPACE_MODE(&(regs->psw)) ^ HOME_SPACE_MODE(&save_psw))
482 && (!REAL_MODE(®s->psw))
483 && ((regs->CR(1) & SSEVENT_BIT) || (regs->CR(13) & SSEVENT_BIT)
484 || OPEN_IC_PER(regs) ))
485 {
486 if (HOME_SPACE_MODE(&(regs->psw)))
487 {
488 /* When switching into home-space mode, set the
489 translation exception address equal to the primary
490 ASN, with the high-order bit set equal to the value
491 of the primary space-switch-event control bit */
492 regs->TEA = regs->CR_LHL(4);
493 if (regs->CR(1) & SSEVENT_BIT)
494 regs->TEA |= TEA_SSEVENT;
495 }
496 else
497 {
498 /* When switching out of home-space mode, set the
499 translation exception address equal to zero, with
500 the high-order bit set equal to the value of the
501 home space-switch-event control bit */
502 regs->TEA = 0;
503 if (regs->CR(13) & SSEVENT_BIT)
504 regs->TEA |= TEA_SSEVENT;
505 }
506 regs->program_interrupt (regs, PGM_SPACE_SWITCH_EVENT);
507 }
508
509 RETURN_INTCHECK(regs);
510
511 } /* end DEF_INST(resume_program) */
512 #endif /*defined(FEATURE_RESUME_PROGRAM)*/
513
514
515 #if defined(FEATURE_ESAME) && defined(FEATURE_TRACING)
516 /*-------------------------------------------------------------------*/
517 /* EB0F TRACG - Trace Long [RSY] */
518 /*-------------------------------------------------------------------*/
DEF_INST(trace_long)519 DEF_INST(trace_long)
520 {
521 int r1, r3; /* Register numbers */
522 int b2; /* effective address base */
523 VADR effective_addr2; /* effective address */
524 #if defined(FEATURE_TRACING)
525 U32 op; /* Operand */
526 #endif /*defined(FEATURE_TRACING)*/
527
528 RSY(inst, regs, r1, r3, b2, effective_addr2);
529
530 PRIV_CHECK(regs);
531
532 FW_CHECK(effective_addr2, regs);
533
534 /* Exit if explicit tracing (control reg 12 bit 31) is off */
535 if ( (regs->CR(12) & CR12_EXTRACE) == 0 )
536 return;
537
538 /* Fetch the trace operand */
539 op = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
540
541 /* Exit if bit zero of the trace operand is one */
542 if ( (op & 0x80000000) )
543 return;
544
545 /* Perform serialization and checkpoint-synchronization */
546 PERFORM_SERIALIZATION (regs);
547 PERFORM_CHKPT_SYNC (regs);
548
549 regs->CR(12) = ARCH_DEP(trace_tg) (r1, r3, op, regs);
550
551 /* Perform serialization and checkpoint-synchronization */
552 PERFORM_SERIALIZATION (regs);
553 PERFORM_CHKPT_SYNC (regs);
554
555 } /* end DEF_INST(trace_long) */
556 #endif /*defined(FEATURE_ESAME) && defined(FEATURE_TRACING)*/
557
558
559 #if defined(FEATURE_ESAME)
560 /*-------------------------------------------------------------------*/
561 /* E30E CVBG - Convert to Binary Long [RXY] */
562 /*-------------------------------------------------------------------*/
DEF_INST(convert_to_binary_long)563 DEF_INST(convert_to_binary_long)
564 {
565 U64 dreg; /* 64-bit result accumulator */
566 int r1; /* Value of R1 field */
567 int b2; /* Base of effective addr */
568 VADR effective_addr2; /* Effective address */
569 int ovf; /* 1=overflow */
570 int dxf; /* 1=data exception */
571 BYTE dec[16]; /* Packed decimal operand */
572
573 RXY(inst, regs, r1, b2, effective_addr2);
574
575 /* Fetch 16-byte packed decimal operand */
576 ARCH_DEP(vfetchc) ( dec, 16-1, effective_addr2, b2, regs );
577
578 /* Convert 16-byte packed decimal to 64-bit signed binary */
579 packed_to_binary (dec, 16-1, &dreg, &ovf, &dxf);
580
581 /* Data exception if invalid digits or sign */
582 if (dxf)
583 {
584 regs->dxc = DXC_DECIMAL;
585 regs->program_interrupt (regs, PGM_DATA_EXCEPTION);
586 }
587
588 /* Exception if overflow (operation suppressed, R1 unchanged) */
589 if (ovf)
590 regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
591
592 /* Store 64-bit result into R1 register */
593 regs->GR_G(r1) = dreg;
594
595 } /* end DEF_INST(convert_to_binary_long) */
596 #endif /*defined(FEATURE_ESAME)*/
597
598
599 #if defined(FEATURE_ESAME)
600 /*-------------------------------------------------------------------*/
601 /* E32E CVDG - Convert to Decimal Long [RXY] */
602 /*-------------------------------------------------------------------*/
DEF_INST(convert_to_decimal_long)603 DEF_INST(convert_to_decimal_long)
604 {
605 S64 bin; /* Signed value to convert */
606 int r1; /* Value of R1 field */
607 int b2; /* Base of effective addr */
608 VADR effective_addr2; /* Effective address */
609 BYTE dec[16]; /* Packed decimal result */
610
611 RXY(inst, regs, r1, b2, effective_addr2);
612
613 /* Load signed value of register */
614 bin = (S64)(regs->GR_G(r1));
615
616 /* Convert to 16-byte packed decimal number */
617 binary_to_packed (bin, dec);
618
619 /* Store 16-byte packed decimal result at operand address */
620 ARCH_DEP(vstorec) ( dec, 16-1, effective_addr2, b2, regs );
621
622 } /* end DEF_INST(convert_to_decimal_long) */
623 #endif /*defined(FEATURE_ESAME)*/
624
625
626 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
627 /*-------------------------------------------------------------------*/
628 /* E396 ML - Multiply Logical [RXY] */
629 /*-------------------------------------------------------------------*/
DEF_INST(multiply_logical)630 DEF_INST(multiply_logical)
631 {
632 int r1; /* Values of R fields */
633 int b2; /* Base of effective addr */
634 VADR effective_addr2; /* Effective Address */
635 U32 m;
636 U64 p;
637
638 RXY(inst, regs, r1, b2, effective_addr2);
639
640 ODD_CHECK(r1, regs);
641
642 /* Load second operand from operand address */
643 m = ARCH_DEP(vfetch4) (effective_addr2, b2, regs);
644
645 /* Multiply unsigned values */
646 p = (U64)regs->GR_L(r1 + 1) * m;
647
648 /* Store the result */
649 regs->GR_L(r1) = (p >> 32);
650 regs->GR_L(r1 + 1) = (p & 0xFFFFFFFF);
651
652 } /* end DEF_INST(multiply_logical) */
653 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
654
655
656 #if defined(FEATURE_ESAME)
657 /*-------------------------------------------------------------------*/
658 /* E386 MLG - Multiply Logical Long [RXY] */
659 /*-------------------------------------------------------------------*/
DEF_INST(multiply_logical_long)660 DEF_INST(multiply_logical_long)
661 {
662 int r1; /* Values of R fields */
663 int b2; /* Base of effective addr */
664 VADR effective_addr2; /* Effective Address */
665 U64 m, ph, pl;
666
667 RXY(inst, regs, r1, b2, effective_addr2);
668
669 ODD_CHECK(r1, regs);
670
671 /* Load second operand from operand address */
672 m = ARCH_DEP(vfetch8) (effective_addr2, b2, regs);
673
674 /* Multiply unsigned values */
675 mult_logical_long(&ph, &pl, regs->GR_G(r1 + 1), m);
676
677 /* Store the result */
678 regs->GR_G(r1) = ph;
679 regs->GR_G(r1 + 1) = pl;
680
681 } /* end DEF_INST(multiply_logical_long) */
682 #endif /*defined(FEATURE_ESAME)*/
683
684
685 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
686 /*-------------------------------------------------------------------*/
687 /* B996 MLR - Multiply Logical Register [RRE] */
688 /*-------------------------------------------------------------------*/
DEF_INST(multiply_logical_register)689 DEF_INST(multiply_logical_register)
690 {
691 int r1, r2; /* Values of R fields */
692 U64 p;
693
694 RRE(inst, regs, r1, r2);
695
696 ODD_CHECK(r1, regs);
697
698 /* Multiply unsigned values */
699 p = (U64)regs->GR_L(r1 + 1) * (U64)regs->GR_L(r2);
700
701 /* Store the result */
702 regs->GR_L(r1) = (p >> 32);
703 regs->GR_L(r1 + 1) = (p & 0xFFFFFFFF);
704
705 } /* end DEF_INST(multiply_logical_register) */
706 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
707
708
709 #if defined(FEATURE_ESAME)
710 /*-------------------------------------------------------------------*/
711 /* B986 MLGR - Multiply Logical Long Register [RRE] */
712 /*-------------------------------------------------------------------*/
DEF_INST(multiply_logical_long_register)713 DEF_INST(multiply_logical_long_register)
714 {
715 int r1, r2; /* Values of R fields */
716 U64 ph, pl;
717
718 RRE(inst, regs, r1, r2);
719
720 ODD_CHECK(r1, regs);
721
722 /* Multiply unsigned values */
723 mult_logical_long(&ph, &pl, regs->GR_G(r1 + 1), regs->GR_G(r2));
724
725 /* Store the result */
726 regs->GR_G(r1) = ph;
727 regs->GR_G(r1 + 1) = pl;
728
729 } /* end DEF_INST(multiply_logical_long_register) */
730 #endif /*defined(FEATURE_ESAME)*/
731
732
733 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
734 /*-------------------------------------------------------------------*/
735 /* E397 DL - Divide Logical [RXY] */
736 /*-------------------------------------------------------------------*/
DEF_INST(divide_logical)737 DEF_INST(divide_logical)
738 {
739 int r1; /* Values of R fields */
740 int b2; /* Base of effective addr */
741 VADR effective_addr2; /* Effective Address */
742 U32 d;
743 U64 n;
744
745 RXY(inst, regs, r1, b2, effective_addr2);
746
747 ODD_CHECK(r1, regs);
748
749 n = ((U64)regs->GR_L(r1) << 32) | (U32)regs->GR_L(r1 + 1);
750
751 /* Load second operand from operand address */
752 d = ARCH_DEP(vfetch4) (effective_addr2, b2, regs);
753
754 if (d == 0
755 || (n / d) > 0xFFFFFFFF)
756 regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
757
758 /* Divide unsigned registers */
759 regs->GR_L(r1) = n % d;
760 regs->GR_L(r1 + 1) = n / d;
761
762 } /* end DEF_INST(divide_logical) */
763 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
764
765
766 #if defined(FEATURE_ESAME)
767 /*-------------------------------------------------------------------*/
768 /* E387 DLG - Divide Logical Long [RXY] */
769 /*-------------------------------------------------------------------*/
DEF_INST(divide_logical_long)770 DEF_INST(divide_logical_long)
771 {
772 int r1; /* Values of R fields */
773 int b2; /* Base of effective addr */
774 VADR effective_addr2; /* Effective Address */
775 U64 d, r, q;
776
777 RXY(inst, regs, r1, b2, effective_addr2);
778
779 ODD_CHECK(r1, regs);
780
781 /* Load second operand from operand address */
782 d = ARCH_DEP(vfetch8) (effective_addr2, b2, regs);
783
784 if (regs->GR_G(r1) == 0) /* check for the simple case */
785 {
786 if (d == 0)
787 regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
788
789 /* Divide signed registers */
790 regs->GR_G(r1) = regs->GR_G(r1 + 1) % d;
791 regs->GR_G(r1 + 1) = regs->GR_G(r1 + 1) / d;
792 }
793 else
794 {
795 if (div_logical_long(&r, &q, regs->GR_G(r1), regs->GR_G(r1 + 1), d) )
796 regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
797 else
798 {
799 regs->GR_G(r1) = r;
800 regs->GR_G(r1 + 1) = q;
801 }
802
803 }
804 } /* end DEF_INST(divide_logical_long) */
805 #endif /*defined(FEATURE_ESAME)*/
806
807
808 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
809 /*-------------------------------------------------------------------*/
810 /* B997 DLR - Divide Logical Register [RRE] */
811 /*-------------------------------------------------------------------*/
DEF_INST(divide_logical_register)812 DEF_INST(divide_logical_register)
813 {
814 int r1, r2; /* Values of R fields */
815 U64 n;
816 U32 d;
817
818 RRE(inst, regs, r1, r2);
819
820 ODD_CHECK(r1, regs);
821
822 n = ((U64)regs->GR_L(r1) << 32) | regs->GR_L(r1 + 1);
823
824 d = regs->GR_L(r2);
825
826 if(d == 0
827 || (n / d) > 0xFFFFFFFF)
828 regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
829
830 /* Divide signed registers */
831 regs->GR_L(r1) = n % d;
832 regs->GR_L(r1 + 1) = n / d;
833
834 } /* end DEF_INST(divide_logical_register) */
835 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
836
837
838 #if defined(FEATURE_ESAME)
839 /*-------------------------------------------------------------------*/
840 /* B987 DLGR - Divide Logical Long Register [RRE] */
841 /*-------------------------------------------------------------------*/
DEF_INST(divide_logical_long_register)842 DEF_INST(divide_logical_long_register)
843 {
844 int r1, r2; /* Values of R fields */
845 U64 r, q, d;
846
847 RRE(inst, regs, r1, r2);
848
849 ODD_CHECK(r1, regs);
850
851 d = regs->GR_G(r2);
852
853 if (regs->GR_G(r1) == 0) /* check for the simple case */
854 {
855 if(d == 0)
856 regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
857
858 /* Divide signed registers */
859 regs->GR_G(r1) = regs->GR_G(r1 + 1) % d;
860 regs->GR_G(r1 + 1) = regs->GR_G(r1 + 1) / d;
861 }
862 else
863 {
864 if (div_logical_long(&r, &q, regs->GR_G(r1), regs->GR_G(r1 + 1), d) )
865 regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
866 else
867 {
868 regs->GR_G(r1) = r;
869 regs->GR_G(r1 + 1) = q;
870 }
871 }
872 } /* end DEF_INST(divide_logical_long_register) */
873 #endif /*defined(FEATURE_ESAME)*/
874
875
876 #if defined(FEATURE_ESAME)
877 /*-------------------------------------------------------------------*/
878 /* B988 ALCGR - Add Logical with Carry Long Register [RRE] */
879 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_carry_long_register)880 DEF_INST(add_logical_carry_long_register)
881 {
882 int r1, r2; /* Values of R fields */
883 int carry = 0;
884 U64 n;
885
886 RRE0(inst, regs, r1, r2);
887
888 n = regs->GR_G(r2);
889
890 /* Add the carry to operand */
891 if(regs->psw.cc & 2)
892 carry = add_logical_long(&(regs->GR_G(r1)),
893 regs->GR_G(r1),
894 1) & 2;
895
896 /* Add unsigned operands and set condition code */
897 regs->psw.cc = add_logical_long(&(regs->GR_G(r1)),
898 regs->GR_G(r1),
899 n) | carry;
900 } /* end DEF_INST(add_logical_carry_long_register) */
901 #endif /*defined(FEATURE_ESAME)*/
902
903
904 #if defined(FEATURE_ESAME)
905 /*-------------------------------------------------------------------*/
906 /* B989 SLBGR - Subtract Logical with Borrow Long Register [RRE] */
907 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_borrow_long_register)908 DEF_INST(subtract_logical_borrow_long_register)
909 {
910 int r1, r2; /* Values of R fields */
911 int borrow = 2;
912 U64 n;
913
914 RRE0(inst, regs, r1, r2);
915
916 n = regs->GR_G(r2);
917
918 /* Subtract the borrow from operand */
919 if(!(regs->psw.cc & 2))
920 borrow = sub_logical_long(&(regs->GR_G(r1)),
921 regs->GR_G(r1),
922 1);
923
924 /* Subtract unsigned operands and set condition code */
925 regs->psw.cc = sub_logical_long(&(regs->GR_G(r1)),
926 regs->GR_G(r1),
927 n) & (borrow|1);
928
929 } /* end DEF_INST(subtract_logical_borrow_long_register) */
930 #endif /*defined(FEATURE_ESAME)*/
931
932
933 #if defined(FEATURE_DAT_ENHANCEMENT)
934 /*-------------------------------------------------------------------*/
935 /* B98A CSPG - Compare and Swap and Purge Long [RRE] */
936 /*-------------------------------------------------------------------*/
DEF_INST(compare_and_swap_and_purge_long)937 DEF_INST(compare_and_swap_and_purge_long)
938 {
939 int r1, r2; /* Values of R fields */
940 U64 n2; /* Virtual address of op2 */
941 BYTE *main2; /* Mainstor address of op2 */
942 U64 old; /* Old value */
943
944 RRE(inst, regs, r1, r2);
945
946 PRIV_CHECK(regs);
947
948 ODD_CHECK(r1, regs);
949
950 #if defined(_FEATURE_SIE)
951 if(SIE_STATB(regs,IC0, IPTECSP))
952 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
953 #endif /*defined(_FEATURE_SIE)*/
954
955 #if defined(_FEATURE_SIE)
956 if(SIE_MODE(regs) && regs->sie_scao)
957 {
958 STORAGE_KEY(regs->sie_scao, regs) |= STORKEY_REF;
959 if(regs->mainstor[regs->sie_scao] & 0x80)
960 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
961 }
962 #endif /*defined(_FEATURE_SIE)*/
963
964 /* Perform serialization before starting operation */
965 PERFORM_SERIALIZATION (regs);
966
967 /* Obtain 2nd operand address from r2 */
968 n2 = regs->GR(r2) & 0xFFFFFFFFFFFFFFF8ULL & ADDRESS_MAXWRAP(regs);
969 main2 = MADDR (n2, r2, regs, ACCTYPE_WRITE, regs->psw.pkey);
970
971 old = CSWAP64 (regs->GR_G(r1));
972
973 /* Obtain main-storage access lock */
974 OBTAIN_MAINLOCK(regs);
975
976 /* Attempt to exchange the values */
977 regs->psw.cc = cmpxchg8 (&old, CSWAP64(regs->GR_G(r1+1)), main2);
978
979 /* Release main-storage access lock */
980 RELEASE_MAINLOCK(regs);
981
982 if (regs->psw.cc == 0)
983 {
984 /* Perform requested funtion specified as per request code in r2 */
985 if (regs->GR_L(r2) & 3)
986 {
987 OBTAIN_INTLOCK(regs);
988 SYNCHRONIZE_CPUS(regs);
989 if (regs->GR_L(r2) & 1)
990 ARCH_DEP(purge_tlb_all)();
991 if (regs->GR_L(r2) & 2)
992 ARCH_DEP(purge_alb_all)();
993 RELEASE_INTLOCK(regs);
994 }
995 }
996 else
997 {
998 PTT(PTT_CL_CSF,"*CSPG",regs->GR_L(r1),regs->GR_L(r2),regs->psw.IA_L);
999
1000 /* Otherwise yield */
1001 regs->GR_G(r1) = CSWAP64(old);
1002 if (sysblk.cpus > 1)
1003 sched_yield();
1004 }
1005
1006 /* Perform serialization after completing operation */
1007 PERFORM_SERIALIZATION (regs);
1008
1009 } /* end DEF_INST(compare_and_swap_and_purge_long) */
1010 #endif /*defined(FEATURE_DAT_ENHANCEMENT)*/
1011
1012
1013 #if defined(FEATURE_DAT_ENHANCEMENT)
1014 /*-------------------------------------------------------------------*/
1015 /* B98E IDTE - Invalidate DAT Table Entry [RRF] */
1016 /*-------------------------------------------------------------------*/
DEF_INST(invalidate_dat_table_entry)1017 DEF_INST(invalidate_dat_table_entry)
1018 {
1019 int r1, r2, r3; /* Values of R fields */
1020 int m4; /* Unused mask field */
1021 U64 asceto; /* ASCE table origin */
1022 int ascedt; /* ASCE designation type */
1023 int count; /* Invalidation counter */
1024 int eiindx; /* Eff. invalidation index */
1025 U64 asce; /* Contents of ASCE */
1026 BYTE *mn; /* Mainstor address of ASCE */
1027
1028 RRF_RM(inst, regs, r1, r2, r3, m4);
1029
1030 SIE_XC_INTERCEPT(regs);
1031
1032 PRIV_CHECK(regs);
1033
1034 /* Program check if bits 44-51 of r2 register are non-zero */
1035 if (regs->GR_L(r2) & 0x000FF000)
1036 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
1037
1038 #if defined(_FEATURE_SIE)
1039 if(SIE_STATB(regs,IC0, IPTECSP))
1040 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1041 #endif /*defined(_FEATURE_SIE)*/
1042
1043 #if defined(_FEATURE_SIE)
1044 if(SIE_MODE(regs) && regs->sie_scao)
1045 {
1046 STORAGE_KEY(regs->sie_scao, regs) |= STORKEY_REF;
1047 if(regs->mainstor[regs->sie_scao] & 0x80)
1048 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1049 }
1050 #endif /*defined(_FEATURE_SIE)*/
1051
1052 /* Perform serialization before starting operation */
1053 PERFORM_SERIALIZATION (regs);
1054
1055 /* Bit 52 of the r2 register determines the operation performed */
1056 if ((regs->GR_L(r2) & 0x00000800) == 0)
1057 {
1058 /* Perform invalidation-and-clearing operation */
1059
1060 /* Extract the invalidation table origin and type from r1 */
1061 asceto = regs->GR_G(r1) & ASCE_TO;
1062 ascedt = regs->GR_L(r1) & ASCE_DT;
1063
1064 /* Extract the effective invalidation index from r2 */
1065 switch(ascedt) {
1066 case TT_R1TABL: /* Region first table */
1067 eiindx = (regs->GR_H(r2) & 0xFF700000) >> 18;
1068 break;
1069 case TT_R2TABL: /* Region second table */
1070 eiindx = (regs->GR_H(r2) & 0x001FFC00) >> 7;
1071 break;
1072 case TT_R3TABL: /* Region third table */
1073 eiindx = (regs->GR_G(r2) & 0x000003FF80000000ULL) >> 28;
1074 break;
1075 case TT_SEGTAB: /* Segment table */
1076 default:
1077 eiindx = (regs->GR_L(r2) & 0x7FF00000) >> 17;
1078 break;
1079 } /* end switch(ascedt) */
1080
1081 /* Calculate the address of table for invalidation, noting
1082 that it is always a 64-bit address regardless of the
1083 current addressing mode, and that overflow is ignored */
1084 asceto += eiindx;
1085
1086 /* Extract the additional entry count from r2 */
1087 count = (regs->GR_L(r2) & 0x7FF) + 1;
1088
1089 /* Perform invalidation of one or more table entries */
1090 while (count-- > 0)
1091 {
1092 /* Fetch the table entry, set the invalid bit, then
1093 store only the byte containing the invalid bit */
1094 mn = MADDR (asceto, USE_REAL_ADDR, regs, ACCTYPE_WRITE, regs->psw.pkey);
1095 FETCH_DW(asce, mn);
1096 asce |= ZSEGTAB_I;
1097 mn[7] = asce & 0xFF;
1098
1099 /* Calculate the address of the next table entry, noting
1100 that it is always a 64-bit address regardless of the
1101 current addressing mode, and that overflow is ignored */
1102 asceto += 8;
1103 } /* end while */
1104
1105 /* Clear the TLB and signal all other CPUs to clear their TLB */
1106 /* Note: Currently we clear all entries regardless of whether
1107 a clearing ASCE is passed in the r3 register. This conforms
1108 to the POP which only specifies the minimum set of entries
1109 which must be cleared from the TLB. */
1110 OBTAIN_INTLOCK(regs);
1111 SYNCHRONIZE_CPUS(regs);
1112 ARCH_DEP(purge_tlb_all)();
1113 RELEASE_INTLOCK(regs);
1114
1115 } /* end if(invalidation-and-clearing) */
1116 else
1117 {
1118 /* Perform clearing-by-ASCE operation */
1119
1120 /* Clear the TLB and signal all other CPUs to clear their TLB */
1121 /* Note: Currently we clear all entries regardless of the
1122 clearing ASCE passed in the r3 register. This conforms
1123 to the POP which only specifies the minimum set of entries
1124 which must be cleared from the TLB. */
1125 OBTAIN_INTLOCK(regs);
1126 SYNCHRONIZE_CPUS(regs);
1127 ARCH_DEP(purge_tlb_all)();
1128 RELEASE_INTLOCK(regs);
1129
1130 } /* end else(clearing-by-ASCE) */
1131
1132 /* Perform serialization after completing operation */
1133 PERFORM_SERIALIZATION (regs);
1134
1135 } /* end DEF_INST(invalidate_dat_table_entry) */
1136 #endif /*defined(FEATURE_DAT_ENHANCEMENT)*/
1137
1138
1139 #if defined(FEATURE_ENHANCED_DAT_FACILITY_2) /*912*/
1140 /*-------------------------------------------------------------------*/
1141 /* B98F CRDTE - Compare and Replace DAT Table Entry [RRF] */
1142 /*-------------------------------------------------------------------*/
DEF_INST(compare_and_replace_dat_table_entry)1143 DEF_INST(compare_and_replace_dat_table_entry) /*912*/
1144 {
1145 int r1, r2, r3; /* Values of R fields */
1146 int m4; /* Value of mask field */
1147 U64 to; /* Table origin */
1148 U64 ei; /* Effective index */
1149 RADR ea; /* Second operand address */
1150 U64 dte; /* Second operand value */
1151 U64 asce = 0; /* Address space control elem*/
1152 int dtt; /* Designated table type */
1153 BYTE *mn; /* Mainstor addr of 2nd opnd */
1154
1155 RRF_RM(inst, regs, r1, r2, r3, m4);
1156
1157 SIE_XC_INTERCEPT(regs);
1158
1159 PRIV_CHECK(regs);
1160
1161 ODD2_CHECK(r1, r2, regs);
1162
1163 /* The designated table type is in R2 bits 59-61 */
1164 dtt = (regs->GR_L(r2) & 0x1C0) >> 2;
1165
1166 /* Calculate the second operand address depending on table type */
1167 switch (dtt) {
1168 case 0: /* Page table */
1169 to = regs->GR_G(r2) & ZSEGTAB_PTO;
1170 ei = (regs->GR_L(r2+1) & 0x000FF000) >> 12;
1171 break;
1172 case 4: /* Segment table */
1173 to = regs->GR_G(r2) & REGTAB_TO;
1174 ei = (regs->GR_L(r2+1) & 0x7FF00000) >> 20;
1175 break;
1176 case 5: /* Region third table */
1177 to = regs->GR_G(r2) & REGTAB_TO;
1178 ei = (regs->GR_G(r2+1) & 0x000003FF80000000ULL) >> 31;
1179 break;
1180 case 6: /* Region second table */
1181 to = regs->GR_G(r2) & REGTAB_TO;
1182 ei = (regs->GR_G(r2+1) & 0x001FFC0000000000ULL) >> 42;
1183 break;
1184 case 7: /* Region first table */
1185 to = regs->GR_G(r2) & ASCE_TO;
1186 ei = (regs->GR_G(r2+1) & 0xFFE0000000000000ULL) >> 53;
1187 break;
1188 default: /* Invalid table type */
1189 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
1190 }
1191
1192 /* Program check if bits 52-63 of R2+1 are non-zero */
1193 if ((regs->GR_L(r2+1) & 0xFFF) != 0) {
1194 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
1195 }
1196
1197 /* Load the address space control element from R3 bits 0-51, 60-61 */
1198 if (r3 != 0) {
1199 asce = regs->GR_G(r3) & (ASCE_TO | ASCE_DT);
1200 }
1201
1202 /* Perform serialization before starting operation */
1203 PERFORM_SERIALIZATION (regs);
1204
1205 /* Load the second operand from storage */
1206 ea = to + 8*ei;
1207 mn = MADDR(ea, USE_REAL_ADDR, regs, ACCTYPE_WRITE, regs->psw.pkey);
1208 FETCH_DW(dte, mn);
1209
1210 /* Compare first and second operands */
1211 if (regs->GR_G(r1) == dte)
1212 {
1213 /* Store R1+1 register at second operand location */
1214 STORE_DW(mn, regs->GR_G(r1+1));
1215
1216 /* Clear the TLB and signal all other CPUs to clear their TLB */
1217 /* Note: Currently we clear all entries regardless of whether
1218 they are related to the original DTE and regardless of whether
1219 a clearing ASCE is passed in the r3 register. This conforms
1220 to the POP which permits the implementation to clear more
1221 entries from the TLB than are strictly necessary. */
1222 OBTAIN_INTLOCK(regs);
1223 SYNCHRONIZE_CPUS(regs);
1224 ARCH_DEP(purge_tlb_all)();
1225 RELEASE_INTLOCK(regs);
1226
1227 /* Set condition code zero to indicate equal operands */
1228 regs->psw.cc = 0;
1229
1230 } else {
1231
1232 /* Load second operand into the R1 register */
1233 regs->GR_G(r1) = dte;
1234
1235 /* Set condition code 1 to indicate unequal operands */
1236 regs->psw.cc = 1;
1237 }
1238
1239 /* Perform serialization after completing operation */
1240 PERFORM_SERIALIZATION (regs);
1241
1242 } /* end DEF_INST(compare_and_replace_dat_table_entry) */
1243 #endif /*defined(FEATURE_ENHANCED_DAT_FACILITY_2)*/
1244
1245
1246 #if defined(FEATURE_DAT_ENHANCEMENT_FACILITY_2)
1247 /*-------------------------------------------------------------------*/
1248 /* B9AA LPTEA - Load Page-Table-Entry Address [RRF] */
1249 /*-------------------------------------------------------------------*/
DEF_INST(load_page_table_entry_address)1250 DEF_INST(load_page_table_entry_address)
1251 {
1252 VADR vaddr; /* Virtual address */
1253 int r1, r2, r3; /* Register numbers */
1254 int m4; /* Mask field */
1255 int n; /* Address space indication */
1256 int cc; /* Condition code */
1257 int acctype = ACCTYPE_LPTEA; /* Storage access type */
1258
1259 RRF_RM(inst, regs, r1, r2, r3, m4);
1260
1261 SIE_XC_INTERCEPT(regs);
1262
1263 PRIV_CHECK(regs);
1264
1265 /* The m4 field determines which address space to use */
1266 switch (m4) {
1267 case 0: /* Use ASCE in control register 1 */
1268 n = USE_PRIMARY_SPACE;
1269 break;
1270 case 1: /* Use ALET in access register r2 */
1271 n = USE_ARMODE | r2;
1272 break;
1273 case 2: /* Use ASCE in control register 7 */
1274 n = USE_SECONDARY_SPACE;
1275 break;
1276 case 3: /* Use ASCE in control register 13 */
1277 n = USE_HOME_SPACE;
1278 break;
1279 case 4: /* Use current addressing mode (PSW bits 16-17) */
1280 n = r2; /* r2 is the access register number if ARMODE */
1281 break;
1282 default: /* Specification exception if invalid value for m4 */
1283 n = -1; /* makes compiler happy */
1284 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
1285 } /* end switch(m4) */
1286
1287 /* Load the virtual address from the r2 register */
1288 vaddr = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
1289
1290 /* Find the page table address and condition code */
1291 cc = ARCH_DEP(translate_addr) (vaddr, n, regs, acctype);
1292
1293 /* Set R1 to real address or exception code depending on cc */
1294 regs->GR_G(r1) = (cc < 3) ? regs->dat.raddr : regs->dat.xcode;
1295
1296 /* Set condition code */
1297 regs->psw.cc = cc;
1298
1299 } /* end DEF_INST(load_page_table_entry_address) */
1300 #endif /*defined(FEATURE_DAT_ENHANCEMENT_FACILITY_2)*/
1301
1302
1303 #if defined(FEATURE_ESAME)
1304 /*-------------------------------------------------------------------*/
1305 /* E388 ALCG - Add Logical with Carry Long [RXY] */
1306 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_carry_long)1307 DEF_INST(add_logical_carry_long)
1308 {
1309 int r1; /* Values of R fields */
1310 int b2; /* Base of effective addr */
1311 VADR effective_addr2; /* Effective address */
1312 U64 n; /* 64-bit operand values */
1313 int carry = 0;
1314
1315 RXY(inst, regs, r1, b2, effective_addr2);
1316
1317 /* Load second operand from operand address */
1318 n = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
1319
1320 /* Add the carry to operand */
1321 if(regs->psw.cc & 2)
1322 carry = add_logical_long(&(regs->GR_G(r1)),
1323 regs->GR_G(r1),
1324 1) & 2;
1325
1326 /* Add unsigned operands and set condition code */
1327 regs->psw.cc = add_logical_long(&(regs->GR_G(r1)),
1328 regs->GR_G(r1),
1329 n) | carry;
1330 } /* end DEF_INST(add_logical_carry_long) */
1331 #endif /*defined(FEATURE_ESAME)*/
1332
1333
1334 #if defined(FEATURE_ESAME)
1335 /*-------------------------------------------------------------------*/
1336 /* E389 SLBG - Subtract Logical with Borrow Long [RXY] */
1337 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_borrow_long)1338 DEF_INST(subtract_logical_borrow_long)
1339 {
1340 int r1; /* Values of R fields */
1341 int b2; /* Base of effective addr */
1342 VADR effective_addr2; /* Effective address */
1343 U64 n; /* 64-bit operand values */
1344 int borrow = 2;
1345
1346 RXY(inst, regs, r1, b2, effective_addr2);
1347
1348 /* Load second operand from operand address */
1349 n = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
1350
1351 /* Subtract the borrow from operand */
1352 if(!(regs->psw.cc & 2))
1353 borrow = sub_logical_long(&(regs->GR_G(r1)),
1354 regs->GR_G(r1),
1355 1);
1356
1357 /* Subtract unsigned operands and set condition code */
1358 regs->psw.cc = sub_logical_long(&(regs->GR_G(r1)),
1359 regs->GR_G(r1),
1360 n) & (borrow|1);
1361
1362 } /* end DEF_INST(subtract_logical_borrow_long) */
1363 #endif /*defined(FEATURE_ESAME)*/
1364
1365
1366 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
1367 /*-------------------------------------------------------------------*/
1368 /* B998 ALCR - Add Logical with Carry Register [RRE] */
1369 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_carry_register)1370 DEF_INST(add_logical_carry_register)
1371 {
1372 int r1, r2; /* Values of R fields */
1373 int carry = 0;
1374 U32 n;
1375
1376 RRE0(inst, regs, r1, r2);
1377
1378 n = regs->GR_L(r2);
1379
1380 /* Add the carry to operand */
1381 if(regs->psw.cc & 2)
1382 carry = add_logical(&(regs->GR_L(r1)),
1383 regs->GR_L(r1),
1384 1) & 2;
1385
1386 /* Add unsigned operands and set condition code */
1387 regs->psw.cc = add_logical(&(regs->GR_L(r1)),
1388 regs->GR_L(r1),
1389 n) | carry;
1390 } /* end DEF_INST(add_logical_carry_register) */
1391 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
1392
1393
1394 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
1395 /*-------------------------------------------------------------------*/
1396 /* B999 SLBR - Subtract Logical with Borrow Register [RRE] */
1397 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_borrow_register)1398 DEF_INST(subtract_logical_borrow_register)
1399 {
1400 int r1, r2; /* Values of R fields */
1401 int borrow = 2;
1402 U32 n;
1403
1404 RRE0(inst, regs, r1, r2);
1405
1406 n = regs->GR_L(r2);
1407
1408 /* Subtract the borrow from operand */
1409 if(!(regs->psw.cc & 2))
1410 borrow = sub_logical(&(regs->GR_L(r1)),
1411 regs->GR_L(r1),
1412 1);
1413
1414 /* Subtract unsigned operands and set condition code */
1415 regs->psw.cc = sub_logical(&(regs->GR_L(r1)),
1416 regs->GR_L(r1),
1417 n) & (borrow|1);
1418
1419 } /* end DEF_INST(subtract_logical_borrow_register) */
1420 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
1421
1422
1423 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
1424 /*-------------------------------------------------------------------*/
1425 /* E398 ALC - Add Logical with Carry [RXY] */
1426 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_carry)1427 DEF_INST(add_logical_carry)
1428 {
1429 int r1; /* Values of R fields */
1430 int b2; /* Base of effective addr */
1431 VADR effective_addr2; /* Effective address */
1432 U32 n; /* 32-bit operand values */
1433 int carry = 0;
1434
1435 RXY(inst, regs, r1, b2, effective_addr2);
1436
1437 /* Load second operand from operand address */
1438 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
1439
1440 /* Add the carry to operand */
1441 if(regs->psw.cc & 2)
1442 carry = add_logical(&(regs->GR_L(r1)),
1443 regs->GR_L(r1),
1444 1) & 2;
1445
1446 /* Add unsigned operands and set condition code */
1447 regs->psw.cc = add_logical(&(regs->GR_L(r1)),
1448 regs->GR_L(r1),
1449 n) | carry;
1450 } /* end DEF_INST(add_logical_carry) */
1451 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
1452
1453
1454 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
1455 /*-------------------------------------------------------------------*/
1456 /* E399 SLB - Subtract Logical with Borrow [RXY] */
1457 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_borrow)1458 DEF_INST(subtract_logical_borrow)
1459 {
1460 int r1; /* Values of R fields */
1461 int b2; /* Base of effective addr */
1462 VADR effective_addr2; /* Effective address */
1463 U32 n; /* 32-bit operand values */
1464 int borrow = 2;
1465
1466 RXY(inst, regs, r1, b2, effective_addr2);
1467
1468 /* Load second operand from operand address */
1469 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
1470
1471 /* Subtract the borrow from operand */
1472 if(!(regs->psw.cc & 2))
1473 borrow = sub_logical(&(regs->GR_L(r1)),
1474 regs->GR_L(r1),
1475 1);
1476
1477 /* Subtract unsigned operands and set condition code */
1478 regs->psw.cc = sub_logical(&(regs->GR_L(r1)),
1479 regs->GR_L(r1),
1480 n) & (borrow|1);
1481
1482 } /* end DEF_INST(subtract_logical_borrow) */
1483 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
1484
1485
1486 #if defined(FEATURE_ESAME)
1487 /*-------------------------------------------------------------------*/
1488 /* E30D DSG - Divide Single Long [RXY] */
1489 /*-------------------------------------------------------------------*/
DEF_INST(divide_single_long)1490 DEF_INST(divide_single_long)
1491 {
1492 int r1; /* Values of R fields */
1493 int b2; /* Base of effective addr */
1494 VADR effective_addr2; /* Effective address */
1495 U64 n; /* 64-bit operand values */
1496
1497 RXY(inst, regs, r1, b2, effective_addr2);
1498
1499 ODD_CHECK(r1, regs);
1500
1501 /* Load second operand from operand address */
1502 n = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
1503
1504 if(n == 0
1505 || ((S64)n == -1LL &&
1506 regs->GR_G(r1 + 1) == 0x8000000000000000ULL))
1507 regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
1508
1509 regs->GR_G(r1) = (S64)regs->GR_G(r1 + 1) % (S64)n;
1510 regs->GR_G(r1 + 1) = (S64)regs->GR_G(r1 + 1) / (S64)n;
1511
1512 } /* end DEF_INST(divide_single_long) */
1513 #endif /*defined(FEATURE_ESAME)*/
1514
1515
1516 #if defined(FEATURE_ESAME)
1517 /*-------------------------------------------------------------------*/
1518 /* E31D DSGF - Divide Single Long Fullword [RXY] */
1519 /*-------------------------------------------------------------------*/
DEF_INST(divide_single_long_fullword)1520 DEF_INST(divide_single_long_fullword)
1521 {
1522 int r1; /* Values of R fields */
1523 int b2; /* Base of effective addr */
1524 VADR effective_addr2; /* Effective address */
1525 U32 n; /* 64-bit operand values */
1526
1527 RXY(inst, regs, r1, b2, effective_addr2);
1528
1529 ODD_CHECK(r1, regs);
1530
1531 /* Load second operand from operand address */
1532 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
1533
1534 if(n == 0
1535 || ((S32)n == -1 &&
1536 regs->GR_G(r1 + 1) == 0x8000000000000000ULL))
1537 regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
1538
1539 regs->GR_G(r1) = (S64)regs->GR_G(r1 + 1) % (S32)n;
1540 regs->GR_G(r1 + 1) = (S64)regs->GR_G(r1 + 1) / (S32)n;
1541
1542 } /* end DEF_INST(divide_single_long_fullword) */
1543 #endif /*defined(FEATURE_ESAME)*/
1544
1545
1546 #if defined(FEATURE_ESAME)
1547 /*-------------------------------------------------------------------*/
1548 /* B90D DSGR - Divide Single Long Register [RRE] */
1549 /*-------------------------------------------------------------------*/
DEF_INST(divide_single_long_register)1550 DEF_INST(divide_single_long_register)
1551 {
1552 int r1, r2; /* Values of R fields */
1553 U64 n;
1554
1555 RRE(inst, regs, r1, r2);
1556
1557 ODD_CHECK(r1, regs);
1558
1559 if(regs->GR_G(r2) == 0
1560 || ((S64)regs->GR_G(r2) == -1LL &&
1561 regs->GR_G(r1 + 1) == 0x8000000000000000ULL))
1562 regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
1563
1564 n = regs->GR_G(r2);
1565
1566 /* Divide signed registers */
1567 regs->GR_G(r1) = (S64)regs->GR_G(r1 + 1) % (S64)n;
1568 regs->GR_G(r1 + 1) = (S64)regs->GR_G(r1 + 1) / (S64)n;
1569
1570 } /* end DEF_INST(divide_single_long_register) */
1571 #endif /*defined(FEATURE_ESAME)*/
1572
1573
1574 #if defined(FEATURE_ESAME)
1575 /*-------------------------------------------------------------------*/
1576 /* B91D DSGFR - Divide Single Long Fullword Register [RRE] */
1577 /*-------------------------------------------------------------------*/
DEF_INST(divide_single_long_fullword_register)1578 DEF_INST(divide_single_long_fullword_register)
1579 {
1580 int r1, r2; /* Values of R fields */
1581 U32 n;
1582
1583 RRE(inst, regs, r1, r2);
1584
1585 ODD_CHECK(r1, regs);
1586
1587 if(regs->GR_L(r2) == 0
1588 || ((S32)regs->GR_L(r2) == -1 &&
1589 regs->GR_G(r1 + 1) == 0x8000000000000000ULL))
1590 regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
1591
1592 n = regs->GR_L(r2);
1593
1594 /* Divide signed registers */
1595 regs->GR_G(r1) = (S64)regs->GR_G(r1 + 1) % (S32)n;
1596 regs->GR_G(r1 + 1) = (S64)regs->GR_G(r1 + 1) / (S32)n;
1597
1598 } /* end DEF_INST(divide_single_long_fullword_register) */
1599 #endif /*defined(FEATURE_ESAME)*/
1600
1601
1602 #if defined(FEATURE_ESAME)
1603 /*-------------------------------------------------------------------*/
1604 /* E390 LLGC - Load Logical Long Character [RXY] */
1605 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_long_character)1606 DEF_INST(load_logical_long_character)
1607 {
1608 int r1; /* Value of R field */
1609 int b2; /* Base of effective addr */
1610 VADR effective_addr2; /* Effective address */
1611
1612 RXY(inst, regs, r1, b2, effective_addr2);
1613
1614 regs->GR_G(r1) = ARCH_DEP(vfetchb) ( effective_addr2, b2, regs );
1615
1616 } /* end DEF_INST(load_logical_long_character) */
1617 #endif /*defined(FEATURE_ESAME)*/
1618
1619
1620 #if defined(FEATURE_ESAME)
1621 /*-------------------------------------------------------------------*/
1622 /* E391 LLGH - Load Logical Long Halfword [RXY] */
1623 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_long_halfword)1624 DEF_INST(load_logical_long_halfword)
1625 {
1626 int r1; /* Value of R field */
1627 int b2; /* Base of effective addr */
1628 VADR effective_addr2; /* Effective address */
1629
1630 RXY(inst, regs, r1, b2, effective_addr2);
1631
1632 regs->GR_G(r1) = ARCH_DEP(vfetch2) ( effective_addr2, b2, regs );
1633
1634 } /* end DEF_INST(load_logical_long_halfword) */
1635 #endif /*defined(FEATURE_ESAME)*/
1636
1637
1638 #if defined(FEATURE_ESAME)
1639 /*-------------------------------------------------------------------*/
1640 /* E38E STPQ - Store Pair to Quadword [RXY] */
1641 /*-------------------------------------------------------------------*/
DEF_INST(store_pair_to_quadword)1642 DEF_INST(store_pair_to_quadword)
1643 {
1644 int r1; /* Value of R field */
1645 int b2; /* Base of effective addr */
1646 VADR effective_addr2; /* Effective address */
1647 QWORD qwork; /* Quadword work area */
1648
1649 RXY(inst, regs, r1, b2, effective_addr2);
1650
1651 ODD_CHECK(r1, regs);
1652
1653 QW_CHECK(effective_addr2, regs);
1654
1655 /* Store regs in workarea */
1656 STORE_DW(qwork, regs->GR_G(r1));
1657 STORE_DW(qwork+8, regs->GR_G(r1+1));
1658
1659 /* Store R1 and R1+1 registers to second operand
1660 Provide storage consistancy by means of obtaining
1661 the main storage access lock */
1662 OBTAIN_MAINLOCK(regs);
1663 ARCH_DEP(vstorec) ( qwork, 16-1, effective_addr2, b2, regs );
1664 RELEASE_MAINLOCK(regs);
1665
1666 } /* end DEF_INST(store_pair_to_quadword) */
1667 #endif /*defined(FEATURE_ESAME)*/
1668
1669
1670 #if defined(FEATURE_ESAME)
1671 /*-------------------------------------------------------------------*/
1672 /* E38F LPQ - Load Pair from Quadword [RXY] */
1673 /*-------------------------------------------------------------------*/
DEF_INST(load_pair_from_quadword)1674 DEF_INST(load_pair_from_quadword)
1675 {
1676 int r1; /* Value of R field */
1677 int b2; /* Base of effective addr */
1678 VADR effective_addr2; /* Effective address */
1679 QWORD qwork; /* Quadword work area */
1680
1681 RXY(inst, regs, r1, b2, effective_addr2);
1682
1683 ODD_CHECK(r1, regs);
1684
1685 QW_CHECK(effective_addr2, regs);
1686
1687 /* Load R1 and R1+1 registers contents from second operand
1688 Provide storage consistancy by means of obtaining
1689 the main storage access lock */
1690 OBTAIN_MAINLOCK(regs);
1691 ARCH_DEP(vfetchc) ( qwork, 16-1, effective_addr2, b2, regs );
1692 RELEASE_MAINLOCK(regs);
1693
1694 /* Load regs from workarea */
1695 FETCH_DW(regs->GR_G(r1), qwork);
1696 FETCH_DW(regs->GR_G(r1+1), qwork+8);
1697
1698 } /* end DEF_INST(load_pair_from_quadword) */
1699 #endif /*defined(FEATURE_ESAME)*/
1700
1701
1702 #if defined(FEATURE_ESAME)
1703 /*-------------------------------------------------------------------*/
1704 /* B90E EREGG - Extract Stacked Registers Long [RRE] */
1705 /*-------------------------------------------------------------------*/
DEF_INST(extract_stacked_registers_long)1706 DEF_INST(extract_stacked_registers_long)
1707 {
1708 int r1, r2; /* Values of R fields */
1709 LSED lsed; /* Linkage stack entry desc. */
1710 VADR lsea; /* Linkage stack entry addr */
1711
1712 RRE(inst, regs, r1, r2);
1713
1714 SIE_XC_INTERCEPT(regs);
1715
1716 /* Find the virtual address of the entry descriptor
1717 of the current state entry in the linkage stack */
1718 lsea = ARCH_DEP(locate_stack_entry) (0, &lsed, regs);
1719
1720 /* Load registers from the stack entry */
1721 ARCH_DEP(unstack_registers) (1, lsea, r1, r2, regs);
1722
1723 } /* end DEF_INST(extract_stacked_registers_long) */
1724 #endif /*defined(FEATURE_ESAME)*/
1725
1726
1727 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
1728 /*-------------------------------------------------------------------*/
1729 /* B98D EPSW - Extract PSW [RRE] */
1730 /*-------------------------------------------------------------------*/
DEF_INST(extract_psw)1731 DEF_INST(extract_psw)
1732 {
1733 int r1, r2; /* Values of R fields */
1734 QWORD currpsw; /* Work area for PSW */
1735
1736 RRE(inst, regs, r1, r2);
1737
1738 #if defined(_FEATURE_ZSIE)
1739 if(SIE_STATB(regs, IC1, LPSW))
1740 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1741 #endif /*defined(_FEATURE_ZSIE)*/
1742
1743 /* Store the current PSW in work area */
1744 ARCH_DEP(store_psw) (regs, currpsw);
1745
1746 /* Load PSW bits 0-31 into bits 32-63 of the R1 register */
1747 FETCH_FW(regs->GR_L(r1), currpsw);
1748
1749 /* If R2 specifies a register other than register zero,
1750 load PSW bits 32-63 into bits 32-63 of the R2 register */
1751 if(r2 != 0)
1752 {
1753 FETCH_FW(regs->GR_L(r2), currpsw+4);
1754
1755 #if !defined(FEATURE_ESAME)
1756 /* The Ninth Edition of ESA/390 POP (SA22-7201-08) requires
1757 the low 31 bits to be set to zeroes in ESA/390 mode */
1758 regs->GR_L(r2) &= 0x80000000;
1759 #endif /*!defined(FEATURE_ESAME)*/
1760 }
1761
1762 } /* end DEF_INST(extract_psw) */
1763 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
1764
1765
1766 #if defined(FEATURE_ESAME)
1767 /*-------------------------------------------------------------------*/
1768 /* B99D ESEA - Extract and Set Extended Authority [RRE] */
1769 /*-------------------------------------------------------------------*/
DEF_INST(extract_and_set_extended_authority)1770 DEF_INST(extract_and_set_extended_authority)
1771 {
1772 int r1, unused; /* Value of R field */
1773
1774 RRE(inst, regs, r1, unused);
1775
1776 PRIV_CHECK(regs);
1777
1778 #if 0
1779 #if defined(_FEATURE_ZSIE)
1780 if(SIE_STATB(regs, LCTL1, CR8))
1781 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1782 #endif /*defined(_FEATURE_ZSIE)*/
1783 #endif
1784
1785 regs->GR_LHH(r1) = regs->CR_LHH(8);
1786 regs->CR_LHH(8) = regs->GR_LHL(r1);
1787
1788 } /* end DEF_INST(extract_and_set_extended_authority) */
1789 #endif /*defined(FEATURE_ESAME)*/
1790
1791
1792 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
1793 /*-------------------------------------------------------------------*/
1794 /* C0x0 LARL - Load Address Relative Long [RIL] */
1795 /*-------------------------------------------------------------------*/
DEF_INST(load_address_relative_long)1796 DEF_INST(load_address_relative_long)
1797 {
1798 int r1; /* Register number */
1799 int opcd; /* Opcode */
1800 U32 i2; /* 32-bit operand values */
1801
1802 RIL0(inst, regs, r1, opcd, i2);
1803
1804 SET_GR_A(r1, regs, likely(!regs->execflag)
1805 ? PSW_IA(regs, -6 + 2LL*(S32)i2)
1806 : (regs->ET + 2LL*(S32)i2) & ADDRESS_MAXWRAP(regs));
1807
1808 } /* end DEF_INST(load_address_relative_long) */
1809 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
1810
1811
1812 #if defined(FEATURE_ESAME)
1813 /*-------------------------------------------------------------------*/
1814 /* A5x0 IIHH - Insert Immediate High High [RI] */
1815 /*-------------------------------------------------------------------*/
DEF_INST(insert_immediate_high_high)1816 DEF_INST(insert_immediate_high_high)
1817 {
1818 int r1; /* Register number */
1819 U16 i2; /* 16-bit operand values */
1820
1821 RI0(inst, regs, r1, i2);
1822
1823 regs->GR_HHH(r1) = i2;
1824
1825 } /* end DEF_INST(insert_immediate_high_high) */
1826 #endif /*defined(FEATURE_ESAME)*/
1827
1828
1829 #if defined(FEATURE_ESAME)
1830 /*-------------------------------------------------------------------*/
1831 /* A5x1 IIHL - Insert Immediate High Low [RI] */
1832 /*-------------------------------------------------------------------*/
DEF_INST(insert_immediate_high_low)1833 DEF_INST(insert_immediate_high_low)
1834 {
1835 int r1; /* Register number */
1836 U16 i2; /* 16-bit operand values */
1837
1838 RI0(inst, regs, r1, i2);
1839
1840 regs->GR_HHL(r1) = i2;
1841
1842 } /* end DEF_INST(insert_immediate_high_low) */
1843 #endif /*defined(FEATURE_ESAME)*/
1844
1845
1846 #if defined(FEATURE_ESAME)
1847 /*-------------------------------------------------------------------*/
1848 /* A5x2 IILH - Insert Immediate Low High [RI] */
1849 /*-------------------------------------------------------------------*/
DEF_INST(insert_immediate_low_high)1850 DEF_INST(insert_immediate_low_high)
1851 {
1852 int r1; /* Register number */
1853 U16 i2; /* 16-bit operand values */
1854
1855 RI0(inst, regs, r1, i2);
1856
1857 regs->GR_LHH(r1) = i2;
1858
1859 } /* end DEF_INST(insert_immediate_low_high) */
1860 #endif /*defined(FEATURE_ESAME)*/
1861
1862
1863 #if defined(FEATURE_ESAME)
1864 /*-------------------------------------------------------------------*/
1865 /* A5x3 IILL - Insert Immediate Low Low [RI] */
1866 /*-------------------------------------------------------------------*/
DEF_INST(insert_immediate_low_low)1867 DEF_INST(insert_immediate_low_low)
1868 {
1869 int r1; /* Register number */
1870 U16 i2; /* 16-bit operand values */
1871
1872 RI0(inst, regs, r1, i2);
1873
1874 regs->GR_LHL(r1) = i2;
1875
1876 } /* end DEF_INST(insert_immediate_low_low) */
1877 #endif /*defined(FEATURE_ESAME)*/
1878
1879
1880 #if defined(FEATURE_ESAME)
1881 /*-------------------------------------------------------------------*/
1882 /* A5x4 NIHH - And Immediate High High [RI] */
1883 /*-------------------------------------------------------------------*/
DEF_INST(and_immediate_high_high)1884 DEF_INST(and_immediate_high_high)
1885 {
1886 int r1; /* Register number */
1887 U16 i2; /* 16-bit operand values */
1888
1889 RI0(inst, regs, r1, i2);
1890
1891 regs->GR_HHH(r1) &= i2;
1892
1893 /* Set condition code according to result */
1894 regs->psw.cc = regs->GR_HHH(r1) ? 1 : 0;
1895
1896 } /* end DEF_INST(and_immediate_high_high) */
1897 #endif /*defined(FEATURE_ESAME)*/
1898
1899
1900 #if defined(FEATURE_ESAME)
1901 /*-------------------------------------------------------------------*/
1902 /* A5x5 NIHL - And Immediate High Low [RI] */
1903 /*-------------------------------------------------------------------*/
DEF_INST(and_immediate_high_low)1904 DEF_INST(and_immediate_high_low)
1905 {
1906 int r1; /* Register number */
1907 U16 i2; /* 16-bit operand values */
1908
1909 RI0(inst, regs, r1, i2);
1910
1911 regs->GR_HHL(r1) &= i2;
1912
1913 /* Set condition code according to result */
1914 regs->psw.cc = regs->GR_HHL(r1) ? 1 : 0;
1915
1916 } /* end DEF_INST(and_immediate_high_low) */
1917 #endif /*defined(FEATURE_ESAME)*/
1918
1919
1920 #if defined(FEATURE_ESAME)
1921 /*-------------------------------------------------------------------*/
1922 /* A5x6 NILH - And Immediate Low High [RI] */
1923 /*-------------------------------------------------------------------*/
DEF_INST(and_immediate_low_high)1924 DEF_INST(and_immediate_low_high)
1925 {
1926 int r1; /* Register number */
1927 U16 i2; /* 16-bit operand values */
1928
1929 RI0(inst, regs, r1, i2);
1930
1931 regs->GR_LHH(r1) &= i2;
1932
1933 /* Set condition code according to result */
1934 regs->psw.cc = regs->GR_LHH(r1) ? 1 : 0;
1935
1936 } /* end DEF_INST(and_immediate_low_high) */
1937 #endif /*defined(FEATURE_ESAME)*/
1938
1939
1940 #if defined(FEATURE_ESAME)
1941 /*-------------------------------------------------------------------*/
1942 /* A5x7 NILL - And Immediate Low Low [RI] */
1943 /*-------------------------------------------------------------------*/
DEF_INST(and_immediate_low_low)1944 DEF_INST(and_immediate_low_low)
1945 {
1946 int r1; /* Register number */
1947 U16 i2; /* 16-bit operand values */
1948
1949 RI0(inst, regs, r1, i2);
1950
1951 regs->GR_LHL(r1) &= i2;
1952
1953 /* Set condition code according to result */
1954 regs->psw.cc = regs->GR_LHL(r1) ? 1 : 0;
1955
1956 } /* end DEF_INST(and_immediate_low_low) */
1957 #endif /*defined(FEATURE_ESAME)*/
1958
1959
1960 #if defined(FEATURE_ESAME)
1961 /*-------------------------------------------------------------------*/
1962 /* A5x8 OIHH - Or Immediate High High [RI] */
1963 /*-------------------------------------------------------------------*/
DEF_INST(or_immediate_high_high)1964 DEF_INST(or_immediate_high_high)
1965 {
1966 int r1; /* Register number */
1967 U16 i2; /* 16-bit operand values */
1968
1969 RI0(inst, regs, r1, i2);
1970
1971 regs->GR_HHH(r1) |= i2;
1972
1973 /* Set condition code according to result */
1974 regs->psw.cc = regs->GR_HHH(r1) ? 1 : 0;
1975
1976 } /* end DEF_INST(or_immediate_high_high) */
1977 #endif /*defined(FEATURE_ESAME)*/
1978
1979
1980 #if defined(FEATURE_ESAME)
1981 /*-------------------------------------------------------------------*/
1982 /* A5x9 OIHL - Or Immediate High Low [RI] */
1983 /*-------------------------------------------------------------------*/
DEF_INST(or_immediate_high_low)1984 DEF_INST(or_immediate_high_low)
1985 {
1986 int r1; /* Register number */
1987 U16 i2; /* 16-bit operand values */
1988
1989 RI0(inst, regs, r1, i2);
1990
1991 regs->GR_HHL(r1) |= i2;
1992
1993 /* Set condition code according to result */
1994 regs->psw.cc = regs->GR_HHL(r1) ? 1 : 0;
1995
1996 } /* end DEF_INST(or_immediate_high_low) */
1997 #endif /*defined(FEATURE_ESAME)*/
1998
1999
2000 #if defined(FEATURE_ESAME)
2001 /*-------------------------------------------------------------------*/
2002 /* A5xA OILH - Or Immediate Low High [RI] */
2003 /*-------------------------------------------------------------------*/
DEF_INST(or_immediate_low_high)2004 DEF_INST(or_immediate_low_high)
2005 {
2006 int r1; /* Register number */
2007 U16 i2; /* 16-bit operand values */
2008
2009 RI0(inst, regs, r1, i2);
2010
2011 regs->GR_LHH(r1) |= i2;
2012
2013 /* Set condition code according to result */
2014 regs->psw.cc = regs->GR_LHH(r1) ? 1 : 0;
2015
2016 } /* end DEF_INST(or_immediate_low_high) */
2017 #endif /*defined(FEATURE_ESAME)*/
2018
2019
2020 #if defined(FEATURE_ESAME)
2021 /*-------------------------------------------------------------------*/
2022 /* A5xB OILL - Or Immediate Low Low [RI] */
2023 /*-------------------------------------------------------------------*/
DEF_INST(or_immediate_low_low)2024 DEF_INST(or_immediate_low_low)
2025 {
2026 int r1; /* Register number */
2027 U16 i2; /* 16-bit operand values */
2028
2029 RI0(inst, regs, r1, i2);
2030
2031 regs->GR_LHL(r1) |= i2;
2032
2033 /* Set condition code according to result */
2034 regs->psw.cc = regs->GR_LHL(r1) ? 1 : 0;
2035
2036 } /* end DEF_INST(or_immediate_low_low) */
2037 #endif /*defined(FEATURE_ESAME)*/
2038
2039
2040 #if defined(FEATURE_ESAME)
2041 /*-------------------------------------------------------------------*/
2042 /* A5xC LLIHH - Load Logical Immediate High High [RI] */
2043 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_immediate_high_high)2044 DEF_INST(load_logical_immediate_high_high)
2045 {
2046 int r1; /* Register number */
2047 U16 i2; /* 16-bit operand values */
2048
2049 RI0(inst, regs, r1, i2);
2050
2051 regs->GR_G(r1) = (U64)i2 << 48;
2052
2053 } /* end DEF_INST(load_logical_immediate_high_high) */
2054 #endif /*defined(FEATURE_ESAME)*/
2055
2056
2057 #if defined(FEATURE_ESAME)
2058 /*-------------------------------------------------------------------*/
2059 /* A5xD LLIHL - Load Logical Immediate High Low [RI] */
2060 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_immediate_high_low)2061 DEF_INST(load_logical_immediate_high_low)
2062 {
2063 int r1; /* Register number */
2064 U16 i2; /* 16-bit operand values */
2065
2066 RI0(inst, regs, r1, i2);
2067
2068 regs->GR_G(r1) = (U64)i2 << 32;
2069
2070 } /* end DEF_INST(load_logical_immediate_high_low) */
2071 #endif /*defined(FEATURE_ESAME)*/
2072
2073
2074 #if defined(FEATURE_ESAME)
2075 /*-------------------------------------------------------------------*/
2076 /* A5xE LLILH - Load Logical Immediate Low High [RI] */
2077 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_immediate_low_high)2078 DEF_INST(load_logical_immediate_low_high)
2079 {
2080 int r1; /* Register number */
2081 U16 i2; /* 16-bit operand values */
2082
2083 RI0(inst, regs, r1, i2);
2084
2085 regs->GR_G(r1) = (U64)i2 << 16;
2086
2087 } /* end DEF_INST(load_logical_immediate_low_high) */
2088 #endif /*defined(FEATURE_ESAME)*/
2089
2090
2091 #if defined(FEATURE_ESAME)
2092 /*-------------------------------------------------------------------*/
2093 /* A5xF LLILL - Load Logical Immediate Low Low [RI] */
2094 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_immediate_low_low)2095 DEF_INST(load_logical_immediate_low_low)
2096 {
2097 int r1; /* Register number */
2098 U16 i2; /* 16-bit operand values */
2099
2100 RI0(inst, regs, r1, i2);
2101
2102 regs->GR_G(r1) = (U64)i2;
2103
2104 } /* end DEF_INST(load_logical_immediate_low_low) */
2105 #endif /*defined(FEATURE_ESAME)*/
2106
2107
2108 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
2109 /*-------------------------------------------------------------------*/
2110 /* C0x4 BRCL - Branch Relative on Condition Long [RIL] */
2111 /*-------------------------------------------------------------------*/
DEF_INST(branch_relative_on_condition_long)2112 DEF_INST(branch_relative_on_condition_long)
2113 {
2114 //int r1; /* Register number */
2115 //int opcd; /* Opcode */
2116 //U32 i2; /* 32-bit operand values */
2117
2118 // RIL(inst, regs, r1, opcd, i2);
2119
2120 /* Branch if R1 mask bit is set */
2121 if (inst[1] & (0x80 >> regs->psw.cc))
2122 SUCCESSFUL_RELATIVE_BRANCH_LONG(regs, 2LL*(S32)fetch_fw(inst+2));
2123 else
2124 INST_UPDATE_PSW(regs, 6, 0);
2125
2126 } /* end DEF_INST(branch_relative_on_condition_long) */
2127 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
2128
2129
2130 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
2131 /*-------------------------------------------------------------------*/
2132 /* C0x5 BRASL - Branch Relative And Save Long [RIL] */
2133 /*-------------------------------------------------------------------*/
DEF_INST(branch_relative_and_save_long)2134 DEF_INST(branch_relative_and_save_long)
2135 {
2136 int r1; /* Register number */
2137 int opcd; /* Opcode */
2138 U32 i2; /* 32-bit operand values */
2139
2140 RIL_B(inst, regs, r1, opcd, i2);
2141
2142 #if defined(FEATURE_ESAME)
2143 if(regs->psw.amode64)
2144 regs->GR_G(r1) = PSW_IA64(regs, 6);
2145 else
2146 #endif /*defined(FEATURE_ESAME)*/
2147 if ( regs->psw.amode )
2148 regs->GR_L(r1) = 0x80000000 | PSW_IA31(regs, 6);
2149 else
2150 regs->GR_L(r1) = PSW_IA24(regs, 6);
2151
2152 SUCCESSFUL_RELATIVE_BRANCH_LONG(regs, 2LL*(S32)fetch_fw(inst+2));
2153
2154 } /* end DEF_INST(branch_relative_and_save_long) */
2155 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
2156
2157
2158 #if defined(FEATURE_ESAME)
2159 /*-------------------------------------------------------------------*/
2160 /* EB20 CLMH - Compare Logical Characters under Mask High [RSY] */
2161 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_characters_under_mask_high)2162 DEF_INST(compare_logical_characters_under_mask_high)
2163 {
2164 int r1, r3; /* Register numbers */
2165 int b2; /* effective address base */
2166 VADR effective_addr2; /* effective address */
2167 int i, j; /* Integer work areas */
2168 int cc = 0; /* Condition code */
2169 BYTE rbyte[4], /* Register bytes */
2170 vbyte; /* Virtual storage byte */
2171
2172 RSY(inst, regs, r1, r3, b2, effective_addr2);
2173
2174 /* Set register bytes by mask */
2175 i = 0;
2176 if (r3 & 0x8) rbyte[i++] = (regs->GR_H(r1) >> 24) & 0xFF;
2177 if (r3 & 0x4) rbyte[i++] = (regs->GR_H(r1) >> 16) & 0xFF;
2178 if (r3 & 0x2) rbyte[i++] = (regs->GR_H(r1) >> 8) & 0xFF;
2179 if (r3 & 0x1) rbyte[i++] = (regs->GR_H(r1) ) & 0xFF;
2180
2181 /* Perform access check if mask is 0 */
2182 if (!r3) ARCH_DEP(vfetchb) (effective_addr2, b2, regs);
2183
2184 /* Compare byte by byte */
2185 for (j = 0; j < i && !cc; j++)
2186 {
2187 effective_addr2 &= ADDRESS_MAXWRAP(regs);
2188 vbyte = ARCH_DEP(vfetchb) (effective_addr2++, b2, regs);
2189 if (rbyte[j] != vbyte)
2190 cc = rbyte[j] < vbyte ? 1 : 2;
2191 }
2192
2193 regs->psw.cc = cc;
2194
2195 } /* end DEF_INST(compare_logical_characters_under_mask_high) */
2196 #endif /*defined(FEATURE_ESAME)*/
2197
2198
2199 #if defined(FEATURE_ESAME)
2200 /*-------------------------------------------------------------------*/
2201 /* EB2C STCMH - Store Characters under Mask High [RSY] */
2202 /*-------------------------------------------------------------------*/
DEF_INST(store_characters_under_mask_high)2203 DEF_INST(store_characters_under_mask_high)
2204 {
2205 int r1, r3; /* Register numbers */
2206 int b2; /* effective address base */
2207 VADR effective_addr2; /* effective address */
2208 int i; /* Integer work area */
2209 BYTE rbyte[4]; /* Register bytes from mask */
2210
2211 RSY(inst, regs, r1, r3, b2, effective_addr2);
2212
2213 switch (r3) {
2214
2215 case 15:
2216 /* Optimized case */
2217 ARCH_DEP(vstore4) (regs->GR_H(r1), effective_addr2, b2, regs);
2218 break;
2219
2220 default:
2221 /* Extract value from register by mask */
2222 i = 0;
2223 if (r3 & 0x8) rbyte[i++] = (regs->GR_H(r1) >> 24) & 0xFF;
2224 if (r3 & 0x4) rbyte[i++] = (regs->GR_H(r1) >> 16) & 0xFF;
2225 if (r3 & 0x2) rbyte[i++] = (regs->GR_H(r1) >> 8) & 0xFF;
2226 if (r3 & 0x1) rbyte[i++] = (regs->GR_H(r1) ) & 0xFF;
2227
2228 if (i)
2229 ARCH_DEP(vstorec) (rbyte, i-1, effective_addr2, b2, regs);
2230 #if defined(MODEL_DEPENDENT_STCM)
2231 /* If the mask is all zero, we nevertheless access one byte
2232 from the storage operand, because POP states that an
2233 access exception may be recognized on the first byte */
2234 else
2235 ARCH_DEP(validate_operand) (effective_addr2, b2, 0,
2236 ACCTYPE_WRITE, regs);
2237 #endif
2238 break;
2239
2240 } /* switch (r3) */
2241
2242 } /* end DEF_INST(store_characters_under_mask_high) */
2243 #endif /*defined(FEATURE_ESAME)*/
2244
2245
2246 #if defined(FEATURE_EXTRACT_CPU_TIME)
2247 /*-------------------------------------------------------------------*/
2248 /* C8x1 ECTG - Extract CPU Time [SSF] */
2249 /*-------------------------------------------------------------------*/
DEF_INST(extract_cpu_time)2250 DEF_INST(extract_cpu_time)
2251 {
2252 int b1, b2; /* Base of effective addr */
2253 VADR effective_addr1; /* Effective address */
2254 VADR effective_addr2; /* Effective address */
2255 int r3; /* R3 register number */
2256 S64 dreg; /* Double word workarea */
2257 U64 gr0, gr1; /* Result register workareas */
2258
2259 SSF(inst, regs, b1, effective_addr1, b2, effective_addr2, r3);
2260
2261 #if defined(_FEATURE_SIE)
2262 if(SIE_STATB(regs, IC3, SPT))
2263 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
2264 #endif /*defined(_FEATURE_SIE)*/
2265
2266 OBTAIN_INTLOCK(regs);
2267
2268 /* Save the CPU timer value */
2269 dreg = cpu_timer(regs);
2270
2271 /* Reset the cpu timer pending flag according to its value */
2272 if( CPU_TIMER(regs) < 0 )
2273 {
2274 ON_IC_PTIMER(regs);
2275
2276 /* Roll back the instruction and take the
2277 timer interrupt if we have a pending CPU timer
2278 and we are enabled for such interrupts *JJ */
2279 if( OPEN_IC_PTIMER(regs) )
2280 {
2281 RELEASE_INTLOCK(regs);
2282 UPD_PSW_IA(regs, PSW_IA(regs, !regs->execflag ? -6 :
2283 regs->exrl ? -6 : -4));
2284 RETURN_INTCHECK(regs);
2285 }
2286 }
2287 else
2288 OFF_IC_PTIMER(regs);
2289
2290 RELEASE_INTLOCK(regs);
2291
2292 /* The value of the current CPU timer is subtracted from the first
2293 operand and the result is placed in general register 0 */
2294 gr0 = ARCH_DEP(vfetch8) (effective_addr1, b1, regs) - dreg;
2295
2296 /* The second operand is placed in general register 1 */
2297 gr1 = ARCH_DEP(vfetch8) (effective_addr2, b2, regs);
2298
2299 /* The eight bytes at the third operand location replace the contents
2300 of general register R3. The operands are treated as unsigned 64-bit
2301 integers. The contents of R3 is treated according to current
2302 addressing mode. In AR mode, access register R3 is used. */
2303 regs->GR_G(r3) = ARCH_DEP(wfetch8) (regs->GR_G(r3), r3, regs);
2304 regs->GR_G(0) = gr0;
2305 regs->GR_G(1) = gr1;
2306
2307 RETURN_INTCHECK(regs);
2308 } /* end DEF_INST(extract_cpu_time) */
2309 #endif /*defined(FEATURE_EXTRACT_CPU_TIME)*/
2310
2311
2312 #if defined(FEATURE_ESAME)
2313 /*-------------------------------------------------------------------*/
2314 /* EB80 ICMH - Insert Characters under Mask High [RSY] */
2315 /*-------------------------------------------------------------------*/
DEF_INST(insert_characters_under_mask_high)2316 DEF_INST(insert_characters_under_mask_high)
2317 {
2318 int r1, r3; /* Register numbers */
2319 int b2; /* effective address base */
2320 VADR effective_addr2; /* effective address */
2321 int i; /* Integer work area */
2322 BYTE vbyte[4]; /* Fetched storage bytes */
2323 U32 n; /* Fetched value */
2324 static const int /* Length-1 to fetch by mask */
2325 icmhlen[16] = {0, 0, 0, 1, 0, 1, 1, 2, 0, 1, 1, 2, 1, 2, 2, 3};
2326 static const unsigned int /* Turn reg bytes off by mask*/
2327 icmhmask[16] = {0xFFFFFFFF, 0xFFFFFF00, 0xFFFF00FF, 0xFFFF0000,
2328 0xFF00FFFF, 0xFF00FF00, 0xFF0000FF, 0xFF000000,
2329 0x00FFFFFF, 0x00FFFF00, 0x00FF00FF, 0x00FF0000,
2330 0x0000FFFF, 0x0000FF00, 0x000000FF, 0x00000000};
2331
2332 RSY(inst, regs, r1, r3, b2, effective_addr2);
2333
2334 switch (r3) {
2335
2336 case 15:
2337 /* Optimized case */
2338 regs->GR_H(r1) = ARCH_DEP(vfetch4) (effective_addr2, b2, regs);
2339 regs->psw.cc = regs->GR_H(r1) ? regs->GR_H(r1) & 0x80000000 ?
2340 1 : 2 : 0;
2341 break;
2342
2343 default:
2344 memset (vbyte, 0, 4);
2345 ARCH_DEP(vfetchc)(vbyte, icmhlen[r3], effective_addr2, b2, regs);
2346
2347 /* If mask was 0 then we still had to fetch, according to POP.
2348 If so, set the fetched byte to 0 to force zero cc */
2349 if (!r3) vbyte[0] = 0;
2350
2351 n = fetch_fw (vbyte);
2352 regs->psw.cc = n ? n & 0x80000000 ?
2353 1 : 2 : 0;
2354
2355 /* Turn off the reg bytes we are going to set */
2356 regs->GR_H(r1) &= icmhmask[r3];
2357
2358 /* Set bytes one at a time according to the mask */
2359 i = 0;
2360 if (r3 & 0x8) regs->GR_H(r1) |= vbyte[i++] << 24;
2361 if (r3 & 0x4) regs->GR_H(r1) |= vbyte[i++] << 16;
2362 if (r3 & 0x2) regs->GR_H(r1) |= vbyte[i++] << 8;
2363 if (r3 & 0x1) regs->GR_H(r1) |= vbyte[i];
2364 break;
2365
2366 } /* switch (r3) */
2367
2368 } /* end DEF_INST(insert_characters_under_mask_high) */
2369 #endif /*defined(FEATURE_ESAME)*/
2370
2371
2372 #if defined(FEATURE_ESAME)
2373 /*-------------------------------------------------------------------*/
2374 /* EC44 BRXHG - Branch Relative on Index High Long [RIE] */
2375 /*-------------------------------------------------------------------*/
DEF_INST(branch_relative_on_index_high_long)2376 DEF_INST(branch_relative_on_index_high_long)
2377 {
2378 int r1, r3; /* Register numbers */
2379 S16 i2; /* 16-bit immediate offset */
2380 S64 i,j; /* Integer workareas */
2381
2382 RIE_B(inst, regs, r1, r3, i2);
2383
2384 /* Load the increment value from the R3 register */
2385 i = (S64)regs->GR_G(r3);
2386
2387 /* Load compare value from R3 (if R3 odd), or R3+1 (if even) */
2388 j = (r3 & 1) ? (S64)regs->GR_G(r3) : (S64)regs->GR_G(r3+1);
2389
2390 /* Add the increment value to the R1 register */
2391 regs->GR_G(r1) = (S64)regs->GR_G(r1) + i;
2392
2393 /* Branch if result compares high */
2394 if ( (S64)regs->GR_G(r1) > j )
2395 SUCCESSFUL_RELATIVE_BRANCH(regs, 2*i2, 6);
2396 else
2397 INST_UPDATE_PSW(regs, 6, 0);
2398
2399 } /* end DEF_INST(branch_relative_on_index_high_long) */
2400 #endif /*defined(FEATURE_ESAME)*/
2401
2402
2403 #if defined(FEATURE_ESAME)
2404 /*-------------------------------------------------------------------*/
2405 /* EC45 BRXLG - Branch Relative on Index Low or Equal Long [RIE] */
2406 /*-------------------------------------------------------------------*/
DEF_INST(branch_relative_on_index_low_or_equal_long)2407 DEF_INST(branch_relative_on_index_low_or_equal_long)
2408 {
2409 int r1, r3; /* Register numbers */
2410 S16 i2; /* 16-bit immediate offset */
2411 S64 i,j; /* Integer workareas */
2412
2413 RIE_B(inst, regs, r1, r3, i2);
2414
2415 /* Load the increment value from the R3 register */
2416 i = (S64)regs->GR_G(r3);
2417
2418 /* Load compare value from R3 (if R3 odd), or R3+1 (if even) */
2419 j = (r3 & 1) ? (S64)regs->GR_G(r3) : (S64)regs->GR_G(r3+1);
2420
2421 /* Add the increment value to the R1 register */
2422 regs->GR_G(r1) = (S64)regs->GR_G(r1) + i;
2423
2424 /* Branch if result compares low or equal */
2425 if ( (S64)regs->GR_G(r1) <= j )
2426 SUCCESSFUL_RELATIVE_BRANCH(regs, 2*i2, 6);
2427 else
2428 INST_UPDATE_PSW(regs, 6, 0);
2429
2430 } /* end DEF_INST(branch_relative_on_index_low_or_equal_long) */
2431 #endif /*defined(FEATURE_ESAME)*/
2432
2433
2434 #if defined(FEATURE_ESAME)
2435 /*-------------------------------------------------------------------*/
2436 /* EB44 BXHG - Branch on Index High Long [RSY] */
2437 /*-------------------------------------------------------------------*/
DEF_INST(branch_on_index_high_long)2438 DEF_INST(branch_on_index_high_long)
2439 {
2440 int r1, r3; /* Register numbers */
2441 int b2; /* effective address base */
2442 VADR effective_addr2; /* effective address */
2443 S64 i, j; /* Integer work areas */
2444
2445 RSY_B(inst, regs, r1, r3, b2, effective_addr2);
2446
2447 /* Load the increment value from the R3 register */
2448 i = (S64)regs->GR_G(r3);
2449
2450 /* Load compare value from R3 (if R3 odd), or R3+1 (if even) */
2451 j = (r3 & 1) ? (S64)regs->GR_G(r3) : (S64)regs->GR_G(r3+1);
2452
2453 /* Add the increment value to the R1 register */
2454 regs->GR_G(r1) = (S64)regs->GR_G(r1) + i;
2455
2456 /* Branch if result compares high */
2457 if ( (S64)regs->GR_G(r1) > j )
2458 SUCCESSFUL_BRANCH(regs, effective_addr2, 6);
2459 else
2460 INST_UPDATE_PSW(regs, 6, 0);
2461
2462 } /* end DEF_INST(branch_on_index_high_long) */
2463 #endif /*defined(FEATURE_ESAME)*/
2464
2465
2466 #if defined(FEATURE_ESAME)
2467 /*-------------------------------------------------------------------*/
2468 /* EB45 BXLEG - Branch on Index Low or Equal Long [RSY] */
2469 /*-------------------------------------------------------------------*/
DEF_INST(branch_on_index_low_or_equal_long)2470 DEF_INST(branch_on_index_low_or_equal_long)
2471 {
2472 int r1, r3; /* Register numbers */
2473 int b2; /* effective address base */
2474 VADR effective_addr2; /* effective address */
2475 S64 i, j; /* Integer work areas */
2476
2477 RSY_B(inst, regs, r1, r3, b2, effective_addr2);
2478
2479 /* Load the increment value from the R3 register */
2480 i = regs->GR_G(r3);
2481
2482 /* Load compare value from R3 (if R3 odd), or R3+1 (if even) */
2483 j = (r3 & 1) ? (S64)regs->GR_G(r3) : (S64)regs->GR_G(r3+1);
2484
2485 /* Add the increment value to the R1 register */
2486 regs->GR_G(r1) = (S64)regs->GR_G(r1) + i;
2487
2488 /* Branch if result compares low or equal */
2489 if ( (S64)regs->GR_G(r1) <= j )
2490 SUCCESSFUL_BRANCH(regs, effective_addr2, 6);
2491 else
2492 INST_UPDATE_PSW(regs, 6, 0);
2493
2494 } /* end DEF_INST(branch_on_index_low_or_equal_long) */
2495 #endif /*defined(FEATURE_ESAME)*/
2496
2497
2498 #if defined(FEATURE_ESAME)
2499 /*-------------------------------------------------------------------*/
2500 /* EB30 CSG - Compare and Swap Long [RSY] */
2501 /*-------------------------------------------------------------------*/
DEF_INST(compare_and_swap_long)2502 DEF_INST(compare_and_swap_long)
2503 {
2504 int r1, r3; /* Register numbers */
2505 int b2; /* effective address base */
2506 VADR effective_addr2; /* effective address */
2507 BYTE *main2; /* mainstor address */
2508 U64 old; /* old value */
2509
2510 RSY(inst, regs, r1, r3, b2, effective_addr2);
2511
2512 DW_CHECK(effective_addr2, regs);
2513
2514 /* Perform serialization before starting operation */
2515 PERFORM_SERIALIZATION (regs);
2516
2517 /* Get operand absolute address */
2518 main2 = MADDR (effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
2519
2520 /* Get old value */
2521 old = CSWAP64(regs->GR_G(r1));
2522
2523 /* Obtain main-storage access lock */
2524 OBTAIN_MAINLOCK(regs);
2525
2526 /* Attempt to exchange the values */
2527 regs->psw.cc = cmpxchg8 (&old, CSWAP64(regs->GR_G(r3)), main2);
2528
2529 /* Release main-storage access lock */
2530 RELEASE_MAINLOCK(regs);
2531
2532 /* Perform serialization after completing operation */
2533 PERFORM_SERIALIZATION (regs);
2534
2535 if (regs->psw.cc == 1)
2536 {
2537 regs->GR_G(r1) = CSWAP64(old);
2538 #if defined(_FEATURE_ZSIE)
2539 if(SIE_STATB(regs, IC0, CS1))
2540 {
2541 if( !OPEN_IC_PER(regs) )
2542 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
2543 else
2544 longjmp(regs->progjmp, SIE_INTERCEPT_INSTCOMP);
2545 }
2546 else
2547 #endif /*defined(_FEATURE_ZSIE)*/
2548 if (sysblk.cpus > 1)
2549 sched_yield();
2550 }
2551
2552 } /* end DEF_INST(compare_and_swap_long) */
2553 #endif /*defined(FEATURE_ESAME)*/
2554
2555
2556 #if defined(FEATURE_ESAME)
2557 /*-------------------------------------------------------------------*/
2558 /* EB3E CDSG - Compare Double and Swap Long [RSY] */
2559 /*-------------------------------------------------------------------*/
DEF_INST(compare_double_and_swap_long)2560 DEF_INST(compare_double_and_swap_long)
2561 {
2562 int r1, r3; /* Register numbers */
2563 int b2; /* effective address base */
2564 VADR effective_addr2; /* effective address */
2565 BYTE *main2; /* mainstor address */
2566 U64 old1, old2; /* old value */
2567
2568 RSY(inst, regs, r1, r3, b2, effective_addr2);
2569
2570 ODD2_CHECK(r1, r3, regs);
2571
2572 QW_CHECK(effective_addr2, regs);
2573
2574 /* Perform serialization before starting operation */
2575 PERFORM_SERIALIZATION (regs);
2576
2577 /* Get operand mainstor address */
2578 main2 = MADDR (effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
2579
2580 /* Get old values */
2581 old1 = CSWAP64(regs->GR_G(r1));
2582 old2 = CSWAP64(regs->GR_G(r1+1));
2583
2584 /* Obtain main-storage access lock */
2585 OBTAIN_MAINLOCK(regs);
2586
2587 /* Attempt to exchange the values */
2588 regs->psw.cc = cmpxchg16 (&old1, &old2,
2589 CSWAP64(regs->GR_G(r3)), CSWAP64(regs->GR_G(r3+1)),
2590 main2);
2591
2592 /* Release main-storage access lock */
2593 RELEASE_MAINLOCK(regs);
2594
2595 /* Perform serialization after completing operation */
2596 PERFORM_SERIALIZATION (regs);
2597
2598 if (regs->psw.cc == 1)
2599 {
2600 regs->GR_G(r1) = CSWAP64(old1);
2601 regs->GR_G(r1+1) = CSWAP64(old2);
2602 #if defined(_FEATURE_ZSIE)
2603 if(SIE_STATB(regs, IC0, CS1))
2604 {
2605 if( !OPEN_IC_PER(regs) )
2606 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
2607 else
2608 longjmp(regs->progjmp, SIE_INTERCEPT_INSTCOMP);
2609 }
2610 else
2611 #endif /*defined(_FEATURE_ZSIE)*/
2612 if (sysblk.cpus > 1)
2613 sched_yield();
2614 }
2615
2616 } /* end DEF_INST(compare_double_and_swap_long) */
2617 #endif /*defined(FEATURE_ESAME)*/
2618
2619
2620 #if defined(FEATURE_ESAME)
2621 /*-------------------------------------------------------------------*/
2622 /* E346 BCTG - Branch on Count Long [RXY] */
2623 /*-------------------------------------------------------------------*/
DEF_INST(branch_on_count_long)2624 DEF_INST(branch_on_count_long)
2625 {
2626 int r1; /* Value of R field */
2627 int b2; /* Base of effective addr */
2628 VADR effective_addr2; /* Effective address */
2629
2630 RXY_B(inst, regs, r1, b2, effective_addr2);
2631
2632 /* Subtract 1 from the R1 operand and branch if non-zero */
2633 if ( --(regs->GR_G(r1)) )
2634 SUCCESSFUL_BRANCH(regs, effective_addr2, 6);
2635 else
2636 INST_UPDATE_PSW(regs, 6, 0);
2637
2638 } /* end DEF_INST(branch_on_count_long) */
2639 #endif /*defined(FEATURE_ESAME)*/
2640
2641
2642 #if defined(FEATURE_ESAME)
2643 /*-------------------------------------------------------------------*/
2644 /* B946 BCTGR - Branch on Count Long Register [RRE] */
2645 /*-------------------------------------------------------------------*/
DEF_INST(branch_on_count_long_register)2646 DEF_INST(branch_on_count_long_register)
2647 {
2648 int r1, r2; /* Values of R fields */
2649 VADR newia; /* New instruction address */
2650
2651 RRE_B(inst, regs, r1, r2);
2652
2653 /* Compute the branch address from the R2 operand */
2654 newia = regs->GR_G(r2);
2655
2656 /* Subtract 1 from the R1 operand and branch if result
2657 is non-zero and R2 operand is not register zero */
2658 if ( --(regs->GR_G(r1)) && r2 != 0 )
2659 SUCCESSFUL_BRANCH(regs, newia, 2);
2660 else
2661 INST_UPDATE_PSW(regs, 4, 0);
2662
2663 } /* end DEF_INST(branch_on_count_long_register) */
2664 #endif /*defined(FEATURE_ESAME)*/
2665
2666
2667 #if defined(FEATURE_ESAME)
2668 /*-------------------------------------------------------------------*/
2669 /* B920 CGR - Compare Long Register [RRE] */
2670 /*-------------------------------------------------------------------*/
DEF_INST(compare_long_register)2671 DEF_INST(compare_long_register)
2672 {
2673 int r1, r2; /* Values of R fields */
2674
2675 RRE0(inst, regs, r1, r2);
2676
2677 /* Compare signed operands and set condition code */
2678 regs->psw.cc =
2679 (S64)regs->GR_G(r1) < (S64)regs->GR_G(r2) ? 1 :
2680 (S64)regs->GR_G(r1) > (S64)regs->GR_G(r2) ? 2 : 0;
2681
2682 } /* end DEF_INST(compare_long_register) */
2683 #endif /*defined(FEATURE_ESAME)*/
2684
2685
2686 #if defined(FEATURE_ESAME)
2687 /*-------------------------------------------------------------------*/
2688 /* B930 CGFR - Compare Long Fullword Register [RRE] */
2689 /*-------------------------------------------------------------------*/
DEF_INST(compare_long_fullword_register)2690 DEF_INST(compare_long_fullword_register)
2691 {
2692 int r1, r2; /* Values of R fields */
2693
2694 RRE0(inst, regs, r1, r2);
2695
2696 /* Compare signed operands and set condition code */
2697 regs->psw.cc =
2698 (S64)regs->GR_G(r1) < (S32)regs->GR_L(r2) ? 1 :
2699 (S64)regs->GR_G(r1) > (S32)regs->GR_L(r2) ? 2 : 0;
2700
2701 } /* end DEF_INST(compare_long_fullword_register) */
2702 #endif /*defined(FEATURE_ESAME)*/
2703
2704
2705 #if defined(FEATURE_ESAME)
2706 /*-------------------------------------------------------------------*/
2707 /* E320 CG - Compare Long [RXY] */
2708 /*-------------------------------------------------------------------*/
DEF_INST(compare_long)2709 DEF_INST(compare_long)
2710 {
2711 int r1; /* Values of R fields */
2712 int b2; /* Base of effective addr */
2713 VADR effective_addr2; /* Effective address */
2714 U64 n; /* 64-bit operand values */
2715
2716 RXY(inst, regs, r1, b2, effective_addr2);
2717
2718 /* Load second operand from operand address */
2719 n = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
2720
2721 /* Compare signed operands and set condition code */
2722 regs->psw.cc =
2723 (S64)regs->GR_G(r1) < (S64)n ? 1 :
2724 (S64)regs->GR_G(r1) > (S64)n ? 2 : 0;
2725
2726 } /* end DEF_INST(compare_long) */
2727 #endif /*defined(FEATURE_ESAME)*/
2728
2729
2730 #if defined(FEATURE_ESAME)
2731 /*-------------------------------------------------------------------*/
2732 /* E330 CGF - Compare Long Fullword [RXY] */
2733 /*-------------------------------------------------------------------*/
DEF_INST(compare_long_fullword)2734 DEF_INST(compare_long_fullword)
2735 {
2736 int r1; /* Values of R fields */
2737 int b2; /* Base of effective addr */
2738 VADR effective_addr2; /* Effective address */
2739 U32 n; /* 32-bit operand values */
2740
2741 RXY(inst, regs, r1, b2, effective_addr2);
2742
2743 /* Load second operand from operand address */
2744 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
2745
2746 /* Compare signed operands and set condition code */
2747 regs->psw.cc =
2748 (S64)regs->GR_G(r1) < (S32)n ? 1 :
2749 (S64)regs->GR_G(r1) > (S32)n ? 2 : 0;
2750
2751 } /* end DEF_INST(compare_long_fullword) */
2752 #endif /*defined(FEATURE_ESAME)*/
2753
2754
2755 #if defined(FEATURE_ESAME)
2756 /*-------------------------------------------------------------------*/
2757 /* E30A ALG - Add Logical Long [RXY] */
2758 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_long)2759 DEF_INST(add_logical_long)
2760 {
2761 int r1; /* Values of R fields */
2762 int b2; /* Base of effective addr */
2763 VADR effective_addr2; /* Effective address */
2764 U64 n; /* 64-bit operand values */
2765
2766 RXY(inst, regs, r1, b2, effective_addr2);
2767
2768 /* Load second operand from operand address */
2769 n = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
2770
2771 /* Add unsigned operands and set condition code */
2772 regs->psw.cc = add_logical_long(&(regs->GR_G(r1)),
2773 regs->GR_G(r1),
2774 n);
2775
2776 } /* end DEF_INST(add_logical_long) */
2777 #endif /*defined(FEATURE_ESAME)*/
2778
2779
2780 #if defined(FEATURE_ESAME)
2781 /*-------------------------------------------------------------------*/
2782 /* E31A ALGF - Add Logical Long Fullword [RXY] */
2783 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_long_fullword)2784 DEF_INST(add_logical_long_fullword)
2785 {
2786 int r1; /* Values of R fields */
2787 int b2; /* Base of effective addr */
2788 VADR effective_addr2; /* Effective address */
2789 U32 n; /* 32-bit operand values */
2790
2791 RXY(inst, regs, r1, b2, effective_addr2);
2792
2793 /* Load second operand from operand address */
2794 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
2795
2796 /* Add unsigned operands and set condition code */
2797 regs->psw.cc = add_logical_long(&(regs->GR_G(r1)),
2798 regs->GR_G(r1),
2799 n);
2800
2801 } /* end DEF_INST(add_logical_long_fullword) */
2802 #endif /*defined(FEATURE_ESAME)*/
2803
2804
2805 #if defined(FEATURE_ESAME)
2806 /*-------------------------------------------------------------------*/
2807 /* E318 AGF - Add Long Fullword [RXY] */
2808 /*-------------------------------------------------------------------*/
DEF_INST(add_long_fullword)2809 DEF_INST(add_long_fullword)
2810 {
2811 int r1; /* Values of R fields */
2812 int b2; /* Base of effective addr */
2813 VADR effective_addr2; /* Effective address */
2814 U32 n; /* 32-bit operand values */
2815
2816 RXY(inst, regs, r1, b2, effective_addr2);
2817
2818 /* Load second operand from operand address */
2819 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
2820
2821 /* Add signed operands and set condition code */
2822 regs->psw.cc = add_signed_long (&(regs->GR_G(r1)),
2823 regs->GR_G(r1),
2824 (S32)n);
2825
2826 /* Program check if fixed-point overflow */
2827 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
2828 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
2829
2830 } /* end DEF_INST(add_long_fullword) */
2831 #endif /*defined(FEATURE_ESAME)*/
2832
2833
2834 #if defined(FEATURE_ESAME)
2835 /*-------------------------------------------------------------------*/
2836 /* E308 AG - Add Long [RXY] */
2837 /*-------------------------------------------------------------------*/
DEF_INST(add_long)2838 DEF_INST(add_long)
2839 {
2840 int r1; /* Values of R fields */
2841 int b2; /* Base of effective addr */
2842 VADR effective_addr2; /* Effective address */
2843 U64 n; /* 64-bit operand values */
2844
2845 RXY(inst, regs, r1, b2, effective_addr2);
2846
2847 /* Load second operand from operand address */
2848 n = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
2849
2850 /* Add signed operands and set condition code */
2851 regs->psw.cc = add_signed_long (&(regs->GR_G(r1)),
2852 regs->GR_G(r1),
2853 n);
2854
2855 /* Program check if fixed-point overflow */
2856 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
2857 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
2858
2859 } /* end DEF_INST(add_long) */
2860 #endif /*defined(FEATURE_ESAME)*/
2861
2862
2863 #if defined(FEATURE_ESAME)
2864 /*-------------------------------------------------------------------*/
2865 /* E30B SLG - Subtract Logical Long [RXY] */
2866 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_long)2867 DEF_INST(subtract_logical_long)
2868 {
2869 int r1; /* Values of R fields */
2870 int b2; /* Base of effective addr */
2871 VADR effective_addr2; /* Effective address */
2872 U64 n; /* 64-bit operand values */
2873
2874 RXY(inst, regs, r1, b2, effective_addr2);
2875
2876 /* Load second operand from operand address */
2877 n = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
2878
2879 /* Subtract unsigned operands and set condition code */
2880 regs->psw.cc = sub_logical_long(&(regs->GR_G(r1)),
2881 regs->GR_G(r1),
2882 n);
2883
2884 } /* end DEF_INST(subtract_logical_long) */
2885 #endif /*defined(FEATURE_ESAME)*/
2886
2887
2888 #if defined(FEATURE_ESAME)
2889 /*-------------------------------------------------------------------*/
2890 /* E31B SLGF - Subtract Logical Long Fullword [RXY] */
2891 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_long_fullword)2892 DEF_INST(subtract_logical_long_fullword)
2893 {
2894 int r1; /* Values of R fields */
2895 int b2; /* Base of effective addr */
2896 VADR effective_addr2; /* Effective address */
2897 U32 n; /* 32-bit operand values */
2898
2899 RXY(inst, regs, r1, b2, effective_addr2);
2900
2901 /* Load second operand from operand address */
2902 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
2903
2904 /* Subtract unsigned operands and set condition code */
2905 regs->psw.cc = sub_logical_long(&(regs->GR_G(r1)),
2906 regs->GR_G(r1),
2907 n);
2908
2909 } /* end DEF_INST(subtract_logical_long_fullword) */
2910 #endif /*defined(FEATURE_ESAME)*/
2911
2912
2913 #if defined(FEATURE_ESAME)
2914 /*-------------------------------------------------------------------*/
2915 /* E319 SGF - Subtract Long Fullword [RXY] */
2916 /*-------------------------------------------------------------------*/
DEF_INST(subtract_long_fullword)2917 DEF_INST(subtract_long_fullword)
2918 {
2919 int r1; /* Values of R fields */
2920 int b2; /* Base of effective addr */
2921 VADR effective_addr2; /* Effective address */
2922 U32 n; /* 32-bit operand values */
2923
2924 RXY(inst, regs, r1, b2, effective_addr2);
2925
2926 /* Load second operand from operand address */
2927 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
2928
2929 /* Subtract signed operands and set condition code */
2930 regs->psw.cc = sub_signed_long(&(regs->GR_G(r1)),
2931 regs->GR_G(r1),
2932 (S32)n);
2933
2934 /* Program check if fixed-point overflow */
2935 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
2936 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
2937
2938 } /* end DEF_INST(subtract_long_fullword) */
2939 #endif /*defined(FEATURE_ESAME)*/
2940
2941
2942 #if defined(FEATURE_ESAME)
2943 /*-------------------------------------------------------------------*/
2944 /* E309 SG - Subtract Long [RXY] */
2945 /*-------------------------------------------------------------------*/
DEF_INST(subtract_long)2946 DEF_INST(subtract_long)
2947 {
2948 int r1; /* Values of R fields */
2949 int b2; /* Base of effective addr */
2950 VADR effective_addr2; /* Effective address */
2951 U64 n; /* 64-bit operand values */
2952
2953 RXY(inst, regs, r1, b2, effective_addr2);
2954
2955 /* Load second operand from operand address */
2956 n = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
2957
2958 /* Subtract signed operands and set condition code */
2959 regs->psw.cc = sub_signed_long(&(regs->GR_G(r1)),
2960 regs->GR_G(r1),
2961 n);
2962
2963 /* Program check if fixed-point overflow */
2964 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
2965 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
2966
2967 } /* end DEF_INST(subtract_long) */
2968 #endif /*defined(FEATURE_ESAME)*/
2969
2970
2971 #if defined(FEATURE_ESAME)
2972 /*-------------------------------------------------------------------*/
2973 /* B909 SGR - Subtract Long Register [RRE] */
2974 /*-------------------------------------------------------------------*/
DEF_INST(subtract_long_register)2975 DEF_INST(subtract_long_register)
2976 {
2977 int r1, r2; /* Values of R fields */
2978
2979 RRE(inst, regs, r1, r2);
2980
2981 /* Subtract signed operands and set condition code */
2982 regs->psw.cc = sub_signed_long(&(regs->GR_G(r1)),
2983 regs->GR_G(r1),
2984 regs->GR_G(r2));
2985
2986 /* Program check if fixed-point overflow */
2987 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
2988 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
2989
2990 } /* end DEF_INST(subtract_long_register) */
2991 #endif /*defined(FEATURE_ESAME)*/
2992
2993
2994 #if defined(FEATURE_ESAME)
2995 /*-------------------------------------------------------------------*/
2996 /* B919 SGFR - Subtract Long Fullword Register [RRE] */
2997 /*-------------------------------------------------------------------*/
DEF_INST(subtract_long_fullword_register)2998 DEF_INST(subtract_long_fullword_register)
2999 {
3000 int r1, r2; /* Values of R fields */
3001
3002 RRE(inst, regs, r1, r2);
3003
3004 /* Subtract signed operands and set condition code */
3005 regs->psw.cc = sub_signed_long(&(regs->GR_G(r1)),
3006 regs->GR_G(r1),
3007 (S32)regs->GR_L(r2));
3008
3009 /* Program check if fixed-point overflow */
3010 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
3011 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
3012
3013 } /* end DEF_INST(subtract_long_fullword_register) */
3014 #endif /*defined(FEATURE_ESAME)*/
3015
3016
3017 #if defined(FEATURE_ESAME)
3018 /*-------------------------------------------------------------------*/
3019 /* B908 AGR - Add Long Register [RRE] */
3020 /*-------------------------------------------------------------------*/
DEF_INST(add_long_register)3021 DEF_INST(add_long_register)
3022 {
3023 int r1, r2; /* Values of R fields */
3024
3025 RRE(inst, regs, r1, r2);
3026
3027 /* Add signed operands and set condition code */
3028 regs->psw.cc = add_signed_long(&(regs->GR_G(r1)),
3029 regs->GR_G(r1),
3030 regs->GR_G(r2));
3031
3032 /* Program check if fixed-point overflow */
3033 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
3034 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
3035
3036 } /* end DEF_INST(add_long_register) */
3037 #endif /*defined(FEATURE_ESAME)*/
3038
3039
3040 #if defined(FEATURE_ESAME)
3041 /*-------------------------------------------------------------------*/
3042 /* B918 AGFR - Add Long Fullword Register [RRE] */
3043 /*-------------------------------------------------------------------*/
DEF_INST(add_long_fullword_register)3044 DEF_INST(add_long_fullword_register)
3045 {
3046 int r1, r2; /* Values of R fields */
3047
3048 RRE(inst, regs, r1, r2);
3049
3050 /* Add signed operands and set condition code */
3051 regs->psw.cc = add_signed_long(&(regs->GR_G(r1)),
3052 regs->GR_G(r1),
3053 (S32)regs->GR_L(r2));
3054
3055 /* Program check if fixed-point overflow */
3056 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
3057 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
3058
3059 } /* end DEF_INST(add_long_fullword_register) */
3060 #endif /*defined(FEATURE_ESAME)*/
3061
3062
3063 #if defined(FEATURE_ESAME)
3064 /*-------------------------------------------------------------------*/
3065 /* B900 LPGR - Load Positive Long Register [RRE] */
3066 /*-------------------------------------------------------------------*/
DEF_INST(load_positive_long_register)3067 DEF_INST(load_positive_long_register)
3068 {
3069 int r1, r2; /* Values of R fields */
3070
3071 RRE(inst, regs, r1, r2);
3072
3073 /* Condition code 3 and program check if overflow */
3074 if ( regs->GR_G(r2) == 0x8000000000000000ULL )
3075 {
3076 regs->GR_G(r1) = regs->GR_G(r2);
3077 regs->psw.cc = 3;
3078 if ( FOMASK(®s->psw) )
3079 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
3080 return;
3081 }
3082
3083 /* Load positive value of second operand and set cc */
3084 regs->GR_G(r1) = (S64)regs->GR_G(r2) < 0 ?
3085 -((S64)regs->GR_G(r2)) :
3086 (S64)regs->GR_G(r2);
3087
3088 regs->psw.cc = (S64)regs->GR_G(r1) == 0 ? 0 : 2;
3089
3090 } /* end DEF_INST(load_positive_long_register) */
3091 #endif /*defined(FEATURE_ESAME)*/
3092
3093
3094 #if defined(FEATURE_ESAME)
3095 /*-------------------------------------------------------------------*/
3096 /* B910 LPGFR - Load Positive Long Fullword Register [RRE] */
3097 /*-------------------------------------------------------------------*/
DEF_INST(load_positive_long_fullword_register)3098 DEF_INST(load_positive_long_fullword_register)
3099 {
3100 int r1, r2; /* Values of R fields */
3101 S64 gpr2l;
3102
3103 RRE0(inst, regs, r1, r2);
3104
3105 gpr2l = (S32)regs->GR_L(r2);
3106
3107 /* Load positive value of second operand and set cc */
3108 regs->GR_G(r1) = gpr2l < 0 ? -gpr2l : gpr2l;
3109
3110 regs->psw.cc = (S64)regs->GR_G(r1) == 0 ? 0 : 2;
3111
3112 } /* end DEF_INST(load_positive_long_fullword_register) */
3113 #endif /*defined(FEATURE_ESAME)*/
3114
3115
3116 #if defined(FEATURE_ESAME)
3117 /*-------------------------------------------------------------------*/
3118 /* B901 LNGR - Load Negative Long Register [RRE] */
3119 /*-------------------------------------------------------------------*/
DEF_INST(load_negative_long_register)3120 DEF_INST(load_negative_long_register)
3121 {
3122 int r1, r2; /* Values of R fields */
3123
3124 RRE0(inst, regs, r1, r2);
3125
3126 /* Load negative value of second operand and set cc */
3127 regs->GR_G(r1) = (S64)regs->GR_G(r2) > 0 ?
3128 -((S64)regs->GR_G(r2)) :
3129 (S64)regs->GR_G(r2);
3130
3131 regs->psw.cc = (S64)regs->GR_G(r1) == 0 ? 0 : 1;
3132
3133 } /* end DEF_INST(load_negative_long_register) */
3134 #endif /*defined(FEATURE_ESAME)*/
3135
3136
3137 #if defined(FEATURE_ESAME)
3138 /*-------------------------------------------------------------------*/
3139 /* B911 LNGFR - Load Negative Long Fullword Register [RRE] */
3140 /*-------------------------------------------------------------------*/
DEF_INST(load_negative_long_fullword_register)3141 DEF_INST(load_negative_long_fullword_register)
3142 {
3143 int r1, r2; /* Values of R fields */
3144 S64 gpr2l;
3145
3146 RRE0(inst, regs, r1, r2);
3147
3148 gpr2l = (S32)regs->GR_L(r2);
3149
3150 /* Load negative value of second operand and set cc */
3151 regs->GR_G(r1) = gpr2l > 0 ? -gpr2l : gpr2l;
3152
3153 regs->psw.cc = (S64)regs->GR_G(r1) == 0 ? 0 : 1;
3154
3155 } /* end DEF_INST(load_negative_long_fullword_register) */
3156 #endif /*defined(FEATURE_ESAME)*/
3157
3158
3159 #if defined(FEATURE_ESAME)
3160 /*-------------------------------------------------------------------*/
3161 /* B902 LTGR - Load and Test Long Register [RRE] */
3162 /*-------------------------------------------------------------------*/
DEF_INST(load_and_test_long_register)3163 DEF_INST(load_and_test_long_register)
3164 {
3165 int r1, r2; /* Values of R fields */
3166
3167 RRE0(inst, regs, r1, r2);
3168
3169 /* Copy second operand and set condition code */
3170 regs->GR_G(r1) = regs->GR_G(r2);
3171
3172 regs->psw.cc = (S64)regs->GR_G(r1) < 0 ? 1 :
3173 (S64)regs->GR_G(r1) > 0 ? 2 : 0;
3174
3175 } /* end DEF_INST(load_and_test_long_register) */
3176 #endif /*defined(FEATURE_ESAME)*/
3177
3178
3179 #if defined(FEATURE_ESAME)
3180 /*-------------------------------------------------------------------*/
3181 /* B912 LTGFR - Load and Test Long Fullword Register [RRE] */
3182 /*-------------------------------------------------------------------*/
DEF_INST(load_and_test_long_fullword_register)3183 DEF_INST(load_and_test_long_fullword_register)
3184 {
3185 int r1, r2; /* Values of R fields */
3186
3187 RRE0(inst, regs, r1, r2);
3188
3189 /* Copy second operand and set condition code */
3190 regs->GR_G(r1) = (S32)regs->GR_L(r2);
3191
3192 regs->psw.cc = (S64)regs->GR_G(r1) < 0 ? 1 :
3193 (S64)regs->GR_G(r1) > 0 ? 2 : 0;
3194
3195 } /* end DEF_INST(load_and_test_long_fullword_register) */
3196 #endif /*defined(FEATURE_ESAME)*/
3197
3198
3199 #if defined(FEATURE_ESAME)
3200 /*-------------------------------------------------------------------*/
3201 /* B903 LCGR - Load Complement Long Register [RRE] */
3202 /*-------------------------------------------------------------------*/
DEF_INST(load_complement_long_register)3203 DEF_INST(load_complement_long_register)
3204 {
3205 int r1, r2; /* Values of R fields */
3206
3207 RRE(inst, regs, r1, r2);
3208
3209 /* Condition code 3 and program check if overflow */
3210 if ( regs->GR_G(r2) == 0x8000000000000000ULL )
3211 {
3212 regs->GR_G(r1) = regs->GR_G(r2);
3213 regs->psw.cc = 3;
3214 if ( FOMASK(®s->psw) )
3215 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
3216 return;
3217 }
3218
3219 /* Load complement of second operand and set condition code */
3220 regs->GR_G(r1) = -((S64)regs->GR_G(r2));
3221
3222 regs->psw.cc = (S64)regs->GR_G(r1) < 0 ? 1 :
3223 (S64)regs->GR_G(r1) > 0 ? 2 : 0;
3224
3225 } /* end DEF_INST(load_complement_long_register) */
3226 #endif /*defined(FEATURE_ESAME)*/
3227
3228
3229 #if defined(FEATURE_ESAME)
3230 /*-------------------------------------------------------------------*/
3231 /* B913 LCGFR - Load Complement Long Fullword Register [RRE] */
3232 /*-------------------------------------------------------------------*/
DEF_INST(load_complement_long_fullword_register)3233 DEF_INST(load_complement_long_fullword_register)
3234 {
3235 int r1, r2; /* Values of R fields */
3236 S64 gpr2l;
3237
3238 RRE0(inst, regs, r1, r2);
3239
3240 gpr2l = (S32)regs->GR_L(r2);
3241
3242 /* Load complement of second operand and set condition code */
3243 regs->GR_G(r1) = -gpr2l;
3244
3245 regs->psw.cc = (S64)regs->GR_G(r1) < 0 ? 1 :
3246 (S64)regs->GR_G(r1) > 0 ? 2 : 0;
3247
3248 } /* end DEF_INST(load_complement_long_fullword_register) */
3249 #endif /*defined(FEATURE_ESAME)*/
3250
3251
3252 #if defined(FEATURE_ESAME)
3253 /*-------------------------------------------------------------------*/
3254 /* A7x2 TMHH - Test under Mask High High [RI] */
3255 /*-------------------------------------------------------------------*/
DEF_INST(test_under_mask_high_high)3256 DEF_INST(test_under_mask_high_high)
3257 {
3258 int r1; /* Register number */
3259 U16 i2; /* 16-bit operand values */
3260 U16 h1; /* 16-bit operand values */
3261 U16 h2; /* 16-bit operand values */
3262
3263 RI0(inst, regs, r1, i2);
3264
3265 /* AND register bits 0-15 with immediate operand */
3266 h1 = i2 & regs->GR_HHH(r1);
3267
3268 /* Isolate leftmost bit of immediate operand */
3269 for ( h2 = 0x8000; h2 != 0 && (h2 & i2) == 0; h2 >>= 1 );
3270
3271 /* Set condition code according to result */
3272 regs->psw.cc =
3273 ( h1 == 0 ) ? 0 : /* result all zeroes */
3274 ( h1 == i2) ? 3 : /* result all ones */
3275 ((h1 & h2) == 0) ? 1 : /* leftmost bit zero */
3276 2; /* leftmost bit one */
3277
3278 } /* end DEF_INST(test_under_mask_high_high) */
3279 #endif /*defined(FEATURE_ESAME)*/
3280
3281
3282 #if defined(FEATURE_ESAME)
3283 /*-------------------------------------------------------------------*/
3284 /* A7x3 TMHL - Test under Mask High Low [RI] */
3285 /*-------------------------------------------------------------------*/
DEF_INST(test_under_mask_high_low)3286 DEF_INST(test_under_mask_high_low)
3287 {
3288 int r1; /* Register number */
3289 U16 i2; /* 16-bit operand values */
3290 U16 h1; /* 16-bit operand values */
3291 U16 h2; /* 16-bit operand values */
3292
3293 RI0(inst, regs, r1, i2);
3294
3295 /* AND register bits 16-31 with immediate operand */
3296 h1 = i2 & regs->GR_HHL(r1);
3297
3298 /* Isolate leftmost bit of immediate operand */
3299 for ( h2 = 0x8000; h2 != 0 && (h2 & i2) == 0; h2 >>= 1 );
3300
3301 /* Set condition code according to result */
3302 regs->psw.cc =
3303 ( h1 == 0 ) ? 0 : /* result all zeroes */
3304 ( h1 == i2) ? 3 : /* result all ones */
3305 ((h1 & h2) == 0) ? 1 : /* leftmost bit zero */
3306 2; /* leftmost bit one */
3307
3308 } /* end DEF_INST(test_under_mask_high_low) */
3309 #endif /*defined(FEATURE_ESAME)*/
3310
3311
3312 #if defined(FEATURE_ESAME)
3313 /*-------------------------------------------------------------------*/
3314 /* A7x7 BRCTG - Branch Relative on Count Long [RI] */
3315 /*-------------------------------------------------------------------*/
DEF_INST(branch_relative_on_count_long)3316 DEF_INST(branch_relative_on_count_long)
3317 {
3318 int r1; /* Register number */
3319 U16 i2; /* 16-bit operand values */
3320
3321 RI_B(inst, regs, r1, i2);
3322
3323 /* Subtract 1 from the R1 operand and branch if non-zero */
3324 if ( --(regs->GR_G(r1)) )
3325 SUCCESSFUL_RELATIVE_BRANCH(regs, 2*(S16)i2, 4);
3326 else
3327 INST_UPDATE_PSW(regs, 4, 0);
3328 } /* end DEF_INST(branch_relative_on_count_long) */
3329 #endif /*defined(FEATURE_ESAME)*/
3330
3331
3332 #if defined(FEATURE_ESAME)
3333 /*-------------------------------------------------------------------*/
3334 /* E321 CLG - Compare Logical long [RXY] */
3335 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_long)3336 DEF_INST(compare_logical_long)
3337 {
3338 int r1; /* Values of R fields */
3339 int b2; /* Base of effective addr */
3340 VADR effective_addr2; /* Effective address */
3341 U64 n; /* 64-bit operand values */
3342
3343 RXY(inst, regs, r1, b2, effective_addr2);
3344
3345 /* Load second operand from operand address */
3346 n = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
3347
3348 /* Compare unsigned operands and set condition code */
3349 regs->psw.cc = regs->GR_G(r1) < n ? 1 :
3350 regs->GR_G(r1) > n ? 2 : 0;
3351
3352 } /* end DEF_INST(compare_logical_long) */
3353 #endif /*defined(FEATURE_ESAME)*/
3354
3355
3356 #if defined(FEATURE_ESAME)
3357 /*-------------------------------------------------------------------*/
3358 /* E331 CLGF - Compare Logical long fullword [RXY] */
3359 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_long_fullword)3360 DEF_INST(compare_logical_long_fullword)
3361 {
3362 int r1; /* Values of R fields */
3363 int b2; /* Base of effective addr */
3364 VADR effective_addr2; /* Effective address */
3365 U32 n; /* 32-bit operand values */
3366
3367 RXY(inst, regs, r1, b2, effective_addr2);
3368
3369 /* Load second operand from operand address */
3370 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
3371
3372 /* Compare unsigned operands and set condition code */
3373 regs->psw.cc = regs->GR_G(r1) < n ? 1 :
3374 regs->GR_G(r1) > n ? 2 : 0;
3375
3376 } /* end DEF_INST(compare_logical_long_fullword) */
3377 #endif /*defined(FEATURE_ESAME)*/
3378
3379
3380 #if defined(FEATURE_ESAME)
3381 /*-------------------------------------------------------------------*/
3382 /* B931 CLGFR - Compare Logical Long Fullword Register [RRE] */
3383 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_long_fullword_register)3384 DEF_INST(compare_logical_long_fullword_register)
3385 {
3386 int r1, r2; /* Values of R fields */
3387
3388 RRE0(inst, regs, r1, r2);
3389
3390 /* Compare unsigned operands and set condition code */
3391 regs->psw.cc = regs->GR_G(r1) < regs->GR_L(r2) ? 1 :
3392 regs->GR_G(r1) > regs->GR_L(r2) ? 2 : 0;
3393
3394 } /* end DEF_INST(compare_logical_long_fullword_register) */
3395 #endif /*defined(FEATURE_ESAME)*/
3396
3397
3398 #if defined(FEATURE_ESAME)
3399 /*-------------------------------------------------------------------*/
3400 /* B917 LLGTR - Load Logical Long Thirtyone Register [RRE] */
3401 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_long_thirtyone_register)3402 DEF_INST(load_logical_long_thirtyone_register)
3403 {
3404 int r1, r2; /* Values of R fields */
3405
3406 RRE0(inst, regs, r1, r2);
3407
3408 regs->GR_G(r1) = regs->GR_L(r2) & 0x7FFFFFFF;
3409
3410 } /* end DEF_INST(load_logical_long_thirtyone_register) */
3411 #endif /*defined(FEATURE_ESAME)*/
3412
3413
3414 #if defined(FEATURE_ESAME)
3415 /*-------------------------------------------------------------------*/
3416 /* B921 CLGR - Compare Logical Long Register [RRE] */
3417 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_long_register)3418 DEF_INST(compare_logical_long_register)
3419 {
3420 int r1, r2; /* Values of R fields */
3421
3422 RRE0(inst, regs, r1, r2);
3423
3424 /* Compare unsigned operands and set condition code */
3425 regs->psw.cc = regs->GR_G(r1) < regs->GR_G(r2) ? 1 :
3426 regs->GR_G(r1) > regs->GR_G(r2) ? 2 : 0;
3427
3428 } /* end DEF_INST(compare_logical_long_register) */
3429 #endif /*defined(FEATURE_ESAME)*/
3430
3431
3432 #if defined(FEATURE_ESAME)
3433 /*-------------------------------------------------------------------*/
3434 /* EB1C RLLG - Rotate Left Single Logical Long [RSY] */
3435 /*-------------------------------------------------------------------*/
DEF_INST(rotate_left_single_logical_long)3436 DEF_INST(rotate_left_single_logical_long)
3437 {
3438 int r1, r3; /* Register numbers */
3439 int b2; /* effective address base */
3440 VADR effective_addr2; /* effective address */
3441 U64 n; /* Integer work areas */
3442
3443 RSY0(inst, regs, r1, r3, b2, effective_addr2);
3444
3445 /* Use rightmost six bits of operand address as shift count */
3446 n = effective_addr2 & 0x3F;
3447
3448 /* Rotate and copy contents of r3 to r1 */
3449 regs->GR_G(r1) = (regs->GR_G(r3) << n)
3450 | ((n == 0) ? 0 : (regs->GR_G(r3) >> (64 - n)));
3451
3452 } /* end DEF_INST(rotate_left_single_logical_long) */
3453 #endif /*defined(FEATURE_ESAME)*/
3454
3455
3456 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
3457 /*-------------------------------------------------------------------*/
3458 /* EB1D RLL - Rotate Left Single Logical [RSY] */
3459 /*-------------------------------------------------------------------*/
DEF_INST(rotate_left_single_logical)3460 DEF_INST(rotate_left_single_logical)
3461 {
3462 int r1, r3; /* Register numbers */
3463 int b2; /* effective address base */
3464 VADR effective_addr2; /* effective address */
3465 U64 n; /* Integer work areas */
3466
3467 RSY0(inst, regs, r1, r3, b2, effective_addr2);
3468
3469 /* Use rightmost five bits of operand address as shift count */
3470 n = effective_addr2 & 0x1F;
3471
3472 /* Rotate and copy contents of r3 to r1 */
3473 regs->GR_L(r1) = (regs->GR_L(r3) << n)
3474 | ((n == 0) ? 0 : (regs->GR_L(r3) >> (32 - n)));
3475
3476 } /* end DEF_INST(rotate_left_single_logical) */
3477 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
3478
3479
3480 #if defined(FEATURE_ESAME)
3481 /*-------------------------------------------------------------------*/
3482 /* EB0D SLLG - Shift Left Single Logical Long [RSY] */
3483 /*-------------------------------------------------------------------*/
DEF_INST(shift_left_single_logical_long)3484 DEF_INST(shift_left_single_logical_long)
3485 {
3486 int r1, r3; /* Register numbers */
3487 int b2; /* effective address base */
3488 VADR effective_addr2; /* effective address */
3489 U64 n; /* Integer work areas */
3490
3491 RSY0(inst, regs, r1, r3, b2, effective_addr2);
3492
3493 /* Use rightmost six bits of operand address as shift count */
3494 n = effective_addr2 & 0x3F;
3495
3496 /* Copy contents of r3 to r1 and perform shift */
3497 regs->GR_G(r1) = regs->GR_G(r3) << n;
3498
3499 } /* end DEF_INST(shift_left_single_logical_long) */
3500 #endif /*defined(FEATURE_ESAME)*/
3501
3502
3503 #if defined(FEATURE_ESAME)
3504 /*-------------------------------------------------------------------*/
3505 /* EB0C SRLG - Shift Right Single Logical Long [RSY] */
3506 /*-------------------------------------------------------------------*/
DEF_INST(shift_right_single_logical_long)3507 DEF_INST(shift_right_single_logical_long)
3508 {
3509 int r1, r3; /* Register numbers */
3510 int b2; /* effective address base */
3511 VADR effective_addr2; /* effective address */
3512 U64 n; /* Integer work areas */
3513
3514 RSY0(inst, regs, r1, r3, b2, effective_addr2);
3515
3516 /* Use rightmost six bits of operand address as shift count */
3517 n = effective_addr2 & 0x3F;
3518
3519 /* Copy contents of r3 to r1 and perform shift */
3520 regs->GR_G(r1) = regs->GR_G(r3) >> n;
3521
3522 } /* end DEF_INST(shift_right_single_logical_long) */
3523 #endif /*defined(FEATURE_ESAME)*/
3524
3525
3526 #if defined(FEATURE_ESAME)
3527 /*-------------------------------------------------------------------*/
3528 /* EB0B SLAG - Shift Left Single Long [RSY] */
3529 /*-------------------------------------------------------------------*/
DEF_INST(shift_left_single_long)3530 DEF_INST(shift_left_single_long)
3531 {
3532 U32 r1, r3; /* Register numbers */
3533 U32 b2; /* effective address base */
3534 VADR effective_addr2; /* effective address */
3535 U64 n, n1, n2; /* 64-bit operand values */
3536 U32 i, j; /* Integer work areas */
3537
3538 RSY(inst, regs, r1, r3, b2, effective_addr2);
3539
3540 /* Use rightmost six bits of operand address as shift count */
3541 n = effective_addr2 & 0x3F;
3542
3543 /* Load the numeric and sign portions from the R3 register */
3544 n1 = regs->GR_G(r3) & 0x7FFFFFFFFFFFFFFFULL;
3545 n2 = regs->GR_G(r3) & 0x8000000000000000ULL;
3546
3547 /* Shift the numeric portion left n positions */
3548 for (i = 0, j = 0; i < n; i++)
3549 {
3550 /* Shift bits 1-63 left one bit position */
3551 n1 <<= 1;
3552
3553 /* Overflow if bit shifted out is unlike the sign bit */
3554 if ((n1 & 0x8000000000000000ULL) != n2)
3555 j = 1;
3556 }
3557
3558 /* Load the updated value into the R1 register */
3559 regs->GR_G(r1) = (n1 & 0x7FFFFFFFFFFFFFFFULL) | n2;
3560
3561 /* Condition code 3 and program check if overflow occurred */
3562 if (j)
3563 {
3564 regs->psw.cc = 3;
3565 if ( FOMASK(®s->psw) )
3566 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
3567 return;
3568 }
3569
3570 /* Set the condition code */
3571 regs->psw.cc = (S64)regs->GR_G(r1) > 0 ? 2 :
3572 (S64)regs->GR_G(r1) < 0 ? 1 : 0;
3573
3574 } /* end DEF_INST(shift_left_single_long) */
3575 #endif /*defined(FEATURE_ESAME)*/
3576
3577
3578 #if defined(FEATURE_ESAME)
3579 /*-------------------------------------------------------------------*/
3580 /* EB0A SRAG - Shift Right Single Long [RSY] */
3581 /*-------------------------------------------------------------------*/
DEF_INST(shift_right_single_long)3582 DEF_INST(shift_right_single_long)
3583 {
3584 int r1, r3; /* Register numbers */
3585 int b2; /* effective address base */
3586 VADR effective_addr2; /* effective address */
3587 U64 n; /* Integer work areas */
3588
3589 RSY0(inst, regs, r1, r3, b2, effective_addr2);
3590
3591 /* Use rightmost six bits of operand address as shift count */
3592 n = effective_addr2 & 0x3F;
3593
3594 /* Copy and shift the signed value of the R3 register */
3595 regs->GR_G(r1) = (n > 62) ?
3596 ((S64)regs->GR_G(r3) < 0 ? -1LL : 0) :
3597 (S64)regs->GR_G(r3) >> n;
3598
3599 /* Set the condition code */
3600 regs->psw.cc = (S64)regs->GR_G(r1) > 0 ? 2 :
3601 (S64)regs->GR_G(r1) < 0 ? 1 : 0;
3602
3603 } /* end DEF_INST(shift_right_single_long) */
3604 #endif /*defined(FEATURE_ESAME)*/
3605
3606
3607 #if defined(FEATURE_ESAME)
3608 /*-------------------------------------------------------------------*/
3609 /* E31C MSGF - Multiply Single Long Fullword [RXY] */
3610 /*-------------------------------------------------------------------*/
DEF_INST(multiply_single_long_fullword)3611 DEF_INST(multiply_single_long_fullword)
3612 {
3613 int r1; /* Value of R field */
3614 int b2; /* Base of effective addr */
3615 VADR effective_addr2; /* Effective address */
3616 U32 n; /* 32-bit operand values */
3617
3618 RXY(inst, regs, r1, b2, effective_addr2);
3619
3620 /* Load second operand from operand address */
3621 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
3622
3623 /* Multiply signed operands ignoring overflow */
3624 regs->GR_G(r1) = (S64)regs->GR_G(r1) * (S32)n;
3625
3626 } /* end DEF_INST(multiply_single_long_fullword) */
3627 #endif /*defined(FEATURE_ESAME)*/
3628
3629
3630 #if defined(FEATURE_ESAME)
3631 /*-------------------------------------------------------------------*/
3632 /* E30C MSG - Multiply Single Long [RXY] */
3633 /*-------------------------------------------------------------------*/
DEF_INST(multiply_single_long)3634 DEF_INST(multiply_single_long)
3635 {
3636 int r1; /* Value of R field */
3637 int b2; /* Base of effective addr */
3638 VADR effective_addr2; /* Effective address */
3639 U64 n; /* 64-bit operand values */
3640
3641 RXY(inst, regs, r1, b2, effective_addr2);
3642
3643 /* Load second operand from operand address */
3644 n = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
3645
3646 /* Multiply signed operands ignoring overflow */
3647 regs->GR_G(r1) = (S64)regs->GR_G(r1) * (S64)n;
3648
3649 } /* end DEF_INST(multiply_single_long) */
3650 #endif /*defined(FEATURE_ESAME)*/
3651
3652
3653 #if defined(FEATURE_ESAME)
3654 /*-------------------------------------------------------------------*/
3655 /* B91C MSGFR - Multiply Single Long Fullword Register [RRE] */
3656 /*-------------------------------------------------------------------*/
DEF_INST(multiply_single_long_fullword_register)3657 DEF_INST(multiply_single_long_fullword_register)
3658 {
3659 int r1, r2; /* Values of R fields */
3660
3661 RRE0(inst, regs, r1, r2);
3662
3663 /* Multiply signed registers ignoring overflow */
3664 regs->GR_G(r1) = (S64)regs->GR_G(r1) * (S32)regs->GR_L(r2);
3665
3666 } /* end DEF_INST(multiply_single_long_fullword_register) */
3667 #endif /*defined(FEATURE_ESAME)*/
3668
3669
3670 #if defined(FEATURE_ESAME)
3671 /*-------------------------------------------------------------------*/
3672 /* B90C MSGR - Multiply Single Long Register [RRE] */
3673 /*-------------------------------------------------------------------*/
DEF_INST(multiply_single_long_register)3674 DEF_INST(multiply_single_long_register)
3675 {
3676 int r1, r2; /* Values of R fields */
3677
3678 RRE0(inst, regs, r1, r2);
3679
3680 /* Multiply signed registers ignoring overflow */
3681 regs->GR_G(r1) = (S64)regs->GR_G(r1) * (S64)regs->GR_G(r2);
3682
3683 } /* end DEF_INST(multiply_single_long_register) */
3684 #endif /*defined(FEATURE_ESAME)*/
3685
3686
3687 #if defined(FEATURE_ESAME)
3688 /*-------------------------------------------------------------------*/
3689 /* A7x9 LGHI - Load Long Halfword Immediate [RI] */
3690 /*-------------------------------------------------------------------*/
DEF_INST(load_long_halfword_immediate)3691 DEF_INST(load_long_halfword_immediate)
3692 {
3693 int r1; /* Register number */
3694 U16 i2; /* 16-bit operand values */
3695
3696 RI0(inst, regs, r1, i2);
3697
3698 /* Load operand into register */
3699 regs->GR_G(r1) = (S16)i2;
3700
3701 } /* end DEF_INST(load_long_halfword_immediate) */
3702 #endif /*defined(FEATURE_ESAME)*/
3703
3704
3705 #if defined(FEATURE_ESAME)
3706 /*-------------------------------------------------------------------*/
3707 /* A7xB AGHI - Add Long Halfword Immediate [RI] */
3708 /*-------------------------------------------------------------------*/
DEF_INST(add_long_halfword_immediate)3709 DEF_INST(add_long_halfword_immediate)
3710 {
3711 int r1; /* Register number */
3712 U16 i2; /* 16-bit immediate op */
3713
3714 RI(inst, regs, r1, i2);
3715
3716 /* Add signed operands and set condition code */
3717 regs->psw.cc = add_signed_long(&(regs->GR_G(r1)),
3718 regs->GR_G(r1),
3719 (S16)i2);
3720
3721 /* Program check if fixed-point overflow */
3722 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
3723 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
3724
3725 } /* end DEF_INST(add_long_halfword_immediate) */
3726 #endif /*defined(FEATURE_ESAME)*/
3727
3728
3729 #if defined(FEATURE_ESAME)
3730 /*-------------------------------------------------------------------*/
3731 /* A7xD MGHI - Multiply Long Halfword Immediate [RI] */
3732 /*-------------------------------------------------------------------*/
DEF_INST(multiply_long_halfword_immediate)3733 DEF_INST(multiply_long_halfword_immediate)
3734 {
3735 int r1; /* Register number */
3736 U16 i2; /* 16-bit operand */
3737
3738 RI0(inst, regs, r1, i2);
3739
3740 /* Multiply register by operand ignoring overflow */
3741 regs->GR_G(r1) = (S64)regs->GR_G(r1) * (S16)i2;
3742
3743 } /* end DEF_INST(multiply_long_halfword_immediate) */
3744 #endif /*defined(FEATURE_ESAME)*/
3745
3746
3747 #if defined(FEATURE_ESAME)
3748 /*-------------------------------------------------------------------*/
3749 /* A7xF CGHI - Compare Long Halfword Immediate [RI] */
3750 /*-------------------------------------------------------------------*/
DEF_INST(compare_long_halfword_immediate)3751 DEF_INST(compare_long_halfword_immediate)
3752 {
3753 int r1; /* Register number */
3754 U16 i2; /* 16-bit operand */
3755
3756 RI0(inst, regs, r1, i2);
3757
3758 /* Compare signed operands and set condition code */
3759 regs->psw.cc =
3760 (S64)regs->GR_G(r1) < (S16)i2 ? 1 :
3761 (S64)regs->GR_G(r1) > (S16)i2 ? 2 : 0;
3762
3763 } /* end DEF_INST(compare_long_halfword_immediate) */
3764 #endif /*defined(FEATURE_ESAME)*/
3765
3766
3767 #if defined(FEATURE_ESAME)
3768 /*-------------------------------------------------------------------*/
3769 /* B980 NGR - And Register Long [RRE] */
3770 /*-------------------------------------------------------------------*/
DEF_INST(and_long_register)3771 DEF_INST(and_long_register)
3772 {
3773 int r1, r2; /* Values of R fields */
3774
3775 RRE0(inst, regs, r1, r2);
3776
3777 /* AND second operand with first and set condition code */
3778 regs->psw.cc = ( regs->GR_G(r1) &= regs->GR_G(r2) ) ? 1 : 0;
3779
3780 } /* end DEF_INST(and_long_register) */
3781 #endif /*defined(FEATURE_ESAME)*/
3782
3783
3784 #if defined(FEATURE_ESAME)
3785 /*-------------------------------------------------------------------*/
3786 /* B981 OGR - Or Register Long [RRE] */
3787 /*-------------------------------------------------------------------*/
DEF_INST(or_long_register)3788 DEF_INST(or_long_register)
3789 {
3790 int r1, r2; /* Values of R fields */
3791
3792 RRE0(inst, regs, r1, r2);
3793
3794 /* OR second operand with first and set condition code */
3795 regs->psw.cc = ( regs->GR_G(r1) |= regs->GR_G(r2) ) ? 1 : 0;
3796
3797 } /* end DEF_INST(or_long_register) */
3798 #endif /*defined(FEATURE_ESAME)*/
3799
3800
3801 #if defined(FEATURE_ESAME)
3802 /*-------------------------------------------------------------------*/
3803 /* B982 XGR - Exclusive Or Register Long [RRE] */
3804 /*-------------------------------------------------------------------*/
DEF_INST(exclusive_or_long_register)3805 DEF_INST(exclusive_or_long_register)
3806 {
3807 int r1, r2; /* Values of R fields */
3808
3809 RRE0(inst, regs, r1, r2);
3810
3811 /* XOR second operand with first and set condition code */
3812 regs->psw.cc = ( regs->GR_G(r1) ^= regs->GR_G(r2) ) ? 1 : 0;
3813
3814 } /* end DEF_INST(exclusive_or_long_register) */
3815 #endif /*defined(FEATURE_ESAME)*/
3816
3817
3818 #if defined(FEATURE_ESAME)
3819 /*-------------------------------------------------------------------*/
3820 /* E380 NG - And Long [RXY] */
3821 /*-------------------------------------------------------------------*/
DEF_INST(and_long)3822 DEF_INST(and_long)
3823 {
3824 int r1; /* Value of R field */
3825 int b2; /* Base of effective addr */
3826 VADR effective_addr2; /* Effective address */
3827 U64 n; /* 64-bit operand values */
3828
3829 RXY(inst, regs, r1, b2, effective_addr2);
3830
3831 /* Load second operand from operand address */
3832 n = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
3833
3834 /* AND second operand with first and set condition code */
3835 regs->psw.cc = ( regs->GR_G(r1) &= n ) ? 1 : 0;
3836
3837 } /* end DEF_INST(and_long) */
3838 #endif /*defined(FEATURE_ESAME)*/
3839
3840
3841 #if defined(FEATURE_ESAME)
3842 /*-------------------------------------------------------------------*/
3843 /* E381 OG - Or Long [RXY] */
3844 /*-------------------------------------------------------------------*/
DEF_INST(or_long)3845 DEF_INST(or_long)
3846 {
3847 int r1; /* Value of R field */
3848 int b2; /* Base of effective addr */
3849 VADR effective_addr2; /* Effective address */
3850 U64 n; /* 64-bit operand values */
3851
3852 RXY(inst, regs, r1, b2, effective_addr2);
3853
3854 /* Load second operand from operand address */
3855 n = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
3856
3857 /* OR second operand with first and set condition code */
3858 regs->psw.cc = ( regs->GR_G(r1) |= n ) ? 1 : 0;
3859
3860 } /* end DEF_INST(or_long) */
3861 #endif /*defined(FEATURE_ESAME)*/
3862
3863
3864 #if defined(FEATURE_ESAME)
3865 /*-------------------------------------------------------------------*/
3866 /* E382 XG - Exclusive Or Long [RXY] */
3867 /*-------------------------------------------------------------------*/
DEF_INST(exclusive_or_long)3868 DEF_INST(exclusive_or_long)
3869 {
3870 int r1; /* Values of R fields */
3871 int b2; /* Base of effective addr */
3872 VADR effective_addr2; /* Effective address */
3873 U64 n; /* 64-bit operand values */
3874
3875 RXY(inst, regs, r1, b2, effective_addr2);
3876
3877 /* Load second operand from operand address */
3878 n = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
3879
3880 /* XOR second operand with first and set condition code */
3881 regs->psw.cc = ( regs->GR_G(r1) ^= n ) ? 1 : 0;
3882
3883 } /* end DEF_INST(exclusive_or_long) */
3884 #endif /*defined(FEATURE_ESAME)*/
3885
3886
3887 #if defined(FEATURE_ESAME)
3888 /*-------------------------------------------------------------------*/
3889 /* B904 LGR - Load Long Register [RRE] */
3890 /*-------------------------------------------------------------------*/
DEF_INST(load_long_register)3891 DEF_INST(load_long_register)
3892 {
3893 int r1, r2; /* Values of R fields */
3894
3895 RRE0(inst, regs, r1, r2);
3896
3897 /* Copy second operand to first operand */
3898 regs->GR_G(r1) = regs->GR_G(r2);
3899
3900 } /* end DEF_INST(load_long_register) */
3901 #endif /*defined(FEATURE_ESAME)*/
3902
3903
3904 #if defined(FEATURE_ESAME)
3905 /*-------------------------------------------------------------------*/
3906 /* B916 LLGFR - Load Logical Long Fullword Register [RRE] */
3907 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_long_fullword_register)3908 DEF_INST(load_logical_long_fullword_register)
3909 {
3910 int r1, r2; /* Values of R fields */
3911
3912 RRE0(inst, regs, r1, r2);
3913
3914 /* Copy second operand to first operand */
3915 regs->GR_G(r1) = regs->GR_L(r2);
3916
3917 } /* end DEF_INST(load_logical_long_fullword_register) */
3918 #endif /*defined(FEATURE_ESAME)*/
3919
3920
3921 #if defined(FEATURE_ESAME)
3922 /*-------------------------------------------------------------------*/
3923 /* B914 LGFR - Load Long Fullword Register [RRE] */
3924 /*-------------------------------------------------------------------*/
DEF_INST(load_long_fullword_register)3925 DEF_INST(load_long_fullword_register)
3926 {
3927 int r1, r2; /* Values of R fields */
3928
3929 RRE0(inst, regs, r1, r2);
3930
3931 /* Copy second operand to first operand */
3932 regs->GR_G(r1) = (S32)regs->GR_L(r2);
3933
3934 } /* end DEF_INST(load_long_fullword_register) */
3935 #endif /*defined(FEATURE_ESAME)*/
3936
3937
3938 #if defined(FEATURE_ESAME)
3939 /*-------------------------------------------------------------------*/
3940 /* B90A ALGR - Add Logical Register Long [RRE] */
3941 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_long_register)3942 DEF_INST(add_logical_long_register)
3943 {
3944 int r1, r2; /* Values of R fields */
3945
3946 RRE0(inst, regs, r1, r2);
3947
3948 /* Add unsigned operands and set condition code */
3949 regs->psw.cc = add_logical_long(&(regs->GR_G(r1)),
3950 regs->GR_G(r1),
3951 regs->GR_G(r2));
3952
3953 } /* end DEF_INST(add_logical_long_register) */
3954 #endif /*defined(FEATURE_ESAME)*/
3955
3956
3957 #if defined(FEATURE_ESAME)
3958 /*-------------------------------------------------------------------*/
3959 /* B91A ALGFR - Add Logical Long Fullword Register [RRE] */
3960 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_long_fullword_register)3961 DEF_INST(add_logical_long_fullword_register)
3962 {
3963 int r1, r2; /* Values of R fields */
3964
3965 RRE0(inst, regs, r1, r2);
3966
3967 /* Add unsigned operands and set condition code */
3968 regs->psw.cc = add_logical_long(&(regs->GR_G(r1)),
3969 regs->GR_G(r1),
3970 regs->GR_L(r2));
3971
3972 } /* end DEF_INST(add_logical_long_fullword_register) */
3973 #endif /*defined(FEATURE_ESAME)*/
3974
3975
3976 #if defined(FEATURE_ESAME)
3977 /*-------------------------------------------------------------------*/
3978 /* B91B SLGFR - Subtract Logical Long Fullword Register [RRE] */
3979 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_long_fullword_register)3980 DEF_INST(subtract_logical_long_fullword_register)
3981 {
3982 int r1, r2; /* Values of R fields */
3983
3984 RRE0(inst, regs, r1, r2);
3985
3986 /* Subtract unsigned operands and set condition code */
3987 regs->psw.cc = sub_logical_long(&(regs->GR_G(r1)),
3988 regs->GR_G(r1),
3989 regs->GR_L(r2));
3990
3991 } /* end DEF_INST(subtract_logical_long_fullword_register) */
3992 #endif /*defined(FEATURE_ESAME)*/
3993
3994
3995 #if defined(FEATURE_ESAME)
3996 /*-------------------------------------------------------------------*/
3997 /* B90B SLGR - Subtract Logical Register Long [RRE] */
3998 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_long_register)3999 DEF_INST(subtract_logical_long_register)
4000 {
4001 int r1, r2; /* Values of R fields */
4002
4003 RRE0(inst, regs, r1, r2);
4004
4005 /* Subtract unsigned operands and set condition code */
4006 regs->psw.cc = sub_logical_long(&(regs->GR_G(r1)),
4007 regs->GR_G(r1),
4008 regs->GR_G(r2));
4009
4010 } /* end DEF_INST(subtract_logical_long_register) */
4011 #endif /*defined(FEATURE_ESAME)*/
4012
4013
4014 #if defined(FEATURE_ESAME)
4015 /*-------------------------------------------------------------------*/
4016 /* EF LMD - Load Multiple Disjoint [SS] */
4017 /*-------------------------------------------------------------------*/
DEF_INST(load_multiple_disjoint)4018 DEF_INST(load_multiple_disjoint)
4019 {
4020 int r1, r3; /* Register numbers */
4021 int b2, b4; /* Base register numbers */
4022 VADR effective_addr2; /* Operand2 address */
4023 VADR effective_addr4; /* Operand4 address */
4024 int i, n; /* Integer work areas */
4025 U32 rwork1[16], rwork2[16]; /* Intermediate work areas */
4026
4027 SS(inst, regs, r1, r3, b2, effective_addr2, b4, effective_addr4);
4028
4029 n = ((r3 - r1) & 0xF) + 1;
4030
4031 ARCH_DEP(vfetchc) (rwork1, (n * 4) - 1, effective_addr2, b2, regs);
4032 ARCH_DEP(vfetchc) (rwork2, (n * 4) - 1, effective_addr4, b4, regs);
4033
4034 /* Load a register at a time */
4035 for (i = 0; i < n; i++)
4036 {
4037 regs->GR_H((r1 + i) & 0xF) = fetch_fw(&rwork1[i]);
4038 regs->GR_L((r1 + i) & 0xF) = fetch_fw(&rwork2[i]);
4039 }
4040
4041 } /* end DEF_INST(load_multiple_disjoint) */
4042 #endif /*defined(FEATURE_ESAME)*/
4043
4044
4045 #if defined(FEATURE_ESAME)
4046 /*-------------------------------------------------------------------*/
4047 /* EB96 LMH - Load Multiple High [RSY] */
4048 /*-------------------------------------------------------------------*/
DEF_INST(load_multiple_high)4049 DEF_INST(load_multiple_high)
4050 {
4051 int r1, r3; /* Register numbers */
4052 int b2; /* effective address base */
4053 VADR effective_addr2; /* effective address */
4054 int i, m, n; /* Integer work areas */
4055 U32 *p1, *p2; /* Mainstor pointers */
4056
4057 RSY(inst, regs, r1, r3, b2, effective_addr2);
4058
4059 /* Calculate number of bytes to load */
4060 n = (((r3 - r1) & 0xF) + 1) << 2;
4061
4062 /* Calculate number of bytes to next boundary */
4063 m = 0x800 - ((VADR_L)effective_addr2 & 0x7ff);
4064
4065 /* Address of operand beginning */
4066 p1 = (U32*)MADDR(effective_addr2, b2, regs, ACCTYPE_READ, regs->psw.pkey);
4067
4068 if (likely(n <= m))
4069 {
4070 /* Boundary not crossed */
4071 n >>= 2;
4072 for (i = 0; i < n; i++, p1++)
4073 regs->GR_H((r1 + i) & 0xF) = fetch_fw (p1);
4074 }
4075 else
4076 {
4077 /* Boundary crossed, get 2nd page address */
4078 effective_addr2 += m;
4079 effective_addr2 &= ADDRESS_MAXWRAP(regs);
4080 p2 = (U32*)MADDR(effective_addr2, b2, regs, ACCTYPE_READ, regs->psw.pkey);
4081
4082 if (likely((m & 0x3) == 0))
4083 {
4084 /* Addresses are word aligned */
4085 m >>= 2;
4086 for (i = 0; i < m; i++, p1++)
4087 regs->GR_H((r1 + i) & 0xF) = fetch_fw (p1);
4088 n >>= 2;
4089 for ( ; i < n; i++, p2++)
4090 regs->GR_H((r1 + i) & 0xF) = fetch_fw (p2);
4091 }
4092 else
4093 {
4094 /* Worst case */
4095 U32 rwork[16];
4096 BYTE *b1, *b2;
4097
4098 b1 = (BYTE *)&rwork[0];
4099 b2 = (BYTE *)p1;
4100 for (i = 0; i < m; i++)
4101 *b1++ = *b2++;
4102 b2 = (BYTE *)p2;
4103 for ( ; i < n; i++)
4104 *b1++ = *b2++;
4105
4106 n >>= 2;
4107 for (i = 0; i < n; i++)
4108 regs->GR_H((r1 + i) & 0xF) = CSWAP32(rwork[i]);
4109 }
4110 }
4111
4112 } /* end DEF_INST(load_multiple_high) */
4113 #endif /*defined(FEATURE_ESAME)*/
4114
4115
4116 #if defined(FEATURE_ESAME)
4117 /*-------------------------------------------------------------------*/
4118 /* EB04 LMG - Load Multiple Long [RSY] */
4119 /*-------------------------------------------------------------------*/
DEF_INST(load_multiple_long)4120 DEF_INST(load_multiple_long)
4121 {
4122 int r1, r3; /* Register numbers */
4123 int b2; /* Base of effective addr */
4124 VADR effective_addr2; /* Effective address */
4125 int i, m, n; /* Integer work areas */
4126 U64 *p1, *p2; /* Mainstor pointers */
4127 BYTE *bp1; /* Unaligned Mainstor ptr */
4128
4129 RSY(inst, regs, r1, r3, b2, effective_addr2);
4130
4131 /* Calculate number of bytes to load */
4132 n = (((r3 - r1) & 0xF) + 1) << 3;
4133
4134 /* Calculate number of bytes to next boundary */
4135 m = 0x800 - ((VADR_L)effective_addr2 & 0x7ff);
4136
4137 /* Address of operand beginning */
4138 bp1 = (BYTE*)MADDR(effective_addr2, b2, regs, ACCTYPE_READ, regs->psw.pkey);
4139 p1=(U64*)bp1;
4140
4141 if (likely(n <= m))
4142 {
4143 /* Boundary not crossed */
4144 n >>= 3;
4145 #if defined(OPTION_STRICT_ALIGNMENT)
4146 if(likely(!(((uintptr_t)effective_addr2)&0x07)))
4147 {
4148 #endif
4149 #if defined(OPTION_SINGLE_CPU_DW) && defined(ASSIST_STORE_DW)
4150 if (regs->cpubit == regs->sysblk->started_mask)
4151 for (i = 0; i < n; i++, p1++)
4152 regs->GR_G((r1 + i) & 0xF) = CSWAP64(*p1);
4153 else
4154 #endif
4155 for (i = 0; i < n; i++, p1++)
4156 regs->GR_G((r1 + i) & 0xF) = fetch_dw (p1);
4157 #if defined(OPTION_STRICT_ALIGNMENT)
4158 }
4159 else
4160 {
4161 for (i = 0; i < n; i++, bp1+=8)
4162 regs->GR_G((r1 + i) & 0xF) = fetch_dw (bp1);
4163 }
4164 #endif
4165 }
4166 else
4167 {
4168 /* Boundary crossed, get 2nd page address */
4169 effective_addr2 += m;
4170 effective_addr2 &= ADDRESS_MAXWRAP(regs);
4171 p2 = (U64*)MADDR(effective_addr2, b2, regs, ACCTYPE_READ, regs->psw.pkey);
4172
4173 if (likely((m & 0x7) == 0))
4174 {
4175 /* FIXME: This code blows up on at least Mac OS X Snow Leopard
4176 (10.6) when compiled for a 32-bit Intel host using gcc 4.2.1
4177 unless the PTT call below is present. The problem appears to
4178 be in the gcc 4.2.1 optimizer, as the code works when
4179 compiled with -O0. DO NOT REMOVE this until it's been found
4180 and fixed. -- JRM, 11 Feb 2010 */
4181 // PTT(PTT_CL_INF,"LMG2KIN",p2,0,0);
4182 /* Addresses are double-word aligned */
4183 m >>= 3;
4184 for (i = 0; i < m; i++, p1++)
4185 regs->GR_G((r1 + i) & 0xF) = fetch_dw (p1);
4186 n >>= 3;
4187 for ( ; i < n; i++, p2++)
4188 regs->GR_G((r1 + i) & 0xF) = fetch_dw (p2);
4189 }
4190 else
4191 {
4192 /* Worst case */
4193 U64 rwork[16];
4194 BYTE *b1, *b2;
4195
4196 b1 = (BYTE *)&rwork[0];
4197 b2 = (BYTE *)p1;
4198 for (i = 0; i < m; i++)
4199 *b1++ = *b2++;
4200 b2 = (BYTE *)p2;
4201 for ( ; i < n; i++)
4202 *b1++ = *b2++;
4203
4204 n >>= 3;
4205 for (i = 0; i < n; i++)
4206 regs->GR_G((r1 + i) & 0xF) = CSWAP64(rwork[i]);
4207 }
4208 }
4209
4210 } /* end DEF_INST(load_multiple_long) */
4211 #endif /*defined(FEATURE_ESAME)*/
4212
4213
4214 #if defined(FEATURE_ESAME)
4215 /*-------------------------------------------------------------------*/
4216 /* EB25 STCTG - Store Control Long [RSY] */
4217 /*-------------------------------------------------------------------*/
DEF_INST(store_control_long)4218 DEF_INST(store_control_long)
4219 {
4220 int r1, r3; /* Register numbers */
4221 int b2; /* Base of effective addr */
4222 VADR effective_addr2; /* Effective address */
4223 int i, m, n; /* Integer work areas */
4224 U64 *p1, *p2 = NULL; /* Mainstor pointers */
4225
4226 RSY(inst, regs, r1, r3, b2, effective_addr2);
4227
4228 PRIV_CHECK(regs);
4229
4230 DW_CHECK(effective_addr2, regs);
4231
4232 #if defined(_FEATURE_ZSIE)
4233 if(SIE_STATB(regs, IC1, STCTL))
4234 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
4235 #endif /*defined(_FEATURE_ZSIE)*/
4236
4237 /* Calculate number of regs to store */
4238 n = ((r3 - r1) & 0xF) + 1;
4239
4240 /* Calculate number of double words to next boundary */
4241 m = (0x800 - (effective_addr2 & 0x7ff)) >> 3;
4242
4243 /* Address of operand beginning */
4244 p1 = (U64*)MADDR(effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
4245
4246 /* Get address of next page if boundary crossed */
4247 if (unlikely (m < n))
4248 p2 = (U64*)MADDR(effective_addr2 + (m*8), b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
4249 else
4250 m = n;
4251
4252 /* Store to first page */
4253 for (i = 0; i < m; i++)
4254 store_dw(p1++, regs->CR_G((r1 + i) & 0xF));
4255
4256 /* Store to next page */
4257 for ( ; i < n; i++)
4258 store_dw(p2++, regs->CR_G((r1 + i) & 0xF));
4259
4260 } /* end DEF_INST(store_control_long) */
4261 #endif /*defined(FEATURE_ESAME)*/
4262
4263
4264 #if defined(FEATURE_ESAME)
4265 /*-------------------------------------------------------------------*/
4266 /* EB2F LCTLG - Load Control Long [RSY] */
4267 /*-------------------------------------------------------------------*/
DEF_INST(load_control_long)4268 DEF_INST(load_control_long)
4269 {
4270 int r1, r3; /* Register numbers */
4271 int b2; /* Base of effective addr */
4272 VADR effective_addr2; /* Effective address */
4273 int i, m, n; /* Integer work areas */
4274 U64 *p1, *p2 = NULL; /* Mainstor pointers */
4275 U16 updated = 0; /* Updated control regs */
4276
4277 RSY(inst, regs, r1, r3, b2, effective_addr2);
4278
4279 PRIV_CHECK(regs);
4280
4281 DW_CHECK(effective_addr2, regs);
4282
4283 /* Calculate number of regs to load */
4284 n = ((r3 - r1) & 0xF) + 1;
4285
4286 #if defined(_FEATURE_ZSIE)
4287 if ( SIE_MODE(regs) )
4288 {
4289 U16 cr_mask = fetch_hw (regs->siebk->lctl_ctl);
4290 for (i = 0; i < n; i++)
4291 if (cr_mask & BIT(15 - ((r1 + i) & 0xF)))
4292 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
4293 }
4294 #endif
4295
4296 /* Calculate number of double words to next boundary */
4297 m = (0x800 - (effective_addr2 & 0x7ff)) >> 3;
4298
4299 /* Address of operand beginning */
4300 p1 = (U64*)MADDR(effective_addr2, b2, regs, ACCTYPE_READ, regs->psw.pkey);
4301
4302 /* Get address of next page if boundary crossed */
4303 if (unlikely (m < n))
4304 p2 = (U64*)MADDR(effective_addr2 + (m*8), b2, regs, ACCTYPE_READ, regs->psw.pkey);
4305 else
4306 m = n;
4307
4308 /* Load from first page */
4309 for (i = 0; i < m; i++, p1++)
4310 {
4311 regs->CR_G((r1 + i) & 0xF) = fetch_dw(p1);
4312 updated |= BIT((r1 + i) & 0xF);
4313 }
4314
4315 /* Load from next page */
4316 for ( ; i < n; i++, p2++)
4317 {
4318 regs->CR_G((r1 + i) & 0xF) = fetch_dw(p2);
4319 updated |= BIT((r1 + i) & 0xF);
4320 }
4321
4322 /* Actions based on updated control regs */
4323 SET_IC_MASK(regs);
4324 if (updated & (BIT(1) | BIT(7) | BIT(13)))
4325 SET_AEA_COMMON(regs);
4326 if (updated & BIT(regs->aea_ar[USE_INST_SPACE]))
4327 INVALIDATE_AIA(regs);
4328 if (updated & BIT(9))
4329 {
4330 OBTAIN_INTLOCK(regs);
4331 SET_IC_PER(regs);
4332 RELEASE_INTLOCK(regs);
4333 if (EN_IC_PER_SA(regs))
4334 ARCH_DEP(invalidate_tlb)(regs,~(ACC_WRITE|ACC_CHECK));
4335 }
4336
4337 RETURN_INTCHECK(regs);
4338
4339 } /* end DEF_INST(load_control_long) */
4340 #endif /*defined(FEATURE_ESAME)*/
4341
4342
4343 #if defined(FEATURE_ESAME)
4344 /*-------------------------------------------------------------------*/
4345 /* EB24 STMG - Store Multiple Long [RSY] */
4346 /*-------------------------------------------------------------------*/
DEF_INST(store_multiple_long)4347 DEF_INST(store_multiple_long)
4348 {
4349 int r1, r3; /* Register numbers */
4350 int b2; /* Base of effective addr */
4351 VADR effective_addr2; /* Effective address */
4352 int i, m, n; /* Integer work areas */
4353 U64 *p1, *p2; /* Mainstor pointers */
4354 BYTE *bp1; /* Unaligned Mainstor ptr */
4355
4356 RSY(inst, regs, r1, r3, b2, effective_addr2);
4357
4358 /* Calculate number of bytes to store */
4359 n = (((r3 - r1) & 0xF) + 1) << 3;
4360
4361 /* Calculate number of bytes to next boundary */
4362 m = 0x800 - ((VADR_L)effective_addr2 & 0x7ff);
4363
4364 /* Get address of first page */
4365 bp1 = (BYTE*)MADDR(effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
4366 p1=(U64*)bp1;
4367
4368 if (likely(n <= m))
4369 {
4370 /* Boundary not crossed */
4371 n >>= 3;
4372 #if defined(OPTION_STRICT_ALIGNMENT)
4373 if(likely(!(((uintptr_t)effective_addr2)&0x07)))
4374 {
4375 #endif
4376 #if defined(OPTION_SINGLE_CPU_DW) && defined(ASSIST_STORE_DW)
4377 if (regs->cpubit == regs->sysblk->started_mask)
4378 for (i = 0; i < n; i++)
4379 *p1++ = CSWAP64(regs->GR_G((r1 + i) & 0xF));
4380 else
4381 #endif
4382 for (i = 0; i < n; i++)
4383 store_dw (p1++, regs->GR_G((r1 + i) & 0xF));
4384 #if defined(OPTION_STRICT_ALIGNMENT)
4385 }
4386 else
4387 {
4388 for (i = 0; i < n; i++,bp1+=8)
4389 store_dw (bp1, regs->GR_G((r1 + i) & 0xF));
4390 }
4391 #endif
4392 }
4393 if (likely(n <= m))
4394 {
4395 /* boundary not crossed */
4396 n >>= 3;
4397 }
4398 else
4399 {
4400 /* boundary crossed, get address of the 2nd page */
4401 effective_addr2 += m;
4402 effective_addr2 &= ADDRESS_MAXWRAP(regs);
4403 p2 = (U64*)MADDR(effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
4404
4405 if (likely((m & 0x7) == 0))
4406 {
4407 /* double word aligned */
4408 m >>= 3;
4409 for (i = 0; i < m; i++)
4410 store_dw (p1++, regs->GR_G((r1 + i) & 0xF));
4411 n >>= 3;
4412 for ( ; i < n; i++)
4413 store_dw (p2++, regs->GR_G((r1 + i) & 0xF));
4414 }
4415 else
4416 {
4417 /* worst case */
4418 U64 rwork[16];
4419 BYTE *b1, *b2;
4420
4421 for (i = 0; i < (n >> 3); i++)
4422 rwork[i] = CSWAP64(regs->GR_G((r1 + i) & 0xF));
4423 b1 = (BYTE *)&rwork[0];
4424
4425 b2 = (BYTE *)p1;
4426 for (i = 0; i < m; i++)
4427 *b2++ = *b1++;
4428
4429 b2 = (BYTE *)p2;
4430 for ( ; i < n; i++)
4431 *b2++ = *b1++;
4432 }
4433 }
4434
4435 } /* end DEF_INST(store_multiple_long) */
4436 #endif /*defined(FEATURE_ESAME)*/
4437
4438
4439 #if defined(FEATURE_ESAME)
4440 /*-------------------------------------------------------------------*/
4441 /* EB26 STMH - Store Multiple High [RSY] */
4442 /*-------------------------------------------------------------------*/
DEF_INST(store_multiple_high)4443 DEF_INST(store_multiple_high)
4444 {
4445 int r1, r3; /* Register numbers */
4446 int b2; /* effective address base */
4447 VADR effective_addr2; /* effective address */
4448 int i, m, n; /* Integer work areas */
4449 U32 *p1, *p2; /* Mainstor pointers */
4450
4451 RSY(inst, regs, r1, r3, b2, effective_addr2);
4452
4453 /* Calculate number of bytes to store */
4454 n = (((r3 - r1) & 0xF) + 1) << 2;
4455
4456 /* Calculate number of bytes to next boundary */
4457 m = 0x800 - ((VADR_L)effective_addr2 & 0x7ff);
4458
4459 /* Get address of first page */
4460 p1 = (U32*)MADDR(effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
4461
4462 if (likely(n <= m))
4463 {
4464 /* boundary not crossed */
4465 n >>= 2;
4466 for (i = 0; i < n; i++)
4467 store_fw (p1++, regs->GR_H((r1 + i) & 0xF));
4468 }
4469 else
4470 {
4471 /* boundary crossed, get address of the 2nd page */
4472 effective_addr2 += m;
4473 effective_addr2 &= ADDRESS_MAXWRAP(regs);
4474 p2 = (U32*)MADDR(effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
4475
4476 if (likely((m & 0x3) == 0))
4477 {
4478 /* word aligned */
4479 m >>= 2;
4480 for (i = 0; i < m; i++)
4481 store_fw (p1++, regs->GR_H((r1 + i) & 0xF));
4482 n >>= 2;
4483 for ( ; i < n; i++)
4484 store_fw (p2++, regs->GR_H((r1 + i) & 0xF));
4485 }
4486 else
4487 {
4488 /* worst case */
4489 U32 rwork[16];
4490 BYTE *b1, *b2;
4491
4492 for (i = 0; i < (n >> 2); i++)
4493 rwork[i] = CSWAP32(regs->GR_H((r1 + i) & 0xF));
4494 b1 = (BYTE *)&rwork[0];
4495
4496 b2 = (BYTE *)p1;
4497 for (i = 0; i < m; i++)
4498 *b2++ = *b1++;
4499
4500 b2 = (BYTE *)p2;
4501 for ( ; i < n; i++)
4502 *b2++ = *b1++;
4503 }
4504 }
4505
4506 } /* end DEF_INST(store_multiple_high) */
4507 #endif /*defined(FEATURE_ESAME)*/
4508
4509
4510 #if defined(FEATURE_ESAME)
4511 /*-------------------------------------------------------------------*/
4512 /* B905 LURAG - Load Using Real Address Long [RRE] */
4513 /*-------------------------------------------------------------------*/
DEF_INST(load_using_real_address_long)4514 DEF_INST(load_using_real_address_long)
4515 {
4516 int r1, r2; /* Values of R fields */
4517 RADR n; /* Unsigned work */
4518
4519 RRE(inst, regs, r1, r2);
4520
4521 PRIV_CHECK(regs);
4522
4523 /* R2 register contains operand real storage address */
4524 n = regs->GR_G(r2) & ADDRESS_MAXWRAP(regs);
4525
4526 /* Program check if operand not on doubleword boundary */
4527 DW_CHECK(n, regs);
4528
4529 /* Load R1 register from second operand */
4530 regs->GR_G(r1) = ARCH_DEP(vfetch8) ( n, USE_REAL_ADDR, regs );
4531
4532 } /* end DEF_INST(load_using_real_address_long) */
4533 #endif /*defined(FEATURE_ESAME)*/
4534
4535
4536 #if defined(FEATURE_ESAME)
4537 /*-------------------------------------------------------------------*/
4538 /* B925 STURG - Store Using Real Address Long [RRE] */
4539 /*-------------------------------------------------------------------*/
DEF_INST(store_using_real_address_long)4540 DEF_INST(store_using_real_address_long)
4541 {
4542 int r1, r2; /* Values of R fields */
4543 RADR n; /* Unsigned work */
4544
4545 RRE(inst, regs, r1, r2);
4546
4547 PRIV_CHECK(regs);
4548
4549 /* R2 register contains operand real storage address */
4550 n = regs->GR_G(r2) & ADDRESS_MAXWRAP(regs);
4551
4552 /* Program check if operand not on doubleword boundary */
4553 DW_CHECK(n, regs);
4554
4555 /* Store R1 register at second operand location */
4556 ARCH_DEP(vstore8) (regs->GR_G(r1), n, USE_REAL_ADDR, regs );
4557
4558 #if defined(FEATURE_PER2)
4559 /* Storage alteration must be enabled for STURA to be recognised */
4560 if( EN_IC_PER_SA(regs) && EN_IC_PER_STURA(regs) )
4561 {
4562 ON_IC_PER_SA(regs) ;
4563 ON_IC_PER_STURA(regs) ;
4564 }
4565 #endif /*defined(FEATURE_PER2)*/
4566
4567 } /* end DEF_INST(store_using_real_address_long) */
4568 #endif /*defined(FEATURE_ESAME)*/
4569
4570
4571 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
4572 /*-------------------------------------------------------------------*/
4573 /* 010B TAM - Test Addressing Mode [E] */
4574 /*-------------------------------------------------------------------*/
DEF_INST(test_addressing_mode)4575 DEF_INST(test_addressing_mode)
4576 {
4577 E(inst, regs);
4578
4579 regs->psw.cc =
4580 #if defined(FEATURE_ESAME)
4581 (regs->psw.amode64 << 1) |
4582 #endif /*defined(FEATURE_ESAME)*/
4583 regs->psw.amode;
4584
4585 } /* end DEF_INST(test_addressing_mode) */
4586 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
4587
4588
4589 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
4590 /*-------------------------------------------------------------------*/
4591 /* 010C SAM24 - Set Addressing Mode 24 [E] */
4592 /*-------------------------------------------------------------------*/
DEF_INST(set_addressing_mode_24)4593 DEF_INST(set_addressing_mode_24)
4594 {
4595 VADR ia = PSW_IA(regs, 0); /* Unupdated instruction addr*/
4596
4597 E(inst, regs);
4598
4599 /* Set the bear register */
4600 SET_BEAR_REG(regs, regs->bear_ip);
4601
4602 /* Program check if instruction is located above 16MB */
4603 if (ia > 0xFFFFFFULL)
4604 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
4605
4606 #if defined(FEATURE_ESAME)
4607 /* Add a mode trace entry when switching in/out of 64 bit mode */
4608 if((regs->CR(12) & CR12_MTRACE) && regs->psw.amode64)
4609 regs->CR(12) = ARCH_DEP(trace_ms) (0, 0, regs);
4610 #endif /*defined(FEATURE_ESAME)*/
4611
4612 #if defined(FEATURE_ESAME)
4613 regs->psw.amode64 =
4614 #endif /*defined(FEATURE_ESAME)*/
4615 regs->psw.amode = 0;
4616 regs->psw.AMASK = AMASK24;
4617
4618 } /* end DEF_INST(set_addressing_mode_24) */
4619 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
4620
4621
4622 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
4623 /*-------------------------------------------------------------------*/
4624 /* 010D SAM31 - Set Addressing Mode 31 [E] */
4625 /*-------------------------------------------------------------------*/
DEF_INST(set_addressing_mode_31)4626 DEF_INST(set_addressing_mode_31)
4627 {
4628 VADR ia = PSW_IA(regs, 0); /* Unupdated instruction addr*/
4629
4630 E(inst, regs);
4631
4632 /* Set the bear register */
4633 SET_BEAR_REG(regs, regs->bear_ip);
4634
4635 /* Program check if instruction is located above 2GB */
4636 if (ia > 0x7FFFFFFFULL)
4637 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
4638
4639 #if defined(FEATURE_ESAME)
4640 /* Add a mode trace entry when switching in/out of 64 bit mode */
4641 if((regs->CR(12) & CR12_MTRACE) && regs->psw.amode64)
4642 regs->CR(12) = ARCH_DEP(trace_ms) (0, 0, regs);
4643 #endif /*defined(FEATURE_ESAME)*/
4644
4645 #if defined(FEATURE_ESAME)
4646 regs->psw.amode64 = 0;
4647 #endif /*defined(FEATURE_ESAME)*/
4648 regs->psw.amode = 1;
4649 regs->psw.AMASK = AMASK31;
4650
4651 } /* end DEF_INST(set_addressing_mode_31) */
4652 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
4653
4654
4655 #if defined(FEATURE_ESAME)
4656 /*-------------------------------------------------------------------*/
4657 /* 010E SAM64 - Set Addressing Mode 64 [E] */
4658 /*-------------------------------------------------------------------*/
DEF_INST(set_addressing_mode_64)4659 DEF_INST(set_addressing_mode_64)
4660 {
4661 E(inst, regs);
4662
4663 /* Set the bear register */
4664 SET_BEAR_REG(regs, regs->bear_ip);
4665
4666 #if defined(FEATURE_ESAME)
4667 /* Add a mode trace entry when switching in/out of 64 bit mode */
4668 if((regs->CR(12) & CR12_MTRACE) && !regs->psw.amode64)
4669 regs->CR(12) = ARCH_DEP(trace_ms) (0, 0, regs);
4670 #endif /*defined(FEATURE_ESAME)*/
4671
4672 regs->psw.amode = regs->psw.amode64 = 1;
4673 regs->psw.AMASK = AMASK64;
4674
4675 } /* end DEF_INST(set_addressing_mode_64) */
4676 #endif /*defined(FEATURE_ESAME)*/
4677
4678
4679 #if defined(FEATURE_ESAME)
4680 /*-------------------------------------------------------------------*/
4681 /* E324 STG - Store Long [RXY] */
4682 /*-------------------------------------------------------------------*/
DEF_INST(store_long)4683 DEF_INST(store_long)
4684 {
4685 int r1; /* Values of R fields */
4686 int b2; /* Base of effective addr */
4687 VADR effective_addr2; /* Effective address */
4688
4689 RXY(inst, regs, r1, b2, effective_addr2);
4690
4691 /* Store register contents at operand address */
4692 ARCH_DEP(vstore8) ( regs->GR_G(r1), effective_addr2, b2, regs );
4693
4694 } /* end DEF_INST(store_long) */
4695 #endif /*defined(FEATURE_ESAME)*/
4696
4697
4698 #if defined(FEATURE_ESAME)
4699 /*-------------------------------------------------------------------*/
4700 /* E502 STRAG - Store Real Address [SSE] */
4701 /*-------------------------------------------------------------------*/
DEF_INST(store_real_address)4702 DEF_INST(store_real_address)
4703 {
4704 int b1, b2; /* Values of base registers */
4705 VADR effective_addr1,
4706 effective_addr2; /* Effective addresses */
4707
4708 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
4709
4710 PRIV_CHECK(regs);
4711
4712 DW_CHECK(effective_addr1, regs);
4713
4714 /* Translate virtual address to real address */
4715 if (ARCH_DEP(translate_addr) (effective_addr2, b2, regs, ACCTYPE_STRAG))
4716 regs->program_interrupt (regs, regs->dat.xcode);
4717
4718 /* Store register contents at operand address */
4719 ARCH_DEP(vstore8) (regs->dat.raddr, effective_addr1, b1, regs );
4720
4721 } /* end DEF_INST(store_real_address) */
4722 #endif /*defined(FEATURE_ESAME)*/
4723
4724
4725 #if defined(FEATURE_ESAME)
4726 /*-------------------------------------------------------------------*/
4727 /* E304 LG - Load Long [RXY] */
4728 /*-------------------------------------------------------------------*/
DEF_INST(load_long)4729 DEF_INST(load_long)
4730 {
4731 int r1; /* Value of R field */
4732 int b2; /* Base of effective addr */
4733 VADR effective_addr2; /* Effective address */
4734
4735 RXY(inst, regs, r1, b2, effective_addr2);
4736
4737 /* Load R1 register from second operand */
4738 regs->GR_G(r1) = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
4739
4740 } /* end DEF_INST(load_long) */
4741 #endif /*defined(FEATURE_ESAME)*/
4742
4743
4744 #if defined(FEATURE_ESAME)
4745 /*-------------------------------------------------------------------*/
4746 /* E314 LGF - Load Long Fullword [RXY] */
4747 /*-------------------------------------------------------------------*/
DEF_INST(load_long_fullword)4748 DEF_INST(load_long_fullword)
4749 {
4750 int r1; /* Value of R field */
4751 int b2; /* Base of effective addr */
4752 VADR effective_addr2; /* Effective address */
4753
4754 RXY(inst, regs, r1, b2, effective_addr2);
4755
4756 /* Load R1 register from second operand */
4757 regs->GR_G(r1) = (S32)ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
4758
4759 } /* end DEF_INST(load_long_fullword) */
4760 #endif /*defined(FEATURE_ESAME)*/
4761
4762
4763 #if defined(FEATURE_ESAME)
4764 /*-------------------------------------------------------------------*/
4765 /* E315 LGH - Load Long Halfword [RXY] */
4766 /*-------------------------------------------------------------------*/
DEF_INST(load_long_halfword)4767 DEF_INST(load_long_halfword)
4768 {
4769 int r1; /* Value of R field */
4770 int b2; /* Base of effective addr */
4771 VADR effective_addr2; /* Effective address */
4772
4773 RXY(inst, regs, r1, b2, effective_addr2);
4774
4775 /* Load R1 register from second operand */
4776 regs->GR_G(r1) = (S16)ARCH_DEP(vfetch2) ( effective_addr2, b2, regs );
4777
4778 } /* end DEF_INST(load_long_halfword) */
4779 #endif /*defined(FEATURE_ESAME)*/
4780
4781
4782 #if defined(FEATURE_ESAME)
4783 /*-------------------------------------------------------------------*/
4784 /* E316 LLGF - Load Logical Long Fullword [RXY] */
4785 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_long_fullword)4786 DEF_INST(load_logical_long_fullword)
4787 {
4788 int r1; /* Value of R field */
4789 int b2; /* Base of effective addr */
4790 VADR effective_addr2; /* Effective address */
4791
4792 RXY(inst, regs, r1, b2, effective_addr2);
4793
4794 /* Load R1 register from second operand */
4795 regs->GR_G(r1) = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
4796
4797 } /* end DEF_INST(load_logical_long_fullword) */
4798 #endif /*defined(FEATURE_ESAME)*/
4799
4800
4801 #if defined(FEATURE_ESAME)
4802 /*-------------------------------------------------------------------*/
4803 /* E317 LLGT - Load Logical Long Thirtyone [RXY] */
4804 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_long_thirtyone)4805 DEF_INST(load_logical_long_thirtyone)
4806 {
4807 int r1; /* Value of R field */
4808 int b2; /* Base of effective addr */
4809 VADR effective_addr2; /* Effective address */
4810
4811 RXY(inst, regs, r1, b2, effective_addr2);
4812
4813 /* Load R1 register from second operand */
4814 regs->GR_G(r1) = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs )
4815 & 0x7FFFFFFF;
4816
4817 } /* end DEF_INST(load_logical_long_thirtyone) */
4818 #endif /*defined(FEATURE_ESAME)*/
4819
4820
4821 #if defined(FEATURE_ESAME)
4822 /*-------------------------------------------------------------------*/
4823 /* B2B2 LPSWE - Load PSW Extended [S] */
4824 /*-------------------------------------------------------------------*/
DEF_INST(load_program_status_word_extended)4825 DEF_INST(load_program_status_word_extended)
4826 {
4827 int b2; /* Base of effective addr */
4828 U64 effective_addr2; /* Effective address */
4829 QWORD qword;
4830 int rc;
4831
4832 S(inst, regs, b2, effective_addr2);
4833
4834 PRIV_CHECK(regs);
4835
4836 DW_CHECK(effective_addr2, regs);
4837
4838 #if defined(_FEATURE_ZSIE)
4839 if(SIE_STATB(regs, IC1, LPSW))
4840 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
4841 #endif /*defined(_FEATURE_ZSIE)*/
4842
4843 /* Perform serialization and checkpoint synchronization */
4844 PERFORM_SERIALIZATION (regs);
4845 PERFORM_CHKPT_SYNC (regs);
4846
4847 /* Fetch new PSW from operand address */
4848 ARCH_DEP(vfetchc) ( qword, 16-1, effective_addr2, b2, regs );
4849
4850 /* Set the breaking event address register */
4851 SET_BEAR_REG(regs, regs->ip - 4);
4852
4853 /* Load updated PSW */
4854 if ( ( rc = ARCH_DEP(load_psw) ( regs, qword ) ) )
4855 regs->program_interrupt (regs, rc);
4856
4857 /* Perform serialization and checkpoint synchronization */
4858 PERFORM_SERIALIZATION (regs);
4859 PERFORM_CHKPT_SYNC (regs);
4860
4861 RETURN_INTCHECK(regs);
4862
4863 } /* end DEF_INST(load_program_status_word_extended) */
4864 #endif /*defined(FEATURE_ESAME)*/
4865
4866
4867 #if defined(FEATURE_ESAME)
4868 /*-------------------------------------------------------------------*/
4869 /* E303 LRAG - Load Real Address Long [RXY] */
4870 /*-------------------------------------------------------------------*/
DEF_INST(load_real_address_long)4871 DEF_INST(load_real_address_long)
4872 {
4873 int r1; /* Register number */
4874 int b2; /* Base of effective addr */
4875 VADR effective_addr2; /* Effective address */
4876 int cc; /* Condition code */
4877
4878 RXY(inst, regs, r1, b2, effective_addr2);
4879
4880 SIE_XC_INTERCEPT(regs);
4881
4882 PRIV_CHECK(regs);
4883
4884 /* Translate the effective address to a real address */
4885 cc = ARCH_DEP(translate_addr) (effective_addr2, b2, regs, ACCTYPE_LRA);
4886
4887 /* If ALET exception or ASCE-type or region translation
4888 exception, or if the segment table entry is outside the
4889 table and the entry address exceeds 2GB, set exception
4890 code in R1 bits 48-63, set bit 32 of R1, and set cc 3 */
4891 if (cc > 3
4892 || (cc == 3 && regs->dat.raddr > 0x7FFFFFFF))
4893 {
4894 regs->GR_L(r1) = 0x80000000 | regs->dat.xcode;
4895 cc = 3;
4896 }
4897 else if (cc == 3) /* && regs->dat.raddr <= 0x7FFFFFFF */
4898 {
4899 /* If segment table entry is outside table and entry
4900 address does not exceed 2GB, return bits 32-63 of
4901 the entry address and leave bits 0-31 unchanged */
4902 regs->GR_L(r1) = regs->dat.raddr;
4903 }
4904 else
4905 {
4906 /* Set R1 and condition code as returned by translate_addr */
4907 regs->GR_G(r1) = regs->dat.raddr;
4908 }
4909
4910 /* Set condition code */
4911 regs->psw.cc = cc;
4912
4913 } /* end DEF_INST(load_real_address_long) */
4914 #endif /*defined(FEATURE_ESAME)*/
4915
4916
4917 #if defined(FEATURE_TOD_CLOCK_STEERING)
4918 /*-------------------------------------------------------------------*/
4919 /* 0104 PTFF - Perform Timing Facility Function [E] */
4920 /*-------------------------------------------------------------------*/
DEF_INST(perform_timing_facility_function)4921 DEF_INST(perform_timing_facility_function)
4922 {
4923 E(inst, regs);
4924
4925 SIE_INTERCEPT(regs);
4926
4927 if(regs->GR_L(0) & PTFF_GPR0_RESV)
4928 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
4929
4930 switch(regs->GR_L(0) & PTFF_GPR0_FC_MASK)
4931 {
4932 case PTFF_GPR0_FC_QAF:
4933 ARCH_DEP(query_available_functions) (regs);
4934 regs->psw.cc = 0;
4935 break;
4936 case PTFF_GPR0_FC_QTO:
4937 ARCH_DEP(query_tod_offset) (regs);
4938 regs->psw.cc = 0;
4939 break;
4940 case PTFF_GPR0_FC_QSI:
4941 ARCH_DEP(query_steering_information) (regs);
4942 regs->psw.cc = 0;
4943 break;
4944 case PTFF_GPR0_FC_QPT:
4945 ARCH_DEP(query_physical_clock) (regs);
4946 regs->psw.cc = 0;
4947 break;
4948 case PTFF_GPR0_FC_ATO:
4949 PRIV_CHECK(regs);
4950 ARCH_DEP(adjust_tod_offset) (regs);
4951 regs->psw.cc = 0;
4952 break;
4953 case PTFF_GPR0_FC_STO:
4954 PRIV_CHECK(regs);
4955 ARCH_DEP(set_tod_offset) (regs);
4956 regs->psw.cc = 0;
4957 break;
4958 case PTFF_GPR0_FC_SFS:
4959 PRIV_CHECK(regs);
4960 ARCH_DEP(set_fine_s_rate) (regs);
4961 regs->psw.cc = 0;
4962 break;
4963 case PTFF_GPR0_FC_SGS:
4964 PRIV_CHECK(regs);
4965 ARCH_DEP(set_gross_s_rate) (regs);
4966 regs->psw.cc = 0;
4967 break;
4968 default:
4969 PTT(PTT_CL_ERR,"*PTFF",regs->GR_L(0),regs->GR_L(1),regs->psw.IA_L);
4970 regs->psw.cc = 3;
4971 }
4972
4973 } /* end DEF_INST(perform_timing_facility_function) */
4974 #endif /*defined(FEATURE_TOD_CLOCK_STEERING)*/
4975
4976
4977 #if defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)
4978 /*-------------------------------------------------------------------*/
4979 /* B9A2 PTF - Perform Topology Function [RRE] */
4980 /*-------------------------------------------------------------------*/
DEF_INST(perform_topology_function)4981 DEF_INST(perform_topology_function)
4982 {
4983 int r1, unused; /* Values of R fields */
4984 int fc, rc = 0; /* Function / Reason Code */
4985
4986 RRE(inst, regs, r1, unused);
4987
4988 PTT(PTT_CL_INF,"PTF",regs->GR_G(r1),0,regs->psw.IA_L);
4989
4990 PRIV_CHECK(regs);
4991
4992 SIE_INTERCEPT(regs);
4993
4994 /* Specification Exception if bits 0-55 of general register R1
4995 are not zeros */
4996 if (regs->GR_G(r1) & 0xFFFFFFFFFFFFFF00ULL)
4997 {
4998 PTT(PTT_CL_ERR,"*PTF",regs->GR_G(r1),rc,regs->psw.IA_L);
4999 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
5000 }
5001
5002 /* Extract function code */
5003 fc = (int)(regs->GR_G(r1) & 0x00000000000000FFULL);
5004
5005 /* Perform requested function */
5006 switch (fc)
5007 {
5008 case 0: /* Request horizontal polarization */
5009 if (sysblk.topology == TOPOLOGY_HORIZ) {
5010 regs->psw.cc = 2; /* Request rejected */
5011 rc = 1; /* Already polarized as specified */
5012 } else {
5013 sysblk.topology = TOPOLOGY_HORIZ;
5014 sysblk.topchnge = 1;
5015 regs->psw.cc = 0;
5016 rc = 0;
5017 }
5018 break;
5019
5020 case 1: /* Request vertical polarization */
5021 if (sysblk.topology == TOPOLOGY_VERT) {
5022 regs->psw.cc = 2; /* Request rejected */
5023 rc = 1; /* Already polarized as specified */
5024 } else {
5025 sysblk.topology = TOPOLOGY_VERT;
5026 sysblk.topchnge = 1;
5027 regs->psw.cc = 0;
5028 rc = 0;
5029 }
5030 break;
5031
5032 case 2: /* Check topology-change status */
5033 OBTAIN_INTLOCK(regs);
5034 regs->psw.cc = sysblk.topchnge ? 1 /* (report was pending) */
5035 : 0; /* (report not pending) */
5036 sysblk.topchnge = 0; /* (clear pending flag) */
5037 RELEASE_INTLOCK(regs);
5038 break;
5039
5040 default:
5041 /* Undefined function code */
5042 PTT(PTT_CL_ERR,"*PTF",regs->GR_G(r1),rc,regs->psw.IA_L);
5043 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
5044 }
5045
5046 /* Set reason code in bits 48-55 when condition code is 2 */
5047 if (regs->psw.cc == 2)
5048 regs->GR_G(r1) |= rc << 8;
5049
5050 if (regs->psw.cc != 0)
5051 PTT(PTT_CL_ERR,"*PTF",regs->GR_G(r1),rc,regs->psw.IA_L);
5052 }
5053 #endif /*defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)*/
5054
5055
5056 #if defined(FEATURE_RESET_REFERENCE_BITS_MULTIPLE_FACILITY)
5057 /*-------------------------------------------------------------------*/
5058 /* B9AE RRBM - Reset Reference Bits Multiple [RRE] */
5059 /*-------------------------------------------------------------------*/
DEF_INST(reset_reference_bits_multiple)5060 DEF_INST(reset_reference_bits_multiple)
5061 {
5062 int r1, r2; /* Register values */
5063 RADR a; /* Abs frame addr stor key */
5064 BYTE storkey; /* Storage key */
5065 int i;
5066 U64 bitmap; /* Bitmap to be ret in r1 */
5067
5068 RRE(inst, regs, r1, r2);
5069
5070 PRIV_CHECK(regs);
5071
5072 /* Load 4K block address from R2 register */
5073 a = regs->GR(r2) & ADDRESS_MAXWRAP_E(regs);
5074
5075 /* Addressing exception if block is outside main storage */
5076 if ( a > regs->mainlim )
5077 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
5078
5079 /* Ignore bits 46-63 of the 2nd operand */
5080 a &= ~0x3ffffULL;
5081
5082 #if defined(_FEATURE_SIE)
5083 if(SIE_MODE(regs) && (SIE_STATB(regs, IC2, RRBE)))
5084 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
5085
5086
5087 for(i =0 , bitmap = 0; i < 64; i++, a+= PAGEFRAME_PAGESIZE, bitmap <<= 1)
5088 {
5089 RADR n = a;
5090
5091 if(SIE_MODE(regs))
5092 {
5093 SIE_TRANSLATE(&n, ACCTYPE_SIE, regs);
5094
5095 if(regs->sie_pref)
5096 {
5097 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
5098 if((SIE_STATB(regs, RCPO0, SKA)
5099 #if defined(_FEATURE_ZSIE)
5100 || (regs->hostregs->arch_mode == ARCH_900)
5101 #endif /*defined(_FEATURE_ZSIE)*/
5102 ) && SIE_STATB(regs, RCPO2, RCPBY))
5103 {
5104 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5105 storkey = STORAGE_KEY(n, regs);
5106 #else
5107 storkey = STORAGE_KEY1(n, regs)
5108 | (STORAGE_KEY2(n, regs) & (STORKEY_REF))
5109 #endif
5110 ;
5111 /* Reset the reference bit in the storage key */
5112 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5113 STORAGE_KEY(n, regs) &= ~(STORKEY_REF);
5114 #else
5115 STORAGE_KEY1(n, regs) &= ~(STORKEY_REF);
5116 STORAGE_KEY2(n, regs) &= ~(STORKEY_REF);
5117 #endif
5118 }
5119 else
5120 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
5121 {
5122 BYTE rcpkey, realkey;
5123 RADR ra;
5124 RADR rcpa;
5125
5126 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
5127 if(SIE_STATB(regs, RCPO0, SKA)
5128 #if defined(_FEATURE_ZSIE)
5129 || (regs->hostregs->arch_mode == ARCH_900)
5130 #endif /*defined(_FEATURE_ZSIE)*/
5131 )
5132 {
5133 /* guest absolute to host PTE addr */
5134 if (SIE_TRANSLATE_ADDR (regs->sie_mso + n, USE_PRIMARY_SPACE,
5135 regs->hostregs, ACCTYPE_PTE))
5136 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
5137
5138 /* Convert real address to absolute address */
5139 rcpa = APPLY_PREFIXING (regs->hostregs->dat.raddr, regs->hostregs->PX);
5140
5141 /* For ESA/390 the RCP byte entry is at offset 1 in a
5142 four byte entry directly beyond the page table,
5143 for ESAME mode, this entry is eight bytes long */
5144 rcpa += regs->hostregs->arch_mode == ARCH_900 ? 2049 : 1025;
5145 }
5146 else
5147 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
5148 {
5149 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
5150 if(SIE_STATB(regs, MX, XC))
5151 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
5152 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
5153
5154 /* Obtain address of the RCP area from the state desc */
5155 rcpa = regs->sie_rcpo &= 0x7FFFF000;
5156
5157 /* frame index as byte offset to 4K keys in RCP area */
5158 rcpa += n >> 12;
5159
5160 /* host primary to host absolute */
5161 rcpa = SIE_LOGICAL_TO_ABS (rcpa, USE_PRIMARY_SPACE,
5162 regs->hostregs, ACCTYPE_SIE, 0);
5163 }
5164
5165 /* fetch the RCP key */
5166 rcpkey = regs->mainstor[rcpa];
5167 STORAGE_KEY(rcpa, regs) |= STORKEY_REF;
5168
5169 if (!SIE_TRANSLATE_ADDR (regs->sie_mso + n, USE_PRIMARY_SPACE,
5170 regs->hostregs, ACCTYPE_SIE))
5171 {
5172 ra = APPLY_PREFIXING(regs->hostregs->dat.raddr, regs->hostregs->PX);
5173 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5174 realkey = STORAGE_KEY(ra, regs) & (STORKEY_REF);
5175 #else
5176 realkey = (STORAGE_KEY1(ra, regs) | STORAGE_KEY2(ra, regs))
5177 & (STORKEY_REF);
5178 #endif
5179 /* Reset the reference and change bits in
5180 the real machine storage key */
5181 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5182 STORAGE_KEY(ra, regs) &= ~(STORKEY_REF);
5183 #else
5184 STORAGE_KEY1(ra, regs) &= ~(STORKEY_REF);
5185 STORAGE_KEY2(ra, regs) &= ~(STORKEY_REF);
5186 #endif
5187 }
5188 else
5189 realkey = 0;
5190
5191 /* The storage key is obtained by logical or
5192 or the real and guest RC bits */
5193 storkey = realkey | (rcpkey & (STORKEY_REF));
5194 /* or with host set */
5195 rcpkey |= realkey << 4;
5196 /* Put storage key in guest set */
5197 rcpkey |= storkey;
5198 /* reset the reference bit */
5199 rcpkey &= ~(STORKEY_REF);
5200 regs->mainstor[rcpa] = rcpkey;
5201 STORAGE_KEY(rcpa, regs) |= (STORKEY_REF);
5202 }
5203 }
5204 else
5205 {
5206 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5207 storkey = STORAGE_KEY(n, regs);
5208 #else
5209 storkey = STORAGE_KEY1(n, regs)
5210 | (STORAGE_KEY2(n, regs) & (STORKEY_REF))
5211 #endif
5212 ;
5213 /* Reset the reference bit in the storage key */
5214 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5215 STORAGE_KEY(n, regs) &= ~(STORKEY_REF);
5216 #else
5217 STORAGE_KEY1(n, regs) &= ~(STORKEY_REF);
5218 STORAGE_KEY2(n, regs) &= ~(STORKEY_REF);
5219 #endif
5220 }
5221 }
5222 else
5223 #endif /*defined(_FEATURE_SIE)*/
5224 {
5225 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5226 storkey = STORAGE_KEY(n, regs);
5227 #else
5228 storkey = STORAGE_KEY1(n, regs)
5229 | (STORAGE_KEY2(n, regs) & (STORKEY_REF))
5230 #endif
5231 ;
5232 /* Reset the reference bit in the storage key */
5233 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5234 STORAGE_KEY(n, regs) &= ~(STORKEY_REF);
5235 #else
5236 STORAGE_KEY1(n, regs) &= ~(STORKEY_REF);
5237 STORAGE_KEY2(n, regs) &= ~(STORKEY_REF);
5238 #endif
5239 }
5240
5241 /* Insert the original state of the reference bit
5242 in the bitmap */
5243 bitmap |= (storkey & STORKEY_REF) ? 0x01ULL : 0;
5244
5245 /* If the storage key had the REF bit on then perform
5246 * accelerated lookup invalidations on all CPUs
5247 * so that the REF bit will be set when referenced next.
5248 */
5249 if (storkey & STORKEY_REF)
5250 STORKEY_INVALIDATE(regs, n);
5251 }
5252
5253 regs->GR_G(r1) = bitmap;
5254
5255 } /* end DEF_INST(reset_reference_bits_multiple) */
5256 #endif /*defined(FEATURE_RESET_REFERENCE_BITS_MULTIPLE_FACILITY)*/
5257
5258
5259 #if defined(FEATURE_ENHANCED_DAT_FACILITY)
5260 /*-------------------------------------------------------------------*/
5261 /* SUBROUTINE TO PERFORM CONDITIONAL KEY PROCESSING */
5262 /* Input: */
5263 /* mask PFMF mask bits from R1 register */
5264 /* skey Contents of storage key before modification */
5265 /* r1key Storage key to be set */
5266 /* Output (when conditional SSKE is not indicated): */
5267 /* The function return value is 0. */
5268 /* Output (when conditional SSKE is indicated): */
5269 /* The function return value is 1. */
5270 /*-------------------------------------------------------------------*/
ARCH_DEP(conditional_key_procedure)5271 static inline int ARCH_DEP(conditional_key_procedure) (U32 mask, BYTE skey, BYTE r1key)
5272 {
5273 /* Perform normal SSKE if MR and MC bits are both zero */
5274 if ((mask & (PFMF_MR | PFMF_MC)) == 0)
5275 return 0;
5276
5277 /* Ignore Bad Frame indicator */
5278 skey &= ~(STORKEY_BADFRM);
5279
5280 /* If storage key and fetch bit do not equal new values
5281 in R1 register bits 56-60 then set condition code 1
5282 and return to PFMF to update storage key */
5283 if ((skey & (STORKEY_KEY | STORKEY_FETCH))
5284 != (r1key & (STORKEY_KEY | STORKEY_FETCH)))
5285 return 0;
5286
5287 /* If both MR and MC mask bits are one then set
5288 condition code 0 and leave storage key unchanged */
5289 if ((mask & (PFMF_MR | PFMF_MC)) == (PFMF_MR | PFMF_MC))
5290 return 1;
5291
5292 /* If MR bit is zero and reference bit is equal to
5293 bit 61 of R1 register then set condition code 0
5294 and leave storage key unchanged */
5295 if ((mask & PFMF_MR) == 0
5296 && ((skey & STORKEY_REF)
5297 == (r1key & STORKEY_REF)))
5298 return 1;
5299
5300 /* If MC bit is zero and the change bit is equal to
5301 bit 62 of R1 register then set condition code 0
5302 and leave storage key unchanged */
5303 if ((mask & PFMF_MC) == 0
5304 && ((skey & STORKEY_CHANGE)
5305 == (r1key & STORKEY_CHANGE)))
5306 return 1;
5307
5308 /* Set condition code 1 and let PFMF update storage key */
5309 return 0;
5310
5311 } /* end function conditional_key_procedure */
5312
5313
5314 /*-------------------------------------------------------------------*/
5315 /* B9AF PFMF - Perform Frame Management Function [RRE] */
5316 /*-------------------------------------------------------------------*/
DEF_INST(perform_frame_management_function)5317 DEF_INST(perform_frame_management_function)
5318 {
5319 int r1, r2; /* Register values */
5320 U32 mask; /* Mask bits from R1 */
5321 int fc = 1; /* Frame count */
5322 RADR addr, aaddr; /* Address of storage frame */
5323 int page_offset; /* Low order bits of R2 */
5324
5325 RRE(inst, regs, r1, r2);
5326
5327 PRIV_CHECK(regs);
5328
5329 /* Load mask bits from R1 register */
5330 mask = regs->GR_L(r1);
5331
5332 /* Program check if reserved bits are non-zero */
5333 if ((regs->GR_L(r1) & (PFMF_RESERVED|PFMF_FMFI_RESV))
5334 || (regs->GR_L(r1) & PFMF_NQ))
5335 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
5336
5337 /* Wrap address according to addressing mode */
5338 aaddr = addr = ADDRESS_MAXWRAP(regs) & regs->GR_G(r2) & PAGEFRAME_PAGEMASK;
5339 page_offset = regs->GR_G(r2) & PAGEFRAME_BYTEMASK;
5340
5341 /* Convert real address to absolute address */
5342
5343 switch (PFMF_FSC & regs->GR_L(r1)) {
5344 case PFMF_FSC_1M:
5345 /* Prefixing is not applied in multipage mode */
5346 fc = 0x100 - ((regs->GR_L(r2) & 0xFF000) >> 12);
5347 break;
5348 #if defined(FEATURE_ENHANCED_DAT_FACILITY_2)
5349 case PFMF_FSC_2G:
5350 /* Program check if 2GB frame size with 24-bit addressing mode */
5351 if (regs->psw.amode64 == 0 && regs->psw.amode == 0) {
5352 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
5353 }
5354 /* Prefixing is not applied in multipage mode */
5355 fc = 0x80000 - ((regs->GR_L(r2) & 0x7FFFF000) >> 12);
5356 break;
5357 #endif /*defined(FEATURE_ENHANCED_DAT_FACILITY_2)*/
5358 default:
5359 /* Program check if frame size code is invalid */
5360 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
5361 break;
5362 case PFMF_FSC_4K:
5363 /* Prefixing is applied in single frame operation */
5364 aaddr = addr = APPLY_PREFIXING (addr, regs->PX);
5365 fc = 1;
5366 break;
5367 }
5368
5369 /* Note that real hardware does not update R2 for each page, only on
5370 interrupt or at completion. Nor does it reference R1 more than once.
5371 This has implications for the case of R1 == R2.
5372 The low order 12 bits of R2 must remain unchanged. */
5373 for( ; fc--; )
5374 {
5375 /* Addressing exception if block is outside main storage */
5376 if ( addr > regs->mainlim )
5377 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
5378
5379 if(regs->GR_L(r1) & PFMF_FMFI_CF)
5380 SIE_TRANSLATE(&aaddr, ACCTYPE_SIE, regs);
5381
5382 /* Set Key Control */
5383 if(regs->GR_L(r1) & PFMF_FMFI_SK)
5384 {
5385 BYTE sk = regs->GR_L(r1) & PFMF_KEY;
5386 RADR n = addr;
5387 BYTE rck = 0;
5388
5389 /* Ref Bit must be updated */
5390 if (!(regs->GR_L(r1) & PFMF_MR))
5391 rck |= STORKEY_REF;
5392
5393 /* Change Bit must be updated */
5394 if ((regs->GR_L(r1) & PFMF_MC))
5395 rck |= STORKEY_CHANGE;
5396
5397 /* Mask out R/C bits to be bypassed */
5398 sk &= ~rck;
5399
5400 /* Addressing exception if block is outside main storage */
5401 if ( aaddr > regs->mainlim )
5402 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
5403
5404 #if defined(_FEATURE_SIE)
5405 if(SIE_MODE(regs))
5406 {
5407 if(SIE_STATB(regs, IC2, SSKE))
5408 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
5409
5410 if(!regs->sie_pref)
5411 {
5412 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
5413 if ((SIE_STATB(regs, RCPO0, SKA)
5414 #if defined(_FEATURE_ZSIE)
5415 || (regs->hostregs->arch_mode == ARCH_900)
5416 #endif /*defined(_FEATURE_ZSIE)*/
5417 ) && SIE_STATB(regs, RCPO2, RCPBY))
5418 { SIE_TRANSLATE(&aaddr, ACCTYPE_SIE, regs); }
5419 else
5420 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
5421 {
5422 int sr;
5423 BYTE realkey,
5424 rcpkey,
5425 protkey;
5426 RADR rcpa;
5427
5428 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
5429 if(SIE_STATB(regs, RCPO0, SKA)
5430 #if defined(_FEATURE_ZSIE)
5431 || (regs->hostregs->arch_mode == ARCH_900)
5432 #endif /*defined(_FEATURE_ZSIE)*/
5433 )
5434 {
5435 /* guest absolute to host PTE addr */
5436 if (SIE_TRANSLATE_ADDR (regs->sie_mso + aaddr, USE_PRIMARY_SPACE,
5437 regs->hostregs, ACCTYPE_PTE))
5438 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
5439
5440 /* Convert real address to absolute address */
5441 rcpa = APPLY_PREFIXING (regs->hostregs->dat.raddr, regs->hostregs->PX);
5442
5443 /* For ESA/390 the RCP byte entry is at offset 1 in a
5444 four byte entry directly beyond the page table,
5445 for ESAME mode, this entry is eight bytes long */
5446 rcpa += regs->hostregs->arch_mode == ARCH_900 ? 2049 : 1025;
5447 }
5448 else
5449 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
5450 {
5451 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
5452 if(SIE_STATB(regs, MX, XC))
5453 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
5454 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
5455
5456 /* Obtain address of the RCP area from the state desc */
5457 rcpa = regs->sie_rcpo &= 0x7FFFF000;
5458
5459 /* frame index as byte offset to 4K keys in RCP area */
5460 rcpa += aaddr >> 12;
5461
5462 /* host primary to host absolute */
5463 rcpa = SIE_LOGICAL_TO_ABS (rcpa, USE_PRIMARY_SPACE,
5464 regs->hostregs, ACCTYPE_SIE, 0);
5465 }
5466
5467 /* guest absolute to host real */
5468 sr = SIE_TRANSLATE_ADDR (regs->sie_mso + aaddr, USE_PRIMARY_SPACE,
5469 regs->hostregs, ACCTYPE_SIE);
5470
5471 if (sr
5472 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
5473 && !(SIE_FEATB(regs, RCPO0, SKA)
5474 #if defined(_FEATURE_ZSIE)
5475 || (regs->hostregs->arch_mode == ARCH_900)
5476 #endif /*defined(_FEATURE_ZSIE)*/
5477 )
5478 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
5479 )
5480 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
5481
5482 /* fetch the RCP key */
5483 rcpkey = regs->mainstor[rcpa];
5484 /* set the reference bit in the RCP key */
5485 STORAGE_KEY(rcpa, regs) |= STORKEY_REF;
5486 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
5487 if(sr)
5488 {
5489 realkey = 0;
5490 protkey = rcpkey & (STORKEY_REF | STORKEY_CHANGE);
5491 /* rcpa-1 is correct here - would have been SIE Intercepted otherwise */
5492 protkey |= regs->mainstor[rcpa-1] & (STORKEY_KEY | STORKEY_FETCH);
5493 }
5494 else
5495 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
5496 {
5497 /* host real to host absolute */
5498 n = APPLY_PREFIXING(regs->hostregs->dat.raddr, regs->hostregs->PX);
5499
5500 protkey =
5501 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5502 STORAGE_KEY(n, regs)
5503 #else
5504 (STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs))
5505 #endif
5506 ;
5507 realkey = protkey & (STORKEY_REF | STORKEY_CHANGE);
5508 }
5509
5510 /* Perform conditional SSKE procedure */
5511 if (ARCH_DEP(conditional_key_procedure)(mask, protkey, sk))
5512 return;
5513 /* or with host set */
5514 rcpkey |= realkey << 4;
5515 /* insert new settings of the guest set */
5516 rcpkey &= ~(STORKEY_REF | STORKEY_CHANGE);
5517 rcpkey |= sk & (STORKEY_REF | STORKEY_CHANGE);
5518 regs->mainstor[rcpa] = rcpkey;
5519 STORAGE_KEY(rcpa, regs) |= (STORKEY_REF|STORKEY_CHANGE);
5520 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
5521 /* Insert key in new storage key */
5522 if(SIE_STATB(regs, RCPO0, SKA)
5523 #if defined(_FEATURE_ZSIE)
5524 || (regs->hostregs->arch_mode == ARCH_900)
5525 #endif /*defined(_FEATURE_ZSIE)*/
5526 )
5527 regs->mainstor[rcpa-1] = sk
5528 & (STORKEY_KEY | STORKEY_FETCH);
5529 if(!sr)
5530 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
5531 {
5532 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5533 STORAGE_KEY(aaddr, regs) &= STORKEY_BADFRM;
5534 STORAGE_KEY(aaddr, regs) |= sk
5535 & (STORKEY_KEY | STORKEY_FETCH);
5536 #else
5537 STORAGE_KEY1(aaddr, regs) &= STORKEY_BADFRM;
5538 STORAGE_KEY1(aaddr, regs) |= sk
5539 & (STORKEY_KEY | STORKEY_FETCH);
5540 STORAGE_KEY2(aaddr, regs) &= STORKEY_BADFRM;
5541 STORAGE_KEY2(aaddr, regs) |= sk
5542 & (STORKEY_KEY | STORKEY_FETCH);
5543 #endif
5544 }
5545 }
5546 }
5547 else
5548 {
5549 /* Perform conditional SSKE procedure */
5550 if (ARCH_DEP(conditional_key_procedure)(mask,
5551 #if defined(FEATURE_4K_STORAGE_KEYS) && !defined(_FEATURE_2K_STORAGE_KEYS)
5552 STORAGE_KEY(aaddr, regs),
5553 #else
5554 (STORAGE_KEY1(aaddr, regs) | STORAGE_KEY2(aaddr, regs)),
5555 #endif
5556 sk))
5557 return;
5558 /* Update the storage key from R1 register bits 24-30 */
5559 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5560 STORAGE_KEY(aaddr, regs) &= STORKEY_BADFRM;
5561 STORAGE_KEY(aaddr, regs) |= sk & ~(STORKEY_BADFRM);
5562 #else
5563 STORAGE_KEY1(aaddr, regs) &= STORKEY_BADFRM;
5564 STORAGE_KEY1(aaddr, regs) |= sk & ~(STORKEY_BADFRM);
5565 STORAGE_KEY2(aaddr, regs) &= STORKEY_BADFRM;
5566 STORAGE_KEY2(aaddr, regs) |= sk & ~(STORKEY_BADFRM);
5567 #endif
5568 }
5569 }
5570 else
5571 #endif /*defined(_FEATURE_SIE)*/
5572 {
5573 /* Perform conditional SSKE procedure */
5574 if (ARCH_DEP(conditional_key_procedure)(mask,
5575 #if defined(FEATURE_4K_STORAGE_KEYS) && !defined(_FEATURE_2K_STORAGE_KEYS)
5576 STORAGE_KEY(aaddr, regs),
5577 #else
5578 (STORAGE_KEY1(aaddr, regs) | STORAGE_KEY2(n, regs)),
5579 #endif
5580 sk))
5581 return;
5582
5583 /* Update the storage key from R1 register bits 24-30 */
5584 #if defined(FEATURE_4K_STORAGE_KEYS) && !defined(_FEATURE_2K_STORAGE_KEYS)
5585 STORAGE_KEY(aaddr, regs) &= STORKEY_BADFRM;
5586 STORAGE_KEY(aaddr, regs) |= sk & ~(STORKEY_BADFRM);
5587 #else
5588 STORAGE_KEY1(aaddr, regs) &= STORKEY_BADFRM;
5589 STORAGE_KEY1(aaddr, regs) |= sk & ~(STORKEY_BADFRM);
5590 STORAGE_KEY2(aaddr, regs) &= STORKEY_BADFRM;
5591 STORAGE_KEY2(aaddr, regs) |= sk & ~(STORKEY_BADFRM);
5592 #endif
5593 }
5594
5595 /* Quiesce */
5596 if (!(regs->GR_L(r1) & PFMF_NQ))
5597 {
5598 /* Perform serialization and checkpoint-synchronization */
5599 PERFORM_SERIALIZATION (regs);
5600 PERFORM_CHKPT_SYNC (regs);
5601 }
5602
5603 /* Invalidate AIA/AEA so that the REF and CHANGE bits will be set
5604 when referenced next */
5605 STORKEY_INVALIDATE(regs, n);
5606
5607 }
5608
5609 /* Clear Frame Control */
5610 if(regs->GR_L(r1) & PFMF_FMFI_CF)
5611 memset(regs->mainstor + aaddr, 0, PAGEFRAME_PAGESIZE);
5612
5613 /* Update r2 - point to the next frame */
5614 switch (PFMF_FSC & regs->GR_L(r1)) {
5615 case PFMF_FSC_1M:
5616 case PFMF_FSC_2G:
5617 aaddr = addr += 0x1000;
5618 SET_GR_A(r2, regs, (addr & ADDRESS_MAXWRAP(regs)) + page_offset);
5619 break;
5620 default:
5621 break;
5622 case PFMF_FSC_4K:
5623 /* Leave R2 unchanged */
5624 break;
5625 }
5626
5627 #if 0
5628 /* Usage Indication */
5629 if (regs->GR_L(r1) & PFMF_UI)
5630 { }
5631 #endif
5632
5633 }
5634
5635 } /* end DEF_INST(perform_frame_management_function) */
5636 #endif /*defined(FEATURE_ENHANCED_DAT_FACILITY)*/
5637
5638
5639 #if defined(FEATURE_STORE_FACILITY_LIST)
5640
5641 #define HAVE_STFL_DATA 1
5642
5643 BYTE ARCH_DEP(stfl_data)[] = {
5644 0
5645 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)
5646 | STFL_0_N3
5647 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_ESAME)*/
5648 #if defined(FEATURE_ESAME)
5649 | STFL_0_ESAME_ACTIVE
5650 #endif /*defined(FEATURE_ESAME)*/
5651 #if defined(FEATURE_ESAME)
5652 | STFL_0_ESAME_INSTALLED
5653 #endif /*defined(FEATURE_ESAME)*/
5654 #if defined(FEATURE_DAT_ENHANCEMENT)
5655 | STFL_0_IDTE_INSTALLED
5656 #endif /*defined(FEATURE_DAT_ENHANCEMENT)*/
5657 #if defined(FEATURE_ASN_AND_LX_REUSE)
5658 | STFL_0_ASN_LX_REUSE
5659 #endif /*defined(FEATURE_ASN_AND_LX_REUSE)*/
5660 #if defined(FEATURE_STORE_FACILITY_LIST_EXTENDED)
5661 | STFL_0_STFL_EXTENDED
5662 #endif /*defined(FEATURE_STORE_FACILITY_LIST_EXTENDED)*/
5663 ,
5664 0
5665 #if defined(FEATURE_ENHANCED_DAT_FACILITY) /*208*/
5666 | STFL_1_ENHANCED_DAT /*208*/
5667 #endif /*defined(FEATURE_ENHANCED_DAT_FACILITY)*/ /*208*/
5668 #if defined(FEATURE_SENSE_RUNNING_STATUS)
5669 | STFL_1_SENSE_RUN_STATUS
5670 #endif /*defined(FEATURE_SENSE_RUNNING_STATUS)*/
5671 #if defined(FEATURE_CONDITIONAL_SSKE)
5672 | STFL_1_CONDITIONAL_SSKE
5673 #endif /*defined(FEATURE_CONDITIONAL_SSKE)*/
5674 #if defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY) /*208*/
5675 | STFL_1_CONFIG_TOPOLOGY /*208*/
5676 #endif /*defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)*/ /*208*/
5677 ,
5678 0
5679 #if defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)
5680 | STFL_2_TRAN_FAC2
5681 #endif /*defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)*/
5682 #if defined(FEATURE_MESSAGE_SECURITY_ASSIST)
5683 | STFL_2_MSG_SECURITY
5684 #endif /*defined(FEATURE_MESSAGE_SECURITY_ASSIST)*/
5685 #if defined(FEATURE_LONG_DISPLACEMENT)
5686 | STFL_2_LONG_DISPL_INST
5687 | STFL_2_LONG_DISPL_HPERF
5688 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
5689 #if defined(FEATURE_HFP_MULTIPLY_ADD_SUBTRACT)
5690 | STFL_2_HFP_MULT_ADD_SUB
5691 #endif /*defined(FEATURE_HFP_MULTIPLY_ADD_SUBTRACT)*/
5692 #if defined(FEATURE_EXTENDED_IMMEDIATE)
5693 | STFL_2_EXTENDED_IMMED
5694 #endif /*defined(FEATURE_EXTENDED_IMMEDIATE)*/
5695 #if defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_3)
5696 | STFL_2_TRAN_FAC3
5697 #endif /*defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_3)*/
5698 #if defined(FEATURE_HFP_UNNORMALIZED_EXTENSION)
5699 | STFL_2_HFP_UNNORM_EXT
5700 #endif /*defined(FEATURE_HFP_UNNORMALIZED_EXTENSION)*/
5701 ,
5702 0
5703 #if defined(FEATURE_ETF2_ENHANCEMENT)
5704 | STFL_3_ETF2_ENHANCEMENT
5705 #endif /*defined(FEATURE_ETF2_ENHANCEMENT)*/
5706 #if defined(FEATURE_STORE_CLOCK_FAST)
5707 | STFL_3_STORE_CLOCK_FAST
5708 #endif /*defined(FEATURE_STORE_CLOCK_FAST)*/
5709 #if defined(FEATURE_PARSING_ENHANCEMENT_FACILITY) /*208*/
5710 | STFL_3_PARSING_ENHANCE /*208*/
5711 #endif /*defined(FEATURE_PARSING_ENHANCEMENT_FACILITY)*/ /*208*/
5712 #if defined(FEATURE_MOVE_WITH_OPTIONAL_SPECIFICATIONS) /*208*/
5713 | STFL_3_MVCOS /*208*/
5714 #endif /*defined(FEATURE_MOVE_WITH_OPTIONAL_SPECIFICATIONS)*/ /*208*/
5715 #if defined(FEATURE_TOD_CLOCK_STEERING)
5716 | STFL_3_TOD_CLOCK_STEER
5717 #endif /*defined(FEATURE_TOD_CLOCK_STEERING)*/
5718 #if defined(FEATURE_ETF3_ENHANCEMENT)
5719 | STFL_3_ETF3_ENHANCEMENT
5720 #endif /*defined(FEATURE_ETF3_ENHANCEMENT)*/
5721 #if defined(FEATURE_EXTRACT_CPU_TIME)
5722 | STFL_3_EXTRACT_CPU_TIME
5723 #endif /*defined(FEATURE_EXTRACT_CPU_TIME)*/
5724 ,
5725 0
5726 #if defined(FEATURE_COMPARE_AND_SWAP_AND_STORE)
5727 | STFL_4_CSSF
5728 #endif /*defined(FEATURE_COMPARE_AND_SWAP_AND_STORE)*/
5729 #if defined(FEATURE_COMPARE_AND_SWAP_AND_STORE_FACILITY_2) /*208*/
5730 | STFL_4_CSSF2 /*208*/
5731 #endif /*FEATURE_COMPARE_AND_SWAP_AND_STORE_FACILITY_2*/ /*208*/
5732 #if defined(FEATURE_GENERAL_INSTRUCTIONS_EXTENSION_FACILITY) /*208*/
5733 | STFL_4_GEN_INST_EXTN /*208*/
5734 #endif /*FEATURE_GENERAL_INSTRUCTIONS_EXTENSION_FACILITY*/ /*208*/
5735 #if defined(FEATURE_EXECUTE_EXTENSIONS_FACILITY) /*208*/
5736 | STFL_4_EXECUTE_EXTN /*208*/
5737 #endif /*defined(FEATURE_EXECUTE_EXTENSIONS_FACILITY)*/ /*208*/
5738 #if defined(FEATURE_ENHANCED_MONITOR_FACILITY) /*810*/
5739 | STFL_4_ENH_MONITOR /*810*/
5740 #endif /*defined(FEATURE_ENHANCED_MONITOR_FACILITY)*/ /*810*/
5741 #if defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY) /*810*/
5742 | STFL_4_FP_EXTENSION /*810*/
5743 #endif /*defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY)*/ /*810*/
5744 ,
5745 0
5746 #if defined(FEATURE_LOAD_PROGRAM_PARAMETER_FACILITY)
5747 | STFL_5_LOAD_PROG_PARAM
5748 #endif /*defined(FEATURE_LOAD_PROGRAM_PARAMETER_FACILITY)*/
5749 #if defined(FEATURE_FPS_ENHANCEMENT)
5750 | STFL_5_FPS_ENHANCEMENT
5751 #endif /*defined(FEATURE_FPS_ENHANCEMENT)*/
5752 #if defined(FEATURE_DECIMAL_FLOATING_POINT)
5753 | STFL_5_DECIMAL_FLOAT
5754 | STFL_5_DFP_HPERF
5755 #endif /*defined(FEATURE_DECIMAL_FLOATING_POINT)*/
5756 #if defined(FEATURE_PFPO)
5757 | STFL_5_PFPO
5758 #endif /*defined(FEATURE_PFPO)*/
5759 #if defined(FEATURE_FAST_BCR_SERIALIZATION_FACILITY) /*810*/
5760 | STFL_5_FAST_BCR_SERIAL /*810*/
5761 #endif /*defined(FEATURE_FAST_BCR_SERIALIZATION_FACILITY)*/ /*810*/
5762 ,
5763 0
5764 #if defined(FEATURE_DFP_ZONED_CONVERSION_FACILITY) /*912*/
5765 | STFL_6_DFP_ZONED_CONV /*912*/
5766 #endif /*defined(FEATURE_DFP_ZONED_CONVERSION_FACILITY)*/ /*912*/
5767 #if defined(FEATURE_EXECUTION_HINT_FACILITY) /*912*/ \
5768 && defined(FEATURE_LOAD_AND_TRAP_FACILITY) /*912*/ \
5769 && defined(FEATURE_MISC_INSTRUCTION_EXTENSIONS_FACILITY) /*912*/ \
5770 && defined(FEATURE_PROCESSOR_ASSIST_FACILITY) /*912*/
5771 | STFL_6_MISC_INST_EXT /*912*/
5772 #endif /*912*/
5773 #if defined(FEATURE_TRANSACTIONAL_EXECUTION_FACILITY) /*912*/
5774 | STFL_6_CONSTRAINED_TEF /*912*/
5775 #endif /*defined(FEATURE_TRANSACTIONAL_EXECUTION_FACILITY)*/ /*912*/
5776 #if defined(FEATURE_LOCAL_TLB_CLEARING_FACILITY) /*912*/
5777 | STFL_6_LOCAL_TLB_CLEAR /*912*/
5778 #endif /*defined(FEATURE_LOCAL_TLB_CLEARING_FACILITY)*/ /*912*/
5779 #if defined(FEATURE_INTERLOCKED_ACCESS_FACILITY_2) /*912*/
5780 | STFL_6_INTERLOCK_ACC_2 /*912*/
5781 #endif /*defined(FEATURE_INTERLOCKED_ACCESS_FACILITY_2)*/ /*912*/
5782 ,
5783 0
5784 ,
5785 0
5786 #if defined(FEATURE_RESET_REFERENCE_BITS_MULTIPLE_FACILITY) /*810*/
5787 | STFL_8_RES_REF_BITS_MUL /*810*/
5788 #endif /*defined(FEATURE_RESET_REFERENCE_BITS_MULTIPLE_FACILITY) 810*/
5789 #if defined(FEATURE_CPU_MEASUREMENT_COUNTER_FACILITY)
5790 | STFL_8_CPU_MEAS_COUNTER
5791 #endif /*defined(FEATURE_CPU_MEASUREMENT_COUNTER_FACILITY)*/
5792 #if defined(FEATURE_CPU_MEASUREMENT_SAMPLING_FACILITY)
5793 | STFL_8_CPU_MEAS_SAMPLNG
5794 #endif /*defined(FEATURE_CPU_MEASUREMENT_SAMPLING_FACILITY)*/
5795 ,
5796 0
5797 #if defined(FEATURE_TRANSACTIONAL_EXECUTION_FACILITY) /*912*/
5798 | STFL_9_TRANSACT_EXEC /*912*/
5799 #endif /*defined(FEATURE_TRANSACTIONAL_EXECUTION_FACILITY)*/ /*912*/
5800 #if defined(FEATURE_ACCESS_EXCEPTION_FETCH_STORE_INDICATION) /*810*/
5801 | STFL_9_ACC_EX_FS_INDIC /*810*/
5802 #endif /*defined(FEATURE_ACCESS_EXCEPTION_FETCH_STORE_INDICATION)*/
5803 #if defined(FEATURE_MESSAGE_SECURITY_ASSIST_EXTENSION_3) /*810*/
5804 | STFL_9_MSA_EXTENSION_3 /*810*/
5805 #endif /*defined(FEATURE_MESSAGE_SECURITY_ASSIST_EXTENSION_3)*/ /*810*/
5806 #if defined(FEATURE_MESSAGE_SECURITY_ASSIST_EXTENSION_4) /*810*/
5807 | STFL_9_MSA_EXTENSION_4 /*810*/
5808 #endif /*defined(FEATURE_MESSAGE_SECURITY_ASSIST_EXTENSION_4)*/ /*810*/
5809 #if defined(FEATURE_ENHANCED_DAT_FACILITY_2) /*912*/
5810 | STFL_9_ENHANCED_DAT_2 /*912*/
5811 #endif /*defined(FEATURE_ENHANCED_DAT_FACILITY_2)*/ /*912*/
5812 ,
5813 0
5814 ,
5815 0
5816 ,
5817 0
5818 ,
5819 0
5820 ,
5821 0
5822 ,
5823 0
5824 };
5825
5826 /*-------------------------------------------------------------------*/
5827 /* Adjust the facility list to account for runtime options */
5828 /*-------------------------------------------------------------------*/
ARCH_DEP(adjust_stfl_data)5829 BYTE * ARCH_DEP(adjust_stfl_data) (int *data_len, REGS *regs)
5830 {
5831 int stfl_len; /* Length of STFL data */
5832 BYTE *stfl_data; /* -> STFL data being modified. Depends upon */
5833 /* installed architecture, but not the current */
5834 /* architecture mode being executed. */
5835 /* ARCH_DEP is unreliable choice for STFL data */
5836 /* post IPL of a z/Architecture machine but */
5837 /* before the CPU has been placed in */
5838 /* in z/Architecture mode. In this case, */
5839 /* ARCH_DEP selects ESA/390 STFL data which is */
5840 /* incomplete when z/Architecture is installed. */
5841 /* This creates problems for OS's that expect to */
5842 /* detect z/Architecture features before */
5843 /* entering z/Architecture mode and only find */
5844 /* ESA/390 features. */
5845
5846 if (sysblk.arch_z900)
5847 {
5848 /* 'ARCHMODE z/Arch' in configuration (or console configured) */
5849
5850 /* Locate the STFL data for a z/Architecture system */
5851 stfl_data=get_stfl_data(ARCH_900, &stfl_len);
5852
5853 /* A little overkill, but deals with the possible corner case */
5854 if (!stfl_data)
5855 {
5856 stfl_len=sizeof(ARCH_DEP(stfl_data));
5857 stfl_data=&ARCH_DEP(stfl_data)[0];
5858 }
5859
5860 stfl_data[0] |= STFL_0_ESAME_INSTALLED;
5861
5862 /* Set whether z/Arch is active based upon CPU mode */
5863 if (regs->arch_mode == ARCH_900)
5864 stfl_data[0] |= STFL_0_ESAME_ACTIVE;
5865 else
5866 stfl_data[0] &= ~STFL_0_ESAME_ACTIVE;
5867 }
5868 else
5869 {
5870 /* 'ARCHMODE ESA/390' in configuration (or console configured) */
5871
5872 /* Locate the STFL data for an ESA/390 system */
5873 stfl_data=get_stfl_data(ARCH_390, &stfl_len);
5874
5875 /* Same overkill, but just in case */
5876 if (!stfl_data)
5877 {
5878 stfl_len=sizeof(ARCH_DEP(stfl_data));
5879 stfl_data=&ARCH_DEP(stfl_data)[0];
5880 }
5881
5882 stfl_data[0] &= ~STFL_0_ESAME_INSTALLED;
5883 stfl_data[0] &= ~STFL_0_ESAME_ACTIVE;
5884 }
5885
5886 #if defined(FEATURE_MESSAGE_SECURITY_ASSIST)
5887 /* MSA is enabled only if the dyncrypt DLL module is loaded */
5888 if (ARCH_DEP(cipher_message)) {
5889 stfl_data[2] |= STFL_2_MSG_SECURITY;
5890 #ifdef FEATURE_MESSAGE_SECURITY_ASSIST_EXTENSION_3
5891 stfl_data[9] |= STFL_9_MSA_EXTENSION_3;
5892 #endif
5893 #ifdef FEATURE_MESSAGE_SECURITY_ASSIST_EXTENSION_4
5894 stfl_data[9] |= STFL_9_MSA_EXTENSION_4;
5895 #endif
5896 } else {
5897 stfl_data[2] &= ~(STFL_2_MSG_SECURITY);
5898 #ifdef FEATURE_MESSAGE_SECURITY_ASSIST_EXTENSION_3
5899 stfl_data[9] &= ~(STFL_9_MSA_EXTENSION_3);
5900 #endif
5901 #ifdef FEATURE_MESSAGE_SECURITY_ASSIST_EXTENSION_4
5902 stfl_data[9] &= ~(STFL_9_MSA_EXTENSION_4);
5903 #endif
5904 }
5905 #endif /*defined(FEATURE_MESSAGE_SECURITY_ASSIST)*/
5906
5907 #if defined(_FEATURE_ASN_AND_LX_REUSE)
5908 /* ALRF enablement is an option in the configuration file */
5909 if(sysblk.asnandlxreuse)
5910 stfl_data[0] |= STFL_0_ASN_LX_REUSE;
5911 else
5912 stfl_data[0] &= ~STFL_0_ASN_LX_REUSE;
5913 #endif /*defined(FEATURE_ASN_AND_LX_REUSE)*/
5914
5915 *data_len=stfl_len;
5916 return stfl_data;
5917 } /* end ARCH_DEP(adjust_stfl_data) */
5918
5919
5920
5921 /*-------------------------------------------------------------------*/
5922 /* B2B1 STFL - Store Facility List [S] */
5923 /*-------------------------------------------------------------------*/
DEF_INST(store_facility_list)5924 DEF_INST(store_facility_list)
5925 {
5926 int b2; /* Base of effective addr */
5927 VADR effective_addr2; /* Effective address */
5928 int data_len; /* Size of STFL data */
5929 /* Note: data_len not used here, but STFLE needs it */
5930 PSA *psa; /* -> Prefixed storage area */
5931 BYTE *stfl_data; /* -> STFL data */
5932
5933 S(inst, regs, b2, effective_addr2);
5934
5935 PRIV_CHECK(regs);
5936
5937 #if defined(_FEATURE_SIE)
5938 if(SIE_STATB(regs,IC0, STFL))
5939 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
5940 #endif /*defined(_FEATURE_SIE)*/
5941
5942 SIE_INTERCEPT(regs);
5943
5944 PTT(PTT_CL_INF,"STFL",b2,(U32)(effective_addr2 & 0xffffffff),regs->psw.IA_L);
5945
5946 /* Adjust the facility list to account for runtime options */
5947 stfl_data = ARCH_DEP(adjust_stfl_data)(&data_len, regs);
5948
5949 #if 0
5950 logmsg ("store_facility_list STFL data length %i\n",data_len);
5951 logmsg ("STFL=%2.2X %2.2X %2.2X %2.2X\n",
5952 *stfl_data,*(stfl_data+1),*(stfl_data+2),*(stfl_data+3));
5953 #endif
5954
5955 /* Set the main storage reference and change bits */
5956 STORAGE_KEY(regs->PX, regs) |= (STORKEY_REF | STORKEY_CHANGE);
5957
5958 /* Point to PSA in main storage */
5959 psa = (void*)(regs->mainstor + regs->PX);
5960
5961 memcpy(psa->stfl, stfl_data, sizeof(psa->stfl));
5962
5963 } /* end DEF_INST(store_facility_list) */
5964
5965
5966 #if defined(FEATURE_STORE_FACILITY_LIST_EXTENDED)
5967 /*-------------------------------------------------------------------*/
5968 /* B2B0 STFLE - Store Facility List Extended [S] */
5969 /*-------------------------------------------------------------------*/
DEF_INST(store_facility_list_extended)5970 DEF_INST(store_facility_list_extended)
5971 {
5972 int b2; /* Base of effective addr */
5973 VADR effective_addr2; /* Effective address */
5974 int data_len; /* Size of STFL data */
5975 int nmax; /* #of doublewords defined */
5976 int ndbl; /* #of doublewords to store */
5977 int cc; /* Condition code */
5978 BYTE *stfl_data; /* -> STFL data */
5979
5980 S(inst, regs, b2, effective_addr2);
5981
5982 #if defined(_FEATURE_SIE)
5983 if(SIE_STATB(regs,IC0, STFL))
5984 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
5985 #endif /*defined(_FEATURE_SIE)*/
5986
5987 PTT(PTT_CL_INF,"STFLE",regs->GR_L(0),(U32)(effective_addr2 & 0xffffffff),regs->psw.IA_L);
5988
5989 /* Note: STFLE is NOT a privileged instruction (unlike STFL) */
5990
5991 DW_CHECK(effective_addr2, regs);
5992
5993 /* Adjust the facility list to account for runtime options */
5994 stfl_data = ARCH_DEP(adjust_stfl_data)(&data_len, regs);
5995
5996 /* Calculate number of doublewords of facilities defined */
5997 nmax = (data_len+7) / 8;
5998
5999 /* Obtain operand length from register 0 bits 56-63 */
6000 ndbl = regs->GR_LHLCL(0) + 1;
6001
6002 /* Check if operand length is sufficient */
6003 if (ndbl >= nmax)
6004 {
6005 ndbl = nmax;
6006 cc = 0;
6007 }
6008 else
6009 {
6010 PTT(PTT_CL_ERR,"*STFLE", ndbl, nmax, regs->psw.IA_L);
6011 cc = 3;
6012 }
6013
6014 /* Store facility list at operand location */
6015 ARCH_DEP(vstorec) ( stfl_data, ndbl*8-1,
6016 effective_addr2, b2, regs );
6017
6018 /* Save number of doublewords minus 1 into register 0 bits 56-63 */
6019 regs->GR_LHLCL(0) = (BYTE)(nmax - 1);
6020
6021 /* Set condition code */
6022 regs->psw.cc = cc;
6023
6024 } /* end DEF_INST(store_facility_list_extended) */
6025 #endif /*defined(FEATURE_STORE_FACILITY_LIST_EXTENDED)*/
6026
6027 #endif /*defined(FEATURE_STORE_FACILITY_LIST) */
6028
6029
6030 #if defined(FEATURE_LOAD_REVERSED) && defined(FEATURE_ESAME)
6031 /*-------------------------------------------------------------------*/
6032 /* B90F LRVGR - Load Reversed Long Register [RRE] */
6033 /*-------------------------------------------------------------------*/
DEF_INST(load_reversed_long_register)6034 DEF_INST(load_reversed_long_register)
6035 {
6036 int r1, r2; /* Values of R fields */
6037
6038 RRE0(inst, regs, r1, r2);
6039
6040 /* Copy second operand to first operand */
6041 regs->GR_G(r1) = bswap_64(regs->GR_G(r2));
6042
6043 } /* end DEF_INST(load_reversed_long_register) */
6044 #endif /*defined(FEATURE_LOAD_REVERSED) && defined(FEATURE_ESAME)*/
6045
6046
6047 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_LOAD_REVERSED)
6048 /*-------------------------------------------------------------------*/
6049 /* B91F LRVR - Load Reversed Register [RRE] */
6050 /*-------------------------------------------------------------------*/
DEF_INST(load_reversed_register)6051 DEF_INST(load_reversed_register)
6052 {
6053 int r1, r2; /* Values of R fields */
6054
6055 RRE0(inst, regs, r1, r2);
6056
6057 /* Copy second operand to first operand */
6058 regs->GR_L(r1) = bswap_32(regs->GR_L(r2));
6059
6060 } /* end DEF_INST(load_reversed_register) */
6061 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_LOAD_REVERSED)*/
6062
6063
6064 #if defined(FEATURE_LOAD_REVERSED) && defined(FEATURE_ESAME)
6065 /*-------------------------------------------------------------------*/
6066 /* E30F LRVG - Load Reversed Long [RXY] */
6067 /*-------------------------------------------------------------------*/
DEF_INST(load_reversed_long)6068 DEF_INST(load_reversed_long)
6069 {
6070 int r1; /* Value of R field */
6071 int b2; /* Base of effective addr */
6072 VADR effective_addr2; /* Effective address */
6073
6074 RXY(inst, regs, r1, b2, effective_addr2);
6075
6076 /* Load R1 register from second operand */
6077 regs->GR_G(r1) = bswap_64(ARCH_DEP(vfetch8) ( effective_addr2, b2, regs ));
6078
6079 } /* end DEF_INST(load_reversed_long) */
6080 #endif /*defined(FEATURE_LOAD_REVERSED) && defined(FEATURE_ESAME)*/
6081
6082
6083 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_LOAD_REVERSED)
6084 /*-------------------------------------------------------------------*/
6085 /* E31E LRV - Load Reversed [RXY] */
6086 /*-------------------------------------------------------------------*/
DEF_INST(load_reversed)6087 DEF_INST(load_reversed)
6088 {
6089 int r1; /* Value of R field */
6090 int b2; /* Base of effective addr */
6091 VADR effective_addr2; /* Effective address */
6092
6093 RXY(inst, regs, r1, b2, effective_addr2);
6094
6095 /* Load R1 register from second operand */
6096 regs->GR_L(r1) = bswap_32(ARCH_DEP(vfetch4) ( effective_addr2, b2, regs ));
6097
6098 } /* end DEF_INST(load_reversed) */
6099 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_LOAD_REVERSED)*/
6100
6101
6102 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_LOAD_REVERSED)
6103 /*-------------------------------------------------------------------*/
6104 /* E31F LRVH - Load Reversed Half [RXY] */
6105 /*-------------------------------------------------------------------*/
DEF_INST(load_reversed_half)6106 DEF_INST(load_reversed_half)
6107 {
6108 int r1; /* Value of R field */
6109 int b2; /* Base of effective addr */
6110 VADR effective_addr2; /* Effective address */
6111
6112 RXY(inst, regs, r1, b2, effective_addr2);
6113
6114 /* Load R1 register from second operand */
6115 regs->GR_LHL(r1) = bswap_16(ARCH_DEP(vfetch2) ( effective_addr2, b2, regs ));
6116 } /* end DEF_INST(load_reversed_half) */
6117 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_LOAD_REVERSED)*/
6118
6119
6120 #if defined(FEATURE_LOAD_REVERSED) && defined(FEATURE_ESAME)
6121 /*-------------------------------------------------------------------*/
6122 /* E32F STRVG - Store Reversed Long [RXY] */
6123 /*-------------------------------------------------------------------*/
DEF_INST(store_reversed_long)6124 DEF_INST(store_reversed_long)
6125 {
6126 int r1; /* Values of R fields */
6127 int b2; /* Base of effective addr */
6128 VADR effective_addr2; /* Effective address */
6129
6130 RXY(inst, regs, r1, b2, effective_addr2);
6131
6132 /* Store register contents at operand address */
6133 ARCH_DEP(vstore8) ( bswap_64(regs->GR_G(r1)), effective_addr2, b2, regs );
6134
6135 } /* end DEF_INST(store_reversed_long) */
6136 #endif /*defined(FEATURE_LOAD_REVERSED) && defined(FEATURE_ESAME)*/
6137
6138
6139 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_LOAD_REVERSED)
6140 /*-------------------------------------------------------------------*/
6141 /* E33E STRV - Store Reversed [RXY] */
6142 /*-------------------------------------------------------------------*/
DEF_INST(store_reversed)6143 DEF_INST(store_reversed)
6144 {
6145 int r1; /* Values of R fields */
6146 int b2; /* Base of effective addr */
6147 VADR effective_addr2; /* Effective address */
6148
6149 RXY(inst, regs, r1, b2, effective_addr2);
6150
6151 /* Store register contents at operand address */
6152 ARCH_DEP(vstore4) ( bswap_32(regs->GR_L(r1)), effective_addr2, b2, regs );
6153
6154 } /* end DEF_INST(store_reversed) */
6155 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_LOAD_REVERSED)*/
6156
6157
6158 #if defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_LOAD_REVERSED)
6159 /*-------------------------------------------------------------------*/
6160 /* E33F STRVH - Store Reversed Half [RXY] */
6161 /*-------------------------------------------------------------------*/
DEF_INST(store_reversed_half)6162 DEF_INST(store_reversed_half)
6163 {
6164 int r1; /* Values of R fields */
6165 int b2; /* Base of effective addr */
6166 VADR effective_addr2; /* Effective address */
6167
6168 RXY(inst, regs, r1, b2, effective_addr2);
6169
6170 /* Store register contents at operand address */
6171 ARCH_DEP(vstore2) ( bswap_16(regs->GR_LHL(r1)), effective_addr2, b2, regs );
6172
6173 } /* end DEF_INST(store_reversed_half) */
6174 #endif /*defined(FEATURE_ESAME_N3_ESA390) || defined(FEATURE_LOAD_REVERSED)*/
6175
6176
6177 #if defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)
6178 /*-------------------------------------------------------------------*/
6179 /* E9 PKA - Pack ASCII [SS] */
6180 /*-------------------------------------------------------------------*/
DEF_INST(pack_ascii)6181 DEF_INST(pack_ascii)
6182 {
6183 int len; /* Second operand length */
6184 int b1, b2; /* Base registers */
6185 VADR addr1, addr2; /* Effective addresses */
6186 BYTE source[33]; /* 32 digits + implied sign */
6187 BYTE result[16]; /* 31-digit packed result */
6188 int i, j; /* Array subscripts */
6189
6190 SS_L(inst, regs, len, b1, addr1, b2, addr2);
6191
6192 /* Program check if operand length (len+1) exceeds 32 bytes */
6193 if (len > 31)
6194 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
6195
6196 /* Fetch the second operand and right justify */
6197 memset (source, 0, sizeof(source));
6198 ARCH_DEP(vfetchc) ( source+31-len, len, addr2, b2, regs );
6199
6200 /* Append an implied plus sign */
6201 source[32] = 0x0C;
6202
6203 /* Pack the rightmost 31 digits and sign into the result */
6204 for (i = 1, j = 0; j < 16; i += 2, j++)
6205 {
6206 result[j] = (source[i] << 4) | (source[i+1] & 0x0F);
6207 }
6208
6209 /* Store 16-byte packed decimal result at operand address */
6210 ARCH_DEP(vstorec) ( result, 16-1, addr1, b1, regs );
6211
6212 } /* end DEF_INST(pack_ascii) */
6213 #endif /*defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)*/
6214
6215
6216 #if defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)
6217 /*-------------------------------------------------------------------*/
6218 /* E1 PKU - Pack Unicode [SS] */
6219 /*-------------------------------------------------------------------*/
DEF_INST(pack_unicode)6220 DEF_INST(pack_unicode)
6221 {
6222 int len; /* Second operand length */
6223 int b1, b2; /* Base registers */
6224 VADR addr1, addr2; /* Effective addresses */
6225 BYTE source[66]; /* 32 digits + implied sign */
6226 BYTE result[16]; /* 31-digit packed result */
6227 int i, j; /* Array subscripts */
6228
6229 SS_L(inst, regs, len, b1, addr1, b2, addr2);
6230
6231 /* Program check if byte count (len+1) exceeds 64 or is odd */
6232 if (len > 63 || (len & 1) == 0)
6233 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
6234
6235 /* Fetch the second operand and right justify */
6236 memset (source, 0, sizeof(source));
6237 ARCH_DEP(vfetchc) ( source+63-len, len, addr2, b2, regs );
6238
6239 /* Append an implied plus sign */
6240 source[64] = 0x00;
6241 source[65] = 0x0C;
6242
6243 /* Pack the rightmost 31 digits and sign into the result */
6244 for (i = 2, j = 0; j < 16; i += 4, j++)
6245 {
6246 result[j] = (source[i+1] << 4) | (source[i+3] & 0x0F);
6247 }
6248
6249 /* Store 16-byte packed decimal result at operand address */
6250 ARCH_DEP(vstorec) ( result, 16-1, addr1, b1, regs );
6251
6252 } /* end DEF_INST(pack_unicode) */
6253 #endif /*defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)*/
6254
6255
6256 #if defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)
6257 /*-------------------------------------------------------------------*/
6258 /* EA UNPKA - Unpack ASCII [SS] */
6259 /*-------------------------------------------------------------------*/
DEF_INST(unpack_ascii)6260 DEF_INST(unpack_ascii)
6261 {
6262 int len; /* First operand length */
6263 int b1, b2; /* Base registers */
6264 VADR addr1, addr2; /* Effective addresses */
6265 BYTE result[32]; /* 32-digit result */
6266 BYTE source[16]; /* 31-digit packed operand */
6267 int i, j; /* Array subscripts */
6268 int cc; /* Condition code */
6269
6270 SS_L(inst, regs, len, b1, addr1, b2, addr2);
6271
6272 /* Program check if operand length (len+1) exceeds 32 bytes */
6273 if (len > 31)
6274 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
6275
6276 /* Fetch the 16-byte second operand */
6277 ARCH_DEP(vfetchc) ( source, 15, addr2, b2, regs );
6278
6279 /* Set high-order result byte to ASCII zero */
6280 result[0] = 0x30;
6281
6282 /* Unpack remaining 31 digits into the result */
6283 for (j = 1, i = 0; ; i++)
6284 {
6285 result[j++] = (source[i] >> 4) | 0x30;
6286 if (i == 15) break;
6287 result[j++] = (source[i] & 0x0F) | 0x30;
6288 }
6289
6290 /* Store rightmost digits of result at first operand address */
6291 ARCH_DEP(vstorec) ( result+31-len, len, addr1, b1, regs );
6292
6293 /* Set the condition code according to the sign */
6294 switch (source[15] & 0x0F) {
6295 case 0x0A: case 0x0C: case 0x0E: case 0x0F:
6296 cc = 0; break;
6297 case 0x0B: case 0x0D:
6298 cc = 1; break;
6299 default:
6300 cc = 3;
6301 } /* end switch */
6302 regs->psw.cc = cc;
6303
6304 } /* end DEF_INST(unpack_ascii) */
6305 #endif /*defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)*/
6306
6307
6308 #if defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)
6309 /*-------------------------------------------------------------------*/
6310 /* E2 UNPKU - Unpack Unicode [SS] */
6311 /*-------------------------------------------------------------------*/
DEF_INST(unpack_unicode)6312 DEF_INST(unpack_unicode)
6313 {
6314 int len; /* First operand length */
6315 int b1, b2; /* Base registers */
6316 VADR addr1, addr2; /* Effective addresses */
6317 BYTE result[64]; /* 32-digit result */
6318 BYTE source[16]; /* 31-digit packed operand */
6319 int i, j; /* Array subscripts */
6320 int cc; /* Condition code */
6321
6322 SS_L(inst, regs, len, b1, addr1, b2, addr2);
6323
6324 /* Program check if byte count (len+1) exceeds 64 or is odd */
6325 if (len > 63 || (len & 1) == 0)
6326 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
6327
6328 /* Fetch the 16-byte second operand */
6329 ARCH_DEP(vfetchc) ( source, 15, addr2, b2, regs );
6330
6331 /* Set high-order result pair to Unicode zero */
6332 result[0] = 0x00;
6333 result[1] = 0x30;
6334
6335 /* Unpack remaining 31 digits into the result */
6336 for (j = 2, i = 0; ; i++)
6337 {
6338 result[j++] = 0x00;
6339 result[j++] = (source[i] >> 4) | 0x30;
6340 if (i == 15) break;
6341 result[j++] = 0x00;
6342 result[j++] = (source[i] & 0x0F) | 0x30;
6343 }
6344
6345 /* Store rightmost digits of result at first operand address */
6346 ARCH_DEP(vstorec) ( result+63-len, len, addr1, b1, regs );
6347
6348 /* Set the condition code according to the sign */
6349 switch (source[15] & 0x0F) {
6350 case 0x0A: case 0x0C: case 0x0E: case 0x0F:
6351 cc = 0; break;
6352 case 0x0B: case 0x0D:
6353 cc = 1; break;
6354 default:
6355 cc = 3;
6356 } /* end switch */
6357 regs->psw.cc = cc;
6358
6359 } /* end DEF_INST(unpack_unicode) */
6360 #endif /*defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)*/
6361
6362
6363 #if defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)
6364 /*-------------------------------------------------------------------*/
6365 /* B993 TROO - Translate One to One [RRF] */
6366 /*-------------------------------------------------------------------*/
DEF_INST(translate_one_to_one)6367 DEF_INST(translate_one_to_one)
6368 {
6369 int r1, r2; /* Values of R fields */
6370 VADR addr1, addr2, trtab; /* Effective addresses */
6371 GREG len;
6372 BYTE svalue, dvalue, tvalue;
6373 #ifdef FEATURE_ETF2_ENHANCEMENT
6374 int tccc; /* Test-Character-Comparison Control */
6375 #endif
6376
6377 // NOTE: it's faster to decode with RRE format
6378 // and then to handle the 'tccc' flag separately...
6379
6380 // RRF_M(inst, regs, r1, r2, tccc);
6381 RRE(inst, regs, r1, r2);
6382
6383 ODD_CHECK(r1, regs);
6384
6385 #ifdef FEATURE_ETF2_ENHANCEMENT
6386 /* Set Test-Character-Comparison Control */
6387 if(inst[2] & 0x10)
6388 tccc = 1;
6389 else
6390 tccc = 0;
6391 #endif
6392
6393 /* Determine length */
6394 len = GR_A(r1 + 1,regs);
6395
6396 /* Determine destination, source and translate table address */
6397 addr1 = regs->GR(r1) & ADDRESS_MAXWRAP(regs);
6398 addr2 = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
6399 trtab = regs->GR(1) & ADDRESS_MAXWRAP(regs) & ~7;
6400
6401 /* Determine test value */
6402 tvalue = regs->GR_LHLCL(0);
6403
6404 /* Preset condition code to zero in case of zero length */
6405 if(!len)
6406 regs->psw.cc = 0;
6407
6408 while(len)
6409 {
6410 svalue = ARCH_DEP(vfetchb) (addr2, r2, regs);
6411
6412 /* Fetch value from translation table */
6413 dvalue = ARCH_DEP(vfetchb) (((trtab + svalue)
6414 & ADDRESS_MAXWRAP(regs) ), 1, regs);
6415
6416 #ifdef FEATURE_ETF2_ENHANCEMENT
6417 /* Test-Character-Comparison Control */
6418 if(!tccc)
6419 {
6420 #endif
6421 /* If the testvalue was found then exit with cc1 */
6422 if(dvalue == tvalue)
6423 {
6424 regs->psw.cc = 1;
6425 break;
6426 }
6427 #ifdef FEATURE_ETF2_ENHANCEMENT
6428 }
6429 #endif
6430
6431 /* Store destination value */
6432 ARCH_DEP(vstoreb) (dvalue, addr1, r1, regs);
6433
6434 /* Adjust source addr, destination addr and length */
6435 addr1++; addr1 &= ADDRESS_MAXWRAP(regs);
6436 addr2++; addr2 &= ADDRESS_MAXWRAP(regs);
6437 len--;
6438
6439 /* Update the registers */
6440 SET_GR_A(r1, regs, addr1);
6441 SET_GR_A(r1 + 1, regs, len);
6442 SET_GR_A(r2, regs, addr2);
6443
6444 /* Set cc0 when all values have been processed */
6445 regs->psw.cc = len ? 3 : 0;
6446
6447 /* exit on the cpu determined number of bytes */
6448 if((len != 0) && (!(addr1 & 0xfff) || !(addr2 & 0xfff)))
6449 break;
6450
6451 } /* end while */
6452
6453 } /* end DEF_INST(translate_one_to_one) */
6454 #endif /*defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)*/
6455
6456
6457 #if defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)
6458 /*-------------------------------------------------------------------*/
6459 /* B992 TROT - Translate One to Two [RRF] */
6460 /*-------------------------------------------------------------------*/
DEF_INST(translate_one_to_two)6461 DEF_INST(translate_one_to_two)
6462 {
6463 int r1, r2; /* Values of R fields */
6464 VADR addr1, addr2, trtab; /* Effective addresses */
6465 GREG len;
6466 BYTE svalue;
6467 U16 dvalue, tvalue;
6468 #ifdef FEATURE_ETF2_ENHANCEMENT
6469 int tccc; /* Test-Character-Comparison Control */
6470 #endif
6471
6472 // NOTE: it's faster to decode with RRE format
6473 // and then to handle the 'tccc' flag separately...
6474
6475 // RRF_M(inst, regs, r1, r2, tccc);
6476 RRE(inst, regs, r1, r2);
6477
6478 ODD_CHECK(r1, regs);
6479
6480 #ifdef FEATURE_ETF2_ENHANCEMENT
6481 /* Set Test-Character-Comparison Control */
6482 if(inst[2] & 0x10)
6483 tccc = 1;
6484 else
6485 tccc = 0;
6486 #endif
6487
6488 /* Determine length */
6489 len = GR_A(r1 + 1,regs);
6490
6491 /* Determine destination, source and translate table address */
6492 addr1 = regs->GR(r1) & ADDRESS_MAXWRAP(regs);
6493 addr2 = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
6494 trtab = regs->GR(1) & ADDRESS_MAXWRAP(regs) & ~7;
6495
6496 /* Determine test value */
6497 tvalue = regs->GR_LHL(0);
6498
6499 /* Preset condition code to zero in case of zero length */
6500 if(!len)
6501 regs->psw.cc = 0;
6502
6503 while(len)
6504 {
6505 svalue = ARCH_DEP(vfetchb) (addr2, r2, regs);
6506
6507 /* Fetch value from translation table */
6508 dvalue = ARCH_DEP(vfetch2) (((trtab + (svalue << 1))
6509 & ADDRESS_MAXWRAP(regs) ), 1, regs);
6510
6511 #ifdef FEATURE_ETF2_ENHANCEMENT
6512 /* Test-Character-Comparison Control */
6513 if(!tccc)
6514 {
6515 #endif
6516 /* If the testvalue was found then exit with cc1 */
6517 if(dvalue == tvalue)
6518 {
6519 regs->psw.cc = 1;
6520 break;
6521 }
6522 #ifdef FEATURE_ETF2_ENHANCEMENT
6523 }
6524 #endif
6525
6526 /* Store destination value */
6527 ARCH_DEP(vstore2) (dvalue, addr1, r1, regs);
6528
6529 /* Adjust source addr, destination addr and length */
6530 addr1 += 2; addr1 &= ADDRESS_MAXWRAP(regs);
6531 addr2++; addr2 &= ADDRESS_MAXWRAP(regs);
6532 len--;
6533
6534 /* Update the registers */
6535 SET_GR_A(r1, regs, addr1);
6536 SET_GR_A(r1 + 1, regs, len);
6537 SET_GR_A(r2, regs, addr2);
6538
6539 /* Set cc0 when all values have been processed */
6540 regs->psw.cc = len ? 3 : 0;
6541
6542 /* exit on the cpu determined number of bytes */
6543 if((len != 0) && (!(addr1 & 0xfff) || !(addr2 & 0xfff)))
6544 break;
6545
6546 } /* end while */
6547
6548 } /* end DEF_INST(translate_one_to_two) */
6549 #endif /*defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)*/
6550
6551
6552 #if defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)
6553 /*-------------------------------------------------------------------*/
6554 /* B991 TRTO - Translate Two to One [RRF] */
6555 /*-------------------------------------------------------------------*/
DEF_INST(translate_two_to_one)6556 DEF_INST(translate_two_to_one)
6557 {
6558 int r1, r2; /* Values of R fields */
6559 VADR addr1, addr2, trtab; /* Effective addresses */
6560 GREG len;
6561 U16 svalue;
6562 BYTE dvalue, tvalue;
6563 #ifdef FEATURE_ETF2_ENHANCEMENT
6564 int tccc; /* Test-Character-Comparison Control */
6565 #endif
6566
6567 // NOTE: it's faster to decode with RRE format
6568 // and then to handle the 'tccc' flag separately...
6569
6570 // RRF_M(inst, regs, r1, r2, tccc);
6571 RRE(inst, regs, r1, r2);
6572
6573 ODD_CHECK(r1, regs);
6574
6575 #ifdef FEATURE_ETF2_ENHANCEMENT
6576 /* Set Test-Character-Comparison Control */
6577 if(inst[2] & 0x10)
6578 tccc = 1;
6579 else
6580 tccc = 0;
6581 #endif
6582
6583 /* Determine length */
6584 len = GR_A(r1 + 1,regs);
6585
6586 ODD_CHECK(len, regs);
6587
6588 /* Determine destination, source and translate table address */
6589 addr1 = regs->GR(r1) & ADDRESS_MAXWRAP(regs);
6590 addr2 = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
6591 #ifdef FEATURE_ETF2_ENHANCEMENT
6592 trtab = regs->GR(1) & ADDRESS_MAXWRAP(regs) & ~7;
6593 #else
6594 trtab = regs->GR(1) & ADDRESS_MAXWRAP(regs) & ~0xfff;
6595 #endif
6596
6597 /* Determine test value */
6598 tvalue = regs->GR_LHLCL(0);
6599
6600 /* Preset condition code to zero in case of zero length */
6601 if(!len)
6602 regs->psw.cc = 0;
6603
6604 while(len)
6605 {
6606 svalue = ARCH_DEP(vfetch2) (addr2, r2, regs);
6607
6608 /* Fetch value from translation table */
6609 dvalue = ARCH_DEP(vfetchb) (((trtab + svalue)
6610 & ADDRESS_MAXWRAP(regs) ), 1, regs);
6611
6612 #ifdef FEATURE_ETF2_ENHANCEMENT
6613 /* Test-Character-Comparison Control */
6614 if(!tccc)
6615 {
6616 #endif
6617 /* If the testvalue was found then exit with cc1 */
6618 if(dvalue == tvalue)
6619 {
6620 regs->psw.cc = 1;
6621 break;
6622 }
6623 #ifdef FEATURE_ETF2_ENHANCEMENT
6624 }
6625 #endif
6626
6627 /* Store destination value */
6628 ARCH_DEP(vstoreb) (dvalue, addr1, r1, regs);
6629
6630 /* Adjust source addr, destination addr and length */
6631 addr1++; addr1 &= ADDRESS_MAXWRAP(regs);
6632 addr2 += 2; addr2 &= ADDRESS_MAXWRAP(regs);
6633 len -= 2;
6634
6635 /* Update the registers */
6636 SET_GR_A(r1, regs, addr1);
6637 SET_GR_A(r1 + 1, regs, len);
6638 SET_GR_A(r2, regs, addr2);
6639
6640 /* Set cc0 when all values have been processed */
6641 regs->psw.cc = len ? 3 : 0;
6642
6643 /* exit on the cpu determined number of bytes */
6644 if((len != 0) && (!(addr1 & 0xfff) || !(addr2 & 0xfff)))
6645 break;
6646
6647 } /* end while */
6648
6649 } /* end DEF_INST(translate_two_to_one) */
6650 #endif /*defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)*/
6651
6652
6653 #if defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)
6654 /*-------------------------------------------------------------------*/
6655 /* B990 TRTT - Translate Two to Two [RRF] */
6656 /*-------------------------------------------------------------------*/
DEF_INST(translate_two_to_two)6657 DEF_INST(translate_two_to_two)
6658 {
6659 int r1, r2; /* Values of R fields */
6660 VADR addr1, addr2, trtab; /* Effective addresses */
6661 GREG len;
6662 U16 svalue, dvalue, tvalue;
6663 #ifdef FEATURE_ETF2_ENHANCEMENT
6664 int tccc; /* Test-Character-Comparison Control */
6665 #endif
6666
6667 // NOTE: it's faster to decode with RRE format
6668 // and then to handle the 'tccc' flag separately...
6669
6670 // RRF_M(inst, regs, r1, r2, tccc);
6671 RRE(inst, regs, r1, r2);
6672
6673 ODD_CHECK(r1, regs);
6674
6675 #ifdef FEATURE_ETF2_ENHANCEMENT
6676 /* Set Test-Character-Comparison Control */
6677 if(inst[2] & 0x10)
6678 tccc = 1;
6679 else
6680 tccc = 0;
6681 #endif
6682
6683 /* Determine length */
6684 len = GR_A(r1 + 1,regs);
6685
6686 ODD_CHECK(len, regs);
6687
6688 /* Determine destination, source and translate table address */
6689 addr1 = regs->GR(r1) & ADDRESS_MAXWRAP(regs);
6690 addr2 = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
6691 #ifdef FEATURE_ETF2_ENHANCEMENT
6692 trtab = regs->GR(1) & ADDRESS_MAXWRAP(regs) & ~7;
6693 #else
6694 trtab = regs->GR(1) & ADDRESS_MAXWRAP(regs) & ~0xfff;
6695 #endif
6696
6697 /* Determine test value */
6698 tvalue = regs->GR_LHL(0);
6699
6700 /* Preset condition code to zero in case of zero length */
6701 if(!len)
6702 regs->psw.cc = 0;
6703
6704 while(len)
6705 {
6706 svalue = ARCH_DEP(vfetch2) (addr2, r2, regs);
6707
6708 /* Fetch value from translation table */
6709 dvalue = ARCH_DEP(vfetch2) (((trtab + (svalue << 1))
6710 & ADDRESS_MAXWRAP(regs) ), 1, regs);
6711
6712 #ifdef FEATURE_ETF2_ENHANCEMENT
6713 /* Test-Character-Comparison Control */
6714 if(!tccc)
6715 {
6716 #endif
6717 /* If the testvalue was found then exit with cc1 */
6718 if(dvalue == tvalue)
6719 {
6720 regs->psw.cc = 1;
6721 break;
6722 }
6723 #ifdef FEATURE_ETF2_ENHANCEMENT
6724 }
6725 #endif
6726
6727 /* Store destination value */
6728 ARCH_DEP(vstore2) (dvalue, addr1, r1, regs);
6729
6730 /* Adjust source addr, destination addr and length */
6731 addr1 += 2; addr1 &= ADDRESS_MAXWRAP(regs);
6732 addr2 += 2; addr2 &= ADDRESS_MAXWRAP(regs);
6733 len -= 2;
6734
6735 /* Update the registers */
6736 SET_GR_A(r1, regs, addr1);
6737 SET_GR_A(r1 + 1, regs, len);
6738 SET_GR_A(r2, regs, addr2);
6739
6740 /* Set cc0 when all values have been processed */
6741 regs->psw.cc = len ? 3 : 0;
6742
6743 /* exit on the cpu determined number of bytes */
6744 if((len != 0) && (!(addr1 & 0xfff) || !(addr2 & 0xfff)))
6745 break;
6746
6747 } /* end while */
6748
6749 } /* end DEF_INST(translate_two_to_two) */
6750 #endif /*defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)*/
6751
6752
6753 #if defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)
6754 /*-------------------------------------------------------------------*/
6755 /* EB8E MVCLU - Move Long Unicode [RSY] */
6756 /*-------------------------------------------------------------------*/
DEF_INST(move_long_unicode)6757 DEF_INST(move_long_unicode)
6758 {
6759 int r1, r3; /* Register numbers */
6760 int b2; /* effective address base */
6761 VADR effective_addr2; /* effective address */
6762 int i; /* Loop counter */
6763 int cc; /* Condition code */
6764 VADR addr1, addr3; /* Operand addresses */
6765 GREG len1, len3; /* Operand lengths */
6766 U16 odbyte; /* Operand double byte */
6767 U16 pad; /* Padding double byte */
6768 int cpu_length; /* cpu determined length */
6769
6770 RSY(inst, regs, r1, r3, b2, effective_addr2);
6771
6772 ODD2_CHECK(r1, r3, regs);
6773
6774 /* Load operand lengths from bits 0-31 of R1+1 and R3+1 */
6775 len1 = GR_A(r1 + 1, regs);
6776 len3 = GR_A(r3 + 1, regs);
6777
6778 ODD2_CHECK(len1, len3, regs);
6779
6780 /* Load padding doublebyte from bits 48-63 of effective address */
6781 pad = effective_addr2 & 0xFFFF;
6782
6783 /* Determine the destination and source addresses */
6784 addr1 = regs->GR(r1) & ADDRESS_MAXWRAP(regs);
6785 addr3 = regs->GR(r3) & ADDRESS_MAXWRAP(regs);
6786
6787 /* set cpu_length as shortest distance to new page */
6788 if ((addr1 & 0xFFF) > (addr3 & 0xFFF))
6789 cpu_length = 0x1000 - (addr1 & 0xFFF);
6790 else
6791 cpu_length = 0x1000 - (addr3 & 0xFFF);
6792
6793 /* Set the condition code according to the lengths */
6794 cc = (len1 < len3) ? 1 : (len1 > len3) ? 2 : 0;
6795
6796 /* Process operands from left to right */
6797 for (i = 0; len1 > 0; i += 2)
6798 {
6799 /* If cpu determined length has been moved, exit with cc=3 */
6800 if (i >= cpu_length)
6801 {
6802 cc = 3;
6803 break;
6804 }
6805
6806 /* Fetch byte from source operand, or use padding double byte */
6807 if (len3 > 0)
6808 {
6809 odbyte = ARCH_DEP(vfetch2) ( addr3, r3, regs );
6810 addr3 += 2;
6811 addr3 &= ADDRESS_MAXWRAP(regs);
6812 len3 -= 2;
6813 }
6814 else
6815 odbyte = pad;
6816
6817 /* Store the double byte in the destination operand */
6818 ARCH_DEP(vstore2) ( odbyte, addr1, r1, regs );
6819 addr1 +=2;
6820 addr1 &= ADDRESS_MAXWRAP(regs);
6821 len1 -= 2;
6822
6823 /* Update the registers */
6824 SET_GR_A(r1, regs, addr1);
6825 SET_GR_A(r1 + 1, regs, len1);
6826 SET_GR_A(r3, regs, addr3);
6827 SET_GR_A(r3 + 1, regs, len3);
6828
6829 } /* end for(i) */
6830
6831 regs->psw.cc = cc;
6832
6833 } /* end DEF_INST(move_long_unicode) */
6834 #endif /*defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)*/
6835
6836
6837 #if defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)
6838 /*-------------------------------------------------------------------*/
6839 /* EB8F CLCLU - Compare Logical Long Unicode [RSY] */
6840 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_long_unicode)6841 DEF_INST(compare_logical_long_unicode)
6842 {
6843 int r1, r3; /* Register numbers */
6844 int b2; /* effective address base */
6845 VADR effective_addr2; /* effective address */
6846 int i; /* Loop counter */
6847 int cc = 0; /* Condition code */
6848 VADR addr1, addr3; /* Operand addresses */
6849 GREG len1, len3; /* Operand lengths */
6850 U16 dbyte1, dbyte3; /* Operand double bytes */
6851 U16 pad; /* Padding double byte */
6852 int cpu_length; /* cpu determined length */
6853
6854 RSY(inst, regs, r1, r3, b2, effective_addr2);
6855
6856 ODD2_CHECK(r1, r3, regs);
6857
6858 /* Load operand lengths from bits 0-31 of R1+1 and R3+1 */
6859 len1 = GR_A(r1 + 1, regs);
6860 len3 = GR_A(r3 + 1, regs);
6861
6862 ODD2_CHECK(len1, len3, regs);
6863
6864 /* Load padding doublebyte from bits 48-64 of effective address */
6865 pad = effective_addr2 & 0xFFFF;
6866
6867 /* Determine the destination and source addresses */
6868 addr1 = regs->GR(r1) & ADDRESS_MAXWRAP(regs);
6869 addr3 = regs->GR(r3) & ADDRESS_MAXWRAP(regs);
6870
6871 /* set cpu_length as shortest distance to new page */
6872 if ((addr1 & 0xFFF) > (addr3 & 0xFFF))
6873 cpu_length = 0x1000 - (addr1 & 0xFFF);
6874 else
6875 cpu_length = 0x1000 - (addr3 & 0xFFF);
6876
6877 /* Process operands from left to right */
6878 for (i = 0; len1 > 0 || len3 > 0 ; i += 2)
6879 {
6880 /* If max 4096 bytes have been compared, exit with cc=3 */
6881 if (i >= cpu_length)
6882 {
6883 cc = 3;
6884 break;
6885 }
6886
6887 /* Fetch a byte from each operand, or use padding double byte */
6888 dbyte1 = (len1 > 0) ? ARCH_DEP(vfetch2) (addr1, r1, regs) : pad;
6889 dbyte3 = (len3 > 0) ? ARCH_DEP(vfetch2) (addr3, r3, regs) : pad;
6890
6891 /* Compare operand bytes, set condition code if unequal */
6892 if (dbyte1 != dbyte3)
6893 {
6894 cc = (dbyte1 < dbyte3) ? 1 : 2;
6895 break;
6896 } /* end if */
6897
6898 /* Update the first operand address and length */
6899 if (len1 > 0)
6900 {
6901 addr1 += 2;
6902 addr1 &= ADDRESS_MAXWRAP(regs);
6903 len1 -= 2;
6904 }
6905
6906 /* Update the second operand address and length */
6907 if (len3 > 0)
6908 {
6909 addr3 += 2;
6910 addr3 &= ADDRESS_MAXWRAP(regs);
6911 len3 -= 2;
6912 }
6913
6914 } /* end for(i) */
6915
6916 /* Update the registers */
6917 SET_GR_A(r1, regs, addr1);
6918 SET_GR_A(r1 + 1, regs, len1);
6919 SET_GR_A(r3, regs, addr3);
6920 SET_GR_A(r3 + 1, regs, len3);
6921
6922 regs->psw.cc = cc;
6923
6924 } /* end DEF_INST(compare_logical_long_unicode) */
6925 #endif /*defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_2)*/
6926
6927
6928 #if defined(FEATURE_LONG_DISPLACEMENT)
6929 /*-------------------------------------------------------------------*/
6930 /* E376 LB - Load Byte [RXY] */
6931 /*-------------------------------------------------------------------*/
DEF_INST(load_byte)6932 DEF_INST(load_byte)
6933 {
6934 int r1; /* Value of R field */
6935 int b2; /* Base of effective addr */
6936 VADR effective_addr2; /* Effective address */
6937
6938 RXY(inst, regs, r1, b2, effective_addr2);
6939
6940 /* Load sign-extended byte from operand address */
6941 regs->GR_L(r1) = (S8)ARCH_DEP(vfetchb) ( effective_addr2, b2, regs );
6942
6943 } /* end DEF_INST(load_byte) */
6944 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
6945
6946
6947 #if defined(FEATURE_LONG_DISPLACEMENT)
6948 /*-------------------------------------------------------------------*/
6949 /* E377 LGB - Load Byte Long [RXY] */
6950 /*-------------------------------------------------------------------*/
DEF_INST(load_byte_long)6951 DEF_INST(load_byte_long)
6952 {
6953 int r1; /* Value of R field */
6954 int b2; /* Base of effective addr */
6955 VADR effective_addr2; /* Effective address */
6956
6957 RXY(inst, regs, r1, b2, effective_addr2);
6958
6959 /* Load sign-extended byte from operand address */
6960 regs->GR_G(r1) = (S8)ARCH_DEP(vfetchb) ( effective_addr2, b2, regs );
6961
6962 } /* end DEF_INST(load_byte_long) */
6963 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
6964
6965
6966 #if defined(FEATURE_LONG_DISPLACEMENT)
6967 /*-------------------------------------------------------------------*/
6968 /* E35A AY - Add (Long Displacement) [RXY] */
6969 /*-------------------------------------------------------------------*/
DEF_INST(add_y)6970 DEF_INST(add_y)
6971 {
6972 int r1; /* Values of R fields */
6973 int b2; /* Base of effective addr */
6974 VADR effective_addr2; /* Effective address */
6975 U32 n; /* 32-bit operand values */
6976
6977 RXY(inst, regs, r1, b2, effective_addr2);
6978
6979 /* Load second operand from operand address */
6980 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
6981
6982 /* Add signed operands and set condition code */
6983 regs->psw.cc =
6984 add_signed (&(regs->GR_L(r1)),
6985 regs->GR_L(r1),
6986 n);
6987
6988 /* Program check if fixed-point overflow */
6989 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
6990 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
6991
6992 } /* end DEF_INST(add_y) */
6993 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
6994
6995
6996 #if defined(FEATURE_LONG_DISPLACEMENT)
6997 /*-------------------------------------------------------------------*/
6998 /* E37A AHY - Add Halfword (Long Displacement) [RXY] */
6999 /*-------------------------------------------------------------------*/
DEF_INST(add_halfword_y)7000 DEF_INST(add_halfword_y)
7001 {
7002 int r1; /* Value of R field */
7003 int b2; /* Base of effective addr */
7004 VADR effective_addr2; /* Effective address */
7005 S32 n; /* 32-bit operand values */
7006
7007 RXY(inst, regs, r1, b2, effective_addr2);
7008
7009 /* Load 2 bytes from operand address */
7010 n = (S16)ARCH_DEP(vfetch2) ( effective_addr2, b2, regs );
7011
7012 /* Add signed operands and set condition code */
7013 regs->psw.cc =
7014 add_signed (&(regs->GR_L(r1)),
7015 regs->GR_L(r1),
7016 (U32)n);
7017
7018 /* Program check if fixed-point overflow */
7019 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
7020 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
7021
7022 } /* end DEF_INST(add_halfword_y) */
7023 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7024
7025
7026 #if defined(FEATURE_LONG_DISPLACEMENT)
7027 /*-------------------------------------------------------------------*/
7028 /* E35E ALY - Add Logical (Long Displacement) [RXY] */
7029 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_y)7030 DEF_INST(add_logical_y)
7031 {
7032 int r1; /* Value of R field */
7033 int b2; /* Base of effective addr */
7034 VADR effective_addr2; /* Effective address */
7035 U32 n; /* 32-bit operand values */
7036
7037 RXY(inst, regs, r1, b2, effective_addr2);
7038
7039 /* Load second operand from operand address */
7040 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
7041
7042 /* Add signed operands and set condition code */
7043 regs->psw.cc =
7044 add_logical (&(regs->GR_L(r1)),
7045 regs->GR_L(r1),
7046 n);
7047
7048 } /* end DEF_INST(add_logical_y) */
7049 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7050
7051
7052 #if defined(FEATURE_LONG_DISPLACEMENT)
7053 /*-------------------------------------------------------------------*/
7054 /* EB54 NIY - And Immediate (Long Displacement) [SIY] */
7055 /*-------------------------------------------------------------------*/
DEF_INST(and_immediate_y)7056 DEF_INST(and_immediate_y)
7057 {
7058 BYTE i2; /* Immediate byte of opcode */
7059 int b1; /* Base of effective addr */
7060 VADR effective_addr1; /* Effective address */
7061 BYTE rbyte; /* Result byte */
7062
7063 SIY(inst, regs, i2, b1, effective_addr1);
7064
7065 /* Fetch byte from operand address */
7066 rbyte = ARCH_DEP(vfetchb) ( effective_addr1, b1, regs );
7067
7068 /* AND with immediate operand */
7069 rbyte &= i2;
7070
7071 /* Store result at operand address */
7072 ARCH_DEP(vstoreb) ( rbyte, effective_addr1, b1, regs );
7073
7074 /* Set condition code */
7075 regs->psw.cc = rbyte ? 1 : 0;
7076
7077 } /* end DEF_INST(and_immediate_y) */
7078 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7079
7080
7081 #if defined(FEATURE_LONG_DISPLACEMENT)
7082 /*-------------------------------------------------------------------*/
7083 /* E354 NY - And (Long Displacement) [RXY] */
7084 /*-------------------------------------------------------------------*/
DEF_INST(and_y)7085 DEF_INST(and_y)
7086 {
7087 int r1; /* Value of R field */
7088 int b2; /* Base of effective addr */
7089 VADR effective_addr2; /* Effective address */
7090 U32 n; /* 32-bit operand values */
7091
7092 RXY(inst, regs, r1, b2, effective_addr2);
7093
7094 /* Load second operand from operand address */
7095 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
7096
7097 /* AND second operand with first and set condition code */
7098 regs->psw.cc = ( regs->GR_L(r1) &= n ) ? 1 : 0;
7099
7100 } /* end DEF_INST(and_y) */
7101 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7102
7103
7104 #if defined(FEATURE_LONG_DISPLACEMENT)
7105 /*-------------------------------------------------------------------*/
7106 /* E359 CY - Compare (Long Displacement) [RXY] */
7107 /*-------------------------------------------------------------------*/
DEF_INST(compare_y)7108 DEF_INST(compare_y)
7109 {
7110 int r1; /* Values of R fields */
7111 int b2; /* Base of effective addr */
7112 VADR effective_addr2; /* Effective address */
7113 U32 n; /* 32-bit operand values */
7114
7115 RXY(inst, regs, r1, b2, effective_addr2);
7116
7117 /* Load second operand from operand address */
7118 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
7119
7120 /* Compare signed operands and set condition code */
7121 regs->psw.cc =
7122 (S32)regs->GR_L(r1) < (S32)n ? 1 :
7123 (S32)regs->GR_L(r1) > (S32)n ? 2 : 0;
7124
7125 } /* end DEF_INST(compare_y) */
7126 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7127
7128
7129 #if defined(FEATURE_LONG_DISPLACEMENT)
7130 /*-------------------------------------------------------------------*/
7131 /* E379 CHY - Compare Halfword (Long Displacement) [RXY] */
7132 /*-------------------------------------------------------------------*/
DEF_INST(compare_halfword_y)7133 DEF_INST(compare_halfword_y)
7134 {
7135 int r1; /* Values of R fields */
7136 int b2; /* Base of effective addr */
7137 VADR effective_addr2; /* Effective address */
7138 S32 n; /* 32-bit operand values */
7139
7140 RXY(inst, regs, r1, b2, effective_addr2);
7141
7142 /* Load rightmost 2 bytes of comparand from operand address */
7143 n = (S16)ARCH_DEP(vfetch2) ( effective_addr2, b2, regs );
7144
7145 /* Compare signed operands and set condition code */
7146 regs->psw.cc =
7147 (S32)regs->GR_L(r1) < n ? 1 :
7148 (S32)regs->GR_L(r1) > n ? 2 : 0;
7149
7150 } /* end DEF_INST(compare_halfword_y) */
7151 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7152
7153
7154 #if defined(FEATURE_LONG_DISPLACEMENT)
7155 /*-------------------------------------------------------------------*/
7156 /* E355 CLY - Compare Logical (Long Displacement) [RXY] */
7157 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_y)7158 DEF_INST(compare_logical_y)
7159 {
7160 int r1; /* Values of R fields */
7161 int b2; /* Base of effective addr */
7162 VADR effective_addr2; /* Effective address */
7163 U32 n; /* 32-bit operand values */
7164
7165 RXY(inst, regs, r1, b2, effective_addr2);
7166
7167 /* Load second operand from operand address */
7168 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
7169
7170 /* Compare unsigned operands and set condition code */
7171 regs->psw.cc = regs->GR_L(r1) < n ? 1 :
7172 regs->GR_L(r1) > n ? 2 : 0;
7173
7174 } /* end DEF_INST(compare_logical_y) */
7175 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7176
7177
7178 #if defined(FEATURE_LONG_DISPLACEMENT)
7179 /*-------------------------------------------------------------------*/
7180 /* EB55 CLIY - Compare Logical Immediate (Long Displacement) [SIY] */
7181 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_immediate_y)7182 DEF_INST(compare_logical_immediate_y)
7183 {
7184 BYTE i2; /* Immediate byte */
7185 int b1; /* Base of effective addr */
7186 VADR effective_addr1; /* Effective address */
7187 BYTE cbyte; /* Compare byte */
7188
7189 SIY(inst, regs, i2, b1, effective_addr1);
7190
7191 /* Fetch byte from operand address */
7192 cbyte = ARCH_DEP(vfetchb) ( effective_addr1, b1, regs );
7193
7194 /* Compare with immediate operand and set condition code */
7195 regs->psw.cc = (cbyte < i2) ? 1 :
7196 (cbyte > i2) ? 2 : 0;
7197
7198 } /* end DEF_INST(compare_logical_immediate_y) */
7199 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7200
7201
7202 #if defined(FEATURE_LONG_DISPLACEMENT)
7203 /*-------------------------------------------------------------------*/
7204 /* EB21 CLMY - Compare Logical Characters under Mask Long Disp[RSY] */
7205 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_characters_under_mask_y)7206 DEF_INST(compare_logical_characters_under_mask_y)
7207 {
7208 int r1, r3; /* Register numbers */
7209 int b2; /* effective address base */
7210 VADR effective_addr2; /* effective address */
7211 int i, j; /* Integer work areas */
7212 int cc = 0; /* Condition code */
7213 BYTE rbyte[4], /* Register bytes */
7214 vbyte; /* Virtual storage byte */
7215
7216 RSY(inst, regs, r1, r3, b2, effective_addr2);
7217
7218 /* Set register bytes by mask */
7219 i = 0;
7220 if (r3 & 0x8) rbyte[i++] = (regs->GR_L(r1) >> 24) & 0xFF;
7221 if (r3 & 0x4) rbyte[i++] = (regs->GR_L(r1) >> 16) & 0xFF;
7222 if (r3 & 0x2) rbyte[i++] = (regs->GR_L(r1) >> 8) & 0xFF;
7223 if (r3 & 0x1) rbyte[i++] = (regs->GR_L(r1) ) & 0xFF;
7224
7225 /* Perform access check if mask is 0 */
7226 if (!r3) ARCH_DEP(vfetchb) (effective_addr2, b2, regs);
7227
7228 /* Compare byte by byte */
7229 for (j = 0; j < i && !cc; j++)
7230 {
7231 effective_addr2 &= ADDRESS_MAXWRAP(regs);
7232 vbyte = ARCH_DEP(vfetchb) (effective_addr2++, b2, regs);
7233 if (rbyte[j] != vbyte)
7234 cc = rbyte[j] < vbyte ? 1 : 2;
7235 }
7236
7237 regs->psw.cc = cc;
7238
7239 } /* end DEF_INST(compare_logical_characters_under_mask_y) */
7240 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7241
7242
7243 #if defined(FEATURE_LONG_DISPLACEMENT)
7244 /*-------------------------------------------------------------------*/
7245 /* EB14 CSY - Compare and Swap (Long Displacement) [RSY] */
7246 /*-------------------------------------------------------------------*/
DEF_INST(compare_and_swap_y)7247 DEF_INST(compare_and_swap_y)
7248 {
7249 int r1, r3; /* Register numbers */
7250 int b2; /* effective address base */
7251 VADR effective_addr2; /* effective address */
7252 BYTE *main2; /* mainstor address */
7253 U32 old; /* old value */
7254
7255 RSY(inst, regs, r1, r3, b2, effective_addr2);
7256
7257 FW_CHECK(effective_addr2, regs);
7258
7259 /* Perform serialization before starting operation */
7260 PERFORM_SERIALIZATION (regs);
7261
7262 /* Get operand mainstor address */
7263 main2 = MADDR (effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
7264
7265 /* Get old value */
7266 old = CSWAP32(regs->GR_L(r1));
7267
7268 /* Obtain main-storage access lock */
7269 OBTAIN_MAINLOCK(regs);
7270
7271 /* Attempt to exchange the values */
7272 regs->psw.cc = cmpxchg4 (&old, CSWAP32(regs->GR_L(r3)), main2);
7273
7274 /* Release main-storage access lock */
7275 RELEASE_MAINLOCK(regs);
7276
7277 /* Perform serialization after completing operation */
7278 PERFORM_SERIALIZATION (regs);
7279
7280 if (regs->psw.cc == 1)
7281 {
7282 regs->GR_L(r1) = CSWAP32(old);
7283 #if defined(_FEATURE_SIE)
7284 if(SIE_STATB(regs, IC0, CS1))
7285 {
7286 if( !OPEN_IC_PER(regs) )
7287 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
7288 else
7289 longjmp(regs->progjmp, SIE_INTERCEPT_INSTCOMP);
7290 }
7291 else
7292 #endif /*defined(_FEATURE_SIE)*/
7293 if (sysblk.cpus > 1)
7294 sched_yield();
7295 }
7296
7297 } /* end DEF_INST(compare_and_swap_y) */
7298 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7299
7300
7301 #if defined(FEATURE_LONG_DISPLACEMENT)
7302 /*-------------------------------------------------------------------*/
7303 /* EB31 CDSY - Compare Double and Swap (Long Displacement) [RSY] */
7304 /*-------------------------------------------------------------------*/
DEF_INST(compare_double_and_swap_y)7305 DEF_INST(compare_double_and_swap_y)
7306 {
7307 int r1, r3; /* Register numbers */
7308 int b2; /* effective address base */
7309 VADR effective_addr2; /* effective address */
7310 BYTE *main2; /* mainstor address */
7311 U64 old, new; /* old, new values */
7312
7313 RSY(inst, regs, r1, r3, b2, effective_addr2);
7314
7315 ODD2_CHECK(r1, r3, regs);
7316
7317 DW_CHECK(effective_addr2, regs);
7318
7319 /* Perform serialization before starting operation */
7320 PERFORM_SERIALIZATION (regs);
7321
7322 /* Get operand mainstor address */
7323 main2 = MADDR (effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
7324
7325 /* Get old, new values */
7326 old = CSWAP64(((U64)(regs->GR_L(r1)) << 32) | regs->GR_L(r1+1));
7327 new = CSWAP64(((U64)(regs->GR_L(r3)) << 32) | regs->GR_L(r3+1));
7328
7329 /* Obtain main-storage access lock */
7330 OBTAIN_MAINLOCK(regs);
7331
7332 /* Attempt to exchange the values */
7333 regs->psw.cc = cmpxchg8 (&old, new, main2);
7334
7335 /* Release main-storage access lock */
7336 RELEASE_MAINLOCK(regs);
7337
7338 /* Perform serialization after completing operation */
7339 PERFORM_SERIALIZATION (regs);
7340
7341 if (regs->psw.cc == 1)
7342 {
7343 regs->GR_L(r1) = CSWAP64(old) >> 32;
7344 regs->GR_L(r1+1) = CSWAP64(old) & 0xffffffff;
7345 #if defined(_FEATURE_SIE)
7346 if(SIE_STATB(regs, IC0, CS1))
7347 {
7348 if( !OPEN_IC_PER(regs) )
7349 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
7350 else
7351 longjmp(regs->progjmp, SIE_INTERCEPT_INSTCOMP);
7352 }
7353 else
7354 #endif /*defined(_FEATURE_SIE)*/
7355 if (sysblk.cpus > 1)
7356 sched_yield();
7357 }
7358
7359 } /* end DEF_INST(compare_double_and_swap_y) */
7360 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7361
7362
7363 #if defined(FEATURE_LONG_DISPLACEMENT)
7364 /*-------------------------------------------------------------------*/
7365 /* E306 CVBY - Convert to Binary (Long Displacement) [RXY] */
7366 /*-------------------------------------------------------------------*/
DEF_INST(convert_to_binary_y)7367 DEF_INST(convert_to_binary_y)
7368 {
7369 U64 dreg; /* 64-bit result accumulator */
7370 int r1; /* Value of R1 field */
7371 int b2; /* Base of effective addr */
7372 VADR effective_addr2; /* Effective address */
7373 int ovf; /* 1=overflow */
7374 int dxf; /* 1=data exception */
7375 BYTE dec[8]; /* Packed decimal operand */
7376
7377 RXY(inst, regs, r1, b2, effective_addr2);
7378
7379 /* Fetch 8-byte packed decimal operand */
7380 ARCH_DEP(vfetchc) (dec, 8-1, effective_addr2, b2, regs);
7381
7382 /* Convert 8-byte packed decimal to 64-bit signed binary */
7383 packed_to_binary (dec, 8-1, &dreg, &ovf, &dxf);
7384
7385 /* Data exception if invalid digits or sign */
7386 if (dxf)
7387 {
7388 regs->dxc = DXC_DECIMAL;
7389 regs->program_interrupt (regs, PGM_DATA_EXCEPTION);
7390 }
7391
7392 /* Overflow if result exceeds 31 bits plus sign */
7393 if ((S64)dreg < -2147483648LL || (S64)dreg > 2147483647LL)
7394 ovf = 1;
7395
7396 /* Store low-order 32 bits of result into R1 register */
7397 regs->GR_L(r1) = dreg & 0xFFFFFFFF;
7398
7399 /* Program check if overflow (R1 contains rightmost 32 bits) */
7400 if (ovf)
7401 regs->program_interrupt (regs, PGM_FIXED_POINT_DIVIDE_EXCEPTION);
7402
7403 }
7404 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7405
7406
7407 #if defined(FEATURE_LONG_DISPLACEMENT)
7408 /*-------------------------------------------------------------------*/
7409 /* E326 CVDY - Convert to Decimal (Long Displacement) [RXY] */
7410 /*-------------------------------------------------------------------*/
DEF_INST(convert_to_decimal_y)7411 DEF_INST(convert_to_decimal_y)
7412 {
7413 S64 bin; /* 64-bit signed binary value*/
7414 int r1; /* Value of R1 field */
7415 int b2; /* Base of effective addr */
7416 VADR effective_addr2; /* Effective address */
7417 BYTE dec[16]; /* Packed decimal result */
7418
7419 RXY(inst, regs, r1, b2, effective_addr2);
7420
7421 /* Load value of register and sign-extend to 64 bits */
7422 bin = (S64)((S32)(regs->GR_L(r1)));
7423
7424 /* Convert to 16-byte packed decimal number */
7425 binary_to_packed (bin, dec);
7426
7427 /* Store low 8 bytes of result at operand address */
7428 ARCH_DEP(vstorec) ( dec+8, 8-1, effective_addr2, b2, regs );
7429
7430 } /* end DEF_INST(convert_to_decimal_y) */
7431 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7432
7433
7434 #if defined(FEATURE_LONG_DISPLACEMENT)
7435 /*-------------------------------------------------------------------*/
7436 /* EB57 XIY - Exclusive Or Immediate (Long Displacement) [SIY] */
7437 /*-------------------------------------------------------------------*/
DEF_INST(exclusive_or_immediate_y)7438 DEF_INST(exclusive_or_immediate_y)
7439 {
7440 BYTE i2; /* Immediate operand */
7441 int b1; /* Base of effective addr */
7442 VADR effective_addr1; /* Effective address */
7443 BYTE rbyte; /* Result byte */
7444
7445 SIY(inst, regs, i2, b1, effective_addr1);
7446
7447 /* Fetch byte from operand address */
7448 rbyte = ARCH_DEP(vfetchb) ( effective_addr1, b1, regs );
7449
7450 /* XOR with immediate operand */
7451 rbyte ^= i2;
7452
7453 /* Store result at operand address */
7454 ARCH_DEP(vstoreb) ( rbyte, effective_addr1, b1, regs );
7455
7456 /* Set condition code */
7457 regs->psw.cc = rbyte ? 1 : 0;
7458
7459 } /* end DEF_INST(exclusive_or_immediate_y) */
7460 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7461
7462
7463 #if defined(FEATURE_LONG_DISPLACEMENT)
7464 /*-------------------------------------------------------------------*/
7465 /* E357 XY - Exclusive Or (Long Displacement) [RXY] */
7466 /*-------------------------------------------------------------------*/
DEF_INST(exclusive_or_y)7467 DEF_INST(exclusive_or_y)
7468 {
7469 int r1; /* Values of R fields */
7470 int b2; /* Base of effective addr */
7471 VADR effective_addr2; /* Effective address */
7472 U32 n; /* 32-bit operand values */
7473
7474 RXY(inst, regs, r1, b2, effective_addr2);
7475
7476 /* Load second operand from operand address */
7477 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
7478
7479 /* XOR second operand with first and set condition code */
7480 regs->psw.cc = ( regs->GR_L(r1) ^= n ) ? 1 : 0;
7481
7482 } /* end DEF_INST(exclusive_or_y) */
7483 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7484
7485
7486 #if defined(FEATURE_LONG_DISPLACEMENT)
7487 /*-------------------------------------------------------------------*/
7488 /* E373 ICY - Insert Character (Long Displacement) [RXY] */
7489 /*-------------------------------------------------------------------*/
DEF_INST(insert_character_y)7490 DEF_INST(insert_character_y)
7491 {
7492 int r1; /* Value of R field */
7493 int b2; /* Base of effective addr */
7494 VADR effective_addr2; /* Effective address */
7495
7496 RXY(inst, regs, r1, b2, effective_addr2);
7497
7498 /* Insert character in r1 register */
7499 regs->GR_LHLCL(r1) = ARCH_DEP(vfetchb) ( effective_addr2, b2, regs );
7500
7501 } /* end DEF_INST(insert_character_y) */
7502 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7503
7504
7505 #if defined(FEATURE_LONG_DISPLACEMENT)
7506 /*-------------------------------------------------------------------*/
7507 /* EB81 ICMY - Insert Characters under Mask Long Displacement [RSY] */
7508 /*-------------------------------------------------------------------*/
DEF_INST(insert_characters_under_mask_y)7509 DEF_INST(insert_characters_under_mask_y)
7510 {
7511 int r1, r3; /* Register numbers */
7512 int b2; /* effective address base */
7513 VADR effective_addr2; /* effective address */
7514 int i; /* Integer work area */
7515 BYTE vbyte[4]; /* Fetched storage bytes */
7516 U32 n; /* Fetched value */
7517 static const int /* Length-1 to fetch by mask */
7518 icmylen[16] = {0, 0, 0, 1, 0, 1, 1, 2, 0, 1, 1, 2, 1, 2, 2, 3};
7519 static const unsigned int /* Turn reg bytes off by mask*/
7520 icmymask[16] = {0xFFFFFFFF, 0xFFFFFF00, 0xFFFF00FF, 0xFFFF0000,
7521 0xFF00FFFF, 0xFF00FF00, 0xFF0000FF, 0xFF000000,
7522 0x00FFFFFF, 0x00FFFF00, 0x00FF00FF, 0x00FF0000,
7523 0x0000FFFF, 0x0000FF00, 0x000000FF, 0x00000000};
7524
7525 RSY(inst, regs, r1, r3, b2, effective_addr2);
7526
7527 switch (r3) {
7528
7529 case 15:
7530 /* Optimized case */
7531 regs->GR_L(r1) = ARCH_DEP(vfetch4) (effective_addr2, b2, regs);
7532 regs->psw.cc = regs->GR_L(r1) ? regs->GR_L(r1) & 0x80000000 ?
7533 1 : 2 : 0;
7534 break;
7535
7536 default:
7537 memset (vbyte, 0, 4);
7538 ARCH_DEP(vfetchc)(vbyte, icmylen[r3], effective_addr2, b2, regs);
7539
7540 /* If mask was 0 then we still had to fetch, according to POP.
7541 If so, set the fetched byte to 0 to force zero cc */
7542 if (!r3) vbyte[0] = 0;
7543
7544 n = fetch_fw (vbyte);
7545 regs->psw.cc = n ? n & 0x80000000 ?
7546 1 : 2 : 0;
7547
7548 /* Turn off the reg bytes we are going to set */
7549 regs->GR_L(r1) &= icmymask[r3];
7550
7551 /* Set bytes one at a time according to the mask */
7552 i = 0;
7553 if (r3 & 0x8) regs->GR_L(r1) |= vbyte[i++] << 24;
7554 if (r3 & 0x4) regs->GR_L(r1) |= vbyte[i++] << 16;
7555 if (r3 & 0x2) regs->GR_L(r1) |= vbyte[i++] << 8;
7556 if (r3 & 0x1) regs->GR_L(r1) |= vbyte[i];
7557 break;
7558
7559 } /* switch (r3) */
7560
7561 } /* end DEF_INST(insert_characters_under_mask_y) */
7562 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7563
7564
7565 #if defined(FEATURE_LONG_DISPLACEMENT)
7566 /*-------------------------------------------------------------------*/
7567 /* E358 LY - Load (Long Displacement) [RXY] */
7568 /*-------------------------------------------------------------------*/
DEF_INST(load_y)7569 DEF_INST(load_y)
7570 {
7571 int r1; /* Value of R field */
7572 int b2; /* Base of effective addr */
7573 VADR effective_addr2; /* Effective address */
7574
7575 RXY(inst, regs, r1, b2, effective_addr2);
7576
7577 /* Load R1 register from second operand */
7578 regs->GR_L(r1) = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
7579
7580 } /* end DEF_INST(load_y) */
7581 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7582
7583
7584 #if defined(FEATURE_LONG_DISPLACEMENT)
7585 #if defined(FEATURE_ACCESS_REGISTERS)
7586 /*-------------------------------------------------------------------*/
7587 /* EB9A LAMY - Load Access Multiple (Long Displacement) [RSY] */
7588 /*-------------------------------------------------------------------*/
DEF_INST(load_access_multiple_y)7589 DEF_INST(load_access_multiple_y)
7590 {
7591 int r1, r3; /* Register numbers */
7592 int b2; /* effective address base */
7593 VADR effective_addr2; /* effective address */
7594 int i, m, n; /* Integer work areas */
7595 U32 *p1, *p2 = NULL; /* Mainstor pointers */
7596
7597 RSY(inst, regs, r1, r3, b2, effective_addr2);
7598
7599 FW_CHECK(effective_addr2, regs);
7600
7601 /* Calculate number of regs to load */
7602 n = ((r3 - r1) & 0xF) + 1;
7603
7604 /* Calculate number of words to next boundary */
7605 m = (0x800 - (effective_addr2 & 0x7ff)) >> 2;
7606
7607 /* Address of operand beginning */
7608 p1 = (U32*)MADDR(effective_addr2, b2, regs, ACCTYPE_READ, regs->psw.pkey);
7609
7610 /* Get address of next page if boundary crossed */
7611 if (unlikely (m < n))
7612 p2 = (U32*)MADDR(effective_addr2 + (m*4), b2, regs, ACCTYPE_READ, regs->psw.pkey);
7613 else
7614 m = n;
7615
7616 /* Load from first page */
7617 for (i = 0; i < m; i++, p1++)
7618 {
7619 regs->AR((r1 + i) & 0xF) = fetch_fw (p1);
7620 SET_AEA_AR(regs, (r1 + i) & 0xF);
7621 }
7622
7623 /* Load from next page */
7624 for ( ; i < n; i++, p2++)
7625 {
7626 regs->AR((r1 + i) & 0xF) = fetch_fw (p2);
7627 SET_AEA_AR(regs, (r1 + i) & 0xF);
7628 }
7629
7630 } /* end DEF_INST(load_access_multiple_y) */
7631 #endif /*defined(FEATURE_ACCESS_REGISTERS)*/
7632 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7633
7634
7635 #if defined(FEATURE_LONG_DISPLACEMENT)
7636 /*-------------------------------------------------------------------*/
7637 /* E371 LAY - Load Address (Long Displacement) [RXY] */
7638 /*-------------------------------------------------------------------*/
DEF_INST(load_address_y)7639 DEF_INST(load_address_y)
7640 {
7641 int r1; /* Value of R field */
7642 int b2; /* Base of effective addr */
7643 VADR effective_addr2; /* Effective address */
7644
7645 RXY0(inst, regs, r1, b2, effective_addr2);
7646
7647 /* Load operand address into register */
7648 SET_GR_A(r1, regs, effective_addr2);
7649
7650 } /* end DEF_INST(load_address_y) */
7651 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7652
7653
7654 #if defined(FEATURE_LONG_DISPLACEMENT)
7655 /*-------------------------------------------------------------------*/
7656 /* E378 LHY - Load Halfword (Long Displacement) [RXY] */
7657 /*-------------------------------------------------------------------*/
DEF_INST(load_halfword_y)7658 DEF_INST(load_halfword_y)
7659 {
7660 int r1; /* Value of R field */
7661 int b2; /* Base of effective addr */
7662 VADR effective_addr2; /* Effective address */
7663
7664 RXY(inst, regs, r1, b2, effective_addr2);
7665
7666 /* Load rightmost 2 bytes of register from operand address */
7667 regs->GR_L(r1) = (S16)ARCH_DEP(vfetch2) ( effective_addr2, b2, regs );
7668
7669 } /* end DEF_INST(load_halfword_y) */
7670 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7671
7672
7673 #if defined(FEATURE_LONG_DISPLACEMENT)
7674 /*-------------------------------------------------------------------*/
7675 /* EB98 LMY - Load Multiple (Long Displacement) [RSY] */
7676 /*-------------------------------------------------------------------*/
DEF_INST(load_multiple_y)7677 DEF_INST(load_multiple_y)
7678 {
7679 int r1, r3; /* Register numbers */
7680 int b2; /* effective address base */
7681 VADR effective_addr2; /* effective address */
7682 int i, m, n; /* Integer work areas */
7683 U32 *p1, *p2; /* Mainstor pointers */
7684
7685 RSY(inst, regs, r1, r3, b2, effective_addr2);
7686
7687 /* Calculate number of bytes to load */
7688 n = (((r3 - r1) & 0xF) + 1) << 2;
7689
7690 /* Calculate number of bytes to next boundary */
7691 m = 0x800 - ((VADR_L)effective_addr2 & 0x7ff);
7692
7693 /* Address of operand beginning */
7694 p1 = (U32*)MADDR(effective_addr2, b2, regs, ACCTYPE_READ, regs->psw.pkey);
7695
7696 if (likely(n <= m))
7697 {
7698 /* Boundary not crossed */
7699 n >>= 2;
7700 for (i = 0; i < n; i++, p1++)
7701 regs->GR_L((r1 + i) & 0xF) = fetch_fw (p1);
7702 }
7703 else
7704 {
7705 /* Boundary crossed, get 2nd page address */
7706 effective_addr2 += m;
7707 effective_addr2 &= ADDRESS_MAXWRAP(regs);
7708 p2 = (U32*)MADDR(effective_addr2, b2, regs, ACCTYPE_READ, regs->psw.pkey);
7709
7710 if (likely((m & 0x3) == 0))
7711 {
7712 /* Addresses are word aligned */
7713 m >>= 2;
7714 for (i = 0; i < m; i++, p1++)
7715 regs->GR_L((r1 + i) & 0xF) = fetch_fw (p1);
7716 n >>= 2;
7717 for ( ; i < n; i++, p2++)
7718 regs->GR_L((r1 + i) & 0xF) = fetch_fw (p2);
7719 }
7720 else
7721 {
7722 /* Worst case */
7723 U32 rwork[16];
7724 BYTE *b1, *b2;
7725
7726 b1 = (BYTE *)&rwork[0];
7727 b2 = (BYTE *)p1;
7728 for (i = 0; i < m; i++)
7729 *b1++ = *b2++;
7730 b2 = (BYTE *)p2;
7731 for ( ; i < n; i++)
7732 *b1++ = *b2++;
7733
7734 n >>= 2;
7735 for (i = 0; i < n; i++)
7736 regs->GR_L((r1 + i) & 0xF) = CSWAP32(rwork[i]);
7737 }
7738 }
7739
7740 } /* end DEF_INST(load_multiple_y) */
7741 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7742
7743
7744 #if defined(FEATURE_LONG_DISPLACEMENT)
7745 /*-------------------------------------------------------------------*/
7746 /* E313 LRAY - Load Real Address (Long Displacement) [RXY] */
7747 /*-------------------------------------------------------------------*/
DEF_INST(load_real_address_y)7748 DEF_INST(load_real_address_y)
7749 {
7750 int r1; /* Register number */
7751 int b2; /* Base of effective addr */
7752 VADR effective_addr2; /* Effective address */
7753
7754 RXY(inst, regs, r1, b2, effective_addr2);
7755
7756 ARCH_DEP(load_real_address_proc) (regs, r1, b2, effective_addr2);
7757
7758 } /* end DEF_INST(load_real_address_y) */
7759 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7760
7761
7762 #if defined(FEATURE_LONG_DISPLACEMENT)
7763 /*-------------------------------------------------------------------*/
7764 /* EB52 MVIY - Move Immediate (Long Displacement) [SIY] */
7765 /*-------------------------------------------------------------------*/
DEF_INST(move_immediate_y)7766 DEF_INST(move_immediate_y)
7767 {
7768 BYTE i2; /* Immediate operand */
7769 int b1; /* Base of effective addr */
7770 VADR effective_addr1; /* Effective address */
7771
7772 SIY(inst, regs, i2, b1, effective_addr1);
7773
7774 /* Store immediate operand at operand address */
7775 ARCH_DEP(vstoreb) ( i2, effective_addr1, b1, regs );
7776
7777 } /* end DEF_INST(move_immediate_y) */
7778 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7779
7780
7781 #if defined(FEATURE_LONG_DISPLACEMENT)
7782 /*-------------------------------------------------------------------*/
7783 /* E351 MSY - Multiply Single (Long Displacement) [RXY] */
7784 /*-------------------------------------------------------------------*/
DEF_INST(multiply_single_y)7785 DEF_INST(multiply_single_y)
7786 {
7787 int r1; /* Value of R field */
7788 int b2; /* Base of effective addr */
7789 VADR effective_addr2; /* Effective address */
7790 S32 n; /* 32-bit operand values */
7791
7792 RXY(inst, regs, r1, b2, effective_addr2);
7793
7794 /* Load second operand from operand address */
7795 n = (S32)ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
7796
7797 /* Multiply signed operands ignoring overflow */
7798 regs->GR_L(r1) = (S32)regs->GR_L(r1) * n;
7799
7800 } /* end DEF_INST(multiply_single) */
7801 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7802
7803
7804 #if defined(FEATURE_LONG_DISPLACEMENT)
7805 /*-------------------------------------------------------------------*/
7806 /* EB56 OIY - Or Immediate (Long Displacement) [SIY] */
7807 /*-------------------------------------------------------------------*/
DEF_INST(or_immediate_y)7808 DEF_INST(or_immediate_y)
7809 {
7810 BYTE i2; /* Immediate operand byte */
7811 int b1; /* Base of effective addr */
7812 VADR effective_addr1; /* Effective address */
7813 BYTE rbyte; /* Result byte */
7814
7815 SIY(inst, regs, i2, b1, effective_addr1);
7816
7817 /* Fetch byte from operand address */
7818 rbyte = ARCH_DEP(vfetchb) ( effective_addr1, b1, regs );
7819
7820 /* OR with immediate operand */
7821 rbyte |= i2;
7822
7823 /* Store result at operand address */
7824 ARCH_DEP(vstoreb) ( rbyte, effective_addr1, b1, regs );
7825
7826 /* Set condition code */
7827 regs->psw.cc = rbyte ? 1 : 0;
7828
7829 } /* end DEF_INST(or_immediate_y) */
7830 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7831
7832
7833 #if defined(FEATURE_LONG_DISPLACEMENT)
7834 /*-------------------------------------------------------------------*/
7835 /* E356 OY - Or (Long Displacement) [RXY] */
7836 /*-------------------------------------------------------------------*/
DEF_INST(or_y)7837 DEF_INST(or_y)
7838 {
7839 int r1; /* Value of R field */
7840 int b2; /* Base of effective addr */
7841 VADR effective_addr2; /* Effective address */
7842 U32 n; /* 32-bit operand values */
7843
7844 RXY(inst, regs, r1, b2, effective_addr2);
7845
7846 /* Load second operand from operand address */
7847 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
7848
7849 /* OR second operand with first and set condition code */
7850 regs->psw.cc = ( regs->GR_L(r1) |= n ) ? 1 : 0;
7851
7852 } /* end DEF_INST(or_y) */
7853 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7854
7855
7856 #if defined(FEATURE_LONG_DISPLACEMENT)
7857 /*-------------------------------------------------------------------*/
7858 /* E350 STY - Store (Long Displacement) [RXY] */
7859 /*-------------------------------------------------------------------*/
DEF_INST(store_y)7860 DEF_INST(store_y)
7861 {
7862 int r1; /* Values of R fields */
7863 int b2; /* Base of effective addr */
7864 VADR effective_addr2; /* Effective address */
7865
7866 RXY(inst, regs, r1, b2, effective_addr2);
7867
7868 /* Store register contents at operand address */
7869 ARCH_DEP(vstore4) ( regs->GR_L(r1), effective_addr2, b2, regs );
7870
7871 } /* end DEF_INST(store_y) */
7872 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7873
7874
7875 #if defined(FEATURE_LONG_DISPLACEMENT)
7876 #if defined(FEATURE_ACCESS_REGISTERS)
7877 /*-------------------------------------------------------------------*/
7878 /* EB9B STAMY - Store Access Multiple (Long Displacement) [RSY] */
7879 /*-------------------------------------------------------------------*/
DEF_INST(store_access_multiple_y)7880 DEF_INST(store_access_multiple_y)
7881 {
7882 int r1, r3; /* Register numbers */
7883 int b2; /* effective address base */
7884 VADR effective_addr2; /* effective address */
7885 int i, m, n; /* Integer work area */
7886 U32 *p1, *p2 = NULL; /* Mainstor pointers */
7887
7888 RSY(inst, regs, r1, r3, b2, effective_addr2);
7889
7890 FW_CHECK(effective_addr2, regs);
7891
7892 /* Calculate number of regs to store */
7893 n = ((r3 - r1) & 0xF) + 1;
7894
7895 /* Store 4 bytes at a time */
7896 ARCH_DEP(validate_operand)(effective_addr2, b2, (n*4) - 1, ACCTYPE_WRITE, regs);
7897 for (i = 0; i < n; i++)
7898 ARCH_DEP(vstore4)(regs->AR((r1 + i) & 0xF), effective_addr2 + (i*4), b2, regs);
7899
7900
7901 /* Calculate number of words to next boundary */
7902 m = (0x800 - (effective_addr2 & 0x7ff)) >> 2;
7903
7904 /* Address of operand beginning */
7905 p1 = (U32*)MADDR(effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
7906
7907 /* Get address of next page if boundary crossed */
7908 if (unlikely(m < n))
7909 p2 = (U32*)MADDR(effective_addr2 + (m*4), b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
7910 else
7911 m = n;
7912
7913 /* Store at operand beginning */
7914 for (i = 0; i < m; i++)
7915 store_fw (p1++, regs->AR((r1 + i) & 0xF));
7916
7917 /* Store on next page */
7918 for ( ; i < n; i++)
7919 store_fw (p2++, regs->AR((r1 + i) & 0xF));
7920
7921
7922 } /* end DEF_INST(store_access_multiple_y) */
7923 #endif /*defined(FEATURE_ACCESS_REGISTERS)*/
7924 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7925
7926
7927 #if defined(FEATURE_LONG_DISPLACEMENT)
7928 /*-------------------------------------------------------------------*/
7929 /* E372 STCY - Store Character (Long Displacement) [RXY] */
7930 /*-------------------------------------------------------------------*/
DEF_INST(store_character_y)7931 DEF_INST(store_character_y)
7932 {
7933 int r1; /* Value of R field */
7934 int b2; /* Base of effective addr */
7935 VADR effective_addr2; /* Effective address */
7936
7937 RXY(inst, regs, r1, b2, effective_addr2);
7938
7939 /* Store rightmost byte of R1 register at operand address */
7940 ARCH_DEP(vstoreb) ( regs->GR_LHLCL(r1), effective_addr2, b2, regs );
7941
7942 } /* end DEF_INST(store_character_y) */
7943 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7944
7945
7946 #if defined(FEATURE_LONG_DISPLACEMENT)
7947 /*-------------------------------------------------------------------*/
7948 /* EB2D STCMY - Store Characters under Mask (Long Displacement)[RSY] */
7949 /*-------------------------------------------------------------------*/
DEF_INST(store_characters_under_mask_y)7950 DEF_INST(store_characters_under_mask_y)
7951 {
7952 int r1, r3; /* Register numbers */
7953 int b2; /* effective address base */
7954 VADR effective_addr2; /* effective address */
7955 int i; /* Integer work area */
7956 BYTE rbyte[4]; /* Byte work area */
7957
7958 RSY(inst, regs, r1, r3, b2, effective_addr2);
7959
7960 switch (r3) {
7961
7962 case 15:
7963 /* Optimized case */
7964 ARCH_DEP(vstore4) (regs->GR_L(r1), effective_addr2, b2, regs);
7965 break;
7966
7967 default:
7968 /* Extract value from register by mask */
7969 i = 0;
7970 if (r3 & 0x8) rbyte[i++] = (regs->GR_L(r1) >> 24) & 0xFF;
7971 if (r3 & 0x4) rbyte[i++] = (regs->GR_L(r1) >> 16) & 0xFF;
7972 if (r3 & 0x2) rbyte[i++] = (regs->GR_L(r1) >> 8) & 0xFF;
7973 if (r3 & 0x1) rbyte[i++] = (regs->GR_L(r1) ) & 0xFF;
7974
7975 if (i)
7976 ARCH_DEP(vstorec) (rbyte, i-1, effective_addr2, b2, regs);
7977 #if defined(MODEL_DEPENDENT_STCM)
7978 /* If the mask is all zero, we nevertheless access one byte
7979 from the storage operand, because POP states that an
7980 access exception may be recognized on the first byte */
7981 else
7982 ARCH_DEP(validate_operand) (effective_addr2, b2, 0,
7983 ACCTYPE_WRITE, regs);
7984 #endif
7985 break;
7986
7987 } /* switch (r3) */
7988
7989 } /* end DEF_INST(store_characters_under_mask_y) */
7990 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
7991
7992
7993 #if defined(FEATURE_LONG_DISPLACEMENT)
7994 /*-------------------------------------------------------------------*/
7995 /* E370 STHY - Store Halfword (Long Displacement) [RXY] */
7996 /*-------------------------------------------------------------------*/
DEF_INST(store_halfword_y)7997 DEF_INST(store_halfword_y)
7998 {
7999 int r1; /* Value of R field */
8000 int b2; /* Base of effective addr */
8001 VADR effective_addr2; /* Effective address */
8002
8003 RXY(inst, regs, r1, b2, effective_addr2);
8004
8005 /* Store rightmost 2 bytes of R1 register at operand address */
8006 ARCH_DEP(vstore2) ( regs->GR_LHL(r1), effective_addr2, b2, regs );
8007
8008 } /* end DEF_INST(store_halfword_y) */
8009 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
8010
8011
8012 #if defined(FEATURE_LONG_DISPLACEMENT)
8013 /*-------------------------------------------------------------------*/
8014 /* EB90 STMY - Store Multiple (Long Displacement) [RSY] */
8015 /*-------------------------------------------------------------------*/
DEF_INST(store_multiple_y)8016 DEF_INST(store_multiple_y)
8017 {
8018 int r1, r3; /* Register numbers */
8019 int b2; /* effective address base */
8020 VADR effective_addr2; /* effective address */
8021 int i, m, n; /* Integer work areas */
8022 U32 *p1, *p2; /* Mainstor pointers */
8023
8024 RSY(inst, regs, r1, r3, b2, effective_addr2);
8025
8026 /* Calculate number of bytes to store */
8027 n = (((r3 - r1) & 0xF) + 1) << 2;
8028
8029 /* Calculate number of bytes to next boundary */
8030 m = 0x800 - ((VADR_L)effective_addr2 & 0x7ff);
8031
8032 /* Get address of first page */
8033 p1 = (U32*)MADDR(effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
8034
8035 if (likely(n <= m))
8036 {
8037 /* boundary not crossed */
8038 n >>= 2;
8039 for (i = 0; i < n; i++)
8040 store_fw (p1++, regs->GR_L((r1 + i) & 0xF));
8041 }
8042 else
8043 {
8044 /* boundary crossed, get address of the 2nd page */
8045 effective_addr2 += m;
8046 effective_addr2 &= ADDRESS_MAXWRAP(regs);
8047 p2 = (U32*)MADDR(effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
8048
8049 if (likely((m & 0x3) == 0))
8050 {
8051 /* word aligned */
8052 m >>= 2;
8053 for (i = 0; i < m; i++)
8054 store_fw (p1++, regs->GR_L((r1 + i) & 0xF));
8055 n >>= 2;
8056 for ( ; i < n; i++)
8057 store_fw (p2++, regs->GR_L((r1 + i) & 0xF));
8058 }
8059 else
8060 {
8061 /* worst case */
8062 U32 rwork[16];
8063 BYTE *b1, *b2;
8064
8065 for (i = 0; i < (n >> 2); i++)
8066 rwork[i] = CSWAP32(regs->GR_L((r1 + i) & 0xF));
8067 b1 = (BYTE *)&rwork[0];
8068
8069 b2 = (BYTE *)p1;
8070 for (i = 0; i < m; i++)
8071 *b2++ = *b1++;
8072
8073 b2 = (BYTE *)p2;
8074 for ( ; i < n; i++)
8075 *b2++ = *b1++;
8076 }
8077 }
8078
8079 } /* end DEF_INST(store_multiple_y) */
8080 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
8081
8082
8083 #if defined(FEATURE_LONG_DISPLACEMENT)
8084 /*-------------------------------------------------------------------*/
8085 /* E35B SY - Subtract (Long Displacement) [RXY] */
8086 /*-------------------------------------------------------------------*/
DEF_INST(subtract_y)8087 DEF_INST(subtract_y)
8088 {
8089 int r1; /* Value of R field */
8090 int b2; /* Base of effective addr */
8091 VADR effective_addr2; /* Effective address */
8092 U32 n; /* 32-bit operand values */
8093
8094 RXY(inst, regs, r1, b2, effective_addr2);
8095
8096 /* Load second operand from operand address */
8097 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
8098
8099 /* Subtract signed operands and set condition code */
8100 regs->psw.cc =
8101 sub_signed (&(regs->GR_L(r1)),
8102 regs->GR_L(r1),
8103 n);
8104
8105 /* Program check if fixed-point overflow */
8106 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
8107 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
8108
8109 } /* end DEF_INST(subtract_y) */
8110 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
8111
8112
8113 #if defined(FEATURE_LONG_DISPLACEMENT)
8114 /*-------------------------------------------------------------------*/
8115 /* E37B SHY - Subtract Halfword (Long Displacement) [RXY] */
8116 /*-------------------------------------------------------------------*/
DEF_INST(subtract_halfword_y)8117 DEF_INST(subtract_halfword_y)
8118 {
8119 int r1; /* Value of R field */
8120 int b2; /* Base of effective addr */
8121 VADR effective_addr2; /* Effective address */
8122 S32 n; /* 32-bit operand values */
8123
8124 RXY(inst, regs, r1, b2, effective_addr2);
8125
8126 /* Load 2 bytes from operand address */
8127 n = (S16)ARCH_DEP(vfetch2) ( effective_addr2, b2, regs );
8128
8129 /* Subtract signed operands and set condition code */
8130 regs->psw.cc =
8131 sub_signed (&(regs->GR_L(r1)),
8132 regs->GR_L(r1),
8133 (U32)n);
8134
8135 /* Program check if fixed-point overflow */
8136 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
8137 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
8138
8139 } /* end DEF_INST(subtract_halfword_y) */
8140 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
8141
8142
8143 #if defined(FEATURE_LONG_DISPLACEMENT)
8144 /*-------------------------------------------------------------------*/
8145 /* E35F SLY - Subtract Logical (Long Displacement) [RXY] */
8146 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_y)8147 DEF_INST(subtract_logical_y)
8148 {
8149 int r1; /* Value of R field */
8150 int b2; /* Base of effective addr */
8151 VADR effective_addr2; /* Effective address */
8152 U32 n; /* 32-bit operand values */
8153
8154 RXY(inst, regs, r1, b2, effective_addr2);
8155
8156 /* Load second operand from operand address */
8157 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
8158
8159 /* Subtract unsigned operands and set condition code */
8160 regs->psw.cc =
8161 sub_logical (&(regs->GR_L(r1)),
8162 regs->GR_L(r1),
8163 n);
8164
8165 } /* end DEF_INST(subtract_logical_y) */
8166 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
8167
8168
8169 #if defined(FEATURE_LONG_DISPLACEMENT)
8170 /*-------------------------------------------------------------------*/
8171 /* EB51 TMY - Test under Mask (Long Displacement) [SIY] */
8172 /*-------------------------------------------------------------------*/
DEF_INST(test_under_mask_y)8173 DEF_INST(test_under_mask_y)
8174 {
8175 BYTE i2; /* Immediate operand */
8176 int b1; /* Base of effective addr */
8177 VADR effective_addr1; /* Effective address */
8178 BYTE tbyte; /* Work byte */
8179
8180 SIY(inst, regs, i2, b1, effective_addr1);
8181
8182 /* Fetch byte from operand address */
8183 tbyte = ARCH_DEP(vfetchb) ( effective_addr1, b1, regs );
8184
8185 /* AND with immediate operand mask */
8186 tbyte &= i2;
8187
8188 /* Set condition code according to result */
8189 regs->psw.cc =
8190 ( tbyte == 0 ) ? 0 : /* result all zeroes */
8191 ( tbyte == i2) ? 3 : /* result all ones */
8192 1 ; /* result mixed */
8193
8194 } /* end DEF_INST(test_under_mask_y) */
8195 #endif /*defined(FEATURE_LONG_DISPLACEMENT)*/
8196
8197
8198 #if defined(FEATURE_EXTENDED_IMMEDIATE) /*@Z9*/
8199 /*-------------------------------------------------------------------*/
8200 /* C2x9 AFI - Add Fullword Immediate [RIL] */
8201 /*-------------------------------------------------------------------*/
DEF_INST(add_fullword_immediate)8202 DEF_INST(add_fullword_immediate)
8203 {
8204 int r1; /* Register number */
8205 int opcd; /* Opcode */
8206 U32 i2; /* 32-bit operand value */
8207
8208 RIL(inst, regs, r1, opcd, i2);
8209
8210 /* Add signed operands and set condition code */
8211 regs->psw.cc = add_signed (&(regs->GR_L(r1)),
8212 regs->GR_L(r1),
8213 (S32)i2);
8214
8215 /* Program check if fixed-point overflow */
8216 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
8217 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
8218
8219 } /* end DEF_INST(add_fullword_immediate) */
8220
8221
8222 /*-------------------------------------------------------------------*/
8223 /* C2x8 AGFI - Add Long Fullword Immediate [RIL] */
8224 /*-------------------------------------------------------------------*/
DEF_INST(add_long_fullword_immediate)8225 DEF_INST(add_long_fullword_immediate)
8226 {
8227 int r1; /* Register number */
8228 int opcd; /* Opcode */
8229 U32 i2; /* 32-bit operand value */
8230
8231 RIL(inst, regs, r1, opcd, i2);
8232
8233 /* Add signed operands and set condition code */
8234 regs->psw.cc = add_signed_long (&(regs->GR_G(r1)),
8235 regs->GR_G(r1),
8236 (S32)i2);
8237
8238 /* Program check if fixed-point overflow */
8239 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
8240 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
8241
8242 } /* end DEF_INST(add_long_fullword_immediate) */
8243
8244
8245 /*-------------------------------------------------------------------*/
8246 /* C2xB ALFI - Add Logical Fullword Immediate [RIL] */
8247 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_fullword_immediate)8248 DEF_INST(add_logical_fullword_immediate)
8249 {
8250 int r1; /* Register number */
8251 int opcd; /* Opcode */
8252 U32 i2; /* 32-bit operand value */
8253
8254 RIL0(inst, regs, r1, opcd, i2);
8255
8256 /* Add signed operands and set condition code */
8257 regs->psw.cc = add_logical (&(regs->GR_L(r1)),
8258 regs->GR_L(r1),
8259 i2);
8260
8261 } /* end DEF_INST(add_logical_fullword_immediate) */
8262
8263
8264 /*-------------------------------------------------------------------*/
8265 /* C2xA ALGFI - Add Logical Long Fullword Immediate [RIL] */
8266 /*-------------------------------------------------------------------*/
DEF_INST(add_logical_long_fullword_immediate)8267 DEF_INST(add_logical_long_fullword_immediate)
8268 {
8269 int r1; /* Register number */
8270 int opcd; /* Opcode */
8271 U32 i2; /* 32-bit operand value */
8272
8273 RIL0(inst, regs, r1, opcd, i2);
8274
8275 /* Add unsigned operands and set condition code */
8276 regs->psw.cc = add_logical_long(&(regs->GR_G(r1)),
8277 regs->GR_G(r1),
8278 i2);
8279
8280 } /* end DEF_INST(add_logical_long_fullword_immediate) */
8281
8282
8283 /*-------------------------------------------------------------------*/
8284 /* C0xA NIHF - And Immediate High Fullword [RIL] */
8285 /*-------------------------------------------------------------------*/
DEF_INST(and_immediate_high_fullword)8286 DEF_INST(and_immediate_high_fullword)
8287 {
8288 int r1; /* Register number */
8289 int opcd; /* Opcode */
8290 U32 i2; /* 32-bit operand value */
8291
8292 RIL0(inst, regs, r1, opcd, i2);
8293
8294 /* And fullword operand with high 32 bits of register */
8295 regs->GR_H(r1) &= i2;
8296
8297 /* Set condition code according to result */
8298 regs->psw.cc = regs->GR_H(r1) ? 1 : 0;
8299
8300 } /* end DEF_INST(and_immediate_high_fullword) */
8301
8302
8303 /*-------------------------------------------------------------------*/
8304 /* C0xB NILF - And Immediate Low Fullword [RIL] */
8305 /*-------------------------------------------------------------------*/
DEF_INST(and_immediate_low_fullword)8306 DEF_INST(and_immediate_low_fullword)
8307 {
8308 int r1; /* Register number */
8309 int opcd; /* Opcode */
8310 U32 i2; /* 32-bit operand value */
8311
8312 RIL0(inst, regs, r1, opcd, i2);
8313
8314 /* And fullword operand with low 32 bits of register */
8315 regs->GR_L(r1) &= i2;
8316
8317 /* Set condition code according to result */
8318 regs->psw.cc = regs->GR_L(r1) ? 1 : 0;
8319
8320 } /* end DEF_INST(and_immediate_low_fullword) */
8321
8322
8323 /*-------------------------------------------------------------------*/
8324 /* C2xD CFI - Compare Fullword Immediate [RIL] */
8325 /*-------------------------------------------------------------------*/
DEF_INST(compare_fullword_immediate)8326 DEF_INST(compare_fullword_immediate)
8327 {
8328 int r1; /* Register number */
8329 int opcd; /* Opcode */
8330 U32 i2; /* 32-bit operand value */
8331
8332 RIL0(inst, regs, r1, opcd, i2);
8333
8334 /* Compare signed operands and set condition code */
8335 regs->psw.cc = (S32)regs->GR_L(r1) < (S32)i2 ? 1 :
8336 (S32)regs->GR_L(r1) > (S32)i2 ? 2 : 0;
8337
8338 } /* end DEF_INST(compare_fullword_immediate) */
8339
8340
8341 /*-------------------------------------------------------------------*/
8342 /* C2xC CGFI - Compare Long Fullword Immediate [RIL] */
8343 /*-------------------------------------------------------------------*/
DEF_INST(compare_long_fullword_immediate)8344 DEF_INST(compare_long_fullword_immediate)
8345 {
8346 int r1; /* Register number */
8347 int opcd; /* Opcode */
8348 U32 i2; /* 32-bit operand value */
8349
8350 RIL0(inst, regs, r1, opcd, i2);
8351
8352 /* Compare signed operands and set condition code */
8353 regs->psw.cc = (S64)regs->GR_G(r1) < (S32)i2 ? 1 :
8354 (S64)regs->GR_G(r1) > (S32)i2 ? 2 : 0;
8355
8356 } /* end DEF_INST(compare_long_fullword_immediate) */
8357
8358
8359 /*-------------------------------------------------------------------*/
8360 /* C2xF CLFI - Compare Logical Fullword Immediate [RIL] */
8361 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_fullword_immediate)8362 DEF_INST(compare_logical_fullword_immediate)
8363 {
8364 int r1; /* Register number */
8365 int opcd; /* Opcode */
8366 U32 i2; /* 32-bit operand value */
8367
8368 RIL0(inst, regs, r1, opcd, i2);
8369
8370 /* Compare unsigned operands and set condition code */
8371 regs->psw.cc = regs->GR_L(r1) < i2 ? 1 :
8372 regs->GR_L(r1) > i2 ? 2 : 0;
8373
8374 } /* end DEF_INST(compare_logical_fullword_immediate) */
8375
8376
8377 /*-------------------------------------------------------------------*/
8378 /* C2xE CLGFI - Compare Logical Long Fullword Immediate [RIL] */
8379 /*-------------------------------------------------------------------*/
DEF_INST(compare_logical_long_fullword_immediate)8380 DEF_INST(compare_logical_long_fullword_immediate)
8381 {
8382 int r1; /* Register number */
8383 int opcd; /* Opcode */
8384 U32 i2; /* 32-bit operand value */
8385
8386 RIL0(inst, regs, r1, opcd, i2);
8387
8388 /* Compare unsigned operands and set condition code */
8389 regs->psw.cc = regs->GR_G(r1) < i2 ? 1 :
8390 regs->GR_G(r1) > i2 ? 2 : 0;
8391
8392 } /* end DEF_INST(compare_logical_long_fullword_immediate) */
8393
8394
8395 /*-------------------------------------------------------------------*/
8396 /* C0x6 XIHF - Exclusive Or Immediate High Fullword [RIL] */
8397 /*-------------------------------------------------------------------*/
DEF_INST(exclusive_or_immediate_high_fullword)8398 DEF_INST(exclusive_or_immediate_high_fullword)
8399 {
8400 int r1; /* Register number */
8401 int opcd; /* Opcode */
8402 U32 i2; /* 32-bit operand value */
8403
8404 RIL0(inst, regs, r1, opcd, i2);
8405
8406 /* XOR fullword operand with high 32 bits of register */
8407 regs->GR_H(r1) ^= i2;
8408
8409 /* Set condition code according to result */
8410 regs->psw.cc = regs->GR_H(r1) ? 1 : 0;
8411
8412 } /* end DEF_INST(exclusive_or_immediate_high_fullword) */
8413
8414
8415 /*-------------------------------------------------------------------*/
8416 /* C0x7 XILF - Exclusive Or Immediate Low Fullword [RIL] */
8417 /*-------------------------------------------------------------------*/
DEF_INST(exclusive_or_immediate_low_fullword)8418 DEF_INST(exclusive_or_immediate_low_fullword)
8419 {
8420 int r1; /* Register number */
8421 int opcd; /* Opcode */
8422 U32 i2; /* 32-bit operand value */
8423
8424 RIL0(inst, regs, r1, opcd, i2);
8425
8426 /* XOR fullword operand with low 32 bits of register */
8427 regs->GR_L(r1) ^= i2;
8428
8429 /* Set condition code according to result */
8430 regs->psw.cc = regs->GR_L(r1) ? 1 : 0;
8431
8432 } /* end DEF_INST(exclusive_or_immediate_low_fullword) */
8433
8434
8435 /*-------------------------------------------------------------------*/
8436 /* C0x8 IIHF - Insert Immediate High Fullword [RIL] */
8437 /*-------------------------------------------------------------------*/
DEF_INST(insert_immediate_high_fullword)8438 DEF_INST(insert_immediate_high_fullword)
8439 {
8440 int r1; /* Register number */
8441 int opcd; /* Opcode */
8442 U32 i2; /* 32-bit operand value */
8443
8444 RIL0(inst, regs, r1, opcd, i2);
8445
8446 /* Insert fullword operand into high 32 bits of register */
8447 regs->GR_H(r1) = i2;
8448
8449 } /* end DEF_INST(insert_immediate_high_fullword) */
8450
8451
8452 /*-------------------------------------------------------------------*/
8453 /* C0x9 IILF - Insert Immediate Low Fullword [RIL] */
8454 /*-------------------------------------------------------------------*/
DEF_INST(insert_immediate_low_fullword)8455 DEF_INST(insert_immediate_low_fullword)
8456 {
8457 int r1; /* Register number */
8458 int opcd; /* Opcode */
8459 U32 i2; /* 32-bit operand value */
8460
8461 RIL0(inst, regs, r1, opcd, i2);
8462
8463 /* Insert fullword operand into low 32 bits of register */
8464 regs->GR_L(r1) = i2;
8465
8466 } /* end DEF_INST(insert_immediate_low_fullword) */
8467
8468
8469 /*-------------------------------------------------------------------*/
8470 /* C0xE LLIHF - Load Logical Immediate High Fullword [RIL] */
8471 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_immediate_high_fullword)8472 DEF_INST(load_logical_immediate_high_fullword)
8473 {
8474 int r1; /* Register number */
8475 int opcd; /* Opcode */
8476 U32 i2; /* 32-bit operand value */
8477
8478 RIL0(inst, regs, r1, opcd, i2);
8479
8480 /* Load fullword operand into high 32 bits of register
8481 and set remaining bits to zero */
8482 regs->GR_H(r1) = i2;
8483 regs->GR_L(r1) = 0;
8484
8485 } /* end DEF_INST(load_logical_immediate_high_fullword) */
8486
8487
8488 /*-------------------------------------------------------------------*/
8489 /* C0xF LLILF - Load Logical Immediate Low Fullword [RIL] */
8490 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_immediate_low_fullword)8491 DEF_INST(load_logical_immediate_low_fullword)
8492 {
8493 int r1; /* Register number */
8494 int opcd; /* Opcode */
8495 U32 i2; /* 32-bit operand value */
8496
8497 RIL0(inst, regs, r1, opcd, i2);
8498
8499 /* Load fullword operand into low 32 bits of register
8500 and set remaining bits to zero */
8501 regs->GR_G(r1) = i2;
8502
8503 } /* end DEF_INST(load_logical_immediate_low_fullword) */
8504
8505
8506 /*-------------------------------------------------------------------*/
8507 /* C0x1 LGFI - Load Long Fullword Immediate [RIL] */
8508 /*-------------------------------------------------------------------*/
DEF_INST(load_long_fullword_immediate)8509 DEF_INST(load_long_fullword_immediate)
8510 {
8511 int r1; /* Register number */
8512 int opcd; /* Opcode */
8513 U32 i2; /* 32-bit operand value */
8514
8515 RIL0(inst, regs, r1, opcd, i2);
8516
8517 /* Load operand into register */
8518 regs->GR_G(r1) = (S32)i2;
8519
8520 } /* end DEF_INST(load_long_fullword_immediate) */
8521
8522
8523 /*-------------------------------------------------------------------*/
8524 /* C0xC OIHF - Or Immediate High Fullword [RIL] */
8525 /*-------------------------------------------------------------------*/
DEF_INST(or_immediate_high_fullword)8526 DEF_INST(or_immediate_high_fullword)
8527 {
8528 int r1; /* Register number */
8529 int opcd; /* Opcode */
8530 U32 i2; /* 32-bit operand value */
8531
8532 RIL0(inst, regs, r1, opcd, i2);
8533
8534 /* Or fullword operand with high 32 bits of register */
8535 regs->GR_H(r1) |= i2;
8536
8537 /* Set condition code according to result */
8538 regs->psw.cc = regs->GR_H(r1) ? 1 : 0;
8539
8540 } /* end DEF_INST(or_immediate_high_fullword) */
8541
8542
8543 /*-------------------------------------------------------------------*/
8544 /* C0xD OILF - Or Immediate Low Fullword [RIL] */
8545 /*-------------------------------------------------------------------*/
DEF_INST(or_immediate_low_fullword)8546 DEF_INST(or_immediate_low_fullword)
8547 {
8548 int r1; /* Register number */
8549 int opcd; /* Opcode */
8550 U32 i2; /* 32-bit operand value */
8551
8552 RIL0(inst, regs, r1, opcd, i2);
8553
8554 /* Or fullword operand with low 32 bits of register */
8555 regs->GR_L(r1) |= i2;
8556
8557 /* Set condition code according to result */
8558 regs->psw.cc = regs->GR_L(r1) ? 1 : 0;
8559
8560 } /* end DEF_INST(or_immediate_low_fullword) */
8561
8562
8563 /*-------------------------------------------------------------------*/
8564 /* C2x5 SLFI - Subtract Logical Fullword Immediate [RIL] */
8565 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_fullword_immediate)8566 DEF_INST(subtract_logical_fullword_immediate)
8567 {
8568 int r1; /* Register number */
8569 int opcd; /* Opcode */
8570 U32 i2; /* 32-bit operand value */
8571
8572 RIL0(inst, regs, r1, opcd, i2);
8573
8574 /* Subtract unsigned operands and set condition code */
8575 regs->psw.cc = sub_logical (&(regs->GR_L(r1)),
8576 regs->GR_L(r1),
8577 i2);
8578
8579 } /* end DEF_INST(subtract_logical_fullword_immediate) */
8580
8581
8582 /*-------------------------------------------------------------------*/
8583 /* C2x4 SLGFI - Subtract Logical Long Fullword Immediate [RIL] */
8584 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_long_fullword_immediate)8585 DEF_INST(subtract_logical_long_fullword_immediate)
8586 {
8587 int r1; /* Register number */
8588 int opcd; /* Opcode */
8589 U32 i2; /* 32-bit operand value */
8590
8591 RIL0(inst, regs, r1, opcd, i2);
8592
8593 /* Subtract unsigned operands and set condition code */
8594 regs->psw.cc = sub_logical_long(&(regs->GR_G(r1)),
8595 regs->GR_G(r1),
8596 i2);
8597
8598 } /* end DEF_INST(subtract_logical_long_fullword_immediate) */
8599 #endif /*defined(FEATURE_EXTENDED_IMMEDIATE)*/ /*@Z9*/
8600
8601
8602 #if defined(FEATURE_EXTENDED_IMMEDIATE) /*@Z9*/
8603 /*-------------------------------------------------------------------*/
8604 /* E312 LT - Load and Test [RXY] */
8605 /*-------------------------------------------------------------------*/
DEF_INST(load_and_test)8606 DEF_INST(load_and_test)
8607 {
8608 int r1; /* Value of R field */
8609 int b2; /* Base of effective addr */
8610 VADR effective_addr2; /* Effective address */
8611
8612 RXY(inst, regs, r1, b2, effective_addr2);
8613
8614 /* Load R1 register from second operand */
8615 regs->GR_L(r1) = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
8616
8617 /* Set condition code according to value loaded */
8618 regs->psw.cc = (S32)regs->GR_L(r1) < 0 ? 1 :
8619 (S32)regs->GR_L(r1) > 0 ? 2 : 0;
8620
8621 } /* end DEF_INST(load_and_test) */
8622
8623
8624 /*-------------------------------------------------------------------*/
8625 /* E302 LTG - Load and Test Long [RXY] */
8626 /*-------------------------------------------------------------------*/
DEF_INST(load_and_test_long)8627 DEF_INST(load_and_test_long)
8628 {
8629 int r1; /* Value of R field */
8630 int b2; /* Base of effective addr */
8631 VADR effective_addr2; /* Effective address */
8632
8633 RXY(inst, regs, r1, b2, effective_addr2);
8634
8635 /* Load R1 register from second operand */
8636 regs->GR_G(r1) = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
8637
8638 /* Set condition code according to value loaded */
8639 regs->psw.cc = (S64)regs->GR_G(r1) < 0 ? 1 :
8640 (S64)regs->GR_G(r1) > 0 ? 2 : 0;
8641
8642 } /* end DEF_INST(load_and_test_long) */
8643
8644
8645 /*-------------------------------------------------------------------*/
8646 /* B926 LBR - Load Byte Register [RRE] */
8647 /*-------------------------------------------------------------------*/
DEF_INST(load_byte_register)8648 DEF_INST(load_byte_register)
8649 {
8650 int r1, r2; /* Values of R fields */
8651
8652 RRE0(inst, regs, r1, r2);
8653
8654 /* Load sign-extended byte from second register */
8655 regs->GR_L(r1) = (S32)(S8)(regs->GR_LHLCL(r2));
8656
8657 } /* end DEF_INST(load_byte_register) */
8658
8659
8660 /*-------------------------------------------------------------------*/
8661 /* B906 LGBR - Load Long Byte Register [RRE] */
8662 /*-------------------------------------------------------------------*/
DEF_INST(load_long_byte_register)8663 DEF_INST(load_long_byte_register)
8664 {
8665 int r1, r2; /* Values of R fields */
8666
8667 RRE0(inst, regs, r1, r2);
8668
8669 /* Load sign-extended byte from second register */
8670 regs->GR_G(r1) = (S64)(S8)(regs->GR_LHLCL(r2));
8671
8672 } /* end DEF_INST(load_long_byte_register) */
8673
8674
8675 /*-------------------------------------------------------------------*/
8676 /* B927 LHR - Load Halfword Register [RRE] */
8677 /*-------------------------------------------------------------------*/
DEF_INST(load_halfword_register)8678 DEF_INST(load_halfword_register)
8679 {
8680 int r1, r2; /* Values of R fields */
8681
8682 RRE0(inst, regs, r1, r2);
8683
8684 /* Load sign-extended halfword from second register */
8685 regs->GR_L(r1) = (S32)(S16)(regs->GR_LHL(r2));
8686
8687 } /* end DEF_INST(load_halfword_register) */
8688
8689
8690 /*-------------------------------------------------------------------*/
8691 /* B907 LGHR - Load Long Halfword Register [RRE] */
8692 /*-------------------------------------------------------------------*/
DEF_INST(load_long_halfword_register)8693 DEF_INST(load_long_halfword_register)
8694 {
8695 int r1, r2; /* Values of R fields */
8696
8697 RRE0(inst, regs, r1, r2);
8698
8699 /* Load sign-extended halfword from second register */
8700 regs->GR_G(r1) = (S64)(S16)(regs->GR_LHL(r2));
8701
8702 } /* end DEF_INST(load_long_halfword_register) */
8703
8704
8705 /*-------------------------------------------------------------------*/
8706 /* E394 LLC - Load Logical Character [RXY] */
8707 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_character)8708 DEF_INST(load_logical_character)
8709 {
8710 int r1; /* Value of R field */
8711 int b2; /* Base of effective addr */
8712 VADR effective_addr2; /* Effective address */
8713
8714 RXY(inst, regs, r1, b2, effective_addr2);
8715
8716 regs->GR_L(r1) = ARCH_DEP(vfetchb) ( effective_addr2, b2, regs );
8717
8718 } /* end DEF_INST(load_logical_character) */
8719
8720
8721 /*-------------------------------------------------------------------*/
8722 /* B994 LLCR - Load Logical Character Register [RRE] */
8723 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_character_register)8724 DEF_INST(load_logical_character_register)
8725 {
8726 int r1, r2; /* Values of R fields */
8727
8728 RRE0(inst, regs, r1, r2);
8729
8730 /* Load bits 56-63 from second register and clear bits 32-55 */
8731 regs->GR_L(r1) = regs->GR_LHLCL(r2);
8732
8733 } /* end DEF_INST(load_logical_character_register) */
8734
8735
8736 /*-------------------------------------------------------------------*/
8737 /* B984 LLGCR - Load Logical Long Character Register [RRE] */
8738 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_long_character_register)8739 DEF_INST(load_logical_long_character_register)
8740 {
8741 int r1, r2; /* Values of R fields */
8742
8743 RRE0(inst, regs, r1, r2);
8744
8745 /* Load bits 56-63 from second register and clear bits 0-55 */
8746 regs->GR_G(r1) = regs->GR_LHLCL(r2);
8747
8748 } /* end DEF_INST(load_logical_long_character_register) */
8749
8750
8751 /*-------------------------------------------------------------------*/
8752 /* E395 LLH - Load Logical Halfword [RXY] */
8753 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_halfword)8754 DEF_INST(load_logical_halfword)
8755 {
8756 int r1; /* Value of R field */
8757 int b2; /* Base of effective addr */
8758 VADR effective_addr2; /* Effective address */
8759
8760 RXY(inst, regs, r1, b2, effective_addr2);
8761
8762 regs->GR_L(r1) = ARCH_DEP(vfetch2) ( effective_addr2, b2, regs );
8763
8764 } /* end DEF_INST(load_logical_halfword) */
8765
8766
8767 /*-------------------------------------------------------------------*/
8768 /* B995 LLHR - Load Logical Halfword Register [RRE] */
8769 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_halfword_register)8770 DEF_INST(load_logical_halfword_register)
8771 {
8772 int r1, r2; /* Values of R fields */
8773
8774 RRE0(inst, regs, r1, r2);
8775
8776 /* Load bits 48-63 from second register and clear bits 32-47 */
8777 regs->GR_L(r1) = regs->GR_LHL(r2);
8778
8779 } /* end DEF_INST(load_logical_halfword_register) */
8780
8781
8782 /*-------------------------------------------------------------------*/
8783 /* B985 LLGHR - Load Logical Long Halfword Register [RRE] */
8784 /*-------------------------------------------------------------------*/
DEF_INST(load_logical_long_halfword_register)8785 DEF_INST(load_logical_long_halfword_register)
8786 {
8787 int r1, r2; /* Values of R fields */
8788
8789 RRE0(inst, regs, r1, r2);
8790
8791 /* Load bits 48-63 from second register and clear bits 0-47 */
8792 regs->GR_G(r1) = regs->GR_LHL(r2);
8793
8794 } /* end DEF_INST(load_logical_long_halfword_register) */
8795
8796
8797 /*-------------------------------------------------------------------*/
8798 /* B983 FLOGR - Find Leftmost One Long Register [RRE] */
8799 /*-------------------------------------------------------------------*/
DEF_INST(find_leftmost_one_long_register)8800 DEF_INST(find_leftmost_one_long_register)
8801 {
8802 int r1, r2; /* Values of R fields */
8803 U64 op; /* R2 contents */
8804 U64 mask; /* Bit mask for leftmost one */
8805 int n; /* Position of leftmost one */
8806
8807 RRE(inst, regs, r1, r2);
8808
8809 ODD_CHECK(r1, regs);
8810
8811 /* Load contents of second register */
8812 op = regs->GR_G(r2);
8813
8814 /* If R2 contents is all zero, set R1 register to 64,
8815 set R1+1 register to zero, and return cond code 0 */
8816 if (op == 0)
8817 {
8818 regs->GR_G(r1) = 64;
8819 regs->GR_G(r1+1) = 0;
8820 regs->psw.cc = 0;
8821 }
8822 else
8823 {
8824 /* Find leftmost one */
8825 for (mask = 0x8000000000000000ULL, n=0;
8826 n < 64 && (op & mask) == 0; n++, mask >>= 1);
8827
8828 /* Load leftmost one position into R1 register */
8829 regs->GR_G(r1) = n;
8830
8831 /* Copy original R2 to R1+1 and clear leftmost one */
8832 regs->GR_G(r1+1) = op & (~mask);
8833
8834 /* Return with condition code 2 */
8835 regs->psw.cc = 2;
8836 }
8837
8838 } /* end DEF_INST(find_leftmost_one_long_register) */
8839 #endif /*defined(FEATURE_EXTENDED_IMMEDIATE)*/ /*@Z9*/
8840
8841 #if defined(FEATURE_LOAD_PROGRAM_PARAMETER_FACILITY) /*810*/
8842 /*-------------------------------------------------------------------*/
8843 /* B280 LPP - Load Program Parameter [S] */
8844 /*-------------------------------------------------------------------*/
DEF_INST(load_program_parameter)8845 DEF_INST(load_program_parameter)
8846 {
8847 int b2; /* Base of effective addr */
8848 U64 effective_addr2; /* Effective address */
8849
8850 S(inst, regs, b2, effective_addr2);
8851
8852 PRIV_CHECK(regs);
8853
8854 /* Fetch data from operand address */
8855 sysblk.program_parameter = ARCH_DEP(vfetch8) (effective_addr2, b2, regs);
8856
8857 } /* end DEF_INST(load_program_parameter) */
8858 #endif /*defined(FEATURE_LOAD_PROGRAM_PARAMETER_FACILITY)*/ /*810*/
8859
8860 #if !defined(_GEN_ARCH)
8861
8862 #if defined(_ARCHMODE2)
8863 #define _GEN_ARCH _ARCHMODE2
8864 #include "esame.c"
8865 #endif
8866
8867 #if defined(_ARCHMODE3)
8868 #undef _GEN_ARCH
8869 #define _GEN_ARCH _ARCHMODE3
8870 #include "esame.c"
8871 #endif
8872
8873 #if defined(HAVE_STFL_DATA)
8874 /*-------------------------------------------------------------------*/
8875 /* Locate STFL data independent of current architecture mode setting */
8876 /*-------------------------------------------------------------------*/
8877 /* Note: this function must be here so that all ARCH_DEP(stlf_data) */
8878 /* with correct architecture settings have been defined with */
8879 /* architecture sensitive features */
8880
get_stfl_data(int mode,int * data_len)8881 BYTE* get_stfl_data(int mode, int *data_len)
8882 {
8883 switch(mode)
8884 {
8885 #if defined(_390)
8886 case ARCH_390:
8887 *data_len=sizeof(s390_stfl_data);
8888 return &s390_stfl_data[0];
8889 #endif
8890 #if defined(_900)
8891 case ARCH_900:
8892 *data_len=sizeof(z900_stfl_data);
8893 return &z900_stfl_data[0];
8894 #endif
8895 }
8896 *data_len=0;
8897 return NULL;
8898 }
8899 #endif /* defined(HAVE_STFL_DATA) */
8900
8901 #endif /*!defined(_GEN_ARCH)*/
8902