1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef __DC_HW_SEQUENCER_H__
27 #define __DC_HW_SEQUENCER_H__
28 #include "dc_types.h"
29 #include "inc/clock_source.h"
30 #include "inc/hw/timing_generator.h"
31 #include "inc/hw/opp.h"
32 #include "inc/hw/link_encoder.h"
33 #include "inc/core_status.h"
34 
35 struct pipe_ctx;
36 struct dc_state;
37 struct dc_stream_status;
38 struct dc_writeback_info;
39 struct dchub_init_data;
40 struct dc_static_screen_params;
41 struct resource_pool;
42 struct dc_phy_addr_space_config;
43 struct dc_virtual_addr_space_config;
44 struct dpp;
45 struct dce_hwseq;
46 struct link_resource;
47 struct dc_dmub_cmd;
48 struct pg_block_update;
49 
50 struct subvp_pipe_control_lock_fast_params {
51 	struct dc *dc;
52 	bool lock;
53 	bool subvp_immediate_flip;
54 };
55 
56 struct pipe_control_lock_params {
57 	struct dc *dc;
58 	struct pipe_ctx *pipe_ctx;
59 	bool lock;
60 };
61 
62 struct set_flip_control_gsl_params {
63 	struct pipe_ctx *pipe_ctx;
64 	bool flip_immediate;
65 };
66 
67 struct program_triplebuffer_params {
68 	const struct dc *dc;
69 	struct pipe_ctx *pipe_ctx;
70 	bool enableTripleBuffer;
71 };
72 
73 struct update_plane_addr_params {
74 	struct dc *dc;
75 	struct pipe_ctx *pipe_ctx;
76 };
77 
78 struct set_input_transfer_func_params {
79 	struct dc *dc;
80 	struct pipe_ctx *pipe_ctx;
81 	struct dc_plane_state *plane_state;
82 };
83 
84 struct program_gamut_remap_params {
85 	struct pipe_ctx *pipe_ctx;
86 };
87 
88 struct program_manual_trigger_params {
89 	struct pipe_ctx *pipe_ctx;
90 };
91 
92 struct send_dmcub_cmd_params {
93 	struct dc_context *ctx;
94 	union dmub_rb_cmd *cmd;
95 	enum dm_dmub_wait_type wait_type;
96 };
97 
98 struct setup_dpp_params {
99 	struct pipe_ctx *pipe_ctx;
100 };
101 
102 struct program_bias_and_scale_params {
103 	struct pipe_ctx *pipe_ctx;
104 };
105 
106 struct set_output_transfer_func_params {
107 	struct dc *dc;
108 	struct pipe_ctx *pipe_ctx;
109 	const struct dc_stream_state *stream;
110 };
111 
112 struct update_visual_confirm_params {
113 	struct dc *dc;
114 	struct pipe_ctx *pipe_ctx;
115 	int mpcc_id;
116 };
117 
118 struct power_on_mpc_mem_pwr_params {
119 	struct mpc *mpc;
120 	int mpcc_id;
121 	bool power_on;
122 };
123 
124 struct set_output_csc_params {
125 	struct mpc *mpc;
126 	int opp_id;
127 	const uint16_t *regval;
128 	enum mpc_output_csc_mode ocsc_mode;
129 };
130 
131 struct set_ocsc_default_params {
132 	struct mpc *mpc;
133 	int opp_id;
134 	enum dc_color_space color_space;
135 	enum mpc_output_csc_mode ocsc_mode;
136 };
137 
138 struct subvp_save_surf_addr {
139 	struct dc_dmub_srv *dc_dmub_srv;
140 	const struct dc_plane_address *addr;
141 	uint8_t subvp_index;
142 };
143 
144 struct wait_for_dcc_meta_propagation_params {
145 	const struct dc *dc;
146 	const struct pipe_ctx *top_pipe_to_program;
147 };
148 
149 struct fams2_global_control_lock_fast_params {
150 	struct dc *dc;
151 	bool is_required;
152 	bool lock;
153 };
154 
155 union block_sequence_params {
156 	struct update_plane_addr_params update_plane_addr_params;
157 	struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params;
158 	struct pipe_control_lock_params pipe_control_lock_params;
159 	struct set_flip_control_gsl_params set_flip_control_gsl_params;
160 	struct program_triplebuffer_params program_triplebuffer_params;
161 	struct set_input_transfer_func_params set_input_transfer_func_params;
162 	struct program_gamut_remap_params program_gamut_remap_params;
163 	struct program_manual_trigger_params program_manual_trigger_params;
164 	struct send_dmcub_cmd_params send_dmcub_cmd_params;
165 	struct setup_dpp_params setup_dpp_params;
166 	struct program_bias_and_scale_params program_bias_and_scale_params;
167 	struct set_output_transfer_func_params set_output_transfer_func_params;
168 	struct update_visual_confirm_params update_visual_confirm_params;
169 	struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params;
170 	struct set_output_csc_params set_output_csc_params;
171 	struct set_ocsc_default_params set_ocsc_default_params;
172 	struct subvp_save_surf_addr subvp_save_surf_addr;
173 	struct wait_for_dcc_meta_propagation_params wait_for_dcc_meta_propagation_params;
174 	struct fams2_global_control_lock_fast_params fams2_global_control_lock_fast_params;
175 };
176 
177 enum block_sequence_func {
178 	DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST = 0,
179 	OPTC_PIPE_CONTROL_LOCK,
180 	HUBP_SET_FLIP_CONTROL_GSL,
181 	HUBP_PROGRAM_TRIPLEBUFFER,
182 	HUBP_UPDATE_PLANE_ADDR,
183 	DPP_SET_INPUT_TRANSFER_FUNC,
184 	DPP_PROGRAM_GAMUT_REMAP,
185 	OPTC_PROGRAM_MANUAL_TRIGGER,
186 	DMUB_SEND_DMCUB_CMD,
187 	DPP_SETUP_DPP,
188 	DPP_PROGRAM_BIAS_AND_SCALE,
189 	DPP_SET_OUTPUT_TRANSFER_FUNC,
190 	MPC_UPDATE_VISUAL_CONFIRM,
191 	MPC_POWER_ON_MPC_MEM_PWR,
192 	MPC_SET_OUTPUT_CSC,
193 	MPC_SET_OCSC_DEFAULT,
194 	DMUB_SUBVP_SAVE_SURF_ADDR,
195 	HUBP_WAIT_FOR_DCC_META_PROP,
196 	DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST,
197 
198 };
199 
200 struct block_sequence {
201 	union block_sequence_params params;
202 	enum block_sequence_func func;
203 };
204 
205 struct hw_sequencer_funcs {
206 	void (*hardware_release)(struct dc *dc);
207 	/* Embedded Display Related */
208 	void (*edp_power_control)(struct dc_link *link, bool enable);
209 	void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
210 	void (*edp_wait_for_T12)(struct dc_link *link);
211 
212 	/* Pipe Programming Related */
213 	void (*init_hw)(struct dc *dc);
214 	void (*power_down_on_boot)(struct dc *dc);
215 	void (*enable_accelerated_mode)(struct dc *dc,
216 			struct dc_state *context);
217 	enum dc_status (*apply_ctx_to_hw)(struct dc *dc,
218 			struct dc_state *context);
219 	void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
220 	void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank);
221 	void (*apply_ctx_for_surface)(struct dc *dc,
222 			const struct dc_stream_state *stream,
223 			int num_planes, struct dc_state *context);
224 	void (*program_front_end_for_ctx)(struct dc *dc,
225 			struct dc_state *context);
226 	void (*wait_for_pending_cleared)(struct dc *dc,
227 			struct dc_state *context);
228 	void (*post_unlock_program_front_end)(struct dc *dc,
229 			struct dc_state *context);
230 	void (*update_plane_addr)(const struct dc *dc,
231 			struct pipe_ctx *pipe_ctx);
232 	void (*update_dchub)(struct dce_hwseq *hws,
233 			struct dchub_init_data *dh_data);
234 	void (*wait_for_mpcc_disconnect)(struct dc *dc,
235 			struct resource_pool *res_pool,
236 			struct pipe_ctx *pipe_ctx);
237 	void (*edp_backlight_control)(
238 			struct dc_link *link,
239 			bool enable);
240 	void (*program_triplebuffer)(const struct dc *dc,
241 		struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);
242 	void (*update_pending_status)(struct pipe_ctx *pipe_ctx);
243 	void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable);
244 
245 	/* Pipe Lock Related */
246 	void (*pipe_control_lock)(struct dc *dc,
247 			struct pipe_ctx *pipe, bool lock);
248 	void (*interdependent_update_lock)(struct dc *dc,
249 			struct dc_state *context, bool lock);
250 	void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx,
251 			bool flip_immediate);
252 	void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock);
253 
254 	/* Timing Related */
255 	void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
256 			struct crtc_position *position);
257 	int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx);
258 	void (*calc_vupdate_position)(
259 			struct dc *dc,
260 			struct pipe_ctx *pipe_ctx,
261 			uint32_t *start_line,
262 			uint32_t *end_line);
263 	void (*enable_per_frame_crtc_position_reset)(struct dc *dc,
264 			int group_size, struct pipe_ctx *grouped_pipes[]);
265 	void (*enable_timing_synchronization)(struct dc *dc,
266 			struct dc_state *state,
267 			int group_index, int group_size,
268 			struct pipe_ctx *grouped_pipes[]);
269 	void (*enable_vblanks_synchronization)(struct dc *dc,
270 			int group_index, int group_size,
271 			struct pipe_ctx *grouped_pipes[]);
272 	void (*setup_periodic_interrupt)(struct dc *dc,
273 			struct pipe_ctx *pipe_ctx);
274 	void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
275 			struct dc_crtc_timing_adjust adjust);
276 	void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
277 			int num_pipes,
278 			const struct dc_static_screen_params *events);
279 
280 	/* Stream Related */
281 	void (*enable_stream)(struct pipe_ctx *pipe_ctx);
282 	void (*disable_stream)(struct pipe_ctx *pipe_ctx);
283 	void (*blank_stream)(struct pipe_ctx *pipe_ctx);
284 	void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
285 			struct dc_link_settings *link_settings);
286 
287 	/* Bandwidth Related */
288 	void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context);
289 	bool (*update_bandwidth)(struct dc *dc, struct dc_state *context);
290 	void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context);
291 
292 	/* Infopacket Related */
293 	void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
294 	void (*send_immediate_sdp_message)(
295 			struct pipe_ctx *pipe_ctx,
296 			const uint8_t *custom_sdp_message,
297 			unsigned int sdp_message_size);
298 	void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
299 	void (*set_dmdata_attributes)(struct pipe_ctx *pipe);
300 	void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx);
301 	bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);
302 
303 	/* Cursor Related */
304 	void (*set_cursor_position)(struct pipe_ctx *pipe);
305 	void (*set_cursor_attribute)(struct pipe_ctx *pipe);
306 	void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);
307 
308 	/* Colour Related */
309 	void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx);
310 	void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx,
311 			enum dc_color_space colorspace,
312 			uint16_t *matrix, int opp_id);
313 	void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx);
314 
315 	/* VM Related */
316 	int (*init_sys_ctx)(struct dce_hwseq *hws,
317 			struct dc *dc,
318 			struct dc_phy_addr_space_config *pa_config);
319 	void (*init_vm_ctx)(struct dce_hwseq *hws,
320 			struct dc *dc,
321 			struct dc_virtual_addr_space_config *va_config,
322 			int vmid);
323 
324 	/* Writeback Related */
325 	void (*update_writeback)(struct dc *dc,
326 			struct dc_writeback_info *wb_info,
327 			struct dc_state *context);
328 	void (*enable_writeback)(struct dc *dc,
329 			struct dc_writeback_info *wb_info,
330 			struct dc_state *context);
331 	void (*disable_writeback)(struct dc *dc,
332 			unsigned int dwb_pipe_inst);
333 
334 	bool (*mmhubbub_warmup)(struct dc *dc,
335 			unsigned int num_dwb,
336 			struct dc_writeback_info *wb_info);
337 
338 	/* Clock Related */
339 	enum dc_status (*set_clock)(struct dc *dc,
340 			enum dc_clock_type clock_type,
341 			uint32_t clk_khz, uint32_t stepping);
342 	void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type,
343 			struct dc_clock_config *clock_cfg);
344 	void (*optimize_pwr_state)(const struct dc *dc,
345 			struct dc_state *context);
346 	void (*exit_optimized_pwr_state)(const struct dc *dc,
347 			struct dc_state *context);
348 	void (*calculate_pix_rate_divider)(struct dc *dc,
349 			struct dc_state *context,
350 			const struct dc_stream_state *stream);
351 
352 	/* Audio Related */
353 	void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);
354 	void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx);
355 
356 	/* Stereo 3D Related */
357 	void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc);
358 
359 	/* HW State Logging Related */
360 	void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx);
361 	void (*log_color_state)(struct dc *dc,
362 				struct dc_log_buffer_ctx *log_ctx);
363 	void (*get_hw_state)(struct dc *dc, char *pBuf,
364 			unsigned int bufSize, unsigned int mask);
365 	void (*clear_status_bits)(struct dc *dc, unsigned int mask);
366 
367 	bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx,
368 			uint32_t backlight_pwm_u16_16,
369 			uint32_t frame_ramp);
370 
371 	void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx);
372 
373 	void (*set_pipe)(struct pipe_ctx *pipe_ctx);
374 
375 	void (*enable_dp_link_output)(struct dc_link *link,
376 			const struct link_resource *link_res,
377 			enum signal_type signal,
378 			enum clock_source_id clock_source,
379 			const struct dc_link_settings *link_settings);
380 	void (*enable_tmds_link_output)(struct dc_link *link,
381 			const struct link_resource *link_res,
382 			enum signal_type signal,
383 			enum clock_source_id clock_source,
384 			enum dc_color_depth color_depth,
385 			uint32_t pixel_clock);
386 	void (*enable_lvds_link_output)(struct dc_link *link,
387 			const struct link_resource *link_res,
388 			enum clock_source_id clock_source,
389 			uint32_t pixel_clock);
390 	void (*disable_link_output)(struct dc_link *link,
391 			const struct link_resource *link_res,
392 			enum signal_type signal);
393 
394 	void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits);
395 
396 	/* Idle Optimization Related */
397 	bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);
398 
399 	bool (*does_plane_fit_in_mall)(struct dc *dc,
400 			unsigned int pitch,
401 			unsigned int height,
402 			enum surface_pixel_format format,
403 			struct dc_cursor_attributes *cursor_attr);
404 	void (*commit_subvp_config)(struct dc *dc, struct dc_state *context);
405 	void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context);
406 	void (*disable_phantom_streams)(struct dc *dc, struct dc_state *context);
407 	void (*subvp_pipe_control_lock)(struct dc *dc,
408 			struct dc_state *context,
409 			bool lock,
410 			bool should_lock_all_pipes,
411 			struct pipe_ctx *top_pipe_to_program,
412 			bool subvp_prev_use);
413 	void (*subvp_pipe_control_lock_fast)(union block_sequence_params *params);
414 
415 	void (*z10_restore)(const struct dc *dc);
416 	void (*z10_save_init)(struct dc *dc);
417 	bool (*is_abm_supported)(struct dc *dc,
418 			struct dc_state *context, struct dc_stream_state *stream);
419 
420 	void (*set_disp_pattern_generator)(const struct dc *dc,
421 			struct pipe_ctx *pipe_ctx,
422 			enum controller_dp_test_pattern test_pattern,
423 			enum controller_dp_color_space color_space,
424 			enum dc_color_depth color_depth,
425 			const struct tg_color *solid_color,
426 			int width, int height, int offset);
427 	void (*blank_phantom)(struct dc *dc,
428 			struct timing_generator *tg,
429 			int width,
430 			int height);
431 	void (*update_visual_confirm_color)(struct dc *dc,
432 			struct pipe_ctx *pipe_ctx,
433 			int mpcc_id);
434 	void (*update_phantom_vp_position)(struct dc *dc,
435 			struct dc_state *context,
436 			struct pipe_ctx *phantom_pipe);
437 	void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe);
438 
439 	void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context,
440 		struct pg_block_update *update_state);
441 	void (*calc_blocks_to_ungate)(struct dc *dc, struct dc_state *context,
442 		struct pg_block_update *update_state);
443 	void (*hw_block_power_up)(struct dc *dc,
444 		struct pg_block_update *update_state);
445 	void (*hw_block_power_down)(struct dc *dc,
446 		struct pg_block_update *update_state);
447 	void (*root_clock_control)(struct dc *dc,
448 		struct pg_block_update *update_state, bool power_on);
449 	bool (*is_pipe_topology_transition_seamless)(struct dc *dc,
450 			const struct dc_state *cur_ctx,
451 			const struct dc_state *new_ctx);
452 	void (*wait_for_dcc_meta_propagation)(const struct dc *dc,
453 		const struct pipe_ctx *top_pipe_to_program);
454 	void (*fams2_global_control_lock)(struct dc *dc,
455 			struct dc_state *context,
456 			bool lock);
457 	void (*fams2_update_config)(struct dc *dc,
458 			struct dc_state *context,
459 			bool enable);
460 	void (*fams2_global_control_lock_fast)(union block_sequence_params *params);
461 	void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max);
462 	void (*program_outstanding_updates)(struct dc *dc,
463 			struct dc_state *context);
464 	void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
465 };
466 
467 void color_space_to_black_color(
468 	const struct dc *dc,
469 	enum dc_color_space colorspace,
470 	struct tg_color *black_color);
471 
472 bool hwss_wait_for_blank_complete(
473 		struct timing_generator *tg);
474 
475 const uint16_t *find_color_matrix(
476 		enum dc_color_space color_space,
477 		uint32_t *array_size);
478 
479 void get_surface_tile_visual_confirm_color(
480 		struct pipe_ctx *pipe_ctx,
481 		struct tg_color *color);
482 void get_surface_visual_confirm_color(
483 		const struct pipe_ctx *pipe_ctx,
484 		struct tg_color *color);
485 
486 void get_hdr_visual_confirm_color(
487 		struct pipe_ctx *pipe_ctx,
488 		struct tg_color *color);
489 void get_mpctree_visual_confirm_color(
490 		struct pipe_ctx *pipe_ctx,
491 		struct tg_color *color);
492 
493 void get_subvp_visual_confirm_color(
494 	struct pipe_ctx *pipe_ctx,
495 	struct tg_color *color);
496 
497 void get_fams2_visual_confirm_color(
498 	struct dc *dc,
499 	struct dc_state *context,
500 	struct pipe_ctx *pipe_ctx,
501 	struct tg_color *color);
502 
503 void get_mclk_switch_visual_confirm_color(
504 		struct pipe_ctx *pipe_ctx,
505 		struct tg_color *color);
506 
507 void set_p_state_switch_method(
508 		struct dc *dc,
509 		struct dc_state *context,
510 		struct pipe_ctx *pipe_ctx);
511 
512 void hwss_execute_sequence(struct dc *dc,
513 		struct block_sequence block_sequence[],
514 		int num_steps);
515 
516 void hwss_build_fast_sequence(struct dc *dc,
517 		struct dc_dmub_cmd *dc_dmub_cmd,
518 		unsigned int dmub_cmd_count,
519 		struct block_sequence block_sequence[],
520 		unsigned int *num_steps,
521 		struct pipe_ctx *pipe_ctx,
522 		struct dc_stream_status *stream_status,
523 		struct dc_state *context);
524 
525 void hwss_wait_for_all_blank_complete(struct dc *dc,
526 		struct dc_state *context);
527 
528 void hwss_wait_for_odm_update_pending_complete(struct dc *dc,
529 		struct dc_state *context);
530 
531 void hwss_wait_for_no_pipes_pending(struct dc *dc,
532 		struct dc_state *context);
533 
534 void hwss_wait_for_outstanding_hw_updates(struct dc *dc,
535 		struct dc_state *dc_context);
536 
537 void hwss_process_outstanding_hw_updates(struct dc *dc,
538 		struct dc_state *dc_context);
539 
540 void hwss_send_dmcub_cmd(union block_sequence_params *params);
541 
542 void hwss_program_manual_trigger(union block_sequence_params *params);
543 
544 void hwss_setup_dpp(union block_sequence_params *params);
545 
546 void hwss_program_bias_and_scale(union block_sequence_params *params);
547 
548 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params);
549 
550 void hwss_set_output_csc(union block_sequence_params *params);
551 
552 void hwss_set_ocsc_default(union block_sequence_params *params);
553 
554 void hwss_subvp_save_surf_addr(union block_sequence_params *params);
555 
556 #endif /* __DC_HW_SEQUENCER_H__ */
557