1 //! `x86` and `x86_64` intrinsics.
2
3 use crate::{intrinsics, marker::Sized, mem::transmute};
4
5 #[macro_use]
6 mod macros;
7
8 types! {
9 /// 128-bit wide integer vector type, x86-specific
10 ///
11 /// This type is the same as the `__m128i` type defined by Intel,
12 /// representing a 128-bit SIMD register. Usage of this type typically
13 /// corresponds to the `sse` and up target features for x86/x86_64.
14 ///
15 /// Internally this type may be viewed as:
16 ///
17 /// * `i8x16` - sixteen `i8` variables packed together
18 /// * `i16x8` - eight `i16` variables packed together
19 /// * `i32x4` - four `i32` variables packed together
20 /// * `i64x2` - two `i64` variables packed together
21 ///
22 /// (as well as unsigned versions). Each intrinsic may interpret the
23 /// internal bits differently, check the documentation of the intrinsic
24 /// to see how it's being used.
25 ///
26 /// Note that this means that an instance of `__m128i` typically just means
27 /// a "bag of bits" which is left up to interpretation at the point of use.
28 ///
29 /// Most intrinsics using `__m128i` are prefixed with `_mm_` and the
30 /// integer types tend to correspond to suffixes like "epi8" or "epi32".
31 ///
32 /// # Examples
33 ///
34 /// ```
35 /// #[cfg(target_arch = "x86")]
36 /// use std::arch::x86::*;
37 /// #[cfg(target_arch = "x86_64")]
38 /// use std::arch::x86_64::*;
39 ///
40 /// # fn main() {
41 /// # #[target_feature(enable = "sse2")]
42 /// # unsafe fn foo() {
43 /// let all_bytes_zero = _mm_setzero_si128();
44 /// let all_bytes_one = _mm_set1_epi8(1);
45 /// let four_i32 = _mm_set_epi32(1, 2, 3, 4);
46 /// # }
47 /// # if is_x86_feature_detected!("sse2") { unsafe { foo() } }
48 /// # }
49 /// ```
50 #[stable(feature = "simd_x86", since = "1.27.0")]
51 pub struct __m128i(i64, i64);
52
53 /// 128-bit wide set of four `f32` types, x86-specific
54 ///
55 /// This type is the same as the `__m128` type defined by Intel,
56 /// representing a 128-bit SIMD register which internally is consisted of
57 /// four packed `f32` instances. Usage of this type typically corresponds
58 /// to the `sse` and up target features for x86/x86_64.
59 ///
60 /// Note that unlike `__m128i`, the integer version of the 128-bit
61 /// registers, this `__m128` type has *one* interpretation. Each instance
62 /// of `__m128` always corresponds to `f32x4`, or four `f32` types packed
63 /// together.
64 ///
65 /// Most intrinsics using `__m128` are prefixed with `_mm_` and are
66 /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with
67 /// "pd" which is used for `__m128d`.
68 ///
69 /// # Examples
70 ///
71 /// ```
72 /// #[cfg(target_arch = "x86")]
73 /// use std::arch::x86::*;
74 /// #[cfg(target_arch = "x86_64")]
75 /// use std::arch::x86_64::*;
76 ///
77 /// # fn main() {
78 /// # #[target_feature(enable = "sse")]
79 /// # unsafe fn foo() {
80 /// let four_zeros = _mm_setzero_ps();
81 /// let four_ones = _mm_set1_ps(1.0);
82 /// let four_floats = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
83 /// # }
84 /// # if is_x86_feature_detected!("sse") { unsafe { foo() } }
85 /// # }
86 /// ```
87 #[stable(feature = "simd_x86", since = "1.27.0")]
88 pub struct __m128(f32, f32, f32, f32);
89
90 /// 128-bit wide set of two `f64` types, x86-specific
91 ///
92 /// This type is the same as the `__m128d` type defined by Intel,
93 /// representing a 128-bit SIMD register which internally is consisted of
94 /// two packed `f64` instances. Usage of this type typically corresponds
95 /// to the `sse` and up target features for x86/x86_64.
96 ///
97 /// Note that unlike `__m128i`, the integer version of the 128-bit
98 /// registers, this `__m128d` type has *one* interpretation. Each instance
99 /// of `__m128d` always corresponds to `f64x2`, or two `f64` types packed
100 /// together.
101 ///
102 /// Most intrinsics using `__m128d` are prefixed with `_mm_` and are
103 /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with
104 /// "ps" which is used for `__m128`.
105 ///
106 /// # Examples
107 ///
108 /// ```
109 /// #[cfg(target_arch = "x86")]
110 /// use std::arch::x86::*;
111 /// #[cfg(target_arch = "x86_64")]
112 /// use std::arch::x86_64::*;
113 ///
114 /// # fn main() {
115 /// # #[target_feature(enable = "sse")]
116 /// # unsafe fn foo() {
117 /// let two_zeros = _mm_setzero_pd();
118 /// let two_ones = _mm_set1_pd(1.0);
119 /// let two_floats = _mm_set_pd(1.0, 2.0);
120 /// # }
121 /// # if is_x86_feature_detected!("sse") { unsafe { foo() } }
122 /// # }
123 /// ```
124 #[stable(feature = "simd_x86", since = "1.27.0")]
125 pub struct __m128d(f64, f64);
126
127 /// 256-bit wide integer vector type, x86-specific
128 ///
129 /// This type is the same as the `__m256i` type defined by Intel,
130 /// representing a 256-bit SIMD register. Usage of this type typically
131 /// corresponds to the `avx` and up target features for x86/x86_64.
132 ///
133 /// Internally this type may be viewed as:
134 ///
135 /// * `i8x32` - thirty two `i8` variables packed together
136 /// * `i16x16` - sixteen `i16` variables packed together
137 /// * `i32x8` - eight `i32` variables packed together
138 /// * `i64x4` - four `i64` variables packed together
139 ///
140 /// (as well as unsigned versions). Each intrinsic may interpret the
141 /// internal bits differently, check the documentation of the intrinsic
142 /// to see how it's being used.
143 ///
144 /// Note that this means that an instance of `__m256i` typically just means
145 /// a "bag of bits" which is left up to interpretation at the point of use.
146 ///
147 /// # Examples
148 ///
149 /// ```
150 /// #[cfg(target_arch = "x86")]
151 /// use std::arch::x86::*;
152 /// #[cfg(target_arch = "x86_64")]
153 /// use std::arch::x86_64::*;
154 ///
155 /// # fn main() {
156 /// # #[target_feature(enable = "avx")]
157 /// # unsafe fn foo() {
158 /// let all_bytes_zero = _mm256_setzero_si256();
159 /// let all_bytes_one = _mm256_set1_epi8(1);
160 /// let eight_i32 = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
161 /// # }
162 /// # if is_x86_feature_detected!("avx") { unsafe { foo() } }
163 /// # }
164 /// ```
165 #[stable(feature = "simd_x86", since = "1.27.0")]
166 pub struct __m256i(i64, i64, i64, i64);
167
168 /// 256-bit wide set of eight `f32` types, x86-specific
169 ///
170 /// This type is the same as the `__m256` type defined by Intel,
171 /// representing a 256-bit SIMD register which internally is consisted of
172 /// eight packed `f32` instances. Usage of this type typically corresponds
173 /// to the `avx` and up target features for x86/x86_64.
174 ///
175 /// Note that unlike `__m256i`, the integer version of the 256-bit
176 /// registers, this `__m256` type has *one* interpretation. Each instance
177 /// of `__m256` always corresponds to `f32x8`, or eight `f32` types packed
178 /// together.
179 ///
180 /// Most intrinsics using `__m256` are prefixed with `_mm256_` and are
181 /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with
182 /// "pd" which is used for `__m256d`.
183 ///
184 /// # Examples
185 ///
186 /// ```
187 /// #[cfg(target_arch = "x86")]
188 /// use std::arch::x86::*;
189 /// #[cfg(target_arch = "x86_64")]
190 /// use std::arch::x86_64::*;
191 ///
192 /// # fn main() {
193 /// # #[target_feature(enable = "avx")]
194 /// # unsafe fn foo() {
195 /// let eight_zeros = _mm256_setzero_ps();
196 /// let eight_ones = _mm256_set1_ps(1.0);
197 /// let eight_floats = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
198 /// # }
199 /// # if is_x86_feature_detected!("avx") { unsafe { foo() } }
200 /// # }
201 /// ```
202 #[stable(feature = "simd_x86", since = "1.27.0")]
203 pub struct __m256(f32, f32, f32, f32, f32, f32, f32, f32);
204
205 /// 256-bit wide set of four `f64` types, x86-specific
206 ///
207 /// This type is the same as the `__m256d` type defined by Intel,
208 /// representing a 256-bit SIMD register which internally is consisted of
209 /// four packed `f64` instances. Usage of this type typically corresponds
210 /// to the `avx` and up target features for x86/x86_64.
211 ///
212 /// Note that unlike `__m256i`, the integer version of the 256-bit
213 /// registers, this `__m256d` type has *one* interpretation. Each instance
214 /// of `__m256d` always corresponds to `f64x4`, or four `f64` types packed
215 /// together.
216 ///
217 /// Most intrinsics using `__m256d` are prefixed with `_mm256_` and are
218 /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with
219 /// "ps" which is used for `__m256`.
220 ///
221 /// # Examples
222 ///
223 /// ```
224 /// #[cfg(target_arch = "x86")]
225 /// use std::arch::x86::*;
226 /// #[cfg(target_arch = "x86_64")]
227 /// use std::arch::x86_64::*;
228 ///
229 /// # fn main() {
230 /// # #[target_feature(enable = "avx")]
231 /// # unsafe fn foo() {
232 /// let four_zeros = _mm256_setzero_pd();
233 /// let four_ones = _mm256_set1_pd(1.0);
234 /// let four_floats = _mm256_set_pd(1.0, 2.0, 3.0, 4.0);
235 /// # }
236 /// # if is_x86_feature_detected!("avx") { unsafe { foo() } }
237 /// # }
238 /// ```
239 #[stable(feature = "simd_x86", since = "1.27.0")]
240 pub struct __m256d(f64, f64, f64, f64);
241
242 /// 512-bit wide integer vector type, x86-specific
243 ///
244 /// This type is the same as the `__m512i` type defined by Intel,
245 /// representing a 512-bit SIMD register. Usage of this type typically
246 /// corresponds to the `avx512*` and up target features for x86/x86_64.
247 ///
248 /// Internally this type may be viewed as:
249 ///
250 /// * `i8x64` - sixty-four `i8` variables packed together
251 /// * `i16x32` - thirty-two `i16` variables packed together
252 /// * `i32x16` - sixteen `i32` variables packed together
253 /// * `i64x8` - eight `i64` variables packed together
254 ///
255 /// (as well as unsigned versions). Each intrinsic may interpret the
256 /// internal bits differently, check the documentation of the intrinsic
257 /// to see how it's being used.
258 ///
259 /// Note that this means that an instance of `__m512i` typically just means
260 /// a "bag of bits" which is left up to interpretation at the point of use.
261 pub struct __m512i(i64, i64, i64, i64, i64, i64, i64, i64);
262
263 /// 512-bit wide set of sixteen `f32` types, x86-specific
264 ///
265 /// This type is the same as the `__m512` type defined by Intel,
266 /// representing a 512-bit SIMD register which internally is consisted of
267 /// eight packed `f32` instances. Usage of this type typically corresponds
268 /// to the `avx512*` and up target features for x86/x86_64.
269 ///
270 /// Note that unlike `__m512i`, the integer version of the 512-bit
271 /// registers, this `__m512` type has *one* interpretation. Each instance
272 /// of `__m512` always corresponds to `f32x16`, or sixteen `f32` types
273 /// packed together.
274 ///
275 /// Most intrinsics using `__m512` are prefixed with `_mm512_` and are
276 /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with
277 /// "pd" which is used for `__m512d`.
278 pub struct __m512(
279 f32, f32, f32, f32, f32, f32, f32, f32,
280 f32, f32, f32, f32, f32, f32, f32, f32,
281 );
282
283 /// 512-bit wide set of eight `f64` types, x86-specific
284 ///
285 /// This type is the same as the `__m512d` type defined by Intel,
286 /// representing a 512-bit SIMD register which internally is consisted of
287 /// eight packed `f64` instances. Usage of this type typically corresponds
288 /// to the `avx` and up target features for x86/x86_64.
289 ///
290 /// Note that unlike `__m512i`, the integer version of the 512-bit
291 /// registers, this `__m512d` type has *one* interpretation. Each instance
292 /// of `__m512d` always corresponds to `f64x4`, or eight `f64` types packed
293 /// together.
294 ///
295 /// Most intrinsics using `__m512d` are prefixed with `_mm512_` and are
296 /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with
297 /// "ps" which is used for `__m512`.
298 pub struct __m512d(f64, f64, f64, f64, f64, f64, f64, f64);
299
300 /// 128-bit wide set of eight 'u16' types, x86-specific
301 ///
302 /// This type is representing a 128-bit SIMD register which internally is consisted of
303 /// eight packed `u16` instances. Its purpose is for bf16 related intrinsic
304 /// implementations.
305 pub struct __m128bh(u16, u16, u16, u16, u16, u16, u16, u16);
306
307 /// 256-bit wide set of 16 'u16' types, x86-specific
308 ///
309 /// This type is the same as the `__m128bh` type defined by Intel,
310 /// representing a 256-bit SIMD register which internally is consisted of
311 /// 16 packed `u16` instances. Its purpose is for bf16 related intrinsic
312 /// implementations.
313 pub struct __m256bh(
314 u16, u16, u16, u16, u16, u16, u16, u16,
315 u16, u16, u16, u16, u16, u16, u16, u16
316 );
317
318 /// 512-bit wide set of 32 'u16' types, x86-specific
319 ///
320 /// This type is the same as the `__m128bh` type defined by Intel,
321 /// representing a 512-bit SIMD register which internally is consisted of
322 /// 32 packed `u16` instances. Its purpose is for bf16 related intrinsic
323 /// implementations.
324 pub struct __m512bh(
325 u16, u16, u16, u16, u16, u16, u16, u16,
326 u16, u16, u16, u16, u16, u16, u16, u16,
327 u16, u16, u16, u16, u16, u16, u16, u16,
328 u16, u16, u16, u16, u16, u16, u16, u16
329 );
330 }
331
332 /// The `__mmask64` type used in AVX-512 intrinsics, a 64-bit integer
333 #[allow(non_camel_case_types)]
334 pub type __mmask64 = u64;
335
336 /// The `__mmask32` type used in AVX-512 intrinsics, a 32-bit integer
337 #[allow(non_camel_case_types)]
338 pub type __mmask32 = u32;
339
340 /// The `__mmask16` type used in AVX-512 intrinsics, a 16-bit integer
341 #[allow(non_camel_case_types)]
342 pub type __mmask16 = u16;
343
344 /// The `__mmask8` type used in AVX-512 intrinsics, a 8-bit integer
345 #[allow(non_camel_case_types)]
346 pub type __mmask8 = u8;
347
348 /// The `_MM_CMPINT_ENUM` type used to specify comparison operations in AVX-512 intrinsics.
349 #[allow(non_camel_case_types)]
350 pub type _MM_CMPINT_ENUM = i32;
351
352 /// The `MM_MANTISSA_NORM_ENUM` type used to specify mantissa normalized operations in AVX-512 intrinsics.
353 #[allow(non_camel_case_types)]
354 pub type _MM_MANTISSA_NORM_ENUM = i32;
355
356 /// The `MM_MANTISSA_SIGN_ENUM` type used to specify mantissa signed operations in AVX-512 intrinsics.
357 #[allow(non_camel_case_types)]
358 pub type _MM_MANTISSA_SIGN_ENUM = i32;
359
360 /// The `MM_PERM_ENUM` type used to specify shuffle operations in AVX-512 intrinsics.
361 #[allow(non_camel_case_types)]
362 pub type _MM_PERM_ENUM = i32;
363
364 #[cfg(test)]
365 mod test;
366 #[cfg(test)]
367 pub use self::test::*;
368
369 #[allow(non_camel_case_types)]
370 #[unstable(feature = "stdsimd_internal", issue = "none")]
371 pub(crate) trait m128iExt: Sized {
as_m128i(self) -> __m128i372 fn as_m128i(self) -> __m128i;
373
374 #[inline]
as_u8x16(self) -> crate::core_arch::simd::u8x16375 fn as_u8x16(self) -> crate::core_arch::simd::u8x16 {
376 unsafe { transmute(self.as_m128i()) }
377 }
378
379 #[inline]
as_u16x8(self) -> crate::core_arch::simd::u16x8380 fn as_u16x8(self) -> crate::core_arch::simd::u16x8 {
381 unsafe { transmute(self.as_m128i()) }
382 }
383
384 #[inline]
as_u32x4(self) -> crate::core_arch::simd::u32x4385 fn as_u32x4(self) -> crate::core_arch::simd::u32x4 {
386 unsafe { transmute(self.as_m128i()) }
387 }
388
389 #[inline]
as_u64x2(self) -> crate::core_arch::simd::u64x2390 fn as_u64x2(self) -> crate::core_arch::simd::u64x2 {
391 unsafe { transmute(self.as_m128i()) }
392 }
393
394 #[inline]
as_i8x16(self) -> crate::core_arch::simd::i8x16395 fn as_i8x16(self) -> crate::core_arch::simd::i8x16 {
396 unsafe { transmute(self.as_m128i()) }
397 }
398
399 #[inline]
as_i16x8(self) -> crate::core_arch::simd::i16x8400 fn as_i16x8(self) -> crate::core_arch::simd::i16x8 {
401 unsafe { transmute(self.as_m128i()) }
402 }
403
404 #[inline]
as_i32x4(self) -> crate::core_arch::simd::i32x4405 fn as_i32x4(self) -> crate::core_arch::simd::i32x4 {
406 unsafe { transmute(self.as_m128i()) }
407 }
408
409 #[inline]
as_i64x2(self) -> crate::core_arch::simd::i64x2410 fn as_i64x2(self) -> crate::core_arch::simd::i64x2 {
411 unsafe { transmute(self.as_m128i()) }
412 }
413 }
414
415 impl m128iExt for __m128i {
416 #[inline]
as_m128i(self) -> Self417 fn as_m128i(self) -> Self {
418 self
419 }
420 }
421
422 #[allow(non_camel_case_types)]
423 #[unstable(feature = "stdsimd_internal", issue = "none")]
424 pub(crate) trait m256iExt: Sized {
as_m256i(self) -> __m256i425 fn as_m256i(self) -> __m256i;
426
427 #[inline]
as_u8x32(self) -> crate::core_arch::simd::u8x32428 fn as_u8x32(self) -> crate::core_arch::simd::u8x32 {
429 unsafe { transmute(self.as_m256i()) }
430 }
431
432 #[inline]
as_u16x16(self) -> crate::core_arch::simd::u16x16433 fn as_u16x16(self) -> crate::core_arch::simd::u16x16 {
434 unsafe { transmute(self.as_m256i()) }
435 }
436
437 #[inline]
as_u32x8(self) -> crate::core_arch::simd::u32x8438 fn as_u32x8(self) -> crate::core_arch::simd::u32x8 {
439 unsafe { transmute(self.as_m256i()) }
440 }
441
442 #[inline]
as_u64x4(self) -> crate::core_arch::simd::u64x4443 fn as_u64x4(self) -> crate::core_arch::simd::u64x4 {
444 unsafe { transmute(self.as_m256i()) }
445 }
446
447 #[inline]
as_i8x32(self) -> crate::core_arch::simd::i8x32448 fn as_i8x32(self) -> crate::core_arch::simd::i8x32 {
449 unsafe { transmute(self.as_m256i()) }
450 }
451
452 #[inline]
as_i16x16(self) -> crate::core_arch::simd::i16x16453 fn as_i16x16(self) -> crate::core_arch::simd::i16x16 {
454 unsafe { transmute(self.as_m256i()) }
455 }
456
457 #[inline]
as_i32x8(self) -> crate::core_arch::simd::i32x8458 fn as_i32x8(self) -> crate::core_arch::simd::i32x8 {
459 unsafe { transmute(self.as_m256i()) }
460 }
461
462 #[inline]
as_i64x4(self) -> crate::core_arch::simd::i64x4463 fn as_i64x4(self) -> crate::core_arch::simd::i64x4 {
464 unsafe { transmute(self.as_m256i()) }
465 }
466 }
467
468 impl m256iExt for __m256i {
469 #[inline]
as_m256i(self) -> Self470 fn as_m256i(self) -> Self {
471 self
472 }
473 }
474
475 #[allow(non_camel_case_types)]
476 #[unstable(feature = "stdsimd_internal", issue = "none")]
477 pub(crate) trait m128Ext: Sized {
as_m128(self) -> __m128478 fn as_m128(self) -> __m128;
479
480 #[inline]
as_f32x4(self) -> crate::core_arch::simd::f32x4481 fn as_f32x4(self) -> crate::core_arch::simd::f32x4 {
482 unsafe { transmute(self.as_m128()) }
483 }
484 }
485
486 impl m128Ext for __m128 {
487 #[inline]
as_m128(self) -> Self488 fn as_m128(self) -> Self {
489 self
490 }
491 }
492
493 #[allow(non_camel_case_types)]
494 #[unstable(feature = "stdsimd_internal", issue = "none")]
495 pub(crate) trait m128dExt: Sized {
as_m128d(self) -> __m128d496 fn as_m128d(self) -> __m128d;
497
498 #[inline]
as_f64x2(self) -> crate::core_arch::simd::f64x2499 fn as_f64x2(self) -> crate::core_arch::simd::f64x2 {
500 unsafe { transmute(self.as_m128d()) }
501 }
502 }
503
504 impl m128dExt for __m128d {
505 #[inline]
as_m128d(self) -> Self506 fn as_m128d(self) -> Self {
507 self
508 }
509 }
510
511 #[allow(non_camel_case_types)]
512 #[unstable(feature = "stdsimd_internal", issue = "none")]
513 pub(crate) trait m256Ext: Sized {
as_m256(self) -> __m256514 fn as_m256(self) -> __m256;
515
516 #[inline]
as_f32x8(self) -> crate::core_arch::simd::f32x8517 fn as_f32x8(self) -> crate::core_arch::simd::f32x8 {
518 unsafe { transmute(self.as_m256()) }
519 }
520 }
521
522 impl m256Ext for __m256 {
523 #[inline]
as_m256(self) -> Self524 fn as_m256(self) -> Self {
525 self
526 }
527 }
528
529 #[allow(non_camel_case_types)]
530 #[unstable(feature = "stdsimd_internal", issue = "none")]
531 pub(crate) trait m256dExt: Sized {
as_m256d(self) -> __m256d532 fn as_m256d(self) -> __m256d;
533
534 #[inline]
as_f64x4(self) -> crate::core_arch::simd::f64x4535 fn as_f64x4(self) -> crate::core_arch::simd::f64x4 {
536 unsafe { transmute(self.as_m256d()) }
537 }
538 }
539
540 impl m256dExt for __m256d {
541 #[inline]
as_m256d(self) -> Self542 fn as_m256d(self) -> Self {
543 self
544 }
545 }
546
547 #[allow(non_camel_case_types)]
548 #[unstable(feature = "stdsimd_internal", issue = "none")]
549 pub(crate) trait m512iExt: Sized {
as_m512i(self) -> __m512i550 fn as_m512i(self) -> __m512i;
551
552 #[inline]
as_u8x64(self) -> crate::core_arch::simd::u8x64553 fn as_u8x64(self) -> crate::core_arch::simd::u8x64 {
554 unsafe { transmute(self.as_m512i()) }
555 }
556
557 #[inline]
as_i8x64(self) -> crate::core_arch::simd::i8x64558 fn as_i8x64(self) -> crate::core_arch::simd::i8x64 {
559 unsafe { transmute(self.as_m512i()) }
560 }
561
562 #[inline]
as_u16x32(self) -> crate::core_arch::simd::u16x32563 fn as_u16x32(self) -> crate::core_arch::simd::u16x32 {
564 unsafe { transmute(self.as_m512i()) }
565 }
566
567 #[inline]
as_i16x32(self) -> crate::core_arch::simd::i16x32568 fn as_i16x32(self) -> crate::core_arch::simd::i16x32 {
569 unsafe { transmute(self.as_m512i()) }
570 }
571
572 #[inline]
as_u32x16(self) -> crate::core_arch::simd::u32x16573 fn as_u32x16(self) -> crate::core_arch::simd::u32x16 {
574 unsafe { transmute(self.as_m512i()) }
575 }
576
577 #[inline]
as_i32x16(self) -> crate::core_arch::simd::i32x16578 fn as_i32x16(self) -> crate::core_arch::simd::i32x16 {
579 unsafe { transmute(self.as_m512i()) }
580 }
581
582 #[inline]
as_u64x8(self) -> crate::core_arch::simd::u64x8583 fn as_u64x8(self) -> crate::core_arch::simd::u64x8 {
584 unsafe { transmute(self.as_m512i()) }
585 }
586
587 #[inline]
as_i64x8(self) -> crate::core_arch::simd::i64x8588 fn as_i64x8(self) -> crate::core_arch::simd::i64x8 {
589 unsafe { transmute(self.as_m512i()) }
590 }
591 }
592
593 impl m512iExt for __m512i {
594 #[inline]
as_m512i(self) -> Self595 fn as_m512i(self) -> Self {
596 self
597 }
598 }
599
600 #[allow(non_camel_case_types)]
601 #[unstable(feature = "stdsimd_internal", issue = "none")]
602 pub(crate) trait m512Ext: Sized {
as_m512(self) -> __m512603 fn as_m512(self) -> __m512;
604
605 #[inline]
as_f32x16(self) -> crate::core_arch::simd::f32x16606 fn as_f32x16(self) -> crate::core_arch::simd::f32x16 {
607 unsafe { transmute(self.as_m512()) }
608 }
609 }
610
611 impl m512Ext for __m512 {
612 #[inline]
as_m512(self) -> Self613 fn as_m512(self) -> Self {
614 self
615 }
616 }
617
618 #[allow(non_camel_case_types)]
619 #[unstable(feature = "stdsimd_internal", issue = "none")]
620 pub(crate) trait m512dExt: Sized {
as_m512d(self) -> __m512d621 fn as_m512d(self) -> __m512d;
622
623 #[inline]
as_f64x8(self) -> crate::core_arch::simd::f64x8624 fn as_f64x8(self) -> crate::core_arch::simd::f64x8 {
625 unsafe { transmute(self.as_m512d()) }
626 }
627 }
628
629 impl m512dExt for __m512d {
630 #[inline]
as_m512d(self) -> Self631 fn as_m512d(self) -> Self {
632 self
633 }
634 }
635
636 #[allow(non_camel_case_types)]
637 #[unstable(feature = "stdsimd_internal", issue = "none")]
638 pub(crate) trait m128bhExt: Sized {
as_m128bh(self) -> __m128bh639 fn as_m128bh(self) -> __m128bh;
640
641 #[inline]
as_u16x8(self) -> crate::core_arch::simd::u16x8642 fn as_u16x8(self) -> crate::core_arch::simd::u16x8 {
643 unsafe { transmute(self.as_m128bh()) }
644 }
645
646 #[inline]
as_i16x8(self) -> crate::core_arch::simd::i16x8647 fn as_i16x8(self) -> crate::core_arch::simd::i16x8 {
648 unsafe { transmute(self.as_m128bh()) }
649 }
650
651 #[inline]
as_u32x4(self) -> crate::core_arch::simd::u32x4652 fn as_u32x4(self) -> crate::core_arch::simd::u32x4 {
653 unsafe { transmute(self.as_m128bh()) }
654 }
655
656 #[inline]
as_i32x4(self) -> crate::core_arch::simd::i32x4657 fn as_i32x4(self) -> crate::core_arch::simd::i32x4 {
658 unsafe { transmute(self.as_m128bh()) }
659 }
660 }
661
662 impl m128bhExt for __m128bh {
663 #[inline]
as_m128bh(self) -> Self664 fn as_m128bh(self) -> Self {
665 self
666 }
667 }
668
669 #[allow(non_camel_case_types)]
670 #[unstable(feature = "stdsimd_internal", issue = "none")]
671 pub(crate) trait m256bhExt: Sized {
as_m256bh(self) -> __m256bh672 fn as_m256bh(self) -> __m256bh;
673
674 #[inline]
as_u16x16(self) -> crate::core_arch::simd::u16x16675 fn as_u16x16(self) -> crate::core_arch::simd::u16x16 {
676 unsafe { transmute(self.as_m256bh()) }
677 }
678
679 #[inline]
as_i16x16(self) -> crate::core_arch::simd::i16x16680 fn as_i16x16(self) -> crate::core_arch::simd::i16x16 {
681 unsafe { transmute(self.as_m256bh()) }
682 }
683
684 #[inline]
as_u32x8(self) -> crate::core_arch::simd::u32x8685 fn as_u32x8(self) -> crate::core_arch::simd::u32x8 {
686 unsafe { transmute(self.as_m256bh()) }
687 }
688
689 #[inline]
as_i32x8(self) -> crate::core_arch::simd::i32x8690 fn as_i32x8(self) -> crate::core_arch::simd::i32x8 {
691 unsafe { transmute(self.as_m256bh()) }
692 }
693 }
694
695 impl m256bhExt for __m256bh {
696 #[inline]
as_m256bh(self) -> Self697 fn as_m256bh(self) -> Self {
698 self
699 }
700 }
701
702 #[allow(non_camel_case_types)]
703 #[unstable(feature = "stdsimd_internal", issue = "none")]
704 pub(crate) trait m512bhExt: Sized {
as_m512bh(self) -> __m512bh705 fn as_m512bh(self) -> __m512bh;
706
707 #[inline]
as_u16x32(self) -> crate::core_arch::simd::u16x32708 fn as_u16x32(self) -> crate::core_arch::simd::u16x32 {
709 unsafe { transmute(self.as_m512bh()) }
710 }
711
712 #[inline]
as_i16x32(self) -> crate::core_arch::simd::i16x32713 fn as_i16x32(self) -> crate::core_arch::simd::i16x32 {
714 unsafe { transmute(self.as_m512bh()) }
715 }
716
717 #[inline]
as_u32x16(self) -> crate::core_arch::simd::u32x16718 fn as_u32x16(self) -> crate::core_arch::simd::u32x16 {
719 unsafe { transmute(self.as_m512bh()) }
720 }
721
722 #[inline]
as_i32x16(self) -> crate::core_arch::simd::i32x16723 fn as_i32x16(self) -> crate::core_arch::simd::i32x16 {
724 unsafe { transmute(self.as_m512bh()) }
725 }
726 }
727
728 impl m512bhExt for __m512bh {
729 #[inline]
as_m512bh(self) -> Self730 fn as_m512bh(self) -> Self {
731 self
732 }
733 }
734
735 mod eflags;
736 pub use self::eflags::*;
737
738 mod fxsr;
739 pub use self::fxsr::*;
740
741 mod bswap;
742 pub use self::bswap::*;
743
744 mod rdtsc;
745 pub use self::rdtsc::*;
746
747 mod cpuid;
748 pub use self::cpuid::*;
749 mod xsave;
750 pub use self::xsave::*;
751
752 mod sse;
753 pub use self::sse::*;
754 mod sse2;
755 pub use self::sse2::*;
756 mod sse3;
757 pub use self::sse3::*;
758 mod ssse3;
759 pub use self::ssse3::*;
760 mod sse41;
761 pub use self::sse41::*;
762 mod sse42;
763 pub use self::sse42::*;
764 mod avx;
765 pub use self::avx::*;
766 mod avx2;
767 pub use self::avx2::*;
768 mod fma;
769 pub use self::fma::*;
770
771 mod abm;
772 pub use self::abm::*;
773 mod bmi1;
774 pub use self::bmi1::*;
775
776 mod bmi2;
777 pub use self::bmi2::*;
778
779 #[cfg(not(stdarch_intel_sde))]
780 mod sse4a;
781 #[cfg(not(stdarch_intel_sde))]
782 pub use self::sse4a::*;
783
784 #[cfg(not(stdarch_intel_sde))]
785 mod tbm;
786 #[cfg(not(stdarch_intel_sde))]
787 pub use self::tbm::*;
788
789 mod pclmulqdq;
790 pub use self::pclmulqdq::*;
791
792 mod aes;
793 pub use self::aes::*;
794
795 mod rdrand;
796 pub use self::rdrand::*;
797
798 mod sha;
799 pub use self::sha::*;
800
801 mod adx;
802 pub use self::adx::*;
803
804 #[cfg(test)]
805 use stdarch_test::assert_instr;
806
807 /// Generates the trap instruction `UD2`
808 #[cfg_attr(test, assert_instr(ud2))]
809 #[inline]
ud2() -> !810 pub unsafe fn ud2() -> ! {
811 intrinsics::abort()
812 }
813
814 mod avx512f;
815 pub use self::avx512f::*;
816
817 mod avx512bw;
818 pub use self::avx512bw::*;
819
820 mod avx512cd;
821 pub use self::avx512cd::*;
822
823 mod avx512ifma;
824 pub use self::avx512ifma::*;
825
826 mod avx512vbmi;
827 pub use self::avx512vbmi::*;
828
829 mod avx512vbmi2;
830 pub use self::avx512vbmi2::*;
831
832 mod avx512vnni;
833 pub use self::avx512vnni::*;
834
835 mod avx512bitalg;
836 pub use self::avx512bitalg::*;
837
838 mod avx512gfni;
839 pub use self::avx512gfni::*;
840
841 mod avx512vpopcntdq;
842 pub use self::avx512vpopcntdq::*;
843
844 mod avx512vaes;
845 pub use self::avx512vaes::*;
846
847 mod avx512vpclmulqdq;
848 pub use self::avx512vpclmulqdq::*;
849
850 mod bt;
851 pub use self::bt::*;
852
853 mod rtm;
854 pub use self::rtm::*;
855
856 mod f16c;
857 pub use self::f16c::*;
858
859 mod avx512bf16;
860 pub use self::avx512bf16::*;
861