1 /*****************************************************************************
2 *
3 * m65ce02.c
4 * Portable 65ce02 emulator V1.0beta3
5 *
6 * Copyright (c) 2000 Peter Trauner, all rights reserved
7 * documentation preliminary databook
8 * documentation by michael steil mist@c64.org
9 * available at ftp://ftp.funet.fi/pub/cbm/c65
10 *
11 * - This source code is released as freeware for non-commercial purposes.
12 * - You are free to use and redistribute this code in modified or
13 * unmodified form, provided you list me in the credits.
14 * - If you modify this source code, you must add a notice to each modified
15 * source file that it has been changed. If you're a nice person, you
16 * will clearly mark each change too. :)
17 * - If you wish to use this for commercial purposes, please contact me at
18 * pullmoll@t-online.de
19 * - The author of this copywritten work reserves the right to change the
20 * terms of its usage and license at any time, including retroactively
21 * - This entire notice must remain in the source code.
22 *
23 *****************************************************************************/
24 /* 4. February 2000 PeT fixed relative word operand */
25 /* 4. February 2000 PeT jsr (absolut) jsr (absolut,x) inw dew */
26 /* 17.February 2000 PeT phw */
27 /* 16.March 2000 PeT fixed some instructions accordingly to databook */
28 /* 7. May 2000 PeT splittet into m65ce02 and m4510 */
29
30 /*
31
32 * neg is now simple 2er komplement negation with set of N and Z
33
34 * phw push low order byte, push high order byte!
35
36 * tys txs not interruptable, not implemented
37
38 */
39
40 #include <stdio.h>
41 #include "driver.h"
42 #include "state.h"
43 #include "m65ce02.h"
44
45 #include "ops02.h"
46 #include "opsc02.h"
47 #include "opsce02.h"
48
49 #define VERBOSE 0
50
51 #if VERBOSE
52 #define LOG(x) logerror x
53 #else
54 #define LOG(x)
55 #endif
56
57 typedef struct {
58 void (**insn)(void); /* pointer to the function pointer table */
59 PAIR ppc; /* previous program counter */
60 PAIR pc; /* program counter */
61 PAIR sp; /* stack pointer (always 100 - 1FF) */
62 PAIR zp; /* zero page address */
63 /* contains B register zp.b.h */
64 PAIR ea; /* effective address */
65 UINT8 a; /* Accumulator */
66 UINT8 x; /* X index register */
67 UINT8 y; /* Y index register */
68 UINT8 z; /* Z index register */
69 UINT8 p; /* Processor status */
70 UINT8 pending_irq; /* nonzero if an IRQ is pending */
71 UINT8 after_cli; /* pending IRQ and last insn cleared I */
72 UINT8 nmi_state;
73 UINT8 irq_state;
74 int (*irq_callback)(int irqline); /* IRQ callback */
75 } m65ce02_Regs;
76
77
78 int m65ce02_ICount = 0;
79
80 static m65ce02_Regs m65ce02;
81
82 /***************************************************************
83 * include the opcode macros, functions and tables
84 ***************************************************************/
85
86 #include "t65ce02.c"
87
m65ce02_reset(void * param)88 void m65ce02_reset (void *param)
89 {
90 m65ce02.insn = insn65ce02;
91
92 /* wipe out the rest of the m65ce02 structure */
93 /* read the reset vector into PC */
94 /* reset z index and b bank */
95 PCL = RDMEM(M65CE02_RST_VEC);
96 PCH = RDMEM(M65CE02_RST_VEC+1);
97
98 /* after reset in 6502 compatibility mode */
99 m65ce02.sp.d = 0x01ff; /* high byte descriped in databook */
100 m65ce02.z = 0;
101 B = 0;
102 m65ce02.p = F_E|F_B|F_I|F_Z; /* set E, I and Z flags */
103 m65ce02.pending_irq = 0; /* nonzero if an IRQ is pending */
104 m65ce02.after_cli = 0; /* pending IRQ and last insn cleared I */
105 m65ce02.irq_callback = NULL;
106
107 change_pc16(PCD);
108 }
109
m65ce02_exit(void)110 void m65ce02_exit(void)
111 {
112 /* nothing to do yet */
113 }
114
m65ce02_get_context(void * dst)115 unsigned m65ce02_get_context (void *dst)
116 {
117 if( dst )
118 *(m65ce02_Regs*)dst = m65ce02;
119 return sizeof(m65ce02_Regs);
120 }
121
m65ce02_set_context(void * src)122 void m65ce02_set_context (void *src)
123 {
124 if( src )
125 {
126 m65ce02 = *(m65ce02_Regs*)src;
127 change_pc16(PCD);
128 }
129 }
130
m65ce02_get_pc(void)131 unsigned m65ce02_get_pc (void)
132 {
133 return PCD;
134 }
135
m65ce02_set_pc(unsigned val)136 void m65ce02_set_pc (unsigned val)
137 {
138 PCW = val;
139 change_pc16(PCD);
140 }
141
m65ce02_get_sp(void)142 unsigned m65ce02_get_sp (void)
143 {
144 return S;
145 }
146
m65ce02_set_sp(unsigned val)147 void m65ce02_set_sp (unsigned val)
148 {
149 S = val;
150 }
151
m65ce02_get_reg(int regnum)152 unsigned m65ce02_get_reg (int regnum)
153 {
154 switch( regnum )
155 {
156 case M65CE02_PC: return m65ce02.pc.w.l;
157 case M65CE02_S: return m65ce02.sp.w.l;
158 case M65CE02_P: return m65ce02.p;
159 case M65CE02_A: return m65ce02.a;
160 case M65CE02_X: return m65ce02.x;
161 case M65CE02_Y: return m65ce02.y;
162 case M65CE02_Z: return m65ce02.z;
163 case M65CE02_B: return m65ce02.zp.b.h;
164 case M65CE02_EA: return m65ce02.ea.w.l;
165 case M65CE02_ZP: return m65ce02.zp.b.l;
166 case M65CE02_NMI_STATE: return m65ce02.nmi_state;
167 case M65CE02_IRQ_STATE: return m65ce02.irq_state;
168 case REG_PREVIOUSPC: return m65ce02.ppc.w.l;
169 default:
170 if( regnum <= REG_SP_CONTENTS )
171 {
172 unsigned offset = S + 2 * (REG_SP_CONTENTS - regnum);
173 if( offset < 0x1ff )
174 return RDMEM( offset ) | ( RDMEM( offset + 1 ) << 8 );
175 }
176 }
177 return 0;
178 }
179
m65ce02_set_reg(int regnum,unsigned val)180 void m65ce02_set_reg (int regnum, unsigned val)
181 {
182 switch( regnum )
183 {
184 case M65CE02_PC: m65ce02.pc.w.l = val; break;
185 case M65CE02_S: m65ce02.sp.w.l = val; break;
186 case M65CE02_P: m65ce02.p = val; break;
187 case M65CE02_A: m65ce02.a = val; break;
188 case M65CE02_X: m65ce02.x = val; break;
189 case M65CE02_Y: m65ce02.y = val; break;
190 case M65CE02_Z: m65ce02.z = val; break;
191 case M65CE02_B: m65ce02.zp.b.h = val; break;
192 case M65CE02_EA: m65ce02.ea.w.l = val; break;
193 case M65CE02_ZP: m65ce02.zp.b.l = val; break;
194 case M65CE02_NMI_STATE: m65ce02_set_nmi_line( val ); break;
195 case M65CE02_IRQ_STATE: m65ce02_set_irq_line( 0, val ); break;
196 default:
197 if( regnum <= REG_SP_CONTENTS )
198 {
199 unsigned offset = S + 2 * (REG_SP_CONTENTS - regnum);
200 if( offset < 0x1ff )
201 {
202 WRMEM( offset, val & 0xfff );
203 WRMEM( offset + 1, (val >> 8) & 0xff );
204 }
205 }
206 }
207 }
208
m65ce02_take_irq(void)209 static INLINE void m65ce02_take_irq(void)
210 {
211 if( !(P & F_I) )
212 {
213 EAD = M65CE02_IRQ_VEC;
214 m65ce02_ICount -= 7;
215 PUSH(PCH);
216 PUSH(PCL);
217 PUSH(P & ~F_B);
218 P = (P & ~F_D) | F_I; /* knock out D and set I flag */
219 PCL = RDMEM(EAD);
220 PCH = RDMEM(EAD+1);
221 LOG(("M65ce02#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), PCD));
222 /* call back the cpuintrf to let it clear the line */
223 if (m65ce02.irq_callback) (*m65ce02.irq_callback)(0);
224 change_pc16(PCD);
225 }
226 m65ce02.pending_irq = 0;
227 }
228
m65ce02_execute(int cycles)229 int m65ce02_execute(int cycles)
230 {
231 m65ce02_ICount = cycles;
232
233 change_pc16(PCD);
234
235 do
236 {
237 UINT8 op;
238 PPC = PCD;
239
240 /* if an irq is pending, take it now */
241 if( m65ce02.pending_irq )
242 m65ce02_take_irq();
243
244 op = RDOP();
245 (*insn65ce02[op])();
246
247 /* check if the I flag was just reset (interrupts enabled) */
248 if( m65ce02.after_cli )
249 {
250 LOG(("M65ce02#%d after_cli was >0", cpu_getactivecpu()));
251 m65ce02.after_cli = 0;
252 if (m65ce02.irq_state != CLEAR_LINE)
253 {
254 LOG((": irq line is asserted: set pending IRQ\n"));
255 m65ce02.pending_irq = 1;
256 }
257 else
258 {
259 LOG((": irq line is clear\n"));
260 }
261 }
262 else
263 if( m65ce02.pending_irq )
264 m65ce02_take_irq();
265
266 } while (m65ce02_ICount > 0);
267
268 return cycles - m65ce02_ICount;
269 }
270
m65ce02_set_nmi_line(int state)271 void m65ce02_set_nmi_line(int state)
272 {
273 if (m65ce02.nmi_state == state) return;
274 m65ce02.nmi_state = state;
275 if( state != CLEAR_LINE )
276 {
277 LOG(("M65ce02#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
278 EAD = M65CE02_NMI_VEC;
279 m65ce02_ICount -= 7;
280 PUSH(PCH);
281 PUSH(PCL);
282 PUSH(P & ~F_B);
283 P = (P & ~F_D) | F_I; /* knock out D and set I flag */
284 PCL = RDMEM(EAD);
285 PCH = RDMEM(EAD+1);
286 LOG(("M65ce02#%d takes NMI ($%04x)\n", cpu_getactivecpu(), PCD));
287 change_pc16(PCD);
288 }
289 }
290
m65ce02_set_irq_line(int irqline,int state)291 void m65ce02_set_irq_line(int irqline, int state)
292 {
293 m65ce02.irq_state = state;
294 if( state != CLEAR_LINE )
295 {
296 LOG(("M65ce02#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
297 m65ce02.pending_irq = 1;
298 }
299 }
300
m65ce02_set_irq_callback(int (* callback)(int))301 void m65ce02_set_irq_callback(int (*callback)(int))
302 {
303 m65ce02.irq_callback = callback;
304 }
305
m65ce02_state_save(void * file)306 void m65ce02_state_save(void *file)
307 {
308 int cpu = cpu_getactivecpu();
309 /* insn is set at restore since it's a pointer */
310 state_save_UINT16(file,"m65ce02",cpu,"PC",&m65ce02.pc.w.l,2);
311 state_save_UINT16(file,"m65ce02",cpu,"SP",&m65ce02.sp.w.l,2);
312 state_save_UINT8(file,"m65ce02",cpu,"P",&m65ce02.p,1);
313 state_save_UINT8(file,"m65ce02",cpu,"A",&m65ce02.a,1);
314 state_save_UINT8(file,"m65ce02",cpu,"X",&m65ce02.x,1);
315 state_save_UINT8(file,"m65ce02",cpu,"Y",&m65ce02.y,1);
316 state_save_UINT8(file,"m65ce02",cpu,"Z",&m65ce02.z,1);
317 state_save_UINT8(file,"m65ce02",cpu,"B",&m65ce02.zp.b.h,1);
318 state_save_UINT8(file,"m65ce02",cpu,"PENDING",&m65ce02.pending_irq,1);
319 state_save_UINT8(file,"m65ce02",cpu,"AFTER_CLI",&m65ce02.after_cli,1);
320 state_save_UINT8(file,"m65ce02",cpu,"NMI_STATE",&m65ce02.nmi_state,1);
321 state_save_UINT8(file,"m65ce02",cpu,"IRQ_STATE",&m65ce02.irq_state,1);
322 }
323
m65ce02_state_load(void * file)324 void m65ce02_state_load(void *file)
325 {
326 int cpu = cpu_getactivecpu();
327 m65ce02.insn = insn65ce02;
328 state_load_UINT16(file,"m65ce02",cpu,"PC",&m65ce02.pc.w.l,2);
329 state_load_UINT16(file,"m65ce02",cpu,"SP",&m65ce02.sp.w.l,2);
330 state_load_UINT8(file,"m65ce02",cpu,"P",&m65ce02.p,1);
331 state_load_UINT8(file,"m65ce02",cpu,"A",&m65ce02.a,1);
332 state_load_UINT8(file,"m65ce02",cpu,"X",&m65ce02.x,1);
333 state_load_UINT8(file,"m65ce02",cpu,"Y",&m65ce02.y,1);
334 state_load_UINT8(file,"m65ce02",cpu,"Z",&m65ce02.z,1);
335 state_load_UINT8(file,"m65ce02",cpu,"B",&m65ce02.zp.b.h,1);
336 state_load_UINT8(file,"m65ce02",cpu,"PENDING",&m65ce02.pending_irq,1);
337 state_load_UINT8(file,"m65ce02",cpu,"AFTER_CLI",&m65ce02.after_cli,1);
338 state_load_UINT8(file,"m65ce02",cpu,"NMI_STATE",&m65ce02.nmi_state,1);
339 state_load_UINT8(file,"m65ce02",cpu,"IRQ_STATE",&m65ce02.irq_state,1);
340 }
341
342 /****************************************************************************
343 * Return a formatted string for a register
344 ****************************************************************************/
m65ce02_info(void * context,int regnum)345 const char *m65ce02_info(void *context, int regnum)
346 {
347 switch( regnum )
348 {
349 case CPU_INFO_NAME: return "M65CE02";
350 case CPU_INFO_FAMILY: return "CBM Semiconductor Group CSG 65CE02";
351 case CPU_INFO_VERSION: return "1.0beta";
352 case CPU_INFO_CREDITS:
353 return "Copyright (c) 1998 Juergen Buchmueller\n"
354 "Copyright (c) 2000 Peter Trauner\n"
355 "all rights reserved.";
356 case CPU_INFO_FILE: return __FILE__;
357 }
358 return "";
359 }
360
m65ce02_dasm(char * buffer,unsigned pc)361 unsigned int m65ce02_dasm(char *buffer, unsigned pc)
362 {
363 sprintf( buffer, "$%02X", cpu_readop(pc) );
364 return 1;
365 }
366
367
368
369