1 //===-- RegisterInfoPOSIX_arm64.h -------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H 10 #define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H 11 12 #include "RegisterInfoAndSetInterface.h" 13 #include "lldb/Target/RegisterContext.h" 14 #include "lldb/Utility/Flags.h" 15 #include "lldb/lldb-private.h" 16 #include <map> 17 18 enum class SVEState { Unknown, Disabled, FPSIMD, Full }; 19 20 class RegisterInfoPOSIX_arm64 21 : public lldb_private::RegisterInfoAndSetInterface { 22 public: 23 enum { GPRegSet = 0, FPRegSet }; 24 25 // AArch64 register set mask value 26 enum { 27 eRegsetMaskDefault = 0, 28 eRegsetMaskSVE = 1, 29 eRegsetMaskPAuth = 2, 30 eRegsetMaskMTE = 4, 31 eRegsetMaskDynamic = ~1, 32 }; 33 34 // AArch64 Register set FP/SIMD feature configuration 35 enum { 36 eVectorQuadwordAArch64, 37 eVectorQuadwordAArch64SVE, 38 eVectorQuadwordAArch64SVEMax = 256 39 }; 40 41 // based on RegisterContextDarwin_arm64.h 42 LLVM_PACKED_START 43 struct GPR { 44 uint64_t x[29]; // x0-x28 45 uint64_t fp; // x29 46 uint64_t lr; // x30 47 uint64_t sp; // x31 48 uint64_t pc; // pc 49 uint32_t cpsr; // cpsr 50 uint32_t pad; 51 }; 52 LLVM_PACKED_END 53 54 // based on RegisterContextDarwin_arm64.h 55 struct VReg { 56 uint8_t bytes[16]; 57 }; 58 59 // based on RegisterContextDarwin_arm64.h 60 struct FPU { 61 VReg v[32]; 62 uint32_t fpsr; 63 uint32_t fpcr; 64 }; 65 66 // based on RegisterContextDarwin_arm64.h 67 struct EXC { 68 uint64_t far; // Virtual Fault Address 69 uint32_t esr; // Exception syndrome 70 uint32_t exception; // number of arm exception token 71 }; 72 73 // based on RegisterContextDarwin_arm64.h 74 struct DBG { 75 uint64_t bvr[16]; 76 uint64_t bcr[16]; 77 uint64_t wvr[16]; 78 uint64_t wcr[16]; 79 uint64_t mdscr_el1; 80 }; 81 82 RegisterInfoPOSIX_arm64(const lldb_private::ArchSpec &target_arch, 83 lldb_private::Flags opt_regsets); 84 85 static size_t GetGPRSizeStatic(); GetGPRSize()86 size_t GetGPRSize() const override { return GetGPRSizeStatic(); } 87 88 size_t GetFPRSize() const override; 89 90 const lldb_private::RegisterInfo *GetRegisterInfo() const override; 91 92 uint32_t GetRegisterCount() const override; 93 94 const lldb_private::RegisterSet * 95 GetRegisterSet(size_t reg_set) const override; 96 97 size_t GetRegisterSetCount() const override; 98 99 size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override; 100 101 void AddRegSetPAuth(); 102 103 void AddRegSetMTE(); 104 105 uint32_t ConfigureVectorLength(uint32_t sve_vq); 106 VectorSizeIsValid(uint32_t vq)107 bool VectorSizeIsValid(uint32_t vq) { 108 // coverity[unsigned_compare] 109 if (vq >= eVectorQuadwordAArch64 && vq <= eVectorQuadwordAArch64SVEMax) 110 return true; 111 return false; 112 } 113 IsSVEEnabled()114 bool IsSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSVE); } IsPAuthEnabled()115 bool IsPAuthEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskPAuth); } IsMTEEnabled()116 bool IsMTEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskMTE); } 117 118 bool IsSVEReg(unsigned reg) const; 119 bool IsSVEZReg(unsigned reg) const; 120 bool IsSVEPReg(unsigned reg) const; 121 bool IsSVERegVG(unsigned reg) const; 122 bool IsPAuthReg(unsigned reg) const; 123 bool IsMTEReg(unsigned reg) const; 124 125 uint32_t GetRegNumSVEZ0() const; 126 uint32_t GetRegNumSVEFFR() const; 127 uint32_t GetRegNumFPCR() const; 128 uint32_t GetRegNumFPSR() const; 129 uint32_t GetRegNumSVEVG() const; 130 uint32_t GetPAuthOffset() const; 131 uint32_t GetMTEOffset() const; 132 133 private: 134 typedef std::map<uint32_t, std::vector<lldb_private::RegisterInfo>> 135 per_vq_register_infos; 136 137 per_vq_register_infos m_per_vq_reg_infos; 138 139 uint32_t m_vector_reg_vq = eVectorQuadwordAArch64; 140 141 const lldb_private::RegisterInfo *m_register_info_p; 142 uint32_t m_register_info_count; 143 144 const lldb_private::RegisterSet *m_register_set_p; 145 uint32_t m_register_set_count; 146 147 // Contains pair of [start, end] register numbers of a register set with start 148 // and end included. 149 std::map<uint32_t, std::pair<uint32_t, uint32_t>> m_per_regset_regnum_range; 150 151 lldb_private::Flags m_opt_regsets; 152 153 std::vector<lldb_private::RegisterInfo> m_dynamic_reg_infos; 154 std::vector<lldb_private::RegisterSet> m_dynamic_reg_sets; 155 156 std::vector<uint32_t> pauth_regnum_collection; 157 std::vector<uint32_t> m_mte_regnum_collection; 158 }; 159 160 #endif 161